mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h
- Revision:
- 181:57724642e740
- Parent:
- 167:e84263d55307
--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h Wed Jan 17 15:23:54 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h Fri Feb 16 16:09:33 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l4xx_ll_rcc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
@@ -62,7 +60,9 @@
* @{
*/
-static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+#if defined(RCC_CCIPR2_PLLSAI2DIVR)
+static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16};
+#endif /* RCC_CCIPR2_PLLSAI2DIVR */
/**
* @}
@@ -90,6 +90,7 @@
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
+
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_Exported_Types RCC Exported Types
@@ -127,7 +128,7 @@
/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
* @brief Defines used to adapt values of different oscillators
- * @note These values could be modified in the user environment according to
+ * @note These values could be modified in the user environment according to
* HW set-up.
* @{
*/
@@ -146,8 +147,8 @@
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */
-
#if defined(RCC_HSI48_SUPPORT)
+
#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
#endif /* HSI48_VALUE */
@@ -488,24 +489,50 @@
/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
* @{
*/
+#if defined(RCC_CCIPR2_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
+#else
#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */
#if defined(RCC_PLLSAI2_SUPPORT)
#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */
#endif /* RCC_PLLSAI2_SUPPORT */
#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */
-
-#if defined(RCC_CCIPR_SAI2SEL)
+#endif /* RCC_CCIPR2_SAI1SEL */
+
+#if defined(RCC_CCIPR2_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
+#elif defined(RCC_CCIPR_SAI2SEL)
#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */
#if defined(RCC_PLLSAI2_SUPPORT)
#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */
#endif /* RCC_PLLSAI2_SUPPORT */
#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */
#define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */
-#endif /* RCC_CCIPR_SAI2SEL *//**
+#endif /* RCC_CCIPR2_SAI2SEL */
+/**
* @}
*/
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
+ * @{
+ */
+#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
+#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_SDMMCSEL */
+
/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
* @{
*/
@@ -559,7 +586,7 @@
*/
#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */
#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */
-#if defined(RCC_PLLSAI2_SUPPORT)
+#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */
#endif /* RCC_PLLSAI2_SUPPORT */
#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */
@@ -579,16 +606,69 @@
#endif /* SWPMI1 */
#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection
+ * @{
+ */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
+
/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
* @{
*/
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
+#else
#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
+#endif /* RCC_CCIPR2_DFSDM1SEL */
/**
* @}
*/
#endif /* DFSDM1_Channel0 */
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
+ * @{
+ */
+#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
+#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
+ * @{
+ */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */
+/**
+ * @}
+ */
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
+ * @{
+ */
+#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */
+/**
+ * @}
+ */
+#endif /* OCTOSPI1 */
+
/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
* @{
*/
@@ -651,14 +731,30 @@
/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
* @{
*/
+#if defined(RCC_CCIPR2_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
+#else
#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
-#if defined(RCC_CCIPR_SAI2SEL)
+#endif /* RCC_CCIPR2_SAI1SEL */
+#if defined(RCC_CCIPR2_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */
+#elif defined(RCC_CCIPR_SAI2SEL)
#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */
-#endif /* RCC_CCIPR_SAI2SEL */
+#endif /* RCC_CCIPR2_SAI2SEL */
/**
* @}
*/
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
+ * @{
+ */
+#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_SDMMCSEL */
+
/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
* @{
*/
@@ -704,15 +800,60 @@
#endif /* SWPMI1 */
#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source
+ * @{
+ */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
/** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
* @{
*/
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */
+#else
#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */
+#endif /* RCC_CCIPR2_DFSDM1SEL */
/**
* @}
*/
#endif /* DFSDM1_Channel0 */
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
+ * @{
+ */
+#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
+ * @{
+ */
+#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */
+/**
+ * @}
+ */
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
+ * @{
+ */
+#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */
+/**
+ * @}
+ */
+#endif /* OCTOSPI1 */
+
+
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
@@ -724,6 +865,7 @@
* @}
*/
+
/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
* @{
*/
@@ -735,17 +877,27 @@
* @}
*/
-/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor
+/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
* @{
*/
-#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 */
-#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 */
-#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 */
-#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 */
-#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 */
-#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 */
-#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 */
-#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 */
+#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */
+#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */
+#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */
+#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */
+#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */
+#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */
+#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */
+#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */
+#if defined(RCC_PLLM_DIV_1_16_SUPPORT)
+#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */
+#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */
+#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */
+#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */
+#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */
+#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */
+#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */
+#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */
+#endif /* RCC_PLLM_DIV_1_16_SUPPORT */
/**
* @}
*/
@@ -766,35 +918,35 @@
*/
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
-#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 3 */
+#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
-#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 5 */
-#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 6 */
-#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
+#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
-#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 9 */
-#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 10 */
-#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)) /*!< Main PLL division factor for PLLP output by 11 */
-#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 12 */
-#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 13 */
-#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 14 */
-#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 15 */
+#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
+#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
+#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
+#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
+#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
+#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
+#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
-#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 17 */
-#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 18 */
-#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)) /*!< Main PLL division factor for PLLP output by 19 */
-#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 20 */
-#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 21 */
-#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 22 */
-#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 23 */
-#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 24 */
-#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 25 */
-#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 26 */
-#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 27 */
-#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 28 */
-#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 29 */
-#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 30 */
-#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 31 */
+#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
+#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
+#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
+#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
+#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
+#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
+#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
+#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
+#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
+#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
+#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
+#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
+#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
+#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
+#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
#else
#define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */
#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */
@@ -814,6 +966,31 @@
* @}
*/
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
+ * @{
+ */
+#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */
+#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */
+#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */
+#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */
+#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */
+#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */
+#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */
+#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */
+#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */
+#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */
+#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */
+#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */
+#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */
+#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */
+#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */
+#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
* @{
*/
@@ -830,35 +1007,35 @@
*/
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
-#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
+#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
-#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
-#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
-#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
+#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
+#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
+#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
-#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
-#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
-#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
-#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
-#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
-#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
-#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
+#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
+#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
+#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
+#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
+#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
+#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
+#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
-#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
-#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
-#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
-#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
-#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
-#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
-#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
-#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
-#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
-#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
-#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
-#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
-#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
-#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
-#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
+#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
+#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
+#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
+#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
+#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
+#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
+#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
+#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
+#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
+#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
+#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
+#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
+#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
+#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
+#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
#else
#define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
@@ -879,11 +1056,82 @@
*/
#if defined(RCC_PLLSAI2_SUPPORT)
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M)
+ * @{
+ */
+#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */
+#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */
+#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */
+#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */
+#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */
+#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */
+#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */
+#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */
+#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */
+#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */
+#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */
+#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */
+#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */
+#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */
+#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */
+#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q)
+ * @{
+ */
+#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */
+#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */
+#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */
+#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
+
/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
* @{
*/
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */
+#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */
+#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */
+#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */
+#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */
+#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
+#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */
+#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */
+#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */
+#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */
+#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */
+#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */
+#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */
+#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */
+#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */
+#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
+#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */
+#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */
+#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */
+#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */
+#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */
+#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */
+#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */
+#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */
+#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */
+#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */
+#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */
+#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */
+#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */
+#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
+#else
#define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
/**
* @}
*/
@@ -898,6 +1146,19 @@
/**
* @}
*/
+
+#if defined(RCC_CCIPR2_PLLSAI2DIVR)
+/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR)
+ * @{
+ */
+#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */
+#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */
+#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */
+#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_PLLSAI2DIVR */
#endif /* RCC_PLLSAI2_SUPPORT */
/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
@@ -974,6 +1235,16 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
* @param __PLLN__ Between 8 and 86
* @param __PLLR__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
@@ -1000,6 +1271,16 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
* @param __PLLN__ Between 8 and 86
* @param __PLLP__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
@@ -1035,7 +1316,7 @@
* @retval PLL clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
- ((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos))
+ ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
#else
/**
@@ -1062,6 +1343,7 @@
(((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+
/**
* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
@@ -1076,6 +1358,16 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
* @param __PLLN__ Between 8 and 86
* @param __PLLQ__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
@@ -1087,7 +1379,68 @@
#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI1M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_31
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
+
+#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
/**
* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
@@ -1138,7 +1491,8 @@
*/
#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
- ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos))
+ ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
+
#else
/**
* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
@@ -1163,8 +1517,45 @@
#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
(((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
+
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI1M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1Q__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
+
+#else
/**
* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
@@ -1191,6 +1582,44 @@
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI1M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_8
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
+
+#else
/**
* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
@@ -1217,6 +1646,123 @@
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI2M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param __PLLSAI2N__ Between 8 and 86
+ * @param __PLLSAI2P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
+
+#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI2N__ Between 8 and 86
+ * @param __PLLSAI2P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
+
+#else
/**
* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
@@ -1240,6 +1786,49 @@
#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
(((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
+
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+#if defined(LTDC)
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
+ * @param __PLLSAI2M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param __PLLSAI2N__ Between 8 and 86
+ * @param __PLLSAI2R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_8
+ * @param __PLLSAI2DIVR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
+ (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
+ (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos])))
+#else
/**
* @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
* @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
@@ -1266,6 +1855,45 @@
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
+#endif /* LTDC */
+
+#if defined(DSI)
+/**
+ * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
+ * @param __PLLSAI2M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param __PLLSAI2N__ Between 8 and 86
+ * @param __PLLSAI2Q__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
+#endif /* DSI */
+
+
/**
* @brief Helper macro to calculate the HCLK frequency
@@ -1295,7 +1923,7 @@
* @arg @ref LL_RCC_APB1_DIV_16
* @retval PCLK1 clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
/**
* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
@@ -1308,7 +1936,7 @@
* @arg @ref LL_RCC_APB2_DIV_16
* @retval PCLK2 clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
/**
* @brief Helper macro to calculate the MSI frequency (in Hz)
@@ -1453,6 +2081,16 @@
}
/**
+ * @brief Check if HSI is enabled in stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON));
+}
+
+/**
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
@@ -1579,7 +2217,7 @@
/**
* @brief Get HSI48 Calibration value
* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
- * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
*/
__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
{
@@ -2284,7 +2922,7 @@
*/
__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
{
- __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
}
@@ -2309,7 +2947,11 @@
/**
* @brief Configure SAIx clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource
+ @else
* @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
+ @endif
* @param SAIxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
@@ -2325,8 +2967,29 @@
*/
__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
{
+#if defined(RCC_CCIPR2_SAI1SEL)
+ MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
+#else
MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
-}
+#endif /* RCC_CCIPR2_SAI1SEL */
+}
+
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/**
+ * @brief Configure SDMMC1 kernel clock source
+ * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
+}
+#endif /* RCC_CCIPR2_SDMMCSEL */
/**
* @brief Configure SDMMC1 clock source
@@ -2336,7 +2999,7 @@
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
- * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -2417,9 +3080,29 @@
#endif /* SWPMI1 */
#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/**
+ * @brief Configure DFSDM Audio clock source
+ * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
+}
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
+
/**
* @brief Configure DFSDM Kernel clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
+ @else
* @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
+ @endif
* @param DFSDMxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
@@ -2427,10 +3110,62 @@
*/
__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
{
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
+#else
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
+#endif /* RCC_CCIPR2_DFSDM1SEL */
}
#endif /* DFSDM1_Channel0 */
+#if defined(DSI)
+/**
+ * @brief Configure DSI clock source
+ * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Configure LTDC Clock Source
+ * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
+}
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/**
+ * @brief Configure OCTOSPI clock source
+ * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
+}
+#endif /* OCTOSPI1 */
+
/**
* @brief Get USARTx clock source
* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
@@ -2528,8 +3263,8 @@
*/
__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
{
- __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
- return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x0000FF0000U) >> 16U)) >> ((I2Cx & 0x0000FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
+ return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
}
/**
@@ -2555,7 +3290,11 @@
/**
* @brief Get SAIx clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
+ @else
* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
+ @endif
* @param SAIx This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE
* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
@@ -2575,8 +3314,30 @@
*/
__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
{
+#if defined(RCC_CCIPR2_SAI1SEL)
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
+#else
return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx);
-}
+#endif /* RCC_CCIPR2_SAI1SEL */
+}
+
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/**
+ * @brief Get SDMMCx kernel clock source
+ * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
+ * @param SDMMCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
+}
+#endif /* RCC_CCIPR2_SDMMCSEL */
/**
* @brief Get SDMMCx clock source
@@ -2586,9 +3347,9 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
- * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
- * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
*
* (*) value not defined in all devices.
*/
@@ -2672,9 +3433,30 @@
#endif /* SWPMI1 */
#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/**
+ * @brief Get DFSDM Audio Clock Source
+ * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
+ * @param DFSDMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
+}
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
+
/**
* @brief Get DFSDMx Kernel clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
+ @else
* @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
+ @endif
* @param DFSDMx This parameter can be one of the following values:
* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
* @retval Returned value can be one of the following values:
@@ -2683,10 +3465,64 @@
*/
__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
{
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
+#else
return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
+#endif /* RCC_CCIPR2_DFSDM1SEL */
}
#endif /* DFSDM1_Channel0 */
+#if defined(DSI)
+/**
+ * @brief Get DSI Clock Source
+ * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
+ * @param DSIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Get LTDC Clock Source
+ * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource
+ * @param LTDCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
+}
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/**
+ * @brief Get OCTOSPI clock source
+ * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
+ * @param OCTOSPIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
+}
+#endif /* OCTOSPI1 */
/**
* @}
*/
@@ -2820,8 +3656,8 @@
/**
* @brief Configure PLL used for SYSCLK Domain
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLR can be written only when PLL is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLR can be written only when PLL is disabled.
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
@@ -2840,6 +3676,16 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
* @param PLLN Between 8 and 86
* @param PLLR This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
@@ -2858,8 +3704,8 @@
/**
* @brief Configure PLL used for SAI domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLP can be written only when PLL is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLP can be written only when PLL is disabled.
* @note This can be selected for SAI1 or SAI2 (*)
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
@@ -2879,6 +3725,16 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
* @param PLLN Between 8 and 86
* @param PLLP This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
@@ -2917,8 +3773,8 @@
/**
* @brief Configure PLL used for SAI domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLP can be written only when PLL is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLP can be written only when PLL is disabled.
* @note This can be selected for SAI1 or SAI2 (*)
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
@@ -2959,8 +3815,8 @@
/**
* @brief Configure PLL used for 48Mhz domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLQ can be written only when PLL is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLQ can be written only when PLL is disabled.
* @note This can be selected for USB, RNG, SDMMC
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
@@ -2980,6 +3836,16 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
* @param PLLN Between 8 and 86
* @param PLLQ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
@@ -2995,6 +3861,35 @@
}
/**
+ * @brief Configure PLL clock source
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
* @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
* @retval Between 8 and 86
@@ -3007,7 +3902,7 @@
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
/**
* @brief Get Main PLL division factor for PLLP
- * @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
+ * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
* @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
@@ -3048,7 +3943,7 @@
#else
/**
* @brief Get Main PLL division factor for PLLP
- * @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
+ * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_7
@@ -3062,7 +3957,7 @@
/**
* @brief Get Main PLL division factor for PLLQ
- * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
+ * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
@@ -3077,7 +3972,7 @@
/**
* @brief Get Main PLL division factor for PLLR
- * @note used for PLLCLK (system clock)
+ * @note Used for PLLCLK (system clock)
* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
@@ -3091,20 +3986,6 @@
}
/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_NONE
- * @arg @ref LL_RCC_PLLSOURCE_MSI
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-}
-
-/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
* @retval Returned value can be one of the following values:
@@ -3116,6 +3997,16 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
{
@@ -3232,11 +4123,58 @@
return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
}
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Configure PLLSAI1 used for 48Mhz domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for USB, RNG, SDMMC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param PLLN Between 8 and 86
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
+ PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
+}
+#else
/**
* @brief Configure PLLSAI1 used for 48Mhz domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
* @note This can be selected for USB, RNG, SDMMC
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
@@ -3269,13 +4207,86 @@
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
}
-
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+ * @brief Configure PLLSAI1 used for SAI domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param PLLN Between 8 and 86
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
+ PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+}
+#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
/**
* @brief Configure PLLSAI1 used for SAI domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
* @note This can be selected for SAI1 or SAI2 (*)
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
@@ -3329,12 +4340,18 @@
* @arg @ref LL_RCC_PLLSAI1P_DIV_31
* @retval None
*/
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
+ PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+}
#else
/**
* @brief Configure PLLSAI1 used for SAI domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.
* @note This can be selected for SAI1 or SAI2 (*)
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
@@ -3360,23 +4377,65 @@
* @arg @ref LL_RCC_PLLSAI1P_DIV_17
* @retval None
*/
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
- PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+}
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Configure PLLSAI1 used for ADC domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for ADC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param PLLN Between 8 and 86
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
+ PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
+}
#else
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-}
-
/**
* @brief Configure PLLSAI1 used for ADC domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI1 and PLLSAI2 (*) are disabled
- * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLR can be written only when PLLSAI1 is disabled.
* @note This can be selected for ADC
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
@@ -3409,6 +4468,7 @@
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
}
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
/**
* @brief Get SAI1PLL multiplication factor for VCO
@@ -3423,7 +4483,7 @@
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
/**
* @brief Get SAI1PLL division factor for PLLSAI1P
- * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
+ * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
* @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1P_DIV_2
@@ -3457,28 +4517,28 @@
* @arg @ref LL_RCC_PLLSAI1P_DIV_30
* @arg @ref LL_RCC_PLLSAI1P_DIV_31
*/
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
+}
#else
/**
* @brief Get SAI1PLL division factor for PLLSAI1P
- * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
+ * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
* @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1P_DIV_7
* @arg @ref LL_RCC_PLLSAI1P_DIV_17
*/
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
+}
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
-{
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
-#else
- return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-}
/**
* @brief Get SAI1PLL division factor for PLLSAI1Q
- * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
+ * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
* @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
@@ -3493,7 +4553,7 @@
/**
* @brief Get PLLSAI1 division factor for PLLSAIR
- * @note used for PLLADC1CLK (ADC clock)
+ * @note Used for PLLADC1CLK (ADC clock)
* @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1R_DIV_2
@@ -3506,6 +4566,34 @@
return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
}
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Get Division factor for the PLLSAI1
+ * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
+}
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
/**
* @brief Enable PLLSAI1 output mapped on SAI domain clock
* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
@@ -3611,11 +4699,148 @@
return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
}
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Configure PLLSAI2 used for SAI domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param PLLN Between 8 and 86
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
+ PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
+}
+#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
/**
* @brief Configure PLLSAI2 used for SAI domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI2 and PLLSAI2 are disabled
- * @note PLLN/PLLP can be written only when PLLSAI2 is disabled
+ * PLLSAI1 and PLLSAI2 are disabled.
+ * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
+}
+#else
+/**
+ * @brief Configure PLLSAI2 used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI2 and PLLSAI2 are disabled.
+ * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
* @note This can be selected for SAI1 or SAI2
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
@@ -3646,12 +4871,113 @@
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
}
-
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+#if defined(DSI)
+/**
+ * @brief Configure PLLSAI2 used for DSI domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for DSI
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n
+ * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n
+ * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param PLLN Between 8 and 86
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLQ | PLLM);
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Configure PLLSAI2 used for LTDC domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for LTDC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param PLLN Between 8 and 86
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_8
+ * @param PLLDIVR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR | PLLM);
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
+}
+#else
/**
* @brief Configure PLLSAI2 used for ADC domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLSAI2 and PLLSAI2 are disabled
- * @note PLLN/PLLR can be written only when PLLSAI2 is disabled
+ * PLLSAI2 and PLLSAI2 are disabled.
+ * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
* @note This can be selected for ADC
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
@@ -3684,6 +5010,7 @@
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);
}
+#endif /* LTDC */
/**
* @brief Get SAI2PLL multiplication factor for VCO
@@ -3695,9 +5022,51 @@
return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
}
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
/**
* @brief Get SAI2PLL division factor for PLLSAI2P
- * @note used for PLLSAI2CLK (SAI1 or SAI2 clock).
+ * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
+ * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
+}
+#else
+/**
+ * @brief Get SAI2PLL division factor for PLLSAI2P
+ * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
* @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSAI2P_DIV_7
@@ -3707,10 +5076,28 @@
{
return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
}
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
+/**
+ * @brief Get division factor for PLLSAI2Q
+ * @note Used for PLLDSICLK (DSI clock)
+ * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
+}
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
/**
* @brief Get SAI2PLL division factor for PLLSAI2R
- * @note used for PLLADC2CLK (ADC clock)
+ * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices
* @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSAI2R_DIV_2
@@ -3723,6 +5110,51 @@
return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
}
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+/**
+ * @brief Get Division factor for the PLLSAI2
+ * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
+}
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_CCIPR2_PLLSAI2DIVR)
+/**
+ * @brief Get PLLSAI2 division factor for PLLSAI2DIVR
+ * @note Used for LTDC domain clock
+ * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
+}
+#endif /* RCC_CCIPR2_PLLSAI2DIVR */
+
/**
* @brief Enable PLLSAI2 output mapped on SAI domain clock
* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
@@ -3745,6 +5177,53 @@
CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
}
+#if defined(DSI)
+/**
+ * @brief Enable PLLSAI2 output mapped on DSI domain clock
+ * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
+{
+ SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
+}
+
+/**
+ * @brief Disable PLLSAI2 output mapped on DSI domain clock
+ * @note In order to save power, when of the PLLSAI2 is
+ * not used, Main PLLSAI2 should be 0
+ * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
+{
+ CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Enable PLLSAI2 output mapped on LTDC domain clock
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
+{
+ SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+
+/**
+ * @brief Disable PLLSAI2 output mapped on LTDC domain clock
+ * @note In order to save power, when of the PLLSAI2 is
+ * not used, Main PLLSAI2 should be 0
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
+{
+ CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+#else
/**
* @brief Enable PLLSAI2 output mapped on ADC domain clock
* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
@@ -3766,12 +5245,15 @@
{
CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
}
+#endif /* LTDC */
/**
* @}
*/
#endif /* RCC_PLLSAI2_SUPPORT */
+
+
/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
* @{
*/
@@ -4439,6 +5921,9 @@
uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+#if defined(RCC_CCIPR2_SDMMCSEL)
+uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
+#endif
uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
#if defined(USB_OTG_FS) || defined(USB)
@@ -4450,7 +5935,19 @@
#endif /* SWPMI1 */
#if defined(DFSDM1_Channel0)
uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
+#endif /* RCC_CCIPR2_DFSDM1SEL */
#endif /* DFSDM1_Channel0 */
+#if defined(LTDC)
+uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
+#endif /* LTDC */
+#if defined(DSI)
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+#if defined(OCTOSPI1)
+uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
+#endif /* OCTOSPI1 */
/**
* @}
*/
