mbed-dev - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h@181:57724642e740, 2018-02-16 (annotated)

Committer:: AnnaBridge
Date:: Fri Feb 16 16:09:33 2018 +0000
Revision:: 181:57724642e740
Parent:: 167:e84263d55307

mbed-dev library. Release version 159.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_ll_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief Header file of RCC LL module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
AnnaBridge	167:e84263d55307	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
<>	144:ef7eb2e8f9f7	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	37	#ifndef __STM32L4xx_LL_RCC_H
<>	144:ef7eb2e8f9f7	38	#define __STM32L4xx_LL_RCC_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	45	#include "stm32l4xx.h"
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/** @addtogroup STM32L4xx_LL_Driver
<>	144:ef7eb2e8f9f7	48	* @{
<>	144:ef7eb2e8f9f7	49	*/
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	#if defined(RCC)
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @defgroup RCC_LL RCC
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	59	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
<>	144:ef7eb2e8f9f7	60	* @{
<>	144:ef7eb2e8f9f7	61	*/
<>	144:ef7eb2e8f9f7	62
AnnaBridge	181:57724642e740	63	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	181:57724642e740	64	static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16};
AnnaBridge	181:57724642e740	65	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	/**
<>	144:ef7eb2e8f9f7	68	* @}
<>	144:ef7eb2e8f9f7	69	*/
<>	144:ef7eb2e8f9f7	70
<>	144:ef7eb2e8f9f7	71	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	72	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
<>	144:ef7eb2e8f9f7	73	* @{
<>	144:ef7eb2e8f9f7	74	*/
AnnaBridge	167:e84263d55307	75	/* Defines used to perform offsets*/
AnnaBridge	167:e84263d55307	76	/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
AnnaBridge	167:e84263d55307	77	#define RCC_OFFSET_CCIPR 0U
AnnaBridge	167:e84263d55307	78	#define RCC_OFFSET_CCIPR2 0x14U
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	/**
<>	144:ef7eb2e8f9f7	81	* @}
<>	144:ef7eb2e8f9f7	82	*/
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	85	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	86	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
<>	144:ef7eb2e8f9f7	87	* @{
<>	144:ef7eb2e8f9f7	88	*/
<>	144:ef7eb2e8f9f7	89	/**
<>	144:ef7eb2e8f9f7	90	* @}
<>	144:ef7eb2e8f9f7	91	*/
<>	144:ef7eb2e8f9f7	92	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	181:57724642e740	93
<>	144:ef7eb2e8f9f7	94	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	95	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	96	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	97	* @{
<>	144:ef7eb2e8f9f7	98	*/
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
<>	144:ef7eb2e8f9f7	101	* @{
<>	144:ef7eb2e8f9f7	102	*/
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/**
<>	144:ef7eb2e8f9f7	105	* @brief RCC Clocks Frequency Structure
<>	144:ef7eb2e8f9f7	106	*/
<>	144:ef7eb2e8f9f7	107	typedef struct
<>	144:ef7eb2e8f9f7	108	{
<>	144:ef7eb2e8f9f7	109	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
<>	144:ef7eb2e8f9f7	110	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
<>	144:ef7eb2e8f9f7	111	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
<>	144:ef7eb2e8f9f7	112	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
<>	144:ef7eb2e8f9f7	113	} LL_RCC_ClocksTypeDef;
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	/**
<>	144:ef7eb2e8f9f7	116	* @}
<>	144:ef7eb2e8f9f7	117	*/
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	/**
<>	144:ef7eb2e8f9f7	120	* @}
<>	144:ef7eb2e8f9f7	121	*/
<>	144:ef7eb2e8f9f7	122	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	123
<>	144:ef7eb2e8f9f7	124	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	125	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	126	* @{
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
<>	144:ef7eb2e8f9f7	130	* @brief Defines used to adapt values of different oscillators
AnnaBridge	181:57724642e740	131	* @note These values could be modified in the user environment according to
<>	144:ef7eb2e8f9f7	132	* HW set-up.
<>	144:ef7eb2e8f9f7	133	* @{
<>	144:ef7eb2e8f9f7	134	*/
<>	144:ef7eb2e8f9f7	135	#if !defined (HSE_VALUE)
AnnaBridge	167:e84263d55307	136	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
<>	144:ef7eb2e8f9f7	137	#endif /* HSE_VALUE */
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	#if !defined (HSI_VALUE)
AnnaBridge	167:e84263d55307	140	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
<>	144:ef7eb2e8f9f7	141	#endif /* HSI_VALUE */
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	#if !defined (LSE_VALUE)
AnnaBridge	167:e84263d55307	144	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
<>	144:ef7eb2e8f9f7	145	#endif /* LSE_VALUE */
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	#if !defined (LSI_VALUE)
AnnaBridge	167:e84263d55307	148	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
<>	144:ef7eb2e8f9f7	149	#endif /* LSI_VALUE */
<>	144:ef7eb2e8f9f7	150	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	181:57724642e740	151
<>	144:ef7eb2e8f9f7	152	#if !defined (HSI48_VALUE)
AnnaBridge	167:e84263d55307	153	#define HSI48_VALUE 48000000U /!< Value of the HSI48 oscillator in Hz /
<>	144:ef7eb2e8f9f7	154	#endif /* HSI48_VALUE */
<>	144:ef7eb2e8f9f7	155	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	156	/**
<>	144:ef7eb2e8f9f7	157	* @}
<>	144:ef7eb2e8f9f7	158	*/
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	144:ef7eb2e8f9f7	161	* @brief Flags defines which can be used with LL_RCC_WriteReg function
<>	144:ef7eb2e8f9f7	162	* @{
<>	144:ef7eb2e8f9f7	163	*/
<>	144:ef7eb2e8f9f7	164	#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /!< LSI Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	165	#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /!< LSE Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	166	#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /!< MSI Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	167	#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /!< HSI Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	168	#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /!< HSE Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	169	#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /!< PLL Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	170	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	171	#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	172	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	173	#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /!< PLLSAI1 Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	174	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	175	#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /!< PLLSAI2 Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	176	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	177	#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
<>	144:ef7eb2e8f9f7	178	#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /!< Clock Security System Interrupt Clear /
<>	144:ef7eb2e8f9f7	179	/**
<>	144:ef7eb2e8f9f7	180	* @}
<>	144:ef7eb2e8f9f7	181	*/
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
<>	144:ef7eb2e8f9f7	184	* @brief Flags defines which can be used with LL_RCC_ReadReg function
<>	144:ef7eb2e8f9f7	185	* @{
<>	144:ef7eb2e8f9f7	186	*/
<>	144:ef7eb2e8f9f7	187	#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	188	#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	189	#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	190	#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	191	#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	192	#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	193	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	194	#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	195	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	196	#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	197	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	198	#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	199	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	200	#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	201	#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	202	#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /!< Firewall reset flag /
<>	144:ef7eb2e8f9f7	203	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
<>	144:ef7eb2e8f9f7	204	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
<>	144:ef7eb2e8f9f7	205	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
<>	144:ef7eb2e8f9f7	206	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
<>	144:ef7eb2e8f9f7	207	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
<>	144:ef7eb2e8f9f7	208	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
<>	144:ef7eb2e8f9f7	209	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
<>	144:ef7eb2e8f9f7	210	/**
<>	144:ef7eb2e8f9f7	211	* @}
<>	144:ef7eb2e8f9f7	212	*/
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	/** @defgroup RCC_LL_EC_IT IT Defines
<>	144:ef7eb2e8f9f7	215	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
<>	144:ef7eb2e8f9f7	216	* @{
<>	144:ef7eb2e8f9f7	217	*/
<>	144:ef7eb2e8f9f7	218	#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /!< LSI Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	219	#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /!< LSE Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	220	#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /!< MSI Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	221	#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /!< HSI Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	222	#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /!< HSE Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	223	#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /!< PLL Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	224	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	225	#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	226	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	227	#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /!< PLLSAI1 Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	228	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	229	#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /!< PLLSAI2 Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	230	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	231	#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /!< LSE CSS Interrupt Enable /
<>	144:ef7eb2e8f9f7	232	/**
<>	144:ef7eb2e8f9f7	233	* @}
<>	144:ef7eb2e8f9f7	234	*/
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
<>	144:ef7eb2e8f9f7	237	* @{
<>	144:ef7eb2e8f9f7	238	*/
AnnaBridge	167:e84263d55307	239	#define LL_RCC_LSEDRIVE_LOW 0x00000000U /!< Xtal mode lower driving capability /
<>	144:ef7eb2e8f9f7	240	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< Xtal mode medium low driving capability /
<>	144:ef7eb2e8f9f7	241	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< Xtal mode medium high driving capability /
<>	144:ef7eb2e8f9f7	242	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
<>	144:ef7eb2e8f9f7	243	/**
<>	144:ef7eb2e8f9f7	244	* @}
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
<>	144:ef7eb2e8f9f7	248	* @{
<>	144:ef7eb2e8f9f7	249	*/
<>	144:ef7eb2e8f9f7	250	#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
<>	144:ef7eb2e8f9f7	251	#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
<>	144:ef7eb2e8f9f7	252	#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
<>	144:ef7eb2e8f9f7	253	#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
<>	144:ef7eb2e8f9f7	254	#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
<>	144:ef7eb2e8f9f7	255	#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
<>	144:ef7eb2e8f9f7	256	#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
<>	144:ef7eb2e8f9f7	257	#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
<>	144:ef7eb2e8f9f7	258	#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
<>	144:ef7eb2e8f9f7	259	#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
<>	144:ef7eb2e8f9f7	260	#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
<>	144:ef7eb2e8f9f7	261	#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
<>	144:ef7eb2e8f9f7	262	/**
<>	144:ef7eb2e8f9f7	263	* @}
<>	144:ef7eb2e8f9f7	264	*/
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
<>	144:ef7eb2e8f9f7	267	* @{
<>	144:ef7eb2e8f9f7	268	*/
<>	144:ef7eb2e8f9f7	269	#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /!< MSI = 1 MHz /
<>	144:ef7eb2e8f9f7	270	#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /!< MSI = 2 MHz /
<>	144:ef7eb2e8f9f7	271	#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /!< MSI = 4 MHz /
<>	144:ef7eb2e8f9f7	272	#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /!< MSI = 8 MHz /
<>	144:ef7eb2e8f9f7	273	/**
<>	144:ef7eb2e8f9f7	274	* @}
<>	144:ef7eb2e8f9f7	275	*/
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
<>	144:ef7eb2e8f9f7	278	* @{
<>	144:ef7eb2e8f9f7	279	*/
AnnaBridge	167:e84263d55307	280	#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /!< LSI selection for low speed clock /
<>	144:ef7eb2e8f9f7	281	#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock /
<>	144:ef7eb2e8f9f7	282	/**
<>	144:ef7eb2e8f9f7	283	* @}
<>	144:ef7eb2e8f9f7	284	*/
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
<>	144:ef7eb2e8f9f7	287	* @{
<>	144:ef7eb2e8f9f7	288	*/
<>	144:ef7eb2e8f9f7	289	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
<>	144:ef7eb2e8f9f7	290	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
<>	144:ef7eb2e8f9f7	291	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
<>	144:ef7eb2e8f9f7	292	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
<>	144:ef7eb2e8f9f7	293	/**
<>	144:ef7eb2e8f9f7	294	* @}
<>	144:ef7eb2e8f9f7	295	*/
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
<>	144:ef7eb2e8f9f7	298	* @{
<>	144:ef7eb2e8f9f7	299	*/
<>	144:ef7eb2e8f9f7	300	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
<>	144:ef7eb2e8f9f7	301	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	144:ef7eb2e8f9f7	302	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	144:ef7eb2e8f9f7	303	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	304	/**
<>	144:ef7eb2e8f9f7	305	* @}
<>	144:ef7eb2e8f9f7	306	*/
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
<>	144:ef7eb2e8f9f7	309	* @{
<>	144:ef7eb2e8f9f7	310	*/
<>	144:ef7eb2e8f9f7	311	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	144:ef7eb2e8f9f7	312	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	144:ef7eb2e8f9f7	313	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	144:ef7eb2e8f9f7	314	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	144:ef7eb2e8f9f7	315	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	144:ef7eb2e8f9f7	316	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	144:ef7eb2e8f9f7	317	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	144:ef7eb2e8f9f7	318	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	144:ef7eb2e8f9f7	319	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	144:ef7eb2e8f9f7	320	/**
<>	144:ef7eb2e8f9f7	321	* @}
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
<>	144:ef7eb2e8f9f7	325	* @{
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
<>	144:ef7eb2e8f9f7	328	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
<>	144:ef7eb2e8f9f7	329	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
<>	144:ef7eb2e8f9f7	330	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
<>	144:ef7eb2e8f9f7	331	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	332	/**
<>	144:ef7eb2e8f9f7	333	* @}
<>	144:ef7eb2e8f9f7	334	*/
AnnaBridge	167:e84263d55307	335
<>	144:ef7eb2e8f9f7	336	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
<>	144:ef7eb2e8f9f7	337	* @{
<>	144:ef7eb2e8f9f7	338	*/
<>	144:ef7eb2e8f9f7	339	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
<>	144:ef7eb2e8f9f7	340	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
<>	144:ef7eb2e8f9f7	341	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
<>	144:ef7eb2e8f9f7	342	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
<>	144:ef7eb2e8f9f7	343	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	344	/**
<>	144:ef7eb2e8f9f7	345	* @}
<>	144:ef7eb2e8f9f7	346	*/
AnnaBridge	167:e84263d55307	347
<>	144:ef7eb2e8f9f7	348	/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
<>	144:ef7eb2e8f9f7	349	* @{
<>	144:ef7eb2e8f9f7	350	*/
AnnaBridge	167:e84263d55307	351	#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /!< MSI selection after wake-up from STOP /
<>	144:ef7eb2e8f9f7	352	#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
<>	144:ef7eb2e8f9f7	353	/**
<>	144:ef7eb2e8f9f7	354	* @}
<>	144:ef7eb2e8f9f7	355	*/
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
<>	144:ef7eb2e8f9f7	358	* @{
<>	144:ef7eb2e8f9f7	359	*/
AnnaBridge	167:e84263d55307	360	#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /!< MCO output disabled, no clock on MCO /
<>	144:ef7eb2e8f9f7	361	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
<>	144:ef7eb2e8f9f7	362	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
<>	144:ef7eb2e8f9f7	363	#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI16 selection as MCO1 source /
<>	144:ef7eb2e8f9f7	364	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
<>	144:ef7eb2e8f9f7	365	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< Main PLL selection as MCO1 source /
<>	144:ef7eb2e8f9f7	366	#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
<>	144:ef7eb2e8f9f7	367	#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
<>	144:ef7eb2e8f9f7	368	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	369	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source /
<>	144:ef7eb2e8f9f7	370	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	371	/**
<>	144:ef7eb2e8f9f7	372	* @}
<>	144:ef7eb2e8f9f7	373	*/
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
<>	144:ef7eb2e8f9f7	376	* @{
<>	144:ef7eb2e8f9f7	377	*/
<>	144:ef7eb2e8f9f7	378	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
<>	144:ef7eb2e8f9f7	379	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
<>	144:ef7eb2e8f9f7	380	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
<>	144:ef7eb2e8f9f7	381	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
<>	144:ef7eb2e8f9f7	382	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
<>	144:ef7eb2e8f9f7	383	/**
<>	144:ef7eb2e8f9f7	384	* @}
<>	144:ef7eb2e8f9f7	385	*/
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	388	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
<>	144:ef7eb2e8f9f7	389	* @{
<>	144:ef7eb2e8f9f7	390	*/
AnnaBridge	167:e84263d55307	391	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	167:e84263d55307	392	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
<>	144:ef7eb2e8f9f7	393	/**
<>	144:ef7eb2e8f9f7	394	* @}
<>	144:ef7eb2e8f9f7	395	*/
<>	144:ef7eb2e8f9f7	396	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
<>	144:ef7eb2e8f9f7	399	* @{
<>	144:ef7eb2e8f9f7	400	*/
AnnaBridge	167:e84263d55307	401	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /!< PCLK2 clock used as USART1 clock source /
AnnaBridge	167:e84263d55307	402	#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_0) /!< SYSCLK clock used as USART1 clock source /
AnnaBridge	167:e84263d55307	403	#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_1) /!< HSI clock used as USART1 clock source /
AnnaBridge	167:e84263d55307	404	#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL) /!< LSE clock used as USART1 clock source /
AnnaBridge	167:e84263d55307	405	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /!< PCLK1 clock used as USART2 clock source /
AnnaBridge	167:e84263d55307	406	#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_0) /!< SYSCLK clock used as USART2 clock source /
AnnaBridge	167:e84263d55307	407	#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_1) /!< HSI clock used as USART2 clock source /
AnnaBridge	167:e84263d55307	408	#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL) /!< LSE clock used as USART2 clock source /
<>	144:ef7eb2e8f9f7	409	#if defined(RCC_CCIPR_USART3SEL)
AnnaBridge	167:e84263d55307	410	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /!< PCLK1 clock used as USART3 clock source /
AnnaBridge	167:e84263d55307	411	#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_0) /!< SYSCLK clock used as USART3 clock source /
AnnaBridge	167:e84263d55307	412	#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_1) /!< HSI clock used as USART3 clock source /
AnnaBridge	167:e84263d55307	413	#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL) /!< LSE clock used as USART3 clock source /
<>	144:ef7eb2e8f9f7	414	#endif /* RCC_CCIPR_USART3SEL */
<>	144:ef7eb2e8f9f7	415	/**
<>	144:ef7eb2e8f9f7	416	* @}
<>	144:ef7eb2e8f9f7	417	*/
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
<>	144:ef7eb2e8f9f7	420	/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
<>	144:ef7eb2e8f9f7	421	* @{
<>	144:ef7eb2e8f9f7	422	*/
<>	144:ef7eb2e8f9f7	423	#if defined(RCC_CCIPR_UART4SEL)
AnnaBridge	167:e84263d55307	424	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /!< PCLK1 clock used as UART4 clock source /
AnnaBridge	167:e84263d55307	425	#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_0) /!< SYSCLK clock used as UART4 clock source /
AnnaBridge	167:e84263d55307	426	#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_1) /!< HSI clock used as UART4 clock source /
AnnaBridge	167:e84263d55307	427	#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL) /!< LSE clock used as UART4 clock source /
<>	144:ef7eb2e8f9f7	428	#endif /* RCC_CCIPR_UART4SEL */
<>	144:ef7eb2e8f9f7	429	#if defined(RCC_CCIPR_UART5SEL)
AnnaBridge	167:e84263d55307	430	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /!< PCLK1 clock used as UART5 clock source /
AnnaBridge	167:e84263d55307	431	#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_0) /!< SYSCLK clock used as UART5 clock source /
AnnaBridge	167:e84263d55307	432	#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_1) /!< HSI clock used as UART5 clock source /
AnnaBridge	167:e84263d55307	433	#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL) /!< LSE clock used as UART5 clock source /
<>	144:ef7eb2e8f9f7	434	#endif /* RCC_CCIPR_UART5SEL */
<>	144:ef7eb2e8f9f7	435	/**
<>	144:ef7eb2e8f9f7	436	* @}
<>	144:ef7eb2e8f9f7	437	*/
<>	144:ef7eb2e8f9f7	438	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
<>	144:ef7eb2e8f9f7	441	* @{
<>	144:ef7eb2e8f9f7	442	*/
AnnaBridge	167:e84263d55307	443	#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPUART1 clock source /
<>	144:ef7eb2e8f9f7	444	#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /!< SYSCLK clock used as LPUART1 clock source /
<>	144:ef7eb2e8f9f7	445	#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /!< HSI clock used as LPUART1 clock source /
<>	144:ef7eb2e8f9f7	446	#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /!< LSE clock used as LPUART1 clock source /
<>	144:ef7eb2e8f9f7	447	/**
<>	144:ef7eb2e8f9f7	448	* @}
<>	144:ef7eb2e8f9f7	449	*/
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
<>	144:ef7eb2e8f9f7	452	* @{
<>	144:ef7eb2e8f9f7	453	*/
AnnaBridge	167:e84263d55307	454	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U)) /!< PCLK1 clock used as I2C1 clock source /
AnnaBridge	167:e84263d55307	455	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /!< SYSCLK clock used as I2C1 clock source /
AnnaBridge	167:e84263d55307	456	#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /!< HSI clock used as I2C1 clock source /
<>	144:ef7eb2e8f9f7	457	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	167:e84263d55307	458	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U)) /!< PCLK1 clock used as I2C2 clock source /
AnnaBridge	167:e84263d55307	459	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /!< SYSCLK clock used as I2C2 clock source /
AnnaBridge	167:e84263d55307	460	#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /!< HSI clock used as I2C2 clock source /
<>	144:ef7eb2e8f9f7	461	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	167:e84263d55307	462	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U)) /!< PCLK1 clock used as I2C3 clock source /
AnnaBridge	167:e84263d55307	463	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /!< SYSCLK clock used as I2C3 clock source /
AnnaBridge	167:e84263d55307	464	#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /!< HSI clock used as I2C3 clock source /
AnnaBridge	167:e84263d55307	465	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	167:e84263d55307	466	#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /!< PCLK1 clock used as I2C4 clock source /
AnnaBridge	167:e84263d55307	467	#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< SYSCLK clock used as I2C4 clock source /
AnnaBridge	167:e84263d55307	468	#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< HSI clock used as I2C4 clock source /
AnnaBridge	167:e84263d55307	469	#endif /* RCC_CCIPR2_I2C4SEL */
<>	144:ef7eb2e8f9f7	470	/**
<>	144:ef7eb2e8f9f7	471	* @}
<>	144:ef7eb2e8f9f7	472	*/
<>	144:ef7eb2e8f9f7	473
<>	144:ef7eb2e8f9f7	474	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
<>	144:ef7eb2e8f9f7	475	* @{
<>	144:ef7eb2e8f9f7	476	*/
AnnaBridge	167:e84263d55307	477	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /!< PCLK1 clock used as LPTIM1 clock source /
AnnaBridge	167:e84263d55307	478	#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /!< LSI clock used as LPTIM1 clock source /
AnnaBridge	167:e84263d55307	479	#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /!< HSI clock used as LPTIM1 clock source /
AnnaBridge	167:e84263d55307	480	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL >> 16U)) /!< LSE clock used as LPTIM1 clock source /
AnnaBridge	167:e84263d55307	481	#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /!< PCLK1 clock used as LPTIM2 clock source /
AnnaBridge	167:e84263d55307	482	#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /!< LSI clock used as LPTIM2 clock source /
AnnaBridge	167:e84263d55307	483	#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /!< HSI clock used as LPTIM2 clock source /
AnnaBridge	167:e84263d55307	484	#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL >> 16U)) /!< LSE clock used as LPTIM2 clock source /
<>	144:ef7eb2e8f9f7	485	/**
<>	144:ef7eb2e8f9f7	486	* @}
<>	144:ef7eb2e8f9f7	487	*/
<>	144:ef7eb2e8f9f7	488
<>	144:ef7eb2e8f9f7	489	/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
<>	144:ef7eb2e8f9f7	490	* @{
<>	144:ef7eb2e8f9f7	491	*/
AnnaBridge	181:57724642e740	492	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	181:57724642e740	493	#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /!< PLL clock used as SAI1 clock source /
AnnaBridge	181:57724642e740	494	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_0) /!< PLLSAI1 clock used as SAI1 clock source /
AnnaBridge	181:57724642e740	495	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_1) /!< PLLSAI2 clock used as SAI1 clock source /
AnnaBridge	181:57724642e740	496	#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_2) /!< HSI clock used as SAI1 clock source /
AnnaBridge	181:57724642e740	497	#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) \| (RCC_CCIPR2_SAI1SEL_1 \| RCC_CCIPR2_SAI1SEL_0)) /!< External input clock used as SAI1 clock source /
AnnaBridge	181:57724642e740	498	#else
AnnaBridge	167:e84263d55307	499	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /!< PLLSAI1 clock used as SAI1 clock source /
<>	144:ef7eb2e8f9f7	500	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	167:e84263d55307	501	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI1 clock source /
<>	144:ef7eb2e8f9f7	502	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	503	#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_1 >> 16U)) /!< PLL clock used as SAI1 clock source /
AnnaBridge	167:e84263d55307	504	#define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL >> 16U)) /!< External input clock used as SAI1 clock source /
AnnaBridge	181:57724642e740	505	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	181:57724642e740	506
AnnaBridge	181:57724642e740	507	#if defined(RCC_CCIPR2_SAI2SEL)
AnnaBridge	181:57724642e740	508	#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /!< PLL clock used as SAI2 clock source /
AnnaBridge	181:57724642e740	509	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_0) /!< PLLSAI1 clock used as SAI2 clock source /
AnnaBridge	181:57724642e740	510	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_1) /!< PLLSAI2 clock used as SAI2 clock source /
AnnaBridge	181:57724642e740	511	#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_2) /!< HSI clock used as SAI2 clock source /
AnnaBridge	181:57724642e740	512	#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) \| (RCC_CCIPR2_SAI2SEL_1 \| RCC_CCIPR2_SAI2SEL_0)) /!< External input clock used as SAI2 clock source /
AnnaBridge	181:57724642e740	513	#elif defined(RCC_CCIPR_SAI2SEL)
AnnaBridge	167:e84263d55307	514	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /!< PLLSAI1 clock used as SAI2 clock source /
<>	144:ef7eb2e8f9f7	515	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	167:e84263d55307	516	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI2 clock source /
<>	144:ef7eb2e8f9f7	517	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	518	#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_1 >> 16U)) /!< PLL clock used as SAI2 clock source /
AnnaBridge	167:e84263d55307	519	#define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL >> 16U)) /!< External input clock used as SAI2 clock source /
AnnaBridge	181:57724642e740	520	#endif /* RCC_CCIPR2_SAI2SEL */
AnnaBridge	181:57724642e740	521	/**
<>	144:ef7eb2e8f9f7	522	* @}
<>	144:ef7eb2e8f9f7	523	*/
<>	144:ef7eb2e8f9f7	524
AnnaBridge	181:57724642e740	525	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	181:57724642e740	526	/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
AnnaBridge	181:57724642e740	527	* @{
AnnaBridge	181:57724642e740	528	*/
AnnaBridge	181:57724642e740	529	#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /!< 48MHz clock from internal multiplexor used as SDMMC1 clock source /
AnnaBridge	181:57724642e740	530	#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /!< PLLSAI3CLK clock used as SDMMC1 clock source /
AnnaBridge	181:57724642e740	531	/**
AnnaBridge	181:57724642e740	532	* @}
AnnaBridge	181:57724642e740	533	*/
AnnaBridge	181:57724642e740	534	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	181:57724642e740	535
<>	144:ef7eb2e8f9f7	536	/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
<>	144:ef7eb2e8f9f7	537	* @{
<>	144:ef7eb2e8f9f7	538	*/
AnnaBridge	167:e84263d55307	539	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:e84263d55307	540	#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as SDMMC1 clock source /
AnnaBridge	167:e84263d55307	541	#else
AnnaBridge	167:e84263d55307	542	#define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /!< No clock used as SDMMC1 clock source /
AnnaBridge	167:e84263d55307	543	#endif
AnnaBridge	167:e84263d55307	544	#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as SDMMC1 clock source /
AnnaBridge	167:e84263d55307	545	#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as SDMMC1 clock source /
AnnaBridge	167:e84263d55307	546	#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as SDMMC1 clock source /
<>	144:ef7eb2e8f9f7	547	/**
<>	144:ef7eb2e8f9f7	548	* @}
<>	144:ef7eb2e8f9f7	549	*/
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
<>	144:ef7eb2e8f9f7	552	* @{
<>	144:ef7eb2e8f9f7	553	*/
AnnaBridge	167:e84263d55307	554	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:e84263d55307	555	#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as RNG clock source /
AnnaBridge	167:e84263d55307	556	#else
AnnaBridge	167:e84263d55307	557	#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /!< No clock used as RNG clock source /
AnnaBridge	167:e84263d55307	558	#endif
AnnaBridge	167:e84263d55307	559	#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as RNG clock source /
AnnaBridge	167:e84263d55307	560	#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as RNG clock source /
AnnaBridge	167:e84263d55307	561	#define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as RNG clock source /
<>	144:ef7eb2e8f9f7	562	/**
<>	144:ef7eb2e8f9f7	563	* @}
<>	144:ef7eb2e8f9f7	564	*/
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	144:ef7eb2e8f9f7	567	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
<>	144:ef7eb2e8f9f7	568	* @{
<>	144:ef7eb2e8f9f7	569	*/
AnnaBridge	167:e84263d55307	570	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:e84263d55307	571	#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as USB clock source /
AnnaBridge	167:e84263d55307	572	#else
AnnaBridge	167:e84263d55307	573	#define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /!< No clock used as USB clock source /
AnnaBridge	167:e84263d55307	574	#endif
AnnaBridge	167:e84263d55307	575	#define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as USB clock source /
AnnaBridge	167:e84263d55307	576	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as USB clock source /
AnnaBridge	167:e84263d55307	577	#define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as USB clock source /
<>	144:ef7eb2e8f9f7	578	/**
<>	144:ef7eb2e8f9f7	579	* @}
<>	144:ef7eb2e8f9f7	580	*/
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	#endif /* USB_OTG_FS \|\| USB */
<>	144:ef7eb2e8f9f7	583
<>	144:ef7eb2e8f9f7	584	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
<>	144:ef7eb2e8f9f7	585	* @{
<>	144:ef7eb2e8f9f7	586	*/
AnnaBridge	167:e84263d55307	587	#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /!< No clock used as ADC clock source /
AnnaBridge	167:e84263d55307	588	#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /!< PLLSAI1 clock used as ADC clock source /
AnnaBridge	181:57724642e740	589	#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
AnnaBridge	167:e84263d55307	590	#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /!< PLLSAI2 clock used as ADC clock source /
<>	144:ef7eb2e8f9f7	591	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	592	#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /!< SYSCLK clock used as ADC clock source /
<>	144:ef7eb2e8f9f7	593	/**
<>	144:ef7eb2e8f9f7	594	* @}
<>	144:ef7eb2e8f9f7	595	*/
<>	144:ef7eb2e8f9f7	596
AnnaBridge	167:e84263d55307	597	#if defined(SWPMI1)
AnnaBridge	167:e84263d55307	598	/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection
<>	144:ef7eb2e8f9f7	599	* @{
<>	144:ef7eb2e8f9f7	600	*/
AnnaBridge	167:e84263d55307	601	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 used as SWPMI1 clock source /
AnnaBridge	167:e84263d55307	602	#define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /!< HSI used as SWPMI1 clock source /
<>	144:ef7eb2e8f9f7	603	/**
<>	144:ef7eb2e8f9f7	604	* @}
<>	144:ef7eb2e8f9f7	605	*/
AnnaBridge	167:e84263d55307	606	#endif /* SWPMI1 */
<>	144:ef7eb2e8f9f7	607
<>	144:ef7eb2e8f9f7	608	#if defined(DFSDM1_Channel0)
AnnaBridge	181:57724642e740	609	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	181:57724642e740	610	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection
AnnaBridge	181:57724642e740	611	* @{
AnnaBridge	181:57724642e740	612	*/
AnnaBridge	181:57724642e740	613	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /!< SAI1 clock used as DFSDM1 Audio clock /
AnnaBridge	181:57724642e740	614	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /!< HSI clock used as DFSDM1 Audio clock /
AnnaBridge	181:57724642e740	615	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /!< MSI clock used as DFSDM1 Audio clock /
AnnaBridge	181:57724642e740	616	/**
AnnaBridge	181:57724642e740	617	* @}
AnnaBridge	181:57724642e740	618	*/
AnnaBridge	181:57724642e740	619	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	181:57724642e740	620
AnnaBridge	167:e84263d55307	621	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
<>	144:ef7eb2e8f9f7	622	* @{
<>	144:ef7eb2e8f9f7	623	*/
AnnaBridge	181:57724642e740	624	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	181:57724642e740	625	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 used as DFSDM1 clock source /
AnnaBridge	181:57724642e740	626	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /!< SYSCLK used as DFSDM1 clock source /
AnnaBridge	181:57724642e740	627	#else
AnnaBridge	167:e84263d55307	628	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 used as DFSDM1 clock source /
AnnaBridge	167:e84263d55307	629	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /!< SYSCLK used as DFSDM1 clock source /
AnnaBridge	181:57724642e740	630	#endif /* RCC_CCIPR2_DFSDM1SEL */
<>	144:ef7eb2e8f9f7	631	/**
<>	144:ef7eb2e8f9f7	632	* @}
<>	144:ef7eb2e8f9f7	633	*/
<>	144:ef7eb2e8f9f7	634	#endif /* DFSDM1_Channel0 */
<>	144:ef7eb2e8f9f7	635
AnnaBridge	181:57724642e740	636	#if defined(DSI)
AnnaBridge	181:57724642e740	637	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
AnnaBridge	181:57724642e740	638	* @{
AnnaBridge	181:57724642e740	639	*/
AnnaBridge	181:57724642e740	640	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
AnnaBridge	181:57724642e740	641	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /!< PLL clock used as DSI byte lane clock source /
AnnaBridge	181:57724642e740	642	/**
AnnaBridge	181:57724642e740	643	* @}
AnnaBridge	181:57724642e740	644	*/
AnnaBridge	181:57724642e740	645	#endif /* DSI */
AnnaBridge	181:57724642e740	646
AnnaBridge	181:57724642e740	647	#if defined(LTDC)
AnnaBridge	181:57724642e740	648	/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
AnnaBridge	181:57724642e740	649	* @{
AnnaBridge	181:57724642e740	650	*/
AnnaBridge	181:57724642e740	651	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /!< PLLSAI2DIVR divided by 2 used as LTDC clock source /
AnnaBridge	181:57724642e740	652	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /!< PLLSAI2DIVR divided by 4 used as LTDC clock source /
AnnaBridge	181:57724642e740	653	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /!< PLLSAI2DIVR divided by 8 used as LTDC clock source /
AnnaBridge	181:57724642e740	654	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /!< PLLSAI2DIVR divided by 16 used as LTDC clock source /
AnnaBridge	181:57724642e740	655	/**
AnnaBridge	181:57724642e740	656	* @}
AnnaBridge	181:57724642e740	657	*/
AnnaBridge	181:57724642e740	658	#endif /* LTDC */
AnnaBridge	181:57724642e740	659
AnnaBridge	181:57724642e740	660	#if defined(OCTOSPI1)
AnnaBridge	181:57724642e740	661	/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
AnnaBridge	181:57724642e740	662	* @{
AnnaBridge	181:57724642e740	663	*/
AnnaBridge	181:57724642e740	664	#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /!< SYSCLK used as OctoSPI clock source /
AnnaBridge	181:57724642e740	665	#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /!< MSI used as OctoSPI clock source /
AnnaBridge	181:57724642e740	666	#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /!< PLL used as OctoSPI clock source /
AnnaBridge	181:57724642e740	667	/**
AnnaBridge	181:57724642e740	668	* @}
AnnaBridge	181:57724642e740	669	*/
AnnaBridge	181:57724642e740	670	#endif /* OCTOSPI1 */
AnnaBridge	181:57724642e740	671
<>	144:ef7eb2e8f9f7	672	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
<>	144:ef7eb2e8f9f7	673	* @{
<>	144:ef7eb2e8f9f7	674	*/
<>	144:ef7eb2e8f9f7	675	#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /!< USART1 Clock source selection /
<>	144:ef7eb2e8f9f7	676	#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /!< USART2 Clock source selection /
<>	144:ef7eb2e8f9f7	677	#if defined(RCC_CCIPR_USART3SEL)
<>	144:ef7eb2e8f9f7	678	#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /!< USART3 Clock source selection /
<>	144:ef7eb2e8f9f7	679	#endif /* RCC_CCIPR_USART3SEL */
<>	144:ef7eb2e8f9f7	680	/**
<>	144:ef7eb2e8f9f7	681	* @}
<>	144:ef7eb2e8f9f7	682	*/
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
<>	144:ef7eb2e8f9f7	685	/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
<>	144:ef7eb2e8f9f7	686	* @{
<>	144:ef7eb2e8f9f7	687	*/
<>	144:ef7eb2e8f9f7	688	#if defined(RCC_CCIPR_UART4SEL)
<>	144:ef7eb2e8f9f7	689	#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /!< UART4 Clock source selection /
<>	144:ef7eb2e8f9f7	690	#endif /* RCC_CCIPR_UART4SEL */
<>	144:ef7eb2e8f9f7	691	#if defined(RCC_CCIPR_UART5SEL)
<>	144:ef7eb2e8f9f7	692	#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /!< UART5 Clock source selection /
<>	144:ef7eb2e8f9f7	693	#endif /* RCC_CCIPR_UART5SEL */
<>	144:ef7eb2e8f9f7	694	/**
<>	144:ef7eb2e8f9f7	695	* @}
<>	144:ef7eb2e8f9f7	696	*/
<>	144:ef7eb2e8f9f7	697	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
<>	144:ef7eb2e8f9f7	698
<>	144:ef7eb2e8f9f7	699	/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
<>	144:ef7eb2e8f9f7	700	* @{
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702	#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /!< LPUART1 Clock source selection /
<>	144:ef7eb2e8f9f7	703	/**
<>	144:ef7eb2e8f9f7	704	* @}
<>	144:ef7eb2e8f9f7	705	*/
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
<>	144:ef7eb2e8f9f7	708	* @{
<>	144:ef7eb2e8f9f7	709	*/
AnnaBridge	167:e84263d55307	710	#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /!< I2C1 Clock source selection /
<>	144:ef7eb2e8f9f7	711	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	167:e84263d55307	712	#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /!< I2C2 Clock source selection /
<>	144:ef7eb2e8f9f7	713	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	167:e84263d55307	714	#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /!< I2C3 Clock source selection /
AnnaBridge	167:e84263d55307	715	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	167:e84263d55307	716	#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /!< I2C4 Clock source selection /
AnnaBridge	167:e84263d55307	717	#endif /* RCC_CCIPR2_I2C4SEL */
<>	144:ef7eb2e8f9f7	718	/**
<>	144:ef7eb2e8f9f7	719	* @}
<>	144:ef7eb2e8f9f7	720	*/
<>	144:ef7eb2e8f9f7	721
<>	144:ef7eb2e8f9f7	722	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
<>	144:ef7eb2e8f9f7	723	* @{
<>	144:ef7eb2e8f9f7	724	*/
<>	144:ef7eb2e8f9f7	725	#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /!< LPTIM1 Clock source selection /
<>	144:ef7eb2e8f9f7	726	#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /!< LPTIM2 Clock source selection /
<>	144:ef7eb2e8f9f7	727	/**
<>	144:ef7eb2e8f9f7	728	* @}
<>	144:ef7eb2e8f9f7	729	*/
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
<>	144:ef7eb2e8f9f7	732	* @{
<>	144:ef7eb2e8f9f7	733	*/
AnnaBridge	181:57724642e740	734	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	181:57724642e740	735	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /!< SAI1 Clock source selection /
AnnaBridge	181:57724642e740	736	#else
<>	144:ef7eb2e8f9f7	737	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /!< SAI1 Clock source selection /
AnnaBridge	181:57724642e740	738	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	181:57724642e740	739	#if defined(RCC_CCIPR2_SAI2SEL)
AnnaBridge	181:57724642e740	740	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /!< SAI2 Clock source selection /
AnnaBridge	181:57724642e740	741	#elif defined(RCC_CCIPR_SAI2SEL)
<>	144:ef7eb2e8f9f7	742	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /!< SAI2 Clock source selection /
AnnaBridge	181:57724642e740	743	#endif /* RCC_CCIPR2_SAI2SEL */
<>	144:ef7eb2e8f9f7	744	/**
<>	144:ef7eb2e8f9f7	745	* @}
<>	144:ef7eb2e8f9f7	746	*/
<>	144:ef7eb2e8f9f7	747
AnnaBridge	181:57724642e740	748	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	181:57724642e740	749	/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
AnnaBridge	181:57724642e740	750	* @{
AnnaBridge	181:57724642e740	751	*/
AnnaBridge	181:57724642e740	752	#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /!< SDMMC1 Kernel Clock source selection /
AnnaBridge	181:57724642e740	753	/**
AnnaBridge	181:57724642e740	754	* @}
AnnaBridge	181:57724642e740	755	*/
AnnaBridge	181:57724642e740	756	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	181:57724642e740	757
<>	144:ef7eb2e8f9f7	758	/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
<>	144:ef7eb2e8f9f7	759	* @{
<>	144:ef7eb2e8f9f7	760	*/
<>	144:ef7eb2e8f9f7	761	#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /!< SDMMC1 Clock source selection /
<>	144:ef7eb2e8f9f7	762	/**
<>	144:ef7eb2e8f9f7	763	* @}
<>	144:ef7eb2e8f9f7	764	*/
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
<>	144:ef7eb2e8f9f7	767	* @{
<>	144:ef7eb2e8f9f7	768	*/
<>	144:ef7eb2e8f9f7	769	#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /!< RNG Clock source selection /
<>	144:ef7eb2e8f9f7	770	/**
<>	144:ef7eb2e8f9f7	771	* @}
<>	144:ef7eb2e8f9f7	772	*/
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	144:ef7eb2e8f9f7	775	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
<>	144:ef7eb2e8f9f7	776	* @{
<>	144:ef7eb2e8f9f7	777	*/
<>	144:ef7eb2e8f9f7	778	#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /!< USB Clock source selection /
<>	144:ef7eb2e8f9f7	779	/**
<>	144:ef7eb2e8f9f7	780	* @}
<>	144:ef7eb2e8f9f7	781	*/
<>	144:ef7eb2e8f9f7	782	#endif /* USB_OTG_FS \|\| USB */
<>	144:ef7eb2e8f9f7	783
<>	144:ef7eb2e8f9f7	784	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
<>	144:ef7eb2e8f9f7	785	* @{
<>	144:ef7eb2e8f9f7	786	*/
<>	144:ef7eb2e8f9f7	787	#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /!< ADC Clock source selection /
<>	144:ef7eb2e8f9f7	788	/**
<>	144:ef7eb2e8f9f7	789	* @}
<>	144:ef7eb2e8f9f7	790	*/
<>	144:ef7eb2e8f9f7	791
AnnaBridge	167:e84263d55307	792	#if defined(SWPMI1)
AnnaBridge	167:e84263d55307	793	/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source
<>	144:ef7eb2e8f9f7	794	* @{
<>	144:ef7eb2e8f9f7	795	*/
<>	144:ef7eb2e8f9f7	796	#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /!< SWPMI1 Clock source selection /
<>	144:ef7eb2e8f9f7	797	/**
<>	144:ef7eb2e8f9f7	798	* @}
<>	144:ef7eb2e8f9f7	799	*/
AnnaBridge	167:e84263d55307	800	#endif /* SWPMI1 */
<>	144:ef7eb2e8f9f7	801
<>	144:ef7eb2e8f9f7	802	#if defined(DFSDM1_Channel0)
AnnaBridge	181:57724642e740	803	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	181:57724642e740	804	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source
AnnaBridge	181:57724642e740	805	* @{
AnnaBridge	181:57724642e740	806	*/
AnnaBridge	181:57724642e740	807	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
AnnaBridge	181:57724642e740	808	/**
AnnaBridge	181:57724642e740	809	* @}
AnnaBridge	181:57724642e740	810	*/
AnnaBridge	181:57724642e740	811
AnnaBridge	181:57724642e740	812	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	167:e84263d55307	813	/** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
<>	144:ef7eb2e8f9f7	814	* @{
<>	144:ef7eb2e8f9f7	815	*/
AnnaBridge	181:57724642e740	816	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	181:57724642e740	817	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /!< DFSDM1 Clock source selection /
AnnaBridge	181:57724642e740	818	#else
<>	144:ef7eb2e8f9f7	819	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /!< DFSDM1 Clock source selection /
AnnaBridge	181:57724642e740	820	#endif /* RCC_CCIPR2_DFSDM1SEL */
<>	144:ef7eb2e8f9f7	821	/**
<>	144:ef7eb2e8f9f7	822	* @}
<>	144:ef7eb2e8f9f7	823	*/
<>	144:ef7eb2e8f9f7	824	#endif /* DFSDM1_Channel0 */
<>	144:ef7eb2e8f9f7	825
AnnaBridge	181:57724642e740	826	#if defined(DSI)
AnnaBridge	181:57724642e740	827	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
AnnaBridge	181:57724642e740	828	* @{
AnnaBridge	181:57724642e740	829	*/
AnnaBridge	181:57724642e740	830	#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /!< DSI Clock source selection /
AnnaBridge	181:57724642e740	831	/**
AnnaBridge	181:57724642e740	832	* @}
AnnaBridge	181:57724642e740	833	*/
AnnaBridge	181:57724642e740	834	#endif /* DSI */
AnnaBridge	181:57724642e740	835
AnnaBridge	181:57724642e740	836	#if defined(LTDC)
AnnaBridge	181:57724642e740	837	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
AnnaBridge	181:57724642e740	838	* @{
AnnaBridge	181:57724642e740	839	*/
AnnaBridge	181:57724642e740	840	#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /!< LTDC Clock source selection /
AnnaBridge	181:57724642e740	841	/**
AnnaBridge	181:57724642e740	842	* @}
AnnaBridge	181:57724642e740	843	*/
AnnaBridge	181:57724642e740	844	#endif /* LTDC */
AnnaBridge	181:57724642e740	845
AnnaBridge	181:57724642e740	846	#if defined(OCTOSPI1)
AnnaBridge	181:57724642e740	847	/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
AnnaBridge	181:57724642e740	848	* @{
AnnaBridge	181:57724642e740	849	*/
AnnaBridge	181:57724642e740	850	#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /!< OctoSPI Clock source selection /
AnnaBridge	181:57724642e740	851	/**
AnnaBridge	181:57724642e740	852	* @}
AnnaBridge	181:57724642e740	853	*/
AnnaBridge	181:57724642e740	854	#endif /* OCTOSPI1 */
AnnaBridge	181:57724642e740	855
AnnaBridge	181:57724642e740	856
<>	144:ef7eb2e8f9f7	857	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
<>	144:ef7eb2e8f9f7	858	* @{
<>	144:ef7eb2e8f9f7	859	*/
AnnaBridge	167:e84263d55307	860	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
<>	144:ef7eb2e8f9f7	861	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	862	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	863	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
<>	144:ef7eb2e8f9f7	864	/**
<>	144:ef7eb2e8f9f7	865	* @}
<>	144:ef7eb2e8f9f7	866	*/
<>	144:ef7eb2e8f9f7	867
AnnaBridge	181:57724642e740	868
<>	144:ef7eb2e8f9f7	869	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
<>	144:ef7eb2e8f9f7	870	* @{
<>	144:ef7eb2e8f9f7	871	*/
AnnaBridge	167:e84263d55307	872	#define LL_RCC_PLLSOURCE_NONE 0x00000000U /!< No clock /
<>	144:ef7eb2e8f9f7	873	#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	874	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	875	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	876	/**
<>	144:ef7eb2e8f9f7	877	* @}
<>	144:ef7eb2e8f9f7	878	*/
<>	144:ef7eb2e8f9f7	879
AnnaBridge	181:57724642e740	880	/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
<>	144:ef7eb2e8f9f7	881	* @{
<>	144:ef7eb2e8f9f7	882	*/
AnnaBridge	181:57724642e740	883	#define LL_RCC_PLLM_DIV_1 0x00000000U /!< Main PLL division factor for PLLM input by 1 /
AnnaBridge	181:57724642e740	884	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 2 /
AnnaBridge	181:57724642e740	885	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 3 /
AnnaBridge	181:57724642e740	886	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 4 /
AnnaBridge	181:57724642e740	887	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /!< Main PLL division factor for PLLM input by 5 /
AnnaBridge	181:57724642e740	888	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 6 /
AnnaBridge	181:57724642e740	889	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 7 /
AnnaBridge	181:57724642e740	890	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 8 /
AnnaBridge	181:57724642e740	891	#if defined(RCC_PLLM_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	892	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /!< Main PLL division factor for PLLM input by 9 /
AnnaBridge	181:57724642e740	893	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 10 /
AnnaBridge	181:57724642e740	894	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 11 /
AnnaBridge	181:57724642e740	895	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 12 /
AnnaBridge	181:57724642e740	896	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< Main PLL division factor for PLLM input by 13 /
AnnaBridge	181:57724642e740	897	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 14 /
AnnaBridge	181:57724642e740	898	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 15 /
AnnaBridge	181:57724642e740	899	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 16 /
AnnaBridge	181:57724642e740	900	#endif /* RCC_PLLM_DIV_1_16_SUPPORT */
<>	144:ef7eb2e8f9f7	901	/**
<>	144:ef7eb2e8f9f7	902	* @}
<>	144:ef7eb2e8f9f7	903	*/
<>	144:ef7eb2e8f9f7	904
<>	144:ef7eb2e8f9f7	905	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
<>	144:ef7eb2e8f9f7	906	* @{
<>	144:ef7eb2e8f9f7	907	*/
AnnaBridge	167:e84263d55307	908	#define LL_RCC_PLLR_DIV_2 0x00000000U /!< Main PLL division factor for PLLCLK (system clock) by 2 /
<>	144:ef7eb2e8f9f7	909	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
<>	144:ef7eb2e8f9f7	910	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
<>	144:ef7eb2e8f9f7	911	#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 8 /
<>	144:ef7eb2e8f9f7	912	/**
<>	144:ef7eb2e8f9f7	913	* @}
<>	144:ef7eb2e8f9f7	914	*/
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
<>	144:ef7eb2e8f9f7	917	* @{
<>	144:ef7eb2e8f9f7	918	*/
<>	144:ef7eb2e8f9f7	919	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	920	#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 2 /
AnnaBridge	181:57724642e740	921	#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 3 /
<>	144:ef7eb2e8f9f7	922	#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 4 /
AnnaBridge	181:57724642e740	923	#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 5 /
AnnaBridge	181:57724642e740	924	#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 6 /
AnnaBridge	181:57724642e740	925	#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 7 /
<>	144:ef7eb2e8f9f7	926	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 8 /
AnnaBridge	181:57724642e740	927	#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 9 /
AnnaBridge	181:57724642e740	928	#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 10 /
AnnaBridge	181:57724642e740	929	#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 11 /
AnnaBridge	181:57724642e740	930	#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 12 /
AnnaBridge	181:57724642e740	931	#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 13 /
AnnaBridge	181:57724642e740	932	#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 14 /
AnnaBridge	181:57724642e740	933	#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 15 /
<>	144:ef7eb2e8f9f7	934	#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 16 /
AnnaBridge	181:57724642e740	935	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 17 /
AnnaBridge	181:57724642e740	936	#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 18 /
AnnaBridge	181:57724642e740	937	#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 19 /
AnnaBridge	181:57724642e740	938	#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 20 /
AnnaBridge	181:57724642e740	939	#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 21 /
AnnaBridge	181:57724642e740	940	#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 22 /
AnnaBridge	181:57724642e740	941	#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 23 /
AnnaBridge	181:57724642e740	942	#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 24 /
AnnaBridge	181:57724642e740	943	#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 25 /
AnnaBridge	181:57724642e740	944	#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 26 /
AnnaBridge	181:57724642e740	945	#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 27 /
AnnaBridge	181:57724642e740	946	#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 28 /
AnnaBridge	181:57724642e740	947	#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 29 /
AnnaBridge	181:57724642e740	948	#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 30 /
AnnaBridge	181:57724642e740	949	#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 31 /
<>	144:ef7eb2e8f9f7	950	#else
AnnaBridge	167:e84263d55307	951	#define LL_RCC_PLLP_DIV_7 0x00000000U /!< Main PLL division factor for PLLP output by 7 /
<>	144:ef7eb2e8f9f7	952	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /!< Main PLL division factor for PLLP output by 17 /
<>	144:ef7eb2e8f9f7	953	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	954	/**
<>	144:ef7eb2e8f9f7	955	* @}
<>	144:ef7eb2e8f9f7	956	*/
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
<>	144:ef7eb2e8f9f7	959	* @{
<>	144:ef7eb2e8f9f7	960	*/
AnnaBridge	167:e84263d55307	961	#define LL_RCC_PLLQ_DIV_2 0x00000000U /!< Main PLL division factor for PLLQ output by 2 /
<>	144:ef7eb2e8f9f7	962	#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 4 /
<>	144:ef7eb2e8f9f7	963	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
<>	144:ef7eb2e8f9f7	964	#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /!< Main PLL division factor for PLLQ output by 8 /
<>	144:ef7eb2e8f9f7	965	/**
<>	144:ef7eb2e8f9f7	966	* @}
<>	144:ef7eb2e8f9f7	967	*/
<>	144:ef7eb2e8f9f7	968
AnnaBridge	181:57724642e740	969	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	970	/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
AnnaBridge	181:57724642e740	971	* @{
AnnaBridge	181:57724642e740	972	*/
AnnaBridge	181:57724642e740	973	#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /!< PLLSAI1 division factor for PLLSAI1M input by 1 /
AnnaBridge	181:57724642e740	974	#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 2 /
AnnaBridge	181:57724642e740	975	#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 3 /
AnnaBridge	181:57724642e740	976	#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 4 /
AnnaBridge	181:57724642e740	977	#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /!< PLLSAI1 division factor for PLLSAI1M input by 5 /
AnnaBridge	181:57724642e740	978	#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 6 /
AnnaBridge	181:57724642e740	979	#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 7 /
AnnaBridge	181:57724642e740	980	#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 8 /
AnnaBridge	181:57724642e740	981	#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /!< PLLSAI1 division factor for PLLSAI1M input by 9 /
AnnaBridge	181:57724642e740	982	#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 10 /
AnnaBridge	181:57724642e740	983	#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 11 /
AnnaBridge	181:57724642e740	984	#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 12 /
AnnaBridge	181:57724642e740	985	#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2) /!< PLLSAI1 division factor for PLLSAI1M input by 13 /
AnnaBridge	181:57724642e740	986	#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 14 /
AnnaBridge	181:57724642e740	987	#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 15 /
AnnaBridge	181:57724642e740	988	#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 16 /
AnnaBridge	181:57724642e740	989	/**
AnnaBridge	181:57724642e740	990	* @}
AnnaBridge	181:57724642e740	991	*/
AnnaBridge	181:57724642e740	992	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	181:57724642e740	993
<>	144:ef7eb2e8f9f7	994	/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
<>	144:ef7eb2e8f9f7	995	* @{
<>	144:ef7eb2e8f9f7	996	*/
AnnaBridge	167:e84263d55307	997	#define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1Q output by 2 /
<>	144:ef7eb2e8f9f7	998	#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /!< PLLSAI1 division factor for PLLSAI1Q output by 4 /
<>	144:ef7eb2e8f9f7	999	#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /!< PLLSAI1 division factor for PLLSAI1Q output by 6 /
<>	144:ef7eb2e8f9f7	1000	#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /!< PLLSAI1 division factor for PLLSAI1Q output by 8 /
<>	144:ef7eb2e8f9f7	1001	/**
<>	144:ef7eb2e8f9f7	1002	* @}
<>	144:ef7eb2e8f9f7	1003	*/
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
<>	144:ef7eb2e8f9f7	1006	* @{
<>	144:ef7eb2e8f9f7	1007	*/
<>	144:ef7eb2e8f9f7	1008	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	1009	#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 2 /
AnnaBridge	181:57724642e740	1010	#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 3 /
<>	144:ef7eb2e8f9f7	1011	#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 4 /
AnnaBridge	181:57724642e740	1012	#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 5 /
AnnaBridge	181:57724642e740	1013	#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 6 /
AnnaBridge	181:57724642e740	1014	#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
<>	144:ef7eb2e8f9f7	1015	#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 8 /
AnnaBridge	181:57724642e740	1016	#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 9 /
AnnaBridge	181:57724642e740	1017	#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 10 /
AnnaBridge	181:57724642e740	1018	#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 1 /
AnnaBridge	181:57724642e740	1019	#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 12 /
AnnaBridge	181:57724642e740	1020	#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 13 /
AnnaBridge	181:57724642e740	1021	#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 14 /
AnnaBridge	181:57724642e740	1022	#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 15 /
<>	144:ef7eb2e8f9f7	1023	#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 16 /
AnnaBridge	181:57724642e740	1024	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
AnnaBridge	181:57724642e740	1025	#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 18 /
AnnaBridge	181:57724642e740	1026	#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 19 /
AnnaBridge	181:57724642e740	1027	#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 20 /
AnnaBridge	181:57724642e740	1028	#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division fctor for PLLSAI1P output by 21 /
AnnaBridge	181:57724642e740	1029	#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 22 /
AnnaBridge	181:57724642e740	1030	#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 23 /
AnnaBridge	181:57724642e740	1031	#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 24 /
AnnaBridge	181:57724642e740	1032	#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 25 /
AnnaBridge	181:57724642e740	1033	#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 26 /
AnnaBridge	181:57724642e740	1034	#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 27 /
AnnaBridge	181:57724642e740	1035	#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 28 /
AnnaBridge	181:57724642e740	1036	#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 29 /
AnnaBridge	181:57724642e740	1037	#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 30 /
AnnaBridge	181:57724642e740	1038	#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
<>	144:ef7eb2e8f9f7	1039	#else
AnnaBridge	167:e84263d55307	1040	#define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
<>	144:ef7eb2e8f9f7	1041	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
<>	144:ef7eb2e8f9f7	1042	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	1043	/**
<>	144:ef7eb2e8f9f7	1044	* @}
<>	144:ef7eb2e8f9f7	1045	*/
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
<>	144:ef7eb2e8f9f7	1048	* @{
<>	144:ef7eb2e8f9f7	1049	*/
AnnaBridge	167:e84263d55307	1050	#define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1R output by 2 /
<>	144:ef7eb2e8f9f7	1051	#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /!< PLLSAI1 division factor for PLLSAI1R output by 4 /
<>	144:ef7eb2e8f9f7	1052	#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /!< PLLSAI1 division factor for PLLSAI1R output by 6 /
<>	144:ef7eb2e8f9f7	1053	#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /!< PLLSAI1 division factor for PLLSAI1R output by 8 /
<>	144:ef7eb2e8f9f7	1054	/**
<>	144:ef7eb2e8f9f7	1055	* @}
<>	144:ef7eb2e8f9f7	1056	*/
<>	144:ef7eb2e8f9f7	1057
<>	144:ef7eb2e8f9f7	1058	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	181:57724642e740	1059	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	1060	/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M)
AnnaBridge	181:57724642e740	1061	* @{
AnnaBridge	181:57724642e740	1062	*/
AnnaBridge	181:57724642e740	1063	#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /!< PLLSAI2 division factor for PLLSAI2M input by 1 /
AnnaBridge	181:57724642e740	1064	#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 2 /
AnnaBridge	181:57724642e740	1065	#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 3 /
AnnaBridge	181:57724642e740	1066	#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 4 /
AnnaBridge	181:57724642e740	1067	#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /!< PLLSAI2 division factor for PLLSAI2M input by 5 /
AnnaBridge	181:57724642e740	1068	#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 6 /
AnnaBridge	181:57724642e740	1069	#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 7 /
AnnaBridge	181:57724642e740	1070	#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 8 /
AnnaBridge	181:57724642e740	1071	#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /!< PLLSAI2 division factor for PLLSAI2M input by 9 /
AnnaBridge	181:57724642e740	1072	#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 10 /
AnnaBridge	181:57724642e740	1073	#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 11 /
AnnaBridge	181:57724642e740	1074	#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 12 /
AnnaBridge	181:57724642e740	1075	#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2) /!< PLLSAI2 division factor for PLLSAI2M input by 13 /
AnnaBridge	181:57724642e740	1076	#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 14 /
AnnaBridge	181:57724642e740	1077	#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 15 /
AnnaBridge	181:57724642e740	1078	#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 16 /
AnnaBridge	181:57724642e740	1079	/**
AnnaBridge	181:57724642e740	1080	* @}
AnnaBridge	181:57724642e740	1081	*/
AnnaBridge	181:57724642e740	1082	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	181:57724642e740	1083
AnnaBridge	181:57724642e740	1084	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	181:57724642e740	1085	/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q)
AnnaBridge	181:57724642e740	1086	* @{
AnnaBridge	181:57724642e740	1087	*/
AnnaBridge	181:57724642e740	1088	#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2Q output by 2 /
AnnaBridge	181:57724642e740	1089	#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /!< PLLSAI2 division factor for PLLSAI2Q output by 4 /
AnnaBridge	181:57724642e740	1090	#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /!< PLLSAI2 division factor for PLLSAI2Q output by 6 /
AnnaBridge	181:57724642e740	1091	#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /!< PLLSAI2 division factor for PLLSAI2Q output by 8 /
AnnaBridge	181:57724642e740	1092	/**
AnnaBridge	181:57724642e740	1093	* @}
AnnaBridge	181:57724642e740	1094	*/
AnnaBridge	181:57724642e740	1095	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	181:57724642e740	1096
<>	144:ef7eb2e8f9f7	1097	/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
<>	144:ef7eb2e8f9f7	1098	* @{
<>	144:ef7eb2e8f9f7	1099	*/
AnnaBridge	181:57724642e740	1100	#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	181:57724642e740	1101	#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 2 /
AnnaBridge	181:57724642e740	1102	#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 3 /
AnnaBridge	181:57724642e740	1103	#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 4 /
AnnaBridge	181:57724642e740	1104	#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 5 /
AnnaBridge	181:57724642e740	1105	#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 6 /
AnnaBridge	181:57724642e740	1106	#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
AnnaBridge	181:57724642e740	1107	#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /!< PLLSAI2 division factor for PLLSAI2P output by 8 /
AnnaBridge	181:57724642e740	1108	#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 9 /
AnnaBridge	181:57724642e740	1109	#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 10 /
AnnaBridge	181:57724642e740	1110	#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 1 /
AnnaBridge	181:57724642e740	1111	#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 12 /
AnnaBridge	181:57724642e740	1112	#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 13 /
AnnaBridge	181:57724642e740	1113	#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 14 /
AnnaBridge	181:57724642e740	1114	#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 15 /
AnnaBridge	181:57724642e740	1115	#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /!< PLLSAI2 division factor for PLLSAI2P output by 16 /
AnnaBridge	181:57724642e740	1116	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
AnnaBridge	181:57724642e740	1117	#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 18 /
AnnaBridge	181:57724642e740	1118	#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 19 /
AnnaBridge	181:57724642e740	1119	#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 20 /
AnnaBridge	181:57724642e740	1120	#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division fctor for PLLSAI2P output by 21 /
AnnaBridge	181:57724642e740	1121	#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 22 /
AnnaBridge	181:57724642e740	1122	#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 23 /
AnnaBridge	181:57724642e740	1123	#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /!< PLLSAI2 division factor for PLLSAI2P output by 24 /
AnnaBridge	181:57724642e740	1124	#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 25 /
AnnaBridge	181:57724642e740	1125	#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 26 /
AnnaBridge	181:57724642e740	1126	#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 27 /
AnnaBridge	181:57724642e740	1127	#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 28 /
AnnaBridge	181:57724642e740	1128	#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 29 /
AnnaBridge	181:57724642e740	1129	#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 30 /
AnnaBridge	181:57724642e740	1130	#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
AnnaBridge	181:57724642e740	1131	#else
AnnaBridge	167:e84263d55307	1132	#define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
<>	144:ef7eb2e8f9f7	1133	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
AnnaBridge	181:57724642e740	1134	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	1135	/**
<>	144:ef7eb2e8f9f7	1136	* @}
<>	144:ef7eb2e8f9f7	1137	*/
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
<>	144:ef7eb2e8f9f7	1140	* @{
<>	144:ef7eb2e8f9f7	1141	*/
AnnaBridge	167:e84263d55307	1142	#define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2R output by 2 /
<>	144:ef7eb2e8f9f7	1143	#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /!< PLLSAI2 division factor for PLLSAI2R output by 4 /
<>	144:ef7eb2e8f9f7	1144	#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /!< PLLSAI2 division factor for PLLSAI2R output by 6 /
<>	144:ef7eb2e8f9f7	1145	#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /!< PLLSAI2 division factor for PLLSAI2R output by 8 /
<>	144:ef7eb2e8f9f7	1146	/**
<>	144:ef7eb2e8f9f7	1147	* @}
<>	144:ef7eb2e8f9f7	1148	*/
AnnaBridge	181:57724642e740	1149
AnnaBridge	181:57724642e740	1150	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	181:57724642e740	1151	/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR)
AnnaBridge	181:57724642e740	1152	* @{
AnnaBridge	181:57724642e740	1153	*/
AnnaBridge	181:57724642e740	1154	#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 /
AnnaBridge	181:57724642e740	1155	#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 /
AnnaBridge	181:57724642e740	1156	#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 /
AnnaBridge	181:57724642e740	1157	#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 \| RCC_CCIPR2_PLLSAI2DIVR_0) /!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 /
AnnaBridge	181:57724642e740	1158	/**
AnnaBridge	181:57724642e740	1159	* @}
AnnaBridge	181:57724642e740	1160	*/
AnnaBridge	181:57724642e740	1161	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
<>	144:ef7eb2e8f9f7	1162	#endif /* RCC_PLLSAI2_SUPPORT */
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
<>	144:ef7eb2e8f9f7	1165	* @{
<>	144:ef7eb2e8f9f7	1166	*/
AnnaBridge	167:e84263d55307	1167	#define LL_RCC_MSIRANGESEL_STANDBY 0U /!< MSI Range is provided by MSISRANGE /
AnnaBridge	167:e84263d55307	1168	#define LL_RCC_MSIRANGESEL_RUN 1U /!< MSI Range is provided by MSIRANGE /
<>	144:ef7eb2e8f9f7	1169	/**
<>	144:ef7eb2e8f9f7	1170	* @}
<>	144:ef7eb2e8f9f7	1171	*/
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	/** Legacy definitions for compatibility purpose
<>	144:ef7eb2e8f9f7	1174	@cond 0
<>	144:ef7eb2e8f9f7	1175	*/
<>	144:ef7eb2e8f9f7	1176	#if defined(DFSDM1_Channel0)
AnnaBridge	167:e84263d55307	1177	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	167:e84263d55307	1178	#define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
<>	144:ef7eb2e8f9f7	1179	#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	1180	#define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
<>	144:ef7eb2e8f9f7	1181	#endif /* DFSDM1_Channel0 */
AnnaBridge	167:e84263d55307	1182	#if defined(SWPMI1)
AnnaBridge	167:e84263d55307	1183	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	167:e84263d55307	1184	#endif /* SWPMI1 */
<>	144:ef7eb2e8f9f7	1185	/**
<>	144:ef7eb2e8f9f7	1186	@endcond
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188
<>	144:ef7eb2e8f9f7	1189	/**
<>	144:ef7eb2e8f9f7	1190	* @}
<>	144:ef7eb2e8f9f7	1191	*/
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1194	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
<>	144:ef7eb2e8f9f7	1195	* @{
<>	144:ef7eb2e8f9f7	1196	*/
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
<>	144:ef7eb2e8f9f7	1199	* @{
<>	144:ef7eb2e8f9f7	1200	*/
<>	144:ef7eb2e8f9f7	1201
<>	144:ef7eb2e8f9f7	1202	/**
<>	144:ef7eb2e8f9f7	1203	* @brief Write a value in RCC register
<>	144:ef7eb2e8f9f7	1204	* @param __REG__ Register to be written
<>	144:ef7eb2e8f9f7	1205	* @param __VALUE__ Value to be written in the register
<>	144:ef7eb2e8f9f7	1206	* @retval None
<>	144:ef7eb2e8f9f7	1207	*/
<>	144:ef7eb2e8f9f7	1208	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
<>	144:ef7eb2e8f9f7	1209
<>	144:ef7eb2e8f9f7	1210	/**
<>	144:ef7eb2e8f9f7	1211	* @brief Read a value in RCC register
<>	144:ef7eb2e8f9f7	1212	* @param __REG__ Register to be read
<>	144:ef7eb2e8f9f7	1213	* @retval Register value
<>	144:ef7eb2e8f9f7	1214	*/
<>	144:ef7eb2e8f9f7	1215	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
<>	144:ef7eb2e8f9f7	1216	/**
<>	144:ef7eb2e8f9f7	1217	* @}
<>	144:ef7eb2e8f9f7	1218	*/
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
<>	144:ef7eb2e8f9f7	1221	* @{
<>	144:ef7eb2e8f9f7	1222	*/
<>	144:ef7eb2e8f9f7	1223
<>	144:ef7eb2e8f9f7	1224	/**
<>	144:ef7eb2e8f9f7	1225	* @brief Helper macro to calculate the PLLCLK frequency on system domain
<>	144:ef7eb2e8f9f7	1226	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1227	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
<>	144:ef7eb2e8f9f7	1228	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1229	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1230	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1231	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1232	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1233	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1234	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1235	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1236	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1237	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	1238	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	181:57724642e740	1239	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	181:57724642e740	1240	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	181:57724642e740	1241	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	181:57724642e740	1242	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	181:57724642e740	1243	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	181:57724642e740	1244	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	181:57724642e740	1245	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	181:57724642e740	1246	*
AnnaBridge	181:57724642e740	1247	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	1248	* @param __PLLN__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1249	* @param __PLLR__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1250	* @arg @ref LL_RCC_PLLR_DIV_2
<>	144:ef7eb2e8f9f7	1251	* @arg @ref LL_RCC_PLLR_DIV_4
<>	144:ef7eb2e8f9f7	1252	* @arg @ref LL_RCC_PLLR_DIV_6
<>	144:ef7eb2e8f9f7	1253	* @arg @ref LL_RCC_PLLR_DIV_8
<>	144:ef7eb2e8f9f7	1254	* @retval PLL clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1255	*/
AnnaBridge	167:e84263d55307	1256	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	167:e84263d55307	1257	((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
<>	144:ef7eb2e8f9f7	1258
<>	144:ef7eb2e8f9f7	1259	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	1260	/**
<>	144:ef7eb2e8f9f7	1261	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
<>	144:ef7eb2e8f9f7	1262	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1263	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
<>	144:ef7eb2e8f9f7	1264	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1265	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1266	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1267	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1268	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1269	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1270	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1271	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1272	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1273	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	1274	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	181:57724642e740	1275	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	181:57724642e740	1276	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	181:57724642e740	1277	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	181:57724642e740	1278	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	181:57724642e740	1279	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	181:57724642e740	1280	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	181:57724642e740	1281	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	181:57724642e740	1282	*
AnnaBridge	181:57724642e740	1283	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	1284	* @param __PLLN__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1285	* @param __PLLP__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1286	* @arg @ref LL_RCC_PLLP_DIV_2
<>	144:ef7eb2e8f9f7	1287	* @arg @ref LL_RCC_PLLP_DIV_3
<>	144:ef7eb2e8f9f7	1288	* @arg @ref LL_RCC_PLLP_DIV_4
<>	144:ef7eb2e8f9f7	1289	* @arg @ref LL_RCC_PLLP_DIV_5
<>	144:ef7eb2e8f9f7	1290	* @arg @ref LL_RCC_PLLP_DIV_6
<>	144:ef7eb2e8f9f7	1291	* @arg @ref LL_RCC_PLLP_DIV_7
<>	144:ef7eb2e8f9f7	1292	* @arg @ref LL_RCC_PLLP_DIV_8
<>	144:ef7eb2e8f9f7	1293	* @arg @ref LL_RCC_PLLP_DIV_9
<>	144:ef7eb2e8f9f7	1294	* @arg @ref LL_RCC_PLLP_DIV_10
<>	144:ef7eb2e8f9f7	1295	* @arg @ref LL_RCC_PLLP_DIV_11
<>	144:ef7eb2e8f9f7	1296	* @arg @ref LL_RCC_PLLP_DIV_12
<>	144:ef7eb2e8f9f7	1297	* @arg @ref LL_RCC_PLLP_DIV_13
<>	144:ef7eb2e8f9f7	1298	* @arg @ref LL_RCC_PLLP_DIV_14
<>	144:ef7eb2e8f9f7	1299	* @arg @ref LL_RCC_PLLP_DIV_15
<>	144:ef7eb2e8f9f7	1300	* @arg @ref LL_RCC_PLLP_DIV_16
<>	144:ef7eb2e8f9f7	1301	* @arg @ref LL_RCC_PLLP_DIV_17
<>	144:ef7eb2e8f9f7	1302	* @arg @ref LL_RCC_PLLP_DIV_18
<>	144:ef7eb2e8f9f7	1303	* @arg @ref LL_RCC_PLLP_DIV_19
<>	144:ef7eb2e8f9f7	1304	* @arg @ref LL_RCC_PLLP_DIV_20
<>	144:ef7eb2e8f9f7	1305	* @arg @ref LL_RCC_PLLP_DIV_21
<>	144:ef7eb2e8f9f7	1306	* @arg @ref LL_RCC_PLLP_DIV_22
<>	144:ef7eb2e8f9f7	1307	* @arg @ref LL_RCC_PLLP_DIV_23
<>	144:ef7eb2e8f9f7	1308	* @arg @ref LL_RCC_PLLP_DIV_24
<>	144:ef7eb2e8f9f7	1309	* @arg @ref LL_RCC_PLLP_DIV_25
<>	144:ef7eb2e8f9f7	1310	* @arg @ref LL_RCC_PLLP_DIV_26
<>	144:ef7eb2e8f9f7	1311	* @arg @ref LL_RCC_PLLP_DIV_27
<>	144:ef7eb2e8f9f7	1312	* @arg @ref LL_RCC_PLLP_DIV_28
<>	144:ef7eb2e8f9f7	1313	* @arg @ref LL_RCC_PLLP_DIV_29
<>	144:ef7eb2e8f9f7	1314	* @arg @ref LL_RCC_PLLP_DIV_30
<>	144:ef7eb2e8f9f7	1315	* @arg @ref LL_RCC_PLLP_DIV_31
<>	144:ef7eb2e8f9f7	1316	* @retval PLL clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1317	*/
AnnaBridge	167:e84263d55307	1318	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	181:57724642e740	1319	((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	#else
<>	144:ef7eb2e8f9f7	1322	/**
<>	144:ef7eb2e8f9f7	1323	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
<>	144:ef7eb2e8f9f7	1324	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1325	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
<>	144:ef7eb2e8f9f7	1326	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1327	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1328	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1329	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1330	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1331	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1332	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1333	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1334	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1335	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	1336	* @param __PLLN__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1337	* @param __PLLP__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1338	* @arg @ref LL_RCC_PLLP_DIV_7
<>	144:ef7eb2e8f9f7	1339	* @arg @ref LL_RCC_PLLP_DIV_17
<>	144:ef7eb2e8f9f7	1340	* @retval PLL clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1341	*/
AnnaBridge	167:e84263d55307	1342	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	167:e84263d55307	1343	(((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
<>	144:ef7eb2e8f9f7	1344
<>	144:ef7eb2e8f9f7	1345	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	181:57724642e740	1346
<>	144:ef7eb2e8f9f7	1347	/**
<>	144:ef7eb2e8f9f7	1348	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
<>	144:ef7eb2e8f9f7	1349	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1350	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
<>	144:ef7eb2e8f9f7	1351	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1352	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1353	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1354	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1355	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1356	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1357	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1358	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1359	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1360	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	1361	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	181:57724642e740	1362	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	181:57724642e740	1363	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	181:57724642e740	1364	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	181:57724642e740	1365	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	181:57724642e740	1366	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	181:57724642e740	1367	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	181:57724642e740	1368	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	181:57724642e740	1369	*
AnnaBridge	181:57724642e740	1370	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	1371	* @param __PLLN__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1372	* @param __PLLQ__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1373	* @arg @ref LL_RCC_PLLQ_DIV_2
<>	144:ef7eb2e8f9f7	1374	* @arg @ref LL_RCC_PLLQ_DIV_4
<>	144:ef7eb2e8f9f7	1375	* @arg @ref LL_RCC_PLLQ_DIV_6
<>	144:ef7eb2e8f9f7	1376	* @arg @ref LL_RCC_PLLQ_DIV_8
<>	144:ef7eb2e8f9f7	1377	* @retval PLL clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1378	*/
AnnaBridge	167:e84263d55307	1379	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	167:e84263d55307	1380	((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
<>	144:ef7eb2e8f9f7	1381
AnnaBridge	181:57724642e740	1382	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	181:57724642e740	1383	/**
AnnaBridge	181:57724642e740	1384	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
AnnaBridge	181:57724642e740	1385	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	181:57724642e740	1386	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
AnnaBridge	181:57724642e740	1387	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	181:57724642e740	1388	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1389	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	181:57724642e740	1390	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	181:57724642e740	1391	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	181:57724642e740	1392	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	181:57724642e740	1393	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	181:57724642e740	1394	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	181:57724642e740	1395	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	181:57724642e740	1396	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	181:57724642e740	1397	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	181:57724642e740	1398	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	181:57724642e740	1399	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	181:57724642e740	1400	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	181:57724642e740	1401	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	181:57724642e740	1402	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	181:57724642e740	1403	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	181:57724642e740	1404	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	181:57724642e740	1405	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	181:57724642e740	1406	* @param __PLLSAI1P__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1407	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	181:57724642e740	1408	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	181:57724642e740	1409	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	181:57724642e740	1410	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	181:57724642e740	1411	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	181:57724642e740	1412	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	181:57724642e740	1413	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	181:57724642e740	1414	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	181:57724642e740	1415	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	181:57724642e740	1416	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	181:57724642e740	1417	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	181:57724642e740	1418	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	181:57724642e740	1419	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	181:57724642e740	1420	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	181:57724642e740	1421	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	181:57724642e740	1422	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	181:57724642e740	1423	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	181:57724642e740	1424	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	181:57724642e740	1425	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	181:57724642e740	1426	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	181:57724642e740	1427	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	181:57724642e740	1428	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	181:57724642e740	1429	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	181:57724642e740	1430	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	181:57724642e740	1431	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	181:57724642e740	1432	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	181:57724642e740	1433	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	181:57724642e740	1434	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	181:57724642e740	1435	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	181:57724642e740	1436	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	181:57724642e740	1437	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	181:57724642e740	1438	*/
AnnaBridge	181:57724642e740	1439	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	181:57724642e740	1440	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	181:57724642e740	1441	((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
AnnaBridge	181:57724642e740	1442
AnnaBridge	181:57724642e740	1443	#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	1444	/**
<>	144:ef7eb2e8f9f7	1445	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
<>	144:ef7eb2e8f9f7	1446	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1447	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
<>	144:ef7eb2e8f9f7	1448	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1449	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1450	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1451	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1452	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1453	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1454	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1455	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1456	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1457	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	1458	* @param __PLLSAI1N__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1459	* @param __PLLSAI1P__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1460	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
<>	144:ef7eb2e8f9f7	1461	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
<>	144:ef7eb2e8f9f7	1462	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
<>	144:ef7eb2e8f9f7	1463	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
<>	144:ef7eb2e8f9f7	1464	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
<>	144:ef7eb2e8f9f7	1465	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
<>	144:ef7eb2e8f9f7	1466	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
<>	144:ef7eb2e8f9f7	1467	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
<>	144:ef7eb2e8f9f7	1468	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
<>	144:ef7eb2e8f9f7	1469	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
<>	144:ef7eb2e8f9f7	1470	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
<>	144:ef7eb2e8f9f7	1471	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
<>	144:ef7eb2e8f9f7	1472	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
<>	144:ef7eb2e8f9f7	1473	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
<>	144:ef7eb2e8f9f7	1474	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
<>	144:ef7eb2e8f9f7	1475	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
<>	144:ef7eb2e8f9f7	1476	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
<>	144:ef7eb2e8f9f7	1477	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
<>	144:ef7eb2e8f9f7	1478	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
<>	144:ef7eb2e8f9f7	1479	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
<>	144:ef7eb2e8f9f7	1480	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
<>	144:ef7eb2e8f9f7	1481	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
<>	144:ef7eb2e8f9f7	1482	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
<>	144:ef7eb2e8f9f7	1483	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
<>	144:ef7eb2e8f9f7	1484	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
<>	144:ef7eb2e8f9f7	1485	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
<>	144:ef7eb2e8f9f7	1486	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
<>	144:ef7eb2e8f9f7	1487	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
<>	144:ef7eb2e8f9f7	1488	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
<>	144:ef7eb2e8f9f7	1489	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
<>	144:ef7eb2e8f9f7	1490	* @retval PLLSAI1 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1491	*/
AnnaBridge	167:e84263d55307	1492	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	167:e84263d55307	1493	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	181:57724642e740	1494	((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
AnnaBridge	181:57724642e740	1495
<>	144:ef7eb2e8f9f7	1496	#else
<>	144:ef7eb2e8f9f7	1497	/**
<>	144:ef7eb2e8f9f7	1498	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
<>	144:ef7eb2e8f9f7	1499	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1500	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
<>	144:ef7eb2e8f9f7	1501	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1502	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1503	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1504	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1505	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1506	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1507	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1508	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1509	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1510	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	1511	* @param __PLLSAI1N__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1512	* @param __PLLSAI1P__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1513	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
<>	144:ef7eb2e8f9f7	1514	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
<>	144:ef7eb2e8f9f7	1515	* @retval PLLSAI1 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1516	*/
AnnaBridge	167:e84263d55307	1517	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	167:e84263d55307	1518	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	167:e84263d55307	1519	(((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
AnnaBridge	181:57724642e740	1520
<>	144:ef7eb2e8f9f7	1521	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	1522
AnnaBridge	181:57724642e740	1523	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	1524	/**
AnnaBridge	181:57724642e740	1525	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
AnnaBridge	181:57724642e740	1526	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	181:57724642e740	1527	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
AnnaBridge	181:57724642e740	1528	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	181:57724642e740	1529	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1530	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	181:57724642e740	1531	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	181:57724642e740	1532	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	181:57724642e740	1533	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	181:57724642e740	1534	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	181:57724642e740	1535	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	181:57724642e740	1536	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	181:57724642e740	1537	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	181:57724642e740	1538	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	181:57724642e740	1539	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	181:57724642e740	1540	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	181:57724642e740	1541	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	181:57724642e740	1542	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	181:57724642e740	1543	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	181:57724642e740	1544	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	181:57724642e740	1545	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	181:57724642e740	1546	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	181:57724642e740	1547	* @param __PLLSAI1Q__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1548	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	181:57724642e740	1549	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	181:57724642e740	1550	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	181:57724642e740	1551	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	181:57724642e740	1552	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	181:57724642e740	1553	*/
AnnaBridge	181:57724642e740	1554	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
AnnaBridge	181:57724642e740	1555	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	181:57724642e740	1556	((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
AnnaBridge	181:57724642e740	1557
AnnaBridge	181:57724642e740	1558	#else
<>	144:ef7eb2e8f9f7	1559	/**
<>	144:ef7eb2e8f9f7	1560	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
<>	144:ef7eb2e8f9f7	1561	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1562	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
<>	144:ef7eb2e8f9f7	1563	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1564	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1565	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1566	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1567	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1568	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1569	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1570	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1571	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1572	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	1573	* @param __PLLSAI1N__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1574	* @param __PLLSAI1Q__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1575	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
<>	144:ef7eb2e8f9f7	1576	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
<>	144:ef7eb2e8f9f7	1577	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
<>	144:ef7eb2e8f9f7	1578	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
<>	144:ef7eb2e8f9f7	1579	* @retval PLLSAI1 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1580	*/
AnnaBridge	167:e84263d55307	1581	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
AnnaBridge	167:e84263d55307	1582	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	167:e84263d55307	1583	((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
<>	144:ef7eb2e8f9f7	1584
AnnaBridge	181:57724642e740	1585	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	181:57724642e740	1586
AnnaBridge	181:57724642e740	1587	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	1588	/**
AnnaBridge	181:57724642e740	1589	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
AnnaBridge	181:57724642e740	1590	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	181:57724642e740	1591	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
AnnaBridge	181:57724642e740	1592	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	181:57724642e740	1593	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1594	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	181:57724642e740	1595	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	181:57724642e740	1596	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	181:57724642e740	1597	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	181:57724642e740	1598	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	181:57724642e740	1599	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	181:57724642e740	1600	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	181:57724642e740	1601	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	181:57724642e740	1602	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	181:57724642e740	1603	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	181:57724642e740	1604	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	181:57724642e740	1605	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	181:57724642e740	1606	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	181:57724642e740	1607	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	181:57724642e740	1608	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	181:57724642e740	1609	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	181:57724642e740	1610	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	181:57724642e740	1611	* @param __PLLSAI1R__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1612	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	181:57724642e740	1613	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	181:57724642e740	1614	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	181:57724642e740	1615	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	181:57724642e740	1616	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	181:57724642e740	1617	*/
AnnaBridge	181:57724642e740	1618	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
AnnaBridge	181:57724642e740	1619	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	181:57724642e740	1620	((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
AnnaBridge	181:57724642e740	1621
AnnaBridge	181:57724642e740	1622	#else
<>	144:ef7eb2e8f9f7	1623	/**
<>	144:ef7eb2e8f9f7	1624	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
<>	144:ef7eb2e8f9f7	1625	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1626	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
<>	144:ef7eb2e8f9f7	1627	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1628	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1629	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1630	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1631	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1632	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1633	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1634	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1635	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1636	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	1637	* @param __PLLSAI1N__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1638	* @param __PLLSAI1R__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1639	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
<>	144:ef7eb2e8f9f7	1640	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
<>	144:ef7eb2e8f9f7	1641	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
<>	144:ef7eb2e8f9f7	1642	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
<>	144:ef7eb2e8f9f7	1643	* @retval PLLSAI1 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1644	*/
AnnaBridge	167:e84263d55307	1645	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
AnnaBridge	167:e84263d55307	1646	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	167:e84263d55307	1647	((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
<>	144:ef7eb2e8f9f7	1648
AnnaBridge	181:57724642e740	1649	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	181:57724642e740	1650
AnnaBridge	181:57724642e740	1651	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	181:57724642e740	1652	/**
AnnaBridge	181:57724642e740	1653	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	181:57724642e740	1654	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	181:57724642e740	1655	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	181:57724642e740	1656	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	181:57724642e740	1657	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1658	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	181:57724642e740	1659	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	181:57724642e740	1660	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	181:57724642e740	1661	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	181:57724642e740	1662	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	181:57724642e740	1663	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	181:57724642e740	1664	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	181:57724642e740	1665	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	181:57724642e740	1666	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	181:57724642e740	1667	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	181:57724642e740	1668	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	181:57724642e740	1669	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	181:57724642e740	1670	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	181:57724642e740	1671	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	181:57724642e740	1672	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	181:57724642e740	1673	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	181:57724642e740	1674	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	181:57724642e740	1675	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1676	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	181:57724642e740	1677	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	181:57724642e740	1678	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	181:57724642e740	1679	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	181:57724642e740	1680	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	181:57724642e740	1681	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	181:57724642e740	1682	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	181:57724642e740	1683	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	181:57724642e740	1684	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	181:57724642e740	1685	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	181:57724642e740	1686	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	181:57724642e740	1687	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	181:57724642e740	1688	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	181:57724642e740	1689	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	181:57724642e740	1690	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	181:57724642e740	1691	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	181:57724642e740	1692	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	181:57724642e740	1693	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	181:57724642e740	1694	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	181:57724642e740	1695	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	181:57724642e740	1696	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	181:57724642e740	1697	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	181:57724642e740	1698	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	181:57724642e740	1699	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	181:57724642e740	1700	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	181:57724642e740	1701	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	181:57724642e740	1702	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	181:57724642e740	1703	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	181:57724642e740	1704	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	181:57724642e740	1705	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	181:57724642e740	1706	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	181:57724642e740	1707	*/
AnnaBridge	181:57724642e740	1708	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	181:57724642e740	1709	((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	181:57724642e740	1710	((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	181:57724642e740	1711
AnnaBridge	181:57724642e740	1712	#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	181:57724642e740	1713	/**
AnnaBridge	181:57724642e740	1714	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	181:57724642e740	1715	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	181:57724642e740	1716	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	181:57724642e740	1717	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	181:57724642e740	1718	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1719	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	181:57724642e740	1720	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	181:57724642e740	1721	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	181:57724642e740	1722	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	181:57724642e740	1723	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	181:57724642e740	1724	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	181:57724642e740	1725	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	181:57724642e740	1726	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	1727	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	181:57724642e740	1728	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1729	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	181:57724642e740	1730	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	181:57724642e740	1731	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	181:57724642e740	1732	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	181:57724642e740	1733	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	181:57724642e740	1734	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	181:57724642e740	1735	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	181:57724642e740	1736	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	181:57724642e740	1737	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	181:57724642e740	1738	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	181:57724642e740	1739	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	181:57724642e740	1740	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	181:57724642e740	1741	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	181:57724642e740	1742	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	181:57724642e740	1743	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	181:57724642e740	1744	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	181:57724642e740	1745	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	181:57724642e740	1746	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	181:57724642e740	1747	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	181:57724642e740	1748	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	181:57724642e740	1749	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	181:57724642e740	1750	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	181:57724642e740	1751	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	181:57724642e740	1752	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	181:57724642e740	1753	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	181:57724642e740	1754	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	181:57724642e740	1755	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	181:57724642e740	1756	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	181:57724642e740	1757	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	181:57724642e740	1758	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	181:57724642e740	1759	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	181:57724642e740	1760	*/
AnnaBridge	181:57724642e740	1761	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	181:57724642e740	1762	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	181:57724642e740	1763	((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	181:57724642e740	1764
AnnaBridge	181:57724642e740	1765	#else
<>	144:ef7eb2e8f9f7	1766	/**
<>	144:ef7eb2e8f9f7	1767	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
<>	144:ef7eb2e8f9f7	1768	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1769	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
<>	144:ef7eb2e8f9f7	1770	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1771	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1772	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1773	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1774	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1775	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1776	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1777	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1778	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1779	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	1780	* @param __PLLSAI2N__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1781	* @param __PLLSAI2P__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1782	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
<>	144:ef7eb2e8f9f7	1783	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
<>	144:ef7eb2e8f9f7	1784	* @retval PLLSAI2 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1785	*/
AnnaBridge	167:e84263d55307	1786	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	167:e84263d55307	1787	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
AnnaBridge	167:e84263d55307	1788	(((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
AnnaBridge	181:57724642e740	1789
AnnaBridge	181:57724642e740	1790	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	181:57724642e740	1791
AnnaBridge	181:57724642e740	1792	#if defined(LTDC)
AnnaBridge	181:57724642e740	1793	/**
AnnaBridge	181:57724642e740	1794	* @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain
AnnaBridge	181:57724642e740	1795	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	181:57724642e740	1796	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());
AnnaBridge	181:57724642e740	1797	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
AnnaBridge	181:57724642e740	1798	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1799	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	181:57724642e740	1800	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	181:57724642e740	1801	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	181:57724642e740	1802	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	181:57724642e740	1803	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	181:57724642e740	1804	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	181:57724642e740	1805	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	181:57724642e740	1806	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	181:57724642e740	1807	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	181:57724642e740	1808	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	181:57724642e740	1809	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	181:57724642e740	1810	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	181:57724642e740	1811	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	181:57724642e740	1812	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	181:57724642e740	1813	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	181:57724642e740	1814	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	181:57724642e740	1815	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	181:57724642e740	1816	* @param __PLLSAI2R__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1817	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	181:57724642e740	1818	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	181:57724642e740	1819	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	181:57724642e740	1820	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	181:57724642e740	1821	* @param __PLLSAI2DIVR__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1822	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	181:57724642e740	1823	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	181:57724642e740	1824	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	181:57724642e740	1825	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	181:57724642e740	1826	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	181:57724642e740	1827	*/
AnnaBridge	181:57724642e740	1828	#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
AnnaBridge	181:57724642e740	1829	(((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	181:57724642e740	1830	(((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos])))
AnnaBridge	181:57724642e740	1831	#else
<>	144:ef7eb2e8f9f7	1832	/**
<>	144:ef7eb2e8f9f7	1833	* @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
<>	144:ef7eb2e8f9f7	1834	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	144:ef7eb2e8f9f7	1835	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
<>	144:ef7eb2e8f9f7	1836	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
<>	144:ef7eb2e8f9f7	1837	* @param __PLLM__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1838	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	1839	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	1840	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	1841	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	1842	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	1843	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	1844	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	1845	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	1846	* @param __PLLSAI2N__ Between 8 and 86
<>	144:ef7eb2e8f9f7	1847	* @param __PLLSAI2R__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1848	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
<>	144:ef7eb2e8f9f7	1849	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
<>	144:ef7eb2e8f9f7	1850	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
<>	144:ef7eb2e8f9f7	1851	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
<>	144:ef7eb2e8f9f7	1852	* @retval PLLSAI2 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1853	*/
AnnaBridge	167:e84263d55307	1854	#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
AnnaBridge	167:e84263d55307	1855	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	167:e84263d55307	1856	((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
AnnaBridge	167:e84263d55307	1857
AnnaBridge	181:57724642e740	1858	#endif /* LTDC */
AnnaBridge	181:57724642e740	1859
AnnaBridge	181:57724642e740	1860	#if defined(DSI)
AnnaBridge	181:57724642e740	1861	/**
AnnaBridge	181:57724642e740	1862	* @brief Helper macro to calculate the PLLDSICLK frequency used on DSI
AnnaBridge	181:57724642e740	1863	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	181:57724642e740	1864	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());
AnnaBridge	181:57724642e740	1865	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
AnnaBridge	181:57724642e740	1866	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1867	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	181:57724642e740	1868	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	181:57724642e740	1869	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	181:57724642e740	1870	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	181:57724642e740	1871	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	181:57724642e740	1872	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	181:57724642e740	1873	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	181:57724642e740	1874	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	181:57724642e740	1875	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	181:57724642e740	1876	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	181:57724642e740	1877	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	181:57724642e740	1878	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	181:57724642e740	1879	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	181:57724642e740	1880	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	181:57724642e740	1881	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	181:57724642e740	1882	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	181:57724642e740	1883	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	181:57724642e740	1884	* @param __PLLSAI2Q__ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	1885	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	181:57724642e740	1886	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	181:57724642e740	1887	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	181:57724642e740	1888	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	181:57724642e740	1889	* @retval PLL clock frequency (in Hz)
AnnaBridge	181:57724642e740	1890	*/
AnnaBridge	181:57724642e740	1891	#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
AnnaBridge	181:57724642e740	1892	((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	181:57724642e740	1893	((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
AnnaBridge	181:57724642e740	1894	#endif /* DSI */
AnnaBridge	181:57724642e740	1895
AnnaBridge	181:57724642e740	1896
<>	144:ef7eb2e8f9f7	1897
<>	144:ef7eb2e8f9f7	1898	/**
<>	144:ef7eb2e8f9f7	1899	* @brief Helper macro to calculate the HCLK frequency
<>	144:ef7eb2e8f9f7	1900	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
<>	144:ef7eb2e8f9f7	1901	* @param __AHBPRESCALER__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1902	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	144:ef7eb2e8f9f7	1903	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	144:ef7eb2e8f9f7	1904	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	144:ef7eb2e8f9f7	1905	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	144:ef7eb2e8f9f7	1906	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	144:ef7eb2e8f9f7	1907	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	144:ef7eb2e8f9f7	1908	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	144:ef7eb2e8f9f7	1909	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	144:ef7eb2e8f9f7	1910	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	144:ef7eb2e8f9f7	1911	* @retval HCLK clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1912	*/
AnnaBridge	167:e84263d55307	1913	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
<>	144:ef7eb2e8f9f7	1914
<>	144:ef7eb2e8f9f7	1915	/**
<>	144:ef7eb2e8f9f7	1916	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
<>	144:ef7eb2e8f9f7	1917	* @param __HCLKFREQ__ HCLK frequency
<>	144:ef7eb2e8f9f7	1918	* @param __APB1PRESCALER__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1919	* @arg @ref LL_RCC_APB1_DIV_1
<>	144:ef7eb2e8f9f7	1920	* @arg @ref LL_RCC_APB1_DIV_2
<>	144:ef7eb2e8f9f7	1921	* @arg @ref LL_RCC_APB1_DIV_4
<>	144:ef7eb2e8f9f7	1922	* @arg @ref LL_RCC_APB1_DIV_8
<>	144:ef7eb2e8f9f7	1923	* @arg @ref LL_RCC_APB1_DIV_16
<>	144:ef7eb2e8f9f7	1924	* @retval PCLK1 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1925	*/
AnnaBridge	181:57724642e740	1926	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
<>	144:ef7eb2e8f9f7	1927
<>	144:ef7eb2e8f9f7	1928	/**
<>	144:ef7eb2e8f9f7	1929	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
<>	144:ef7eb2e8f9f7	1930	* @param __HCLKFREQ__ HCLK frequency
<>	144:ef7eb2e8f9f7	1931	* @param __APB2PRESCALER__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1932	* @arg @ref LL_RCC_APB2_DIV_1
<>	144:ef7eb2e8f9f7	1933	* @arg @ref LL_RCC_APB2_DIV_2
<>	144:ef7eb2e8f9f7	1934	* @arg @ref LL_RCC_APB2_DIV_4
<>	144:ef7eb2e8f9f7	1935	* @arg @ref LL_RCC_APB2_DIV_8
<>	144:ef7eb2e8f9f7	1936	* @arg @ref LL_RCC_APB2_DIV_16
<>	144:ef7eb2e8f9f7	1937	* @retval PCLK2 clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1938	*/
AnnaBridge	181:57724642e740	1939	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
<>	144:ef7eb2e8f9f7	1940
<>	144:ef7eb2e8f9f7	1941	/**
<>	144:ef7eb2e8f9f7	1942	* @brief Helper macro to calculate the MSI frequency (in Hz)
AnnaBridge	167:e84263d55307	1943	* @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
AnnaBridge	167:e84263d55307	1944	* @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
AnnaBridge	167:e84263d55307	1945	* __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
AnnaBridge	167:e84263d55307	1946	* else by LL_RCC_MSI_GetRange()
<>	144:ef7eb2e8f9f7	1947	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<>	144:ef7eb2e8f9f7	1948	* (LL_RCC_MSI_IsEnabledRangeSelect()?
<>	144:ef7eb2e8f9f7	1949	* LL_RCC_MSI_GetRange():
<>	144:ef7eb2e8f9f7	1950	* LL_RCC_MSI_GetRangeAfterStandby()))
<>	144:ef7eb2e8f9f7	1951	* @param __MSISEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1952	* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
<>	144:ef7eb2e8f9f7	1953	* @arg @ref LL_RCC_MSIRANGESEL_RUN
<>	144:ef7eb2e8f9f7	1954	* @param __MSIRANGE__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1955	* @arg @ref LL_RCC_MSIRANGE_0
<>	144:ef7eb2e8f9f7	1956	* @arg @ref LL_RCC_MSIRANGE_1
<>	144:ef7eb2e8f9f7	1957	* @arg @ref LL_RCC_MSIRANGE_2
<>	144:ef7eb2e8f9f7	1958	* @arg @ref LL_RCC_MSIRANGE_3
<>	144:ef7eb2e8f9f7	1959	* @arg @ref LL_RCC_MSIRANGE_4
<>	144:ef7eb2e8f9f7	1960	* @arg @ref LL_RCC_MSIRANGE_5
<>	144:ef7eb2e8f9f7	1961	* @arg @ref LL_RCC_MSIRANGE_6
<>	144:ef7eb2e8f9f7	1962	* @arg @ref LL_RCC_MSIRANGE_7
<>	144:ef7eb2e8f9f7	1963	* @arg @ref LL_RCC_MSIRANGE_8
<>	144:ef7eb2e8f9f7	1964	* @arg @ref LL_RCC_MSIRANGE_9
<>	144:ef7eb2e8f9f7	1965	* @arg @ref LL_RCC_MSIRANGE_10
<>	144:ef7eb2e8f9f7	1966	* @arg @ref LL_RCC_MSIRANGE_11
<>	144:ef7eb2e8f9f7	1967	* @arg @ref LL_RCC_MSISRANGE_4
<>	144:ef7eb2e8f9f7	1968	* @arg @ref LL_RCC_MSISRANGE_5
<>	144:ef7eb2e8f9f7	1969	* @arg @ref LL_RCC_MSISRANGE_6
<>	144:ef7eb2e8f9f7	1970	* @arg @ref LL_RCC_MSISRANGE_7
<>	144:ef7eb2e8f9f7	1971	* @retval MSI clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1972	*/
<>	144:ef7eb2e8f9f7	1973	#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
AnnaBridge	167:e84263d55307	1974	(MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
AnnaBridge	167:e84263d55307	1975	(MSIRangeTable[(__MSIRANGE__) >> 4U]))
<>	144:ef7eb2e8f9f7	1976
<>	144:ef7eb2e8f9f7	1977	/**
<>	144:ef7eb2e8f9f7	1978	* @}
<>	144:ef7eb2e8f9f7	1979	*/
<>	144:ef7eb2e8f9f7	1980
<>	144:ef7eb2e8f9f7	1981	/**
<>	144:ef7eb2e8f9f7	1982	* @}
<>	144:ef7eb2e8f9f7	1983	*/
<>	144:ef7eb2e8f9f7	1984
<>	144:ef7eb2e8f9f7	1985	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1986	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
<>	144:ef7eb2e8f9f7	1987	* @{
<>	144:ef7eb2e8f9f7	1988	*/
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	/** @defgroup RCC_LL_EF_HSE HSE
<>	144:ef7eb2e8f9f7	1991	* @{
<>	144:ef7eb2e8f9f7	1992	*/
<>	144:ef7eb2e8f9f7	1993
<>	144:ef7eb2e8f9f7	1994	/**
<>	144:ef7eb2e8f9f7	1995	* @brief Enable the Clock Security System.
<>	144:ef7eb2e8f9f7	1996	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
<>	144:ef7eb2e8f9f7	1997	* @retval None
<>	144:ef7eb2e8f9f7	1998	*/
<>	144:ef7eb2e8f9f7	1999	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
<>	144:ef7eb2e8f9f7	2000	{
<>	144:ef7eb2e8f9f7	2001	SET_BIT(RCC->CR, RCC_CR_CSSON);
<>	144:ef7eb2e8f9f7	2002	}
<>	144:ef7eb2e8f9f7	2003
<>	144:ef7eb2e8f9f7	2004	/**
<>	144:ef7eb2e8f9f7	2005	* @brief Enable HSE external oscillator (HSE Bypass)
<>	144:ef7eb2e8f9f7	2006	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
<>	144:ef7eb2e8f9f7	2007	* @retval None
<>	144:ef7eb2e8f9f7	2008	*/
<>	144:ef7eb2e8f9f7	2009	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
<>	144:ef7eb2e8f9f7	2010	{
<>	144:ef7eb2e8f9f7	2011	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	144:ef7eb2e8f9f7	2012	}
<>	144:ef7eb2e8f9f7	2013
<>	144:ef7eb2e8f9f7	2014	/**
<>	144:ef7eb2e8f9f7	2015	* @brief Disable HSE external oscillator (HSE Bypass)
<>	144:ef7eb2e8f9f7	2016	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
<>	144:ef7eb2e8f9f7	2017	* @retval None
<>	144:ef7eb2e8f9f7	2018	*/
<>	144:ef7eb2e8f9f7	2019	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
<>	144:ef7eb2e8f9f7	2020	{
<>	144:ef7eb2e8f9f7	2021	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	144:ef7eb2e8f9f7	2022	}
<>	144:ef7eb2e8f9f7	2023
<>	144:ef7eb2e8f9f7	2024	/**
<>	144:ef7eb2e8f9f7	2025	* @brief Enable HSE crystal oscillator (HSE ON)
<>	144:ef7eb2e8f9f7	2026	* @rmtoll CR HSEON LL_RCC_HSE_Enable
<>	144:ef7eb2e8f9f7	2027	* @retval None
<>	144:ef7eb2e8f9f7	2028	*/
<>	144:ef7eb2e8f9f7	2029	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
<>	144:ef7eb2e8f9f7	2030	{
<>	144:ef7eb2e8f9f7	2031	SET_BIT(RCC->CR, RCC_CR_HSEON);
<>	144:ef7eb2e8f9f7	2032	}
<>	144:ef7eb2e8f9f7	2033
<>	144:ef7eb2e8f9f7	2034	/**
<>	144:ef7eb2e8f9f7	2035	* @brief Disable HSE crystal oscillator (HSE ON)
<>	144:ef7eb2e8f9f7	2036	* @rmtoll CR HSEON LL_RCC_HSE_Disable
<>	144:ef7eb2e8f9f7	2037	* @retval None
<>	144:ef7eb2e8f9f7	2038	*/
<>	144:ef7eb2e8f9f7	2039	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
<>	144:ef7eb2e8f9f7	2040	{
<>	144:ef7eb2e8f9f7	2041	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
<>	144:ef7eb2e8f9f7	2042	}
<>	144:ef7eb2e8f9f7	2043
<>	144:ef7eb2e8f9f7	2044	/**
<>	144:ef7eb2e8f9f7	2045	* @brief Check if HSE oscillator Ready
<>	144:ef7eb2e8f9f7	2046	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
<>	144:ef7eb2e8f9f7	2047	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2048	*/
<>	144:ef7eb2e8f9f7	2049	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
<>	144:ef7eb2e8f9f7	2050	{
<>	144:ef7eb2e8f9f7	2051	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
<>	144:ef7eb2e8f9f7	2052	}
<>	144:ef7eb2e8f9f7	2053
<>	144:ef7eb2e8f9f7	2054	/**
<>	144:ef7eb2e8f9f7	2055	* @}
<>	144:ef7eb2e8f9f7	2056	*/
<>	144:ef7eb2e8f9f7	2057
<>	144:ef7eb2e8f9f7	2058	/** @defgroup RCC_LL_EF_HSI HSI
<>	144:ef7eb2e8f9f7	2059	* @{
<>	144:ef7eb2e8f9f7	2060	*/
<>	144:ef7eb2e8f9f7	2061
<>	144:ef7eb2e8f9f7	2062	/**
<>	144:ef7eb2e8f9f7	2063	* @brief Enable HSI even in stop mode
<>	144:ef7eb2e8f9f7	2064	* @note HSI oscillator is forced ON even in Stop mode
<>	144:ef7eb2e8f9f7	2065	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
<>	144:ef7eb2e8f9f7	2066	* @retval None
<>	144:ef7eb2e8f9f7	2067	*/
<>	144:ef7eb2e8f9f7	2068	__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
<>	144:ef7eb2e8f9f7	2069	{
<>	144:ef7eb2e8f9f7	2070	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
<>	144:ef7eb2e8f9f7	2071	}
<>	144:ef7eb2e8f9f7	2072
<>	144:ef7eb2e8f9f7	2073	/**
<>	144:ef7eb2e8f9f7	2074	* @brief Disable HSI in stop mode
<>	144:ef7eb2e8f9f7	2075	* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
<>	144:ef7eb2e8f9f7	2076	* @retval None
<>	144:ef7eb2e8f9f7	2077	*/
<>	144:ef7eb2e8f9f7	2078	__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
<>	144:ef7eb2e8f9f7	2079	{
<>	144:ef7eb2e8f9f7	2080	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
<>	144:ef7eb2e8f9f7	2081	}
<>	144:ef7eb2e8f9f7	2082
<>	144:ef7eb2e8f9f7	2083	/**
AnnaBridge	181:57724642e740	2084	* @brief Check if HSI is enabled in stop mode
AnnaBridge	181:57724642e740	2085	* @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
AnnaBridge	181:57724642e740	2086	* @retval State of bit (1 or 0).
AnnaBridge	181:57724642e740	2087	*/
AnnaBridge	181:57724642e740	2088	__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
AnnaBridge	181:57724642e740	2089	{
AnnaBridge	181:57724642e740	2090	return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON));
AnnaBridge	181:57724642e740	2091	}
AnnaBridge	181:57724642e740	2092
AnnaBridge	181:57724642e740	2093	/**
<>	144:ef7eb2e8f9f7	2094	* @brief Enable HSI oscillator
<>	144:ef7eb2e8f9f7	2095	* @rmtoll CR HSION LL_RCC_HSI_Enable
<>	144:ef7eb2e8f9f7	2096	* @retval None
<>	144:ef7eb2e8f9f7	2097	*/
<>	144:ef7eb2e8f9f7	2098	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
<>	144:ef7eb2e8f9f7	2099	{
<>	144:ef7eb2e8f9f7	2100	SET_BIT(RCC->CR, RCC_CR_HSION);
<>	144:ef7eb2e8f9f7	2101	}
<>	144:ef7eb2e8f9f7	2102
<>	144:ef7eb2e8f9f7	2103	/**
<>	144:ef7eb2e8f9f7	2104	* @brief Disable HSI oscillator
<>	144:ef7eb2e8f9f7	2105	* @rmtoll CR HSION LL_RCC_HSI_Disable
<>	144:ef7eb2e8f9f7	2106	* @retval None
<>	144:ef7eb2e8f9f7	2107	*/
<>	144:ef7eb2e8f9f7	2108	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
<>	144:ef7eb2e8f9f7	2109	{
<>	144:ef7eb2e8f9f7	2110	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
<>	144:ef7eb2e8f9f7	2111	}
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	/**
<>	144:ef7eb2e8f9f7	2114	* @brief Check if HSI clock is ready
<>	144:ef7eb2e8f9f7	2115	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
<>	144:ef7eb2e8f9f7	2116	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2117	*/
<>	144:ef7eb2e8f9f7	2118	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
<>	144:ef7eb2e8f9f7	2119	{
<>	144:ef7eb2e8f9f7	2120	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
<>	144:ef7eb2e8f9f7	2121	}
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	/**
<>	144:ef7eb2e8f9f7	2124	* @brief Enable HSI Automatic from stop mode
<>	144:ef7eb2e8f9f7	2125	* @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
<>	144:ef7eb2e8f9f7	2126	* @retval None
<>	144:ef7eb2e8f9f7	2127	*/
<>	144:ef7eb2e8f9f7	2128	__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
<>	144:ef7eb2e8f9f7	2129	{
<>	144:ef7eb2e8f9f7	2130	SET_BIT(RCC->CR, RCC_CR_HSIASFS);
<>	144:ef7eb2e8f9f7	2131	}
<>	144:ef7eb2e8f9f7	2132
<>	144:ef7eb2e8f9f7	2133	/**
<>	144:ef7eb2e8f9f7	2134	* @brief Disable HSI Automatic from stop mode
<>	144:ef7eb2e8f9f7	2135	* @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
<>	144:ef7eb2e8f9f7	2136	* @retval None
<>	144:ef7eb2e8f9f7	2137	*/
<>	144:ef7eb2e8f9f7	2138	__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
<>	144:ef7eb2e8f9f7	2139	{
<>	144:ef7eb2e8f9f7	2140	CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
<>	144:ef7eb2e8f9f7	2141	}
<>	144:ef7eb2e8f9f7	2142	/**
<>	144:ef7eb2e8f9f7	2143	* @brief Get HSI Calibration value
<>	144:ef7eb2e8f9f7	2144	* @note When HSITRIM is written, HSICAL is updated with the sum of
<>	144:ef7eb2e8f9f7	2145	* HSITRIM and the factory trim value
<>	144:ef7eb2e8f9f7	2146	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
<>	144:ef7eb2e8f9f7	2147	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	144:ef7eb2e8f9f7	2148	*/
<>	144:ef7eb2e8f9f7	2149	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
<>	144:ef7eb2e8f9f7	2150	{
AnnaBridge	167:e84263d55307	2151	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
<>	144:ef7eb2e8f9f7	2152	}
<>	144:ef7eb2e8f9f7	2153
<>	144:ef7eb2e8f9f7	2154	/**
<>	144:ef7eb2e8f9f7	2155	* @brief Set HSI Calibration trimming
<>	144:ef7eb2e8f9f7	2156	* @note user-programmable trimming value that is added to the HSICAL
<>	144:ef7eb2e8f9f7	2157	* @note Default value is 16, which, when added to the HSICAL value,
<>	144:ef7eb2e8f9f7	2158	* should trim the HSI to 16 MHz +/- 1 %
<>	144:ef7eb2e8f9f7	2159	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
<>	144:ef7eb2e8f9f7	2160	* @param Value Between Min_Data = 0 and Max_Data = 31
<>	144:ef7eb2e8f9f7	2161	* @retval None
<>	144:ef7eb2e8f9f7	2162	*/
<>	144:ef7eb2e8f9f7	2163	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
<>	144:ef7eb2e8f9f7	2164	{
AnnaBridge	167:e84263d55307	2165	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
<>	144:ef7eb2e8f9f7	2166	}
<>	144:ef7eb2e8f9f7	2167
<>	144:ef7eb2e8f9f7	2168	/**
<>	144:ef7eb2e8f9f7	2169	* @brief Get HSI Calibration trimming
<>	144:ef7eb2e8f9f7	2170	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
<>	144:ef7eb2e8f9f7	2171	* @retval Between Min_Data = 0 and Max_Data = 31
<>	144:ef7eb2e8f9f7	2172	*/
<>	144:ef7eb2e8f9f7	2173	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
<>	144:ef7eb2e8f9f7	2174	{
AnnaBridge	167:e84263d55307	2175	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
<>	144:ef7eb2e8f9f7	2176	}
<>	144:ef7eb2e8f9f7	2177
<>	144:ef7eb2e8f9f7	2178	/**
<>	144:ef7eb2e8f9f7	2179	* @}
<>	144:ef7eb2e8f9f7	2180	*/
<>	144:ef7eb2e8f9f7	2181
<>	144:ef7eb2e8f9f7	2182	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	2183	/** @defgroup RCC_LL_EF_HSI48 HSI48
<>	144:ef7eb2e8f9f7	2184	* @{
<>	144:ef7eb2e8f9f7	2185	*/
<>	144:ef7eb2e8f9f7	2186
<>	144:ef7eb2e8f9f7	2187	/**
<>	144:ef7eb2e8f9f7	2188	* @brief Enable HSI48
<>	144:ef7eb2e8f9f7	2189	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
<>	144:ef7eb2e8f9f7	2190	* @retval None
<>	144:ef7eb2e8f9f7	2191	*/
<>	144:ef7eb2e8f9f7	2192	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
<>	144:ef7eb2e8f9f7	2193	{
<>	144:ef7eb2e8f9f7	2194	SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
<>	144:ef7eb2e8f9f7	2195	}
<>	144:ef7eb2e8f9f7	2196
<>	144:ef7eb2e8f9f7	2197	/**
<>	144:ef7eb2e8f9f7	2198	* @brief Disable HSI48
<>	144:ef7eb2e8f9f7	2199	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
<>	144:ef7eb2e8f9f7	2200	* @retval None
<>	144:ef7eb2e8f9f7	2201	*/
<>	144:ef7eb2e8f9f7	2202	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
<>	144:ef7eb2e8f9f7	2203	{
<>	144:ef7eb2e8f9f7	2204	CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
<>	144:ef7eb2e8f9f7	2205	}
<>	144:ef7eb2e8f9f7	2206
<>	144:ef7eb2e8f9f7	2207	/**
<>	144:ef7eb2e8f9f7	2208	* @brief Check if HSI48 oscillator Ready
<>	144:ef7eb2e8f9f7	2209	* @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
<>	144:ef7eb2e8f9f7	2210	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2211	*/
<>	144:ef7eb2e8f9f7	2212	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
<>	144:ef7eb2e8f9f7	2213	{
<>	144:ef7eb2e8f9f7	2214	return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
<>	144:ef7eb2e8f9f7	2215	}
<>	144:ef7eb2e8f9f7	2216
<>	144:ef7eb2e8f9f7	2217	/**
<>	144:ef7eb2e8f9f7	2218	* @brief Get HSI48 Calibration value
<>	144:ef7eb2e8f9f7	2219	* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
AnnaBridge	181:57724642e740	2220	* @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
<>	144:ef7eb2e8f9f7	2221	*/
<>	144:ef7eb2e8f9f7	2222	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
<>	144:ef7eb2e8f9f7	2223	{
AnnaBridge	167:e84263d55307	2224	return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
<>	144:ef7eb2e8f9f7	2225	}
<>	144:ef7eb2e8f9f7	2226
<>	144:ef7eb2e8f9f7	2227	/**
<>	144:ef7eb2e8f9f7	2228	* @}
<>	144:ef7eb2e8f9f7	2229	*/
<>	144:ef7eb2e8f9f7	2230	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	2231
<>	144:ef7eb2e8f9f7	2232	/** @defgroup RCC_LL_EF_LSE LSE
<>	144:ef7eb2e8f9f7	2233	* @{
<>	144:ef7eb2e8f9f7	2234	*/
<>	144:ef7eb2e8f9f7	2235
<>	144:ef7eb2e8f9f7	2236	/**
<>	144:ef7eb2e8f9f7	2237	* @brief Enable Low Speed External (LSE) crystal.
<>	144:ef7eb2e8f9f7	2238	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
<>	144:ef7eb2e8f9f7	2239	* @retval None
<>	144:ef7eb2e8f9f7	2240	*/
<>	144:ef7eb2e8f9f7	2241	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
<>	144:ef7eb2e8f9f7	2242	{
<>	144:ef7eb2e8f9f7	2243	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	144:ef7eb2e8f9f7	2244	}
<>	144:ef7eb2e8f9f7	2245
<>	144:ef7eb2e8f9f7	2246	/**
<>	144:ef7eb2e8f9f7	2247	* @brief Disable Low Speed External (LSE) crystal.
<>	144:ef7eb2e8f9f7	2248	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
<>	144:ef7eb2e8f9f7	2249	* @retval None
<>	144:ef7eb2e8f9f7	2250	*/
<>	144:ef7eb2e8f9f7	2251	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
<>	144:ef7eb2e8f9f7	2252	{
<>	144:ef7eb2e8f9f7	2253	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	144:ef7eb2e8f9f7	2254	}
<>	144:ef7eb2e8f9f7	2255
<>	144:ef7eb2e8f9f7	2256	/**
<>	144:ef7eb2e8f9f7	2257	* @brief Enable external clock source (LSE bypass).
<>	144:ef7eb2e8f9f7	2258	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
<>	144:ef7eb2e8f9f7	2259	* @retval None
<>	144:ef7eb2e8f9f7	2260	*/
<>	144:ef7eb2e8f9f7	2261	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
<>	144:ef7eb2e8f9f7	2262	{
<>	144:ef7eb2e8f9f7	2263	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	144:ef7eb2e8f9f7	2264	}
<>	144:ef7eb2e8f9f7	2265
<>	144:ef7eb2e8f9f7	2266	/**
<>	144:ef7eb2e8f9f7	2267	* @brief Disable external clock source (LSE bypass).
<>	144:ef7eb2e8f9f7	2268	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
<>	144:ef7eb2e8f9f7	2269	* @retval None
<>	144:ef7eb2e8f9f7	2270	*/
<>	144:ef7eb2e8f9f7	2271	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
<>	144:ef7eb2e8f9f7	2272	{
<>	144:ef7eb2e8f9f7	2273	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	144:ef7eb2e8f9f7	2274	}
<>	144:ef7eb2e8f9f7	2275
<>	144:ef7eb2e8f9f7	2276	/**
<>	144:ef7eb2e8f9f7	2277	* @brief Set LSE oscillator drive capability
<>	144:ef7eb2e8f9f7	2278	* @note The oscillator is in Xtal mode when it is not in bypass mode.
<>	144:ef7eb2e8f9f7	2279	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
<>	144:ef7eb2e8f9f7	2280	* @param LSEDrive This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2281	* @arg @ref LL_RCC_LSEDRIVE_LOW
<>	144:ef7eb2e8f9f7	2282	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<>	144:ef7eb2e8f9f7	2283	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<>	144:ef7eb2e8f9f7	2284	* @arg @ref LL_RCC_LSEDRIVE_HIGH
<>	144:ef7eb2e8f9f7	2285	* @retval None
<>	144:ef7eb2e8f9f7	2286	*/
<>	144:ef7eb2e8f9f7	2287	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
<>	144:ef7eb2e8f9f7	2288	{
<>	144:ef7eb2e8f9f7	2289	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
<>	144:ef7eb2e8f9f7	2290	}
<>	144:ef7eb2e8f9f7	2291
<>	144:ef7eb2e8f9f7	2292	/**
<>	144:ef7eb2e8f9f7	2293	* @brief Get LSE oscillator drive capability
<>	144:ef7eb2e8f9f7	2294	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
<>	144:ef7eb2e8f9f7	2295	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2296	* @arg @ref LL_RCC_LSEDRIVE_LOW
<>	144:ef7eb2e8f9f7	2297	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<>	144:ef7eb2e8f9f7	2298	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<>	144:ef7eb2e8f9f7	2299	* @arg @ref LL_RCC_LSEDRIVE_HIGH
<>	144:ef7eb2e8f9f7	2300	*/
<>	144:ef7eb2e8f9f7	2301	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
<>	144:ef7eb2e8f9f7	2302	{
<>	144:ef7eb2e8f9f7	2303	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
<>	144:ef7eb2e8f9f7	2304	}
<>	144:ef7eb2e8f9f7	2305
<>	144:ef7eb2e8f9f7	2306	/**
<>	144:ef7eb2e8f9f7	2307	* @brief Enable Clock security system on LSE.
<>	144:ef7eb2e8f9f7	2308	* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
<>	144:ef7eb2e8f9f7	2309	* @retval None
<>	144:ef7eb2e8f9f7	2310	*/
<>	144:ef7eb2e8f9f7	2311	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
<>	144:ef7eb2e8f9f7	2312	{
<>	144:ef7eb2e8f9f7	2313	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
<>	144:ef7eb2e8f9f7	2314	}
<>	144:ef7eb2e8f9f7	2315
<>	144:ef7eb2e8f9f7	2316	/**
<>	144:ef7eb2e8f9f7	2317	* @brief Disable Clock security system on LSE.
<>	144:ef7eb2e8f9f7	2318	* @note Clock security system can be disabled only after a LSE
<>	144:ef7eb2e8f9f7	2319	* failure detection. In that case it MUST be disabled by software.
<>	144:ef7eb2e8f9f7	2320	* @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
<>	144:ef7eb2e8f9f7	2321	* @retval None
<>	144:ef7eb2e8f9f7	2322	*/
<>	144:ef7eb2e8f9f7	2323	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
<>	144:ef7eb2e8f9f7	2324	{
<>	144:ef7eb2e8f9f7	2325	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
<>	144:ef7eb2e8f9f7	2326	}
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328	/**
<>	144:ef7eb2e8f9f7	2329	* @brief Check if LSE oscillator Ready
<>	144:ef7eb2e8f9f7	2330	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
<>	144:ef7eb2e8f9f7	2331	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2332	*/
<>	144:ef7eb2e8f9f7	2333	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
<>	144:ef7eb2e8f9f7	2334	{
<>	144:ef7eb2e8f9f7	2335	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
<>	144:ef7eb2e8f9f7	2336	}
<>	144:ef7eb2e8f9f7	2337
<>	144:ef7eb2e8f9f7	2338	/**
<>	144:ef7eb2e8f9f7	2339	* @brief Check if CSS on LSE failure Detection
<>	144:ef7eb2e8f9f7	2340	* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
<>	144:ef7eb2e8f9f7	2341	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2342	*/
<>	144:ef7eb2e8f9f7	2343	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
<>	144:ef7eb2e8f9f7	2344	{
<>	144:ef7eb2e8f9f7	2345	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
<>	144:ef7eb2e8f9f7	2346	}
<>	144:ef7eb2e8f9f7	2347
<>	144:ef7eb2e8f9f7	2348	/**
<>	144:ef7eb2e8f9f7	2349	* @}
<>	144:ef7eb2e8f9f7	2350	*/
<>	144:ef7eb2e8f9f7	2351
<>	144:ef7eb2e8f9f7	2352	/** @defgroup RCC_LL_EF_LSI LSI
<>	144:ef7eb2e8f9f7	2353	* @{
<>	144:ef7eb2e8f9f7	2354	*/
<>	144:ef7eb2e8f9f7	2355
<>	144:ef7eb2e8f9f7	2356	/**
<>	144:ef7eb2e8f9f7	2357	* @brief Enable LSI Oscillator
<>	144:ef7eb2e8f9f7	2358	* @rmtoll CSR LSION LL_RCC_LSI_Enable
<>	144:ef7eb2e8f9f7	2359	* @retval None
<>	144:ef7eb2e8f9f7	2360	*/
<>	144:ef7eb2e8f9f7	2361	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
<>	144:ef7eb2e8f9f7	2362	{
<>	144:ef7eb2e8f9f7	2363	SET_BIT(RCC->CSR, RCC_CSR_LSION);
<>	144:ef7eb2e8f9f7	2364	}
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/**
<>	144:ef7eb2e8f9f7	2367	* @brief Disable LSI Oscillator
<>	144:ef7eb2e8f9f7	2368	* @rmtoll CSR LSION LL_RCC_LSI_Disable
<>	144:ef7eb2e8f9f7	2369	* @retval None
<>	144:ef7eb2e8f9f7	2370	*/
<>	144:ef7eb2e8f9f7	2371	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
<>	144:ef7eb2e8f9f7	2372	{
<>	144:ef7eb2e8f9f7	2373	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
<>	144:ef7eb2e8f9f7	2374	}
<>	144:ef7eb2e8f9f7	2375
<>	144:ef7eb2e8f9f7	2376	/**
<>	144:ef7eb2e8f9f7	2377	* @brief Check if LSI is Ready
<>	144:ef7eb2e8f9f7	2378	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
<>	144:ef7eb2e8f9f7	2379	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2380	*/
<>	144:ef7eb2e8f9f7	2381	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
<>	144:ef7eb2e8f9f7	2382	{
<>	144:ef7eb2e8f9f7	2383	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
<>	144:ef7eb2e8f9f7	2384	}
<>	144:ef7eb2e8f9f7	2385
<>	144:ef7eb2e8f9f7	2386	/**
<>	144:ef7eb2e8f9f7	2387	* @}
<>	144:ef7eb2e8f9f7	2388	*/
<>	144:ef7eb2e8f9f7	2389
<>	144:ef7eb2e8f9f7	2390	/** @defgroup RCC_LL_EF_MSI MSI
<>	144:ef7eb2e8f9f7	2391	* @{
<>	144:ef7eb2e8f9f7	2392	*/
<>	144:ef7eb2e8f9f7	2393
<>	144:ef7eb2e8f9f7	2394	/**
<>	144:ef7eb2e8f9f7	2395	* @brief Enable MSI oscillator
<>	144:ef7eb2e8f9f7	2396	* @rmtoll CR MSION LL_RCC_MSI_Enable
<>	144:ef7eb2e8f9f7	2397	* @retval None
<>	144:ef7eb2e8f9f7	2398	*/
<>	144:ef7eb2e8f9f7	2399	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
<>	144:ef7eb2e8f9f7	2400	{
<>	144:ef7eb2e8f9f7	2401	SET_BIT(RCC->CR, RCC_CR_MSION);
<>	144:ef7eb2e8f9f7	2402	}
<>	144:ef7eb2e8f9f7	2403
<>	144:ef7eb2e8f9f7	2404	/**
<>	144:ef7eb2e8f9f7	2405	* @brief Disable MSI oscillator
<>	144:ef7eb2e8f9f7	2406	* @rmtoll CR MSION LL_RCC_MSI_Disable
<>	144:ef7eb2e8f9f7	2407	* @retval None
<>	144:ef7eb2e8f9f7	2408	*/
<>	144:ef7eb2e8f9f7	2409	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
<>	144:ef7eb2e8f9f7	2410	{
<>	144:ef7eb2e8f9f7	2411	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
<>	144:ef7eb2e8f9f7	2412	}
<>	144:ef7eb2e8f9f7	2413
<>	144:ef7eb2e8f9f7	2414	/**
<>	144:ef7eb2e8f9f7	2415	* @brief Check if MSI oscillator Ready
<>	144:ef7eb2e8f9f7	2416	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
<>	144:ef7eb2e8f9f7	2417	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2418	*/
<>	144:ef7eb2e8f9f7	2419	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
<>	144:ef7eb2e8f9f7	2420	{
<>	144:ef7eb2e8f9f7	2421	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
<>	144:ef7eb2e8f9f7	2422	}
<>	144:ef7eb2e8f9f7	2423
<>	144:ef7eb2e8f9f7	2424	/**
<>	144:ef7eb2e8f9f7	2425	* @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
<>	144:ef7eb2e8f9f7	2426	* @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
<>	144:ef7eb2e8f9f7	2427	* and ready (LSERDY set by hardware)
<>	144:ef7eb2e8f9f7	2428	* @note hardware protection to avoid enabling MSIPLLEN if LSE is not
<>	144:ef7eb2e8f9f7	2429	* ready
<>	144:ef7eb2e8f9f7	2430	* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
<>	144:ef7eb2e8f9f7	2431	* @retval None
<>	144:ef7eb2e8f9f7	2432	*/
<>	144:ef7eb2e8f9f7	2433	__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
<>	144:ef7eb2e8f9f7	2434	{
<>	144:ef7eb2e8f9f7	2435	SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
<>	144:ef7eb2e8f9f7	2436	}
<>	144:ef7eb2e8f9f7	2437
<>	144:ef7eb2e8f9f7	2438	/**
<>	144:ef7eb2e8f9f7	2439	* @brief Disable MSI-PLL mode
<>	144:ef7eb2e8f9f7	2440	* @note cleared by hardware when LSE is disabled (LSEON = 0) or when
<>	144:ef7eb2e8f9f7	2441	* the Clock Security System on LSE detects a LSE failure
<>	144:ef7eb2e8f9f7	2442	* @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
<>	144:ef7eb2e8f9f7	2443	* @retval None
<>	144:ef7eb2e8f9f7	2444	*/
<>	144:ef7eb2e8f9f7	2445	__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
<>	144:ef7eb2e8f9f7	2446	{
<>	144:ef7eb2e8f9f7	2447	CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
<>	144:ef7eb2e8f9f7	2448	}
<>	144:ef7eb2e8f9f7	2449
<>	144:ef7eb2e8f9f7	2450	/**
<>	144:ef7eb2e8f9f7	2451	* @brief Enable MSI clock range selection with MSIRANGE register
<>	144:ef7eb2e8f9f7	2452	* @note Write 0 has no effect. After a standby or a reset
<>	144:ef7eb2e8f9f7	2453	* MSIRGSEL is at 0 and the MSI range value is provided by
<>	144:ef7eb2e8f9f7	2454	* MSISRANGE
<>	144:ef7eb2e8f9f7	2455	* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
<>	144:ef7eb2e8f9f7	2456	* @retval None
<>	144:ef7eb2e8f9f7	2457	*/
<>	144:ef7eb2e8f9f7	2458	__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
<>	144:ef7eb2e8f9f7	2459	{
<>	144:ef7eb2e8f9f7	2460	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
<>	144:ef7eb2e8f9f7	2461	}
<>	144:ef7eb2e8f9f7	2462
<>	144:ef7eb2e8f9f7	2463	/**
<>	144:ef7eb2e8f9f7	2464	* @brief Check if MSI clock range is selected with MSIRANGE register
<>	144:ef7eb2e8f9f7	2465	* @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
<>	144:ef7eb2e8f9f7	2466	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2467	*/
<>	144:ef7eb2e8f9f7	2468	__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
<>	144:ef7eb2e8f9f7	2469	{
<>	144:ef7eb2e8f9f7	2470	return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
<>	144:ef7eb2e8f9f7	2471	}
<>	144:ef7eb2e8f9f7	2472
<>	144:ef7eb2e8f9f7	2473	/**
<>	144:ef7eb2e8f9f7	2474	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
<>	144:ef7eb2e8f9f7	2475	* @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
<>	144:ef7eb2e8f9f7	2476	* @param Range This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2477	* @arg @ref LL_RCC_MSIRANGE_0
<>	144:ef7eb2e8f9f7	2478	* @arg @ref LL_RCC_MSIRANGE_1
<>	144:ef7eb2e8f9f7	2479	* @arg @ref LL_RCC_MSIRANGE_2
<>	144:ef7eb2e8f9f7	2480	* @arg @ref LL_RCC_MSIRANGE_3
<>	144:ef7eb2e8f9f7	2481	* @arg @ref LL_RCC_MSIRANGE_4
<>	144:ef7eb2e8f9f7	2482	* @arg @ref LL_RCC_MSIRANGE_5
<>	144:ef7eb2e8f9f7	2483	* @arg @ref LL_RCC_MSIRANGE_6
<>	144:ef7eb2e8f9f7	2484	* @arg @ref LL_RCC_MSIRANGE_7
<>	144:ef7eb2e8f9f7	2485	* @arg @ref LL_RCC_MSIRANGE_8
<>	144:ef7eb2e8f9f7	2486	* @arg @ref LL_RCC_MSIRANGE_9
<>	144:ef7eb2e8f9f7	2487	* @arg @ref LL_RCC_MSIRANGE_10
<>	144:ef7eb2e8f9f7	2488	* @arg @ref LL_RCC_MSIRANGE_11
<>	144:ef7eb2e8f9f7	2489	* @retval None
<>	144:ef7eb2e8f9f7	2490	*/
<>	144:ef7eb2e8f9f7	2491	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
<>	144:ef7eb2e8f9f7	2492	{
<>	144:ef7eb2e8f9f7	2493	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
<>	144:ef7eb2e8f9f7	2494	}
<>	144:ef7eb2e8f9f7	2495
<>	144:ef7eb2e8f9f7	2496	/**
<>	144:ef7eb2e8f9f7	2497	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
<>	144:ef7eb2e8f9f7	2498	* @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
<>	144:ef7eb2e8f9f7	2499	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2500	* @arg @ref LL_RCC_MSIRANGE_0
<>	144:ef7eb2e8f9f7	2501	* @arg @ref LL_RCC_MSIRANGE_1
<>	144:ef7eb2e8f9f7	2502	* @arg @ref LL_RCC_MSIRANGE_2
<>	144:ef7eb2e8f9f7	2503	* @arg @ref LL_RCC_MSIRANGE_3
<>	144:ef7eb2e8f9f7	2504	* @arg @ref LL_RCC_MSIRANGE_4
<>	144:ef7eb2e8f9f7	2505	* @arg @ref LL_RCC_MSIRANGE_5
<>	144:ef7eb2e8f9f7	2506	* @arg @ref LL_RCC_MSIRANGE_6
<>	144:ef7eb2e8f9f7	2507	* @arg @ref LL_RCC_MSIRANGE_7
<>	144:ef7eb2e8f9f7	2508	* @arg @ref LL_RCC_MSIRANGE_8
<>	144:ef7eb2e8f9f7	2509	* @arg @ref LL_RCC_MSIRANGE_9
<>	144:ef7eb2e8f9f7	2510	* @arg @ref LL_RCC_MSIRANGE_10
<>	144:ef7eb2e8f9f7	2511	* @arg @ref LL_RCC_MSIRANGE_11
<>	144:ef7eb2e8f9f7	2512	*/
<>	144:ef7eb2e8f9f7	2513	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
<>	144:ef7eb2e8f9f7	2514	{
<>	144:ef7eb2e8f9f7	2515	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
<>	144:ef7eb2e8f9f7	2516	}
<>	144:ef7eb2e8f9f7	2517
<>	144:ef7eb2e8f9f7	2518	/**
<>	144:ef7eb2e8f9f7	2519	* @brief Configure MSI range used after standby
<>	144:ef7eb2e8f9f7	2520	* @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
<>	144:ef7eb2e8f9f7	2521	* @param Range This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2522	* @arg @ref LL_RCC_MSISRANGE_4
<>	144:ef7eb2e8f9f7	2523	* @arg @ref LL_RCC_MSISRANGE_5
<>	144:ef7eb2e8f9f7	2524	* @arg @ref LL_RCC_MSISRANGE_6
<>	144:ef7eb2e8f9f7	2525	* @arg @ref LL_RCC_MSISRANGE_7
<>	144:ef7eb2e8f9f7	2526	* @retval None
<>	144:ef7eb2e8f9f7	2527	*/
<>	144:ef7eb2e8f9f7	2528	__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
<>	144:ef7eb2e8f9f7	2529	{
<>	144:ef7eb2e8f9f7	2530	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
<>	144:ef7eb2e8f9f7	2531	}
<>	144:ef7eb2e8f9f7	2532
<>	144:ef7eb2e8f9f7	2533	/**
<>	144:ef7eb2e8f9f7	2534	* @brief Get MSI range used after standby
<>	144:ef7eb2e8f9f7	2535	* @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
<>	144:ef7eb2e8f9f7	2536	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2537	* @arg @ref LL_RCC_MSISRANGE_4
<>	144:ef7eb2e8f9f7	2538	* @arg @ref LL_RCC_MSISRANGE_5
<>	144:ef7eb2e8f9f7	2539	* @arg @ref LL_RCC_MSISRANGE_6
<>	144:ef7eb2e8f9f7	2540	* @arg @ref LL_RCC_MSISRANGE_7
<>	144:ef7eb2e8f9f7	2541	*/
<>	144:ef7eb2e8f9f7	2542	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
<>	144:ef7eb2e8f9f7	2543	{
<>	144:ef7eb2e8f9f7	2544	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
<>	144:ef7eb2e8f9f7	2545	}
<>	144:ef7eb2e8f9f7	2546
<>	144:ef7eb2e8f9f7	2547	/**
<>	144:ef7eb2e8f9f7	2548	* @brief Get MSI Calibration value
<>	144:ef7eb2e8f9f7	2549	* @note When MSITRIM is written, MSICAL is updated with the sum of
<>	144:ef7eb2e8f9f7	2550	* MSITRIM and the factory trim value
<>	144:ef7eb2e8f9f7	2551	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
<>	144:ef7eb2e8f9f7	2552	* @retval Between Min_Data = 0 and Max_Data = 255
<>	144:ef7eb2e8f9f7	2553	*/
<>	144:ef7eb2e8f9f7	2554	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
<>	144:ef7eb2e8f9f7	2555	{
AnnaBridge	167:e84263d55307	2556	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
<>	144:ef7eb2e8f9f7	2557	}
<>	144:ef7eb2e8f9f7	2558
<>	144:ef7eb2e8f9f7	2559	/**
<>	144:ef7eb2e8f9f7	2560	* @brief Set MSI Calibration trimming
<>	144:ef7eb2e8f9f7	2561	* @note user-programmable trimming value that is added to the MSICAL
<>	144:ef7eb2e8f9f7	2562	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
<>	144:ef7eb2e8f9f7	2563	* @param Value Between Min_Data = 0 and Max_Data = 255
<>	144:ef7eb2e8f9f7	2564	* @retval None
<>	144:ef7eb2e8f9f7	2565	*/
<>	144:ef7eb2e8f9f7	2566	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
<>	144:ef7eb2e8f9f7	2567	{
AnnaBridge	167:e84263d55307	2568	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
<>	144:ef7eb2e8f9f7	2569	}
<>	144:ef7eb2e8f9f7	2570
<>	144:ef7eb2e8f9f7	2571	/**
<>	144:ef7eb2e8f9f7	2572	* @brief Get MSI Calibration trimming
<>	144:ef7eb2e8f9f7	2573	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
<>	144:ef7eb2e8f9f7	2574	* @retval Between 0 and 255
<>	144:ef7eb2e8f9f7	2575	*/
<>	144:ef7eb2e8f9f7	2576	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
<>	144:ef7eb2e8f9f7	2577	{
AnnaBridge	167:e84263d55307	2578	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
<>	144:ef7eb2e8f9f7	2579	}
<>	144:ef7eb2e8f9f7	2580
<>	144:ef7eb2e8f9f7	2581	/**
<>	144:ef7eb2e8f9f7	2582	* @}
<>	144:ef7eb2e8f9f7	2583	*/
<>	144:ef7eb2e8f9f7	2584
<>	144:ef7eb2e8f9f7	2585	/** @defgroup RCC_LL_EF_LSCO LSCO
<>	144:ef7eb2e8f9f7	2586	* @{
<>	144:ef7eb2e8f9f7	2587	*/
<>	144:ef7eb2e8f9f7	2588
<>	144:ef7eb2e8f9f7	2589	/**
<>	144:ef7eb2e8f9f7	2590	* @brief Enable Low speed clock
<>	144:ef7eb2e8f9f7	2591	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
<>	144:ef7eb2e8f9f7	2592	* @retval None
<>	144:ef7eb2e8f9f7	2593	*/
<>	144:ef7eb2e8f9f7	2594	__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
<>	144:ef7eb2e8f9f7	2595	{
<>	144:ef7eb2e8f9f7	2596	SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
<>	144:ef7eb2e8f9f7	2597	}
<>	144:ef7eb2e8f9f7	2598
<>	144:ef7eb2e8f9f7	2599	/**
<>	144:ef7eb2e8f9f7	2600	* @brief Disable Low speed clock
<>	144:ef7eb2e8f9f7	2601	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
<>	144:ef7eb2e8f9f7	2602	* @retval None
<>	144:ef7eb2e8f9f7	2603	*/
<>	144:ef7eb2e8f9f7	2604	__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
<>	144:ef7eb2e8f9f7	2605	{
<>	144:ef7eb2e8f9f7	2606	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
<>	144:ef7eb2e8f9f7	2607	}
<>	144:ef7eb2e8f9f7	2608
<>	144:ef7eb2e8f9f7	2609	/**
<>	144:ef7eb2e8f9f7	2610	* @brief Configure Low speed clock selection
<>	144:ef7eb2e8f9f7	2611	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
<>	144:ef7eb2e8f9f7	2612	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2613	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	2614	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2615	* @retval None
<>	144:ef7eb2e8f9f7	2616	*/
<>	144:ef7eb2e8f9f7	2617	__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
<>	144:ef7eb2e8f9f7	2618	{
<>	144:ef7eb2e8f9f7	2619	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
<>	144:ef7eb2e8f9f7	2620	}
<>	144:ef7eb2e8f9f7	2621
<>	144:ef7eb2e8f9f7	2622	/**
<>	144:ef7eb2e8f9f7	2623	* @brief Get Low speed clock selection
<>	144:ef7eb2e8f9f7	2624	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
<>	144:ef7eb2e8f9f7	2625	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2626	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	2627	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2628	*/
<>	144:ef7eb2e8f9f7	2629	__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
<>	144:ef7eb2e8f9f7	2630	{
<>	144:ef7eb2e8f9f7	2631	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
<>	144:ef7eb2e8f9f7	2632	}
<>	144:ef7eb2e8f9f7	2633
<>	144:ef7eb2e8f9f7	2634	/**
<>	144:ef7eb2e8f9f7	2635	* @}
<>	144:ef7eb2e8f9f7	2636	*/
<>	144:ef7eb2e8f9f7	2637
<>	144:ef7eb2e8f9f7	2638	/** @defgroup RCC_LL_EF_System System
<>	144:ef7eb2e8f9f7	2639	* @{
<>	144:ef7eb2e8f9f7	2640	*/
<>	144:ef7eb2e8f9f7	2641
<>	144:ef7eb2e8f9f7	2642	/**
<>	144:ef7eb2e8f9f7	2643	* @brief Configure the system clock source
<>	144:ef7eb2e8f9f7	2644	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
<>	144:ef7eb2e8f9f7	2645	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2646	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
<>	144:ef7eb2e8f9f7	2647	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2648	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
<>	144:ef7eb2e8f9f7	2649	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	2650	* @retval None
<>	144:ef7eb2e8f9f7	2651	*/
<>	144:ef7eb2e8f9f7	2652	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
<>	144:ef7eb2e8f9f7	2653	{
<>	144:ef7eb2e8f9f7	2654	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
<>	144:ef7eb2e8f9f7	2655	}
<>	144:ef7eb2e8f9f7	2656
<>	144:ef7eb2e8f9f7	2657	/**
<>	144:ef7eb2e8f9f7	2658	* @brief Get the system clock source
<>	144:ef7eb2e8f9f7	2659	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
<>	144:ef7eb2e8f9f7	2660	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2661	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
<>	144:ef7eb2e8f9f7	2662	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
<>	144:ef7eb2e8f9f7	2663	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
<>	144:ef7eb2e8f9f7	2664	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
<>	144:ef7eb2e8f9f7	2665	*/
<>	144:ef7eb2e8f9f7	2666	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
<>	144:ef7eb2e8f9f7	2667	{
<>	144:ef7eb2e8f9f7	2668	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
<>	144:ef7eb2e8f9f7	2669	}
<>	144:ef7eb2e8f9f7	2670
<>	144:ef7eb2e8f9f7	2671	/**
<>	144:ef7eb2e8f9f7	2672	* @brief Set AHB prescaler
<>	144:ef7eb2e8f9f7	2673	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
<>	144:ef7eb2e8f9f7	2674	* @param Prescaler This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2675	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	144:ef7eb2e8f9f7	2676	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	144:ef7eb2e8f9f7	2677	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	144:ef7eb2e8f9f7	2678	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	144:ef7eb2e8f9f7	2679	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	144:ef7eb2e8f9f7	2680	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	144:ef7eb2e8f9f7	2681	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	144:ef7eb2e8f9f7	2682	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	144:ef7eb2e8f9f7	2683	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	144:ef7eb2e8f9f7	2684	* @retval None
<>	144:ef7eb2e8f9f7	2685	*/
<>	144:ef7eb2e8f9f7	2686	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
<>	144:ef7eb2e8f9f7	2687	{
<>	144:ef7eb2e8f9f7	2688	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
<>	144:ef7eb2e8f9f7	2689	}
<>	144:ef7eb2e8f9f7	2690
<>	144:ef7eb2e8f9f7	2691	/**
<>	144:ef7eb2e8f9f7	2692	* @brief Set APB1 prescaler
<>	144:ef7eb2e8f9f7	2693	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
<>	144:ef7eb2e8f9f7	2694	* @param Prescaler This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2695	* @arg @ref LL_RCC_APB1_DIV_1
<>	144:ef7eb2e8f9f7	2696	* @arg @ref LL_RCC_APB1_DIV_2
<>	144:ef7eb2e8f9f7	2697	* @arg @ref LL_RCC_APB1_DIV_4
<>	144:ef7eb2e8f9f7	2698	* @arg @ref LL_RCC_APB1_DIV_8
<>	144:ef7eb2e8f9f7	2699	* @arg @ref LL_RCC_APB1_DIV_16
<>	144:ef7eb2e8f9f7	2700	* @retval None
<>	144:ef7eb2e8f9f7	2701	*/
<>	144:ef7eb2e8f9f7	2702	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
<>	144:ef7eb2e8f9f7	2703	{
<>	144:ef7eb2e8f9f7	2704	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
<>	144:ef7eb2e8f9f7	2705	}
<>	144:ef7eb2e8f9f7	2706
<>	144:ef7eb2e8f9f7	2707	/**
<>	144:ef7eb2e8f9f7	2708	* @brief Set APB2 prescaler
<>	144:ef7eb2e8f9f7	2709	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
<>	144:ef7eb2e8f9f7	2710	* @param Prescaler This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2711	* @arg @ref LL_RCC_APB2_DIV_1
<>	144:ef7eb2e8f9f7	2712	* @arg @ref LL_RCC_APB2_DIV_2
<>	144:ef7eb2e8f9f7	2713	* @arg @ref LL_RCC_APB2_DIV_4
<>	144:ef7eb2e8f9f7	2714	* @arg @ref LL_RCC_APB2_DIV_8
<>	144:ef7eb2e8f9f7	2715	* @arg @ref LL_RCC_APB2_DIV_16
<>	144:ef7eb2e8f9f7	2716	* @retval None
<>	144:ef7eb2e8f9f7	2717	*/
<>	144:ef7eb2e8f9f7	2718	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
<>	144:ef7eb2e8f9f7	2719	{
<>	144:ef7eb2e8f9f7	2720	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
<>	144:ef7eb2e8f9f7	2721	}
<>	144:ef7eb2e8f9f7	2722
<>	144:ef7eb2e8f9f7	2723	/**
<>	144:ef7eb2e8f9f7	2724	* @brief Get AHB prescaler
<>	144:ef7eb2e8f9f7	2725	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
<>	144:ef7eb2e8f9f7	2726	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2727	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	144:ef7eb2e8f9f7	2728	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	144:ef7eb2e8f9f7	2729	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	144:ef7eb2e8f9f7	2730	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	144:ef7eb2e8f9f7	2731	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	144:ef7eb2e8f9f7	2732	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	144:ef7eb2e8f9f7	2733	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	144:ef7eb2e8f9f7	2734	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	144:ef7eb2e8f9f7	2735	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	144:ef7eb2e8f9f7	2736	*/
<>	144:ef7eb2e8f9f7	2737	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
<>	144:ef7eb2e8f9f7	2738	{
<>	144:ef7eb2e8f9f7	2739	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
<>	144:ef7eb2e8f9f7	2740	}
<>	144:ef7eb2e8f9f7	2741
<>	144:ef7eb2e8f9f7	2742	/**
<>	144:ef7eb2e8f9f7	2743	* @brief Get APB1 prescaler
<>	144:ef7eb2e8f9f7	2744	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
<>	144:ef7eb2e8f9f7	2745	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2746	* @arg @ref LL_RCC_APB1_DIV_1
<>	144:ef7eb2e8f9f7	2747	* @arg @ref LL_RCC_APB1_DIV_2
<>	144:ef7eb2e8f9f7	2748	* @arg @ref LL_RCC_APB1_DIV_4
<>	144:ef7eb2e8f9f7	2749	* @arg @ref LL_RCC_APB1_DIV_8
<>	144:ef7eb2e8f9f7	2750	* @arg @ref LL_RCC_APB1_DIV_16
<>	144:ef7eb2e8f9f7	2751	*/
<>	144:ef7eb2e8f9f7	2752	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
<>	144:ef7eb2e8f9f7	2753	{
<>	144:ef7eb2e8f9f7	2754	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
<>	144:ef7eb2e8f9f7	2755	}
<>	144:ef7eb2e8f9f7	2756
<>	144:ef7eb2e8f9f7	2757	/**
<>	144:ef7eb2e8f9f7	2758	* @brief Get APB2 prescaler
<>	144:ef7eb2e8f9f7	2759	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
<>	144:ef7eb2e8f9f7	2760	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2761	* @arg @ref LL_RCC_APB2_DIV_1
<>	144:ef7eb2e8f9f7	2762	* @arg @ref LL_RCC_APB2_DIV_2
<>	144:ef7eb2e8f9f7	2763	* @arg @ref LL_RCC_APB2_DIV_4
<>	144:ef7eb2e8f9f7	2764	* @arg @ref LL_RCC_APB2_DIV_8
<>	144:ef7eb2e8f9f7	2765	* @arg @ref LL_RCC_APB2_DIV_16
<>	144:ef7eb2e8f9f7	2766	*/
<>	144:ef7eb2e8f9f7	2767	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
<>	144:ef7eb2e8f9f7	2768	{
<>	144:ef7eb2e8f9f7	2769	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
<>	144:ef7eb2e8f9f7	2770	}
<>	144:ef7eb2e8f9f7	2771
<>	144:ef7eb2e8f9f7	2772	/**
<>	144:ef7eb2e8f9f7	2773	* @brief Set Clock After Wake-Up From Stop mode
<>	144:ef7eb2e8f9f7	2774	* @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
<>	144:ef7eb2e8f9f7	2775	* @param Clock This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2776	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
<>	144:ef7eb2e8f9f7	2777	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
<>	144:ef7eb2e8f9f7	2778	* @retval None
<>	144:ef7eb2e8f9f7	2779	*/
<>	144:ef7eb2e8f9f7	2780	__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
<>	144:ef7eb2e8f9f7	2781	{
<>	144:ef7eb2e8f9f7	2782	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
<>	144:ef7eb2e8f9f7	2783	}
<>	144:ef7eb2e8f9f7	2784
<>	144:ef7eb2e8f9f7	2785	/**
<>	144:ef7eb2e8f9f7	2786	* @brief Get Clock After Wake-Up From Stop mode
<>	144:ef7eb2e8f9f7	2787	* @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
<>	144:ef7eb2e8f9f7	2788	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2789	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
<>	144:ef7eb2e8f9f7	2790	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
<>	144:ef7eb2e8f9f7	2791	*/
<>	144:ef7eb2e8f9f7	2792	__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
<>	144:ef7eb2e8f9f7	2793	{
<>	144:ef7eb2e8f9f7	2794	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
<>	144:ef7eb2e8f9f7	2795	}
<>	144:ef7eb2e8f9f7	2796
<>	144:ef7eb2e8f9f7	2797	/**
<>	144:ef7eb2e8f9f7	2798	* @}
<>	144:ef7eb2e8f9f7	2799	*/
<>	144:ef7eb2e8f9f7	2800
<>	144:ef7eb2e8f9f7	2801	/** @defgroup RCC_LL_EF_MCO MCO
<>	144:ef7eb2e8f9f7	2802	* @{
<>	144:ef7eb2e8f9f7	2803	*/
<>	144:ef7eb2e8f9f7	2804
<>	144:ef7eb2e8f9f7	2805	/**
<>	144:ef7eb2e8f9f7	2806	* @brief Configure MCOx
<>	144:ef7eb2e8f9f7	2807	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
<>	144:ef7eb2e8f9f7	2808	* CFGR MCOPRE LL_RCC_ConfigMCO
<>	144:ef7eb2e8f9f7	2809	* @param MCOxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2810	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
<>	144:ef7eb2e8f9f7	2811	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2812	* @arg @ref LL_RCC_MCO1SOURCE_MSI
<>	144:ef7eb2e8f9f7	2813	* @arg @ref LL_RCC_MCO1SOURCE_HSI
<>	144:ef7eb2e8f9f7	2814	* @arg @ref LL_RCC_MCO1SOURCE_HSE
<>	144:ef7eb2e8f9f7	2815	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
<>	144:ef7eb2e8f9f7	2816	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
<>	144:ef7eb2e8f9f7	2817	* @arg @ref LL_RCC_MCO1SOURCE_LSI
<>	144:ef7eb2e8f9f7	2818	* @arg @ref LL_RCC_MCO1SOURCE_LSE
<>	144:ef7eb2e8f9f7	2819	*
<>	144:ef7eb2e8f9f7	2820	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	2821	* @param MCOxPrescaler This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2822	* @arg @ref LL_RCC_MCO1_DIV_1
<>	144:ef7eb2e8f9f7	2823	* @arg @ref LL_RCC_MCO1_DIV_2
<>	144:ef7eb2e8f9f7	2824	* @arg @ref LL_RCC_MCO1_DIV_4
<>	144:ef7eb2e8f9f7	2825	* @arg @ref LL_RCC_MCO1_DIV_8
<>	144:ef7eb2e8f9f7	2826	* @arg @ref LL_RCC_MCO1_DIV_16
<>	144:ef7eb2e8f9f7	2827	* @retval None
<>	144:ef7eb2e8f9f7	2828	*/
<>	144:ef7eb2e8f9f7	2829	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
<>	144:ef7eb2e8f9f7	2830	{
<>	144:ef7eb2e8f9f7	2831	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
<>	144:ef7eb2e8f9f7	2832	}
<>	144:ef7eb2e8f9f7	2833
<>	144:ef7eb2e8f9f7	2834	/**
<>	144:ef7eb2e8f9f7	2835	* @}
<>	144:ef7eb2e8f9f7	2836	*/
<>	144:ef7eb2e8f9f7	2837
<>	144:ef7eb2e8f9f7	2838	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
<>	144:ef7eb2e8f9f7	2839	* @{
<>	144:ef7eb2e8f9f7	2840	*/
<>	144:ef7eb2e8f9f7	2841
<>	144:ef7eb2e8f9f7	2842	/**
<>	144:ef7eb2e8f9f7	2843	* @brief Configure USARTx clock source
<>	144:ef7eb2e8f9f7	2844	* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
<>	144:ef7eb2e8f9f7	2845	* @param USARTxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2846	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
<>	144:ef7eb2e8f9f7	2847	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2848	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2849	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2850	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2851	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2852	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2853	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2854	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
<>	144:ef7eb2e8f9f7	2855	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
<>	144:ef7eb2e8f9f7	2856	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
<>	144:ef7eb2e8f9f7	2857	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
<>	144:ef7eb2e8f9f7	2858	*
<>	144:ef7eb2e8f9f7	2859	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	2860	* @retval None
<>	144:ef7eb2e8f9f7	2861	*/
<>	144:ef7eb2e8f9f7	2862	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
<>	144:ef7eb2e8f9f7	2863	{
<>	144:ef7eb2e8f9f7	2864	MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
<>	144:ef7eb2e8f9f7	2865	}
<>	144:ef7eb2e8f9f7	2866
<>	144:ef7eb2e8f9f7	2867	#if defined(UART4) \|\| defined(UART5)
<>	144:ef7eb2e8f9f7	2868	/**
<>	144:ef7eb2e8f9f7	2869	* @brief Configure UARTx clock source
<>	144:ef7eb2e8f9f7	2870	* @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
<>	144:ef7eb2e8f9f7	2871	* @param UARTxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2872	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2873	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2874	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2875	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2876	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2877	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2878	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2879	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2880	* @retval None
<>	144:ef7eb2e8f9f7	2881	*/
<>	144:ef7eb2e8f9f7	2882	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
<>	144:ef7eb2e8f9f7	2883	{
<>	144:ef7eb2e8f9f7	2884	MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
<>	144:ef7eb2e8f9f7	2885	}
<>	144:ef7eb2e8f9f7	2886	#endif /* UART4 \|\| UART5 */
<>	144:ef7eb2e8f9f7	2887
<>	144:ef7eb2e8f9f7	2888	/**
<>	144:ef7eb2e8f9f7	2889	* @brief Configure LPUART1x clock source
<>	144:ef7eb2e8f9f7	2890	* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
<>	144:ef7eb2e8f9f7	2891	* @param LPUARTxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2892	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2893	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2894	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2895	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2896	* @retval None
<>	144:ef7eb2e8f9f7	2897	*/
<>	144:ef7eb2e8f9f7	2898	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
<>	144:ef7eb2e8f9f7	2899	{
<>	144:ef7eb2e8f9f7	2900	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
<>	144:ef7eb2e8f9f7	2901	}
<>	144:ef7eb2e8f9f7	2902
<>	144:ef7eb2e8f9f7	2903	/**
<>	144:ef7eb2e8f9f7	2904	* @brief Configure I2Cx clock source
<>	144:ef7eb2e8f9f7	2905	* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
<>	144:ef7eb2e8f9f7	2906	* @param I2CxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2907	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2908	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2909	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2910	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
<>	144:ef7eb2e8f9f7	2911	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
<>	144:ef7eb2e8f9f7	2912	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
<>	144:ef7eb2e8f9f7	2913	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2914	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2915	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	167:e84263d55307	2916	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	167:e84263d55307	2917	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	167:e84263d55307	2918	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
<>	144:ef7eb2e8f9f7	2919	*
<>	144:ef7eb2e8f9f7	2920	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	2921	* @retval None
<>	144:ef7eb2e8f9f7	2922	*/
<>	144:ef7eb2e8f9f7	2923	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
<>	144:ef7eb2e8f9f7	2924	{
AnnaBridge	181:57724642e740	2925	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
AnnaBridge	167:e84263d55307	2926	MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
<>	144:ef7eb2e8f9f7	2927	}
<>	144:ef7eb2e8f9f7	2928
<>	144:ef7eb2e8f9f7	2929	/**
<>	144:ef7eb2e8f9f7	2930	* @brief Configure LPTIMx clock source
<>	144:ef7eb2e8f9f7	2931	* @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
<>	144:ef7eb2e8f9f7	2932	* @param LPTIMxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2933	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2934	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	2935	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2936	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2937	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	2938	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	2939	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	2940	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	2941	* @retval None
<>	144:ef7eb2e8f9f7	2942	*/
<>	144:ef7eb2e8f9f7	2943	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
<>	144:ef7eb2e8f9f7	2944	{
AnnaBridge	167:e84263d55307	2945	MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
<>	144:ef7eb2e8f9f7	2946	}
<>	144:ef7eb2e8f9f7	2947
<>	144:ef7eb2e8f9f7	2948	/**
<>	144:ef7eb2e8f9f7	2949	* @brief Configure SAIx clock source
AnnaBridge	181:57724642e740	2950	@if STM32L4S9xx
AnnaBridge	181:57724642e740	2951	* @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource
AnnaBridge	181:57724642e740	2952	@else
<>	144:ef7eb2e8f9f7	2953	* @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
AnnaBridge	181:57724642e740	2954	@endif
<>	144:ef7eb2e8f9f7	2955	* @param SAIxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2956	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	2957	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
<>	144:ef7eb2e8f9f7	2958	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	2959	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
<>	144:ef7eb2e8f9f7	2960	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
<>	144:ef7eb2e8f9f7	2961	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
<>	144:ef7eb2e8f9f7	2962	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
<>	144:ef7eb2e8f9f7	2963	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
<>	144:ef7eb2e8f9f7	2964	*
<>	144:ef7eb2e8f9f7	2965	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	2966	* @retval None
<>	144:ef7eb2e8f9f7	2967	*/
<>	144:ef7eb2e8f9f7	2968	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
<>	144:ef7eb2e8f9f7	2969	{
AnnaBridge	181:57724642e740	2970	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	181:57724642e740	2971	MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
AnnaBridge	181:57724642e740	2972	#else
AnnaBridge	167:e84263d55307	2973	MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
AnnaBridge	181:57724642e740	2974	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	181:57724642e740	2975	}
AnnaBridge	181:57724642e740	2976
AnnaBridge	181:57724642e740	2977	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	181:57724642e740	2978	/**
AnnaBridge	181:57724642e740	2979	* @brief Configure SDMMC1 kernel clock source
AnnaBridge	181:57724642e740	2980	* @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
AnnaBridge	181:57724642e740	2981	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	181:57724642e740	2982	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
AnnaBridge	181:57724642e740	2983	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
AnnaBridge	181:57724642e740	2984	*
AnnaBridge	181:57724642e740	2985	* (*) value not defined in all devices.
AnnaBridge	181:57724642e740	2986	* @retval None
AnnaBridge	181:57724642e740	2987	*/
AnnaBridge	181:57724642e740	2988	__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
AnnaBridge	181:57724642e740	2989	{
AnnaBridge	181:57724642e740	2990	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
AnnaBridge	181:57724642e740	2991	}
AnnaBridge	181:57724642e740	2992	#endif /* RCC_CCIPR2_SDMMCSEL */
<>	144:ef7eb2e8f9f7	2993
<>	144:ef7eb2e8f9f7	2994	/**
<>	144:ef7eb2e8f9f7	2995	* @brief Configure SDMMC1 clock source
<>	144:ef7eb2e8f9f7	2996	* @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
<>	144:ef7eb2e8f9f7	2997	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2998	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	167:e84263d55307	2999	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
AnnaBridge	167:e84263d55307	3000	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
<>	144:ef7eb2e8f9f7	3001	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
AnnaBridge	181:57724642e740	3002	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
AnnaBridge	167:e84263d55307	3003	*
AnnaBridge	167:e84263d55307	3004	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3005	* @retval None
<>	144:ef7eb2e8f9f7	3006	*/
<>	144:ef7eb2e8f9f7	3007	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
<>	144:ef7eb2e8f9f7	3008	{
<>	144:ef7eb2e8f9f7	3009	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
<>	144:ef7eb2e8f9f7	3010	}
<>	144:ef7eb2e8f9f7	3011
<>	144:ef7eb2e8f9f7	3012	/**
<>	144:ef7eb2e8f9f7	3013	* @brief Configure RNG clock source
<>	144:ef7eb2e8f9f7	3014	* @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
<>	144:ef7eb2e8f9f7	3015	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	3016	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	167:e84263d55307	3017	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
<>	144:ef7eb2e8f9f7	3018	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	3019	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	3020	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	167:e84263d55307	3021	*
AnnaBridge	167:e84263d55307	3022	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3023	* @retval None
<>	144:ef7eb2e8f9f7	3024	*/
<>	144:ef7eb2e8f9f7	3025	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
<>	144:ef7eb2e8f9f7	3026	{
<>	144:ef7eb2e8f9f7	3027	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
<>	144:ef7eb2e8f9f7	3028	}
<>	144:ef7eb2e8f9f7	3029
<>	144:ef7eb2e8f9f7	3030	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	144:ef7eb2e8f9f7	3031	/**
<>	144:ef7eb2e8f9f7	3032	* @brief Configure USB clock source
<>	144:ef7eb2e8f9f7	3033	* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
<>	144:ef7eb2e8f9f7	3034	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	3035	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	167:e84263d55307	3036	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
<>	144:ef7eb2e8f9f7	3037	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	3038	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	3039	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	167:e84263d55307	3040	*
AnnaBridge	167:e84263d55307	3041	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3042	* @retval None
<>	144:ef7eb2e8f9f7	3043	*/
<>	144:ef7eb2e8f9f7	3044	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
<>	144:ef7eb2e8f9f7	3045	{
<>	144:ef7eb2e8f9f7	3046	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
<>	144:ef7eb2e8f9f7	3047	}
<>	144:ef7eb2e8f9f7	3048	#endif /* USB_OTG_FS \|\| USB */
<>	144:ef7eb2e8f9f7	3049
<>	144:ef7eb2e8f9f7	3050	/**
<>	144:ef7eb2e8f9f7	3051	* @brief Configure ADC clock source
<>	144:ef7eb2e8f9f7	3052	* @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
<>	144:ef7eb2e8f9f7	3053	* @param ADCxSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3054	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
<>	144:ef7eb2e8f9f7	3055	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	3056	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
<>	144:ef7eb2e8f9f7	3057	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3058	*
<>	144:ef7eb2e8f9f7	3059	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3060	* @retval None
<>	144:ef7eb2e8f9f7	3061	*/
<>	144:ef7eb2e8f9f7	3062	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
<>	144:ef7eb2e8f9f7	3063	{
<>	144:ef7eb2e8f9f7	3064	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
<>	144:ef7eb2e8f9f7	3065	}
<>	144:ef7eb2e8f9f7	3066
AnnaBridge	167:e84263d55307	3067	#if defined(SWPMI1)
<>	144:ef7eb2e8f9f7	3068	/**
<>	144:ef7eb2e8f9f7	3069	* @brief Configure SWPMI clock source
<>	144:ef7eb2e8f9f7	3070	* @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
<>	144:ef7eb2e8f9f7	3071	* @param SWPMIxSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	3072	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3073	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3074	* @retval None
<>	144:ef7eb2e8f9f7	3075	*/
<>	144:ef7eb2e8f9f7	3076	__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
<>	144:ef7eb2e8f9f7	3077	{
<>	144:ef7eb2e8f9f7	3078	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
<>	144:ef7eb2e8f9f7	3079	}
AnnaBridge	167:e84263d55307	3080	#endif /* SWPMI1 */
<>	144:ef7eb2e8f9f7	3081
<>	144:ef7eb2e8f9f7	3082	#if defined(DFSDM1_Channel0)
AnnaBridge	181:57724642e740	3083	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	181:57724642e740	3084	/**
AnnaBridge	181:57724642e740	3085	* @brief Configure DFSDM Audio clock source
AnnaBridge	181:57724642e740	3086	* @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
AnnaBridge	181:57724642e740	3087	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3088	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	181:57724642e740	3089	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
AnnaBridge	181:57724642e740	3090	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
AnnaBridge	181:57724642e740	3091	* @retval None
AnnaBridge	181:57724642e740	3092	*/
AnnaBridge	181:57724642e740	3093	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
AnnaBridge	181:57724642e740	3094	{
AnnaBridge	181:57724642e740	3095	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
AnnaBridge	181:57724642e740	3096	}
AnnaBridge	181:57724642e740	3097	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	181:57724642e740	3098
<>	144:ef7eb2e8f9f7	3099	/**
AnnaBridge	167:e84263d55307	3100	* @brief Configure DFSDM Kernel clock source
AnnaBridge	181:57724642e740	3101	@if STM32L4S9xx
AnnaBridge	181:57724642e740	3102	* @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	181:57724642e740	3103	@else
<>	144:ef7eb2e8f9f7	3104	* @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	181:57724642e740	3105	@endif
<>	144:ef7eb2e8f9f7	3106	* @param DFSDMxSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	3107	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
<>	144:ef7eb2e8f9f7	3108	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3109	* @retval None
<>	144:ef7eb2e8f9f7	3110	*/
<>	144:ef7eb2e8f9f7	3111	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
<>	144:ef7eb2e8f9f7	3112	{
AnnaBridge	181:57724642e740	3113	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	181:57724642e740	3114	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
AnnaBridge	181:57724642e740	3115	#else
<>	144:ef7eb2e8f9f7	3116	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
AnnaBridge	181:57724642e740	3117	#endif /* RCC_CCIPR2_DFSDM1SEL */
<>	144:ef7eb2e8f9f7	3118	}
<>	144:ef7eb2e8f9f7	3119	#endif /* DFSDM1_Channel0 */
<>	144:ef7eb2e8f9f7	3120
AnnaBridge	181:57724642e740	3121	#if defined(DSI)
AnnaBridge	181:57724642e740	3122	/**
AnnaBridge	181:57724642e740	3123	* @brief Configure DSI clock source
AnnaBridge	181:57724642e740	3124	* @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
AnnaBridge	181:57724642e740	3125	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3126	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	181:57724642e740	3127	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	181:57724642e740	3128	* @retval None
AnnaBridge	181:57724642e740	3129	*/
AnnaBridge	181:57724642e740	3130	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
AnnaBridge	181:57724642e740	3131	{
AnnaBridge	181:57724642e740	3132	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
AnnaBridge	181:57724642e740	3133	}
AnnaBridge	181:57724642e740	3134	#endif /* DSI */
AnnaBridge	181:57724642e740	3135
AnnaBridge	181:57724642e740	3136	#if defined(LTDC)
AnnaBridge	181:57724642e740	3137	/**
AnnaBridge	181:57724642e740	3138	* @brief Configure LTDC Clock Source
AnnaBridge	181:57724642e740	3139	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource
AnnaBridge	181:57724642e740	3140	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3141	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
AnnaBridge	181:57724642e740	3142	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
AnnaBridge	181:57724642e740	3143	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
AnnaBridge	181:57724642e740	3144	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
AnnaBridge	181:57724642e740	3145	* @retval None
AnnaBridge	181:57724642e740	3146	*/
AnnaBridge	181:57724642e740	3147	__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
AnnaBridge	181:57724642e740	3148	{
AnnaBridge	181:57724642e740	3149	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
AnnaBridge	181:57724642e740	3150	}
AnnaBridge	181:57724642e740	3151	#endif /* LTDC */
AnnaBridge	181:57724642e740	3152
AnnaBridge	181:57724642e740	3153	#if defined(OCTOSPI1)
AnnaBridge	181:57724642e740	3154	/**
AnnaBridge	181:57724642e740	3155	* @brief Configure OCTOSPI clock source
AnnaBridge	181:57724642e740	3156	* @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
AnnaBridge	181:57724642e740	3157	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3158	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
AnnaBridge	181:57724642e740	3159	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
AnnaBridge	181:57724642e740	3160	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
AnnaBridge	181:57724642e740	3161	* @retval None
AnnaBridge	181:57724642e740	3162	*/
AnnaBridge	181:57724642e740	3163	__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
AnnaBridge	181:57724642e740	3164	{
AnnaBridge	181:57724642e740	3165	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
AnnaBridge	181:57724642e740	3166	}
AnnaBridge	181:57724642e740	3167	#endif /* OCTOSPI1 */
AnnaBridge	181:57724642e740	3168
<>	144:ef7eb2e8f9f7	3169	/**
<>	144:ef7eb2e8f9f7	3170	* @brief Get USARTx clock source
<>	144:ef7eb2e8f9f7	3171	* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
<>	144:ef7eb2e8f9f7	3172	* @param USARTx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3173	* @arg @ref LL_RCC_USART1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3174	* @arg @ref LL_RCC_USART2_CLKSOURCE
<>	144:ef7eb2e8f9f7	3175	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
<>	144:ef7eb2e8f9f7	3176	*
<>	144:ef7eb2e8f9f7	3177	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3178	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3179	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
<>	144:ef7eb2e8f9f7	3180	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3181	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3182	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3183	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3184	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3185	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3186	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3187	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
<>	144:ef7eb2e8f9f7	3188	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
<>	144:ef7eb2e8f9f7	3189	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
<>	144:ef7eb2e8f9f7	3190	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
<>	144:ef7eb2e8f9f7	3191	*
<>	144:ef7eb2e8f9f7	3192	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3193	*/
<>	144:ef7eb2e8f9f7	3194	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
<>	144:ef7eb2e8f9f7	3195	{
AnnaBridge	167:e84263d55307	3196	return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) \| (USARTx << 16U));
<>	144:ef7eb2e8f9f7	3197	}
<>	144:ef7eb2e8f9f7	3198
<>	144:ef7eb2e8f9f7	3199	#if defined(UART4) \|\| defined(UART5)
<>	144:ef7eb2e8f9f7	3200	/**
<>	144:ef7eb2e8f9f7	3201	* @brief Get UARTx clock source
<>	144:ef7eb2e8f9f7	3202	* @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
<>	144:ef7eb2e8f9f7	3203	* @param UARTx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3204	* @arg @ref LL_RCC_UART4_CLKSOURCE
<>	144:ef7eb2e8f9f7	3205	* @arg @ref LL_RCC_UART5_CLKSOURCE
<>	144:ef7eb2e8f9f7	3206	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3207	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3208	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3209	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3210	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3211	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3212	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3213	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3214	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3215	*/
<>	144:ef7eb2e8f9f7	3216	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
<>	144:ef7eb2e8f9f7	3217	{
AnnaBridge	167:e84263d55307	3218	return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) \| (UARTx << 16U));
<>	144:ef7eb2e8f9f7	3219	}
<>	144:ef7eb2e8f9f7	3220	#endif /* UART4 \|\| UART5 */
<>	144:ef7eb2e8f9f7	3221
<>	144:ef7eb2e8f9f7	3222	/**
<>	144:ef7eb2e8f9f7	3223	* @brief Get LPUARTx clock source
<>	144:ef7eb2e8f9f7	3224	* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
<>	144:ef7eb2e8f9f7	3225	* @param LPUARTx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3226	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3227	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3228	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3229	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3230	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3231	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3232	*/
<>	144:ef7eb2e8f9f7	3233	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
<>	144:ef7eb2e8f9f7	3234	{
<>	144:ef7eb2e8f9f7	3235	return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
<>	144:ef7eb2e8f9f7	3236	}
<>	144:ef7eb2e8f9f7	3237
<>	144:ef7eb2e8f9f7	3238	/**
<>	144:ef7eb2e8f9f7	3239	* @brief Get I2Cx clock source
<>	144:ef7eb2e8f9f7	3240	* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
<>	144:ef7eb2e8f9f7	3241	* @param I2Cx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3242	* @arg @ref LL_RCC_I2C1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3243	* @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
<>	144:ef7eb2e8f9f7	3244	* @arg @ref LL_RCC_I2C3_CLKSOURCE
AnnaBridge	167:e84263d55307	3245	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
<>	144:ef7eb2e8f9f7	3246	*
<>	144:ef7eb2e8f9f7	3247	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3248	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3249	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3250	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3251	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3252	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
<>	144:ef7eb2e8f9f7	3253	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
<>	144:ef7eb2e8f9f7	3254	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
<>	144:ef7eb2e8f9f7	3255	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3256	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3257	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	167:e84263d55307	3258	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	167:e84263d55307	3259	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	167:e84263d55307	3260	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
<>	144:ef7eb2e8f9f7	3261	*
<>	144:ef7eb2e8f9f7	3262	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3263	*/
<>	144:ef7eb2e8f9f7	3264	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
<>	144:ef7eb2e8f9f7	3265	{
AnnaBridge	181:57724642e740	3266	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
AnnaBridge	181:57724642e740	3267	return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) \| (I2Cx & 0xFFFF0000U));
<>	144:ef7eb2e8f9f7	3268	}
<>	144:ef7eb2e8f9f7	3269
<>	144:ef7eb2e8f9f7	3270	/**
<>	144:ef7eb2e8f9f7	3271	* @brief Get LPTIMx clock source
<>	144:ef7eb2e8f9f7	3272	* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
<>	144:ef7eb2e8f9f7	3273	* @param LPTIMx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3274	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3275	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
<>	144:ef7eb2e8f9f7	3276	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3277	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3278	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	3279	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3280	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3281	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3282	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	3283	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3284	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3285	*/
<>	144:ef7eb2e8f9f7	3286	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
<>	144:ef7eb2e8f9f7	3287	{
AnnaBridge	167:e84263d55307	3288	return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U \| LPTIMx);
<>	144:ef7eb2e8f9f7	3289	}
<>	144:ef7eb2e8f9f7	3290
<>	144:ef7eb2e8f9f7	3291	/**
<>	144:ef7eb2e8f9f7	3292	* @brief Get SAIx clock source
AnnaBridge	181:57724642e740	3293	@if STM32L4S9xx
AnnaBridge	181:57724642e740	3294	* @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
AnnaBridge	181:57724642e740	3295	@else
<>	144:ef7eb2e8f9f7	3296	* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
AnnaBridge	181:57724642e740	3297	@endif
<>	144:ef7eb2e8f9f7	3298	* @param SAIx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3299	* @arg @ref LL_RCC_SAI1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3300	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
<>	144:ef7eb2e8f9f7	3301	*
<>	144:ef7eb2e8f9f7	3302	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3303	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3304	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	3305	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
<>	144:ef7eb2e8f9f7	3306	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	3307	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
<>	144:ef7eb2e8f9f7	3308	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
<>	144:ef7eb2e8f9f7	3309	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
<>	144:ef7eb2e8f9f7	3310	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
<>	144:ef7eb2e8f9f7	3311	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
<>	144:ef7eb2e8f9f7	3312	*
<>	144:ef7eb2e8f9f7	3313	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3314	*/
<>	144:ef7eb2e8f9f7	3315	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
<>	144:ef7eb2e8f9f7	3316	{
AnnaBridge	181:57724642e740	3317	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	181:57724642e740	3318	return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) \| (SAIx << 16U));
AnnaBridge	181:57724642e740	3319	#else
AnnaBridge	167:e84263d55307	3320	return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U \| SAIx);
AnnaBridge	181:57724642e740	3321	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	181:57724642e740	3322	}
AnnaBridge	181:57724642e740	3323
AnnaBridge	181:57724642e740	3324	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	181:57724642e740	3325	/**
AnnaBridge	181:57724642e740	3326	* @brief Get SDMMCx kernel clock source
AnnaBridge	181:57724642e740	3327	* @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
AnnaBridge	181:57724642e740	3328	* @param SDMMCx This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3329	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
AnnaBridge	181:57724642e740	3330	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	3331	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
AnnaBridge	181:57724642e740	3332	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
AnnaBridge	181:57724642e740	3333	*
AnnaBridge	181:57724642e740	3334	* (*) value not defined in all devices.
AnnaBridge	181:57724642e740	3335	*/
AnnaBridge	181:57724642e740	3336	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
AnnaBridge	181:57724642e740	3337	{
AnnaBridge	181:57724642e740	3338	return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
AnnaBridge	181:57724642e740	3339	}
AnnaBridge	181:57724642e740	3340	#endif /* RCC_CCIPR2_SDMMCSEL */
<>	144:ef7eb2e8f9f7	3341
<>	144:ef7eb2e8f9f7	3342	/**
<>	144:ef7eb2e8f9f7	3343	* @brief Get SDMMCx clock source
<>	144:ef7eb2e8f9f7	3344	* @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
<>	144:ef7eb2e8f9f7	3345	* @param SDMMCx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3346	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3347	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	3348	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	167:e84263d55307	3349	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
AnnaBridge	181:57724642e740	3350	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
<>	144:ef7eb2e8f9f7	3351	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
AnnaBridge	181:57724642e740	3352	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
AnnaBridge	167:e84263d55307	3353	*
AnnaBridge	167:e84263d55307	3354	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3355	*/
<>	144:ef7eb2e8f9f7	3356	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
<>	144:ef7eb2e8f9f7	3357	{
<>	144:ef7eb2e8f9f7	3358	return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
<>	144:ef7eb2e8f9f7	3359	}
<>	144:ef7eb2e8f9f7	3360
<>	144:ef7eb2e8f9f7	3361	/**
<>	144:ef7eb2e8f9f7	3362	* @brief Get RNGx clock source
<>	144:ef7eb2e8f9f7	3363	* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
<>	144:ef7eb2e8f9f7	3364	* @param RNGx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3365	* @arg @ref LL_RCC_RNG_CLKSOURCE
<>	144:ef7eb2e8f9f7	3366	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	3367	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	167:e84263d55307	3368	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
<>	144:ef7eb2e8f9f7	3369	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	3370	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	3371	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	167:e84263d55307	3372	*
AnnaBridge	167:e84263d55307	3373	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3374	*/
<>	144:ef7eb2e8f9f7	3375	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
<>	144:ef7eb2e8f9f7	3376	{
<>	144:ef7eb2e8f9f7	3377	return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
<>	144:ef7eb2e8f9f7	3378	}
<>	144:ef7eb2e8f9f7	3379
<>	144:ef7eb2e8f9f7	3380	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	144:ef7eb2e8f9f7	3381	/**
<>	144:ef7eb2e8f9f7	3382	* @brief Get USBx clock source
<>	144:ef7eb2e8f9f7	3383	* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
<>	144:ef7eb2e8f9f7	3384	* @param USBx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3385	* @arg @ref LL_RCC_USB_CLKSOURCE
<>	144:ef7eb2e8f9f7	3386	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	3387	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	167:e84263d55307	3388	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
<>	144:ef7eb2e8f9f7	3389	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	3390	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	3391	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	167:e84263d55307	3392	*
AnnaBridge	167:e84263d55307	3393	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3394	*/
<>	144:ef7eb2e8f9f7	3395	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
<>	144:ef7eb2e8f9f7	3396	{
<>	144:ef7eb2e8f9f7	3397	return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
<>	144:ef7eb2e8f9f7	3398	}
<>	144:ef7eb2e8f9f7	3399	#endif /* USB_OTG_FS \|\| USB */
<>	144:ef7eb2e8f9f7	3400
<>	144:ef7eb2e8f9f7	3401	/**
<>	144:ef7eb2e8f9f7	3402	* @brief Get ADCx clock source
<>	144:ef7eb2e8f9f7	3403	* @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
<>	144:ef7eb2e8f9f7	3404	* @param ADCx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3405	* @arg @ref LL_RCC_ADC_CLKSOURCE
<>	144:ef7eb2e8f9f7	3406	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3407	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
<>	144:ef7eb2e8f9f7	3408	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	3409	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
<>	144:ef7eb2e8f9f7	3410	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3411	*
<>	144:ef7eb2e8f9f7	3412	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3413	*/
<>	144:ef7eb2e8f9f7	3414	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
<>	144:ef7eb2e8f9f7	3415	{
<>	144:ef7eb2e8f9f7	3416	return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
<>	144:ef7eb2e8f9f7	3417	}
<>	144:ef7eb2e8f9f7	3418
AnnaBridge	167:e84263d55307	3419	#if defined(SWPMI1)
<>	144:ef7eb2e8f9f7	3420	/**
<>	144:ef7eb2e8f9f7	3421	* @brief Get SWPMIx clock source
<>	144:ef7eb2e8f9f7	3422	* @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
<>	144:ef7eb2e8f9f7	3423	* @param SPWMIx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3424	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3425	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	3426	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
<>	144:ef7eb2e8f9f7	3427	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
<>	144:ef7eb2e8f9f7	3428	*/
<>	144:ef7eb2e8f9f7	3429	__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
<>	144:ef7eb2e8f9f7	3430	{
<>	144:ef7eb2e8f9f7	3431	return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
<>	144:ef7eb2e8f9f7	3432	}
AnnaBridge	167:e84263d55307	3433	#endif /* SWPMI1 */
<>	144:ef7eb2e8f9f7	3434
<>	144:ef7eb2e8f9f7	3435	#if defined(DFSDM1_Channel0)
AnnaBridge	181:57724642e740	3436	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	181:57724642e740	3437	/**
AnnaBridge	181:57724642e740	3438	* @brief Get DFSDM Audio Clock Source
AnnaBridge	181:57724642e740	3439	* @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
AnnaBridge	181:57724642e740	3440	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3441	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
AnnaBridge	181:57724642e740	3442	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	3443	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	181:57724642e740	3444	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
AnnaBridge	181:57724642e740	3445	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
AnnaBridge	181:57724642e740	3446	*/
AnnaBridge	181:57724642e740	3447	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
AnnaBridge	181:57724642e740	3448	{
AnnaBridge	181:57724642e740	3449	return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
AnnaBridge	181:57724642e740	3450	}
AnnaBridge	181:57724642e740	3451	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	181:57724642e740	3452
<>	144:ef7eb2e8f9f7	3453	/**
AnnaBridge	167:e84263d55307	3454	* @brief Get DFSDMx Kernel clock source
AnnaBridge	181:57724642e740	3455	@if STM32L4S9xx
AnnaBridge	181:57724642e740	3456	* @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	181:57724642e740	3457	@else
<>	144:ef7eb2e8f9f7	3458	* @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	181:57724642e740	3459	@endif
<>	144:ef7eb2e8f9f7	3460	* @param DFSDMx This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3461	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
<>	144:ef7eb2e8f9f7	3462	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	3463	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
<>	144:ef7eb2e8f9f7	3464	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	3465	*/
<>	144:ef7eb2e8f9f7	3466	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
<>	144:ef7eb2e8f9f7	3467	{
AnnaBridge	181:57724642e740	3468	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	181:57724642e740	3469	return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
AnnaBridge	181:57724642e740	3470	#else
<>	144:ef7eb2e8f9f7	3471	return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
AnnaBridge	181:57724642e740	3472	#endif /* RCC_CCIPR2_DFSDM1SEL */
<>	144:ef7eb2e8f9f7	3473	}
<>	144:ef7eb2e8f9f7	3474	#endif /* DFSDM1_Channel0 */
<>	144:ef7eb2e8f9f7	3475
AnnaBridge	181:57724642e740	3476	#if defined(DSI)
AnnaBridge	181:57724642e740	3477	/**
AnnaBridge	181:57724642e740	3478	* @brief Get DSI Clock Source
AnnaBridge	181:57724642e740	3479	* @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
AnnaBridge	181:57724642e740	3480	* @param DSIx This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3481	* @arg @ref LL_RCC_DSI_CLKSOURCE
AnnaBridge	181:57724642e740	3482	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	3483	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	181:57724642e740	3484	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	181:57724642e740	3485	*/
AnnaBridge	181:57724642e740	3486	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
AnnaBridge	181:57724642e740	3487	{
AnnaBridge	181:57724642e740	3488	return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
AnnaBridge	181:57724642e740	3489	}
AnnaBridge	181:57724642e740	3490	#endif /* DSI */
AnnaBridge	181:57724642e740	3491
AnnaBridge	181:57724642e740	3492	#if defined(LTDC)
AnnaBridge	181:57724642e740	3493	/**
AnnaBridge	181:57724642e740	3494	* @brief Get LTDC Clock Source
AnnaBridge	181:57724642e740	3495	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource
AnnaBridge	181:57724642e740	3496	* @param LTDCx This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3497	* @arg @ref LL_RCC_LTDC_CLKSOURCE
AnnaBridge	181:57724642e740	3498	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	3499	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
AnnaBridge	181:57724642e740	3500	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
AnnaBridge	181:57724642e740	3501	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
AnnaBridge	181:57724642e740	3502	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
AnnaBridge	181:57724642e740	3503	*/
AnnaBridge	181:57724642e740	3504	__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
AnnaBridge	181:57724642e740	3505	{
AnnaBridge	181:57724642e740	3506	return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
AnnaBridge	181:57724642e740	3507	}
AnnaBridge	181:57724642e740	3508	#endif /* LTDC */
AnnaBridge	181:57724642e740	3509
AnnaBridge	181:57724642e740	3510	#if defined(OCTOSPI1)
AnnaBridge	181:57724642e740	3511	/**
AnnaBridge	181:57724642e740	3512	* @brief Get OCTOSPI clock source
AnnaBridge	181:57724642e740	3513	* @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
AnnaBridge	181:57724642e740	3514	* @param OCTOSPIx This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3515	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
AnnaBridge	181:57724642e740	3516	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	3517	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
AnnaBridge	181:57724642e740	3518	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
AnnaBridge	181:57724642e740	3519	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
AnnaBridge	181:57724642e740	3520	*/
AnnaBridge	181:57724642e740	3521	__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
AnnaBridge	181:57724642e740	3522	{
AnnaBridge	181:57724642e740	3523	return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
AnnaBridge	181:57724642e740	3524	}
AnnaBridge	181:57724642e740	3525	#endif /* OCTOSPI1 */
<>	144:ef7eb2e8f9f7	3526	/**
<>	144:ef7eb2e8f9f7	3527	* @}
<>	144:ef7eb2e8f9f7	3528	*/
<>	144:ef7eb2e8f9f7	3529
<>	144:ef7eb2e8f9f7	3530	/** @defgroup RCC_LL_EF_RTC RTC
<>	144:ef7eb2e8f9f7	3531	* @{
<>	144:ef7eb2e8f9f7	3532	*/
<>	144:ef7eb2e8f9f7	3533
<>	144:ef7eb2e8f9f7	3534	/**
<>	144:ef7eb2e8f9f7	3535	* @brief Set RTC Clock Source
<>	144:ef7eb2e8f9f7	3536	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
<>	144:ef7eb2e8f9f7	3537	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
<>	144:ef7eb2e8f9f7	3538	* set). The BDRST bit can be used to reset them.
<>	144:ef7eb2e8f9f7	3539	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
<>	144:ef7eb2e8f9f7	3540	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3541	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	144:ef7eb2e8f9f7	3542	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3543	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	3544	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
<>	144:ef7eb2e8f9f7	3545	* @retval None
<>	144:ef7eb2e8f9f7	3546	*/
<>	144:ef7eb2e8f9f7	3547	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
<>	144:ef7eb2e8f9f7	3548	{
<>	144:ef7eb2e8f9f7	3549	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
<>	144:ef7eb2e8f9f7	3550	}
<>	144:ef7eb2e8f9f7	3551
<>	144:ef7eb2e8f9f7	3552	/**
<>	144:ef7eb2e8f9f7	3553	* @brief Get RTC Clock Source
<>	144:ef7eb2e8f9f7	3554	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
<>	144:ef7eb2e8f9f7	3555	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3556	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	144:ef7eb2e8f9f7	3557	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	144:ef7eb2e8f9f7	3558	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	144:ef7eb2e8f9f7	3559	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
<>	144:ef7eb2e8f9f7	3560	*/
<>	144:ef7eb2e8f9f7	3561	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
<>	144:ef7eb2e8f9f7	3562	{
<>	144:ef7eb2e8f9f7	3563	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
<>	144:ef7eb2e8f9f7	3564	}
<>	144:ef7eb2e8f9f7	3565
<>	144:ef7eb2e8f9f7	3566	/**
<>	144:ef7eb2e8f9f7	3567	* @brief Enable RTC
<>	144:ef7eb2e8f9f7	3568	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
<>	144:ef7eb2e8f9f7	3569	* @retval None
<>	144:ef7eb2e8f9f7	3570	*/
<>	144:ef7eb2e8f9f7	3571	__STATIC_INLINE void LL_RCC_EnableRTC(void)
<>	144:ef7eb2e8f9f7	3572	{
<>	144:ef7eb2e8f9f7	3573	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	144:ef7eb2e8f9f7	3574	}
<>	144:ef7eb2e8f9f7	3575
<>	144:ef7eb2e8f9f7	3576	/**
<>	144:ef7eb2e8f9f7	3577	* @brief Disable RTC
<>	144:ef7eb2e8f9f7	3578	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
<>	144:ef7eb2e8f9f7	3579	* @retval None
<>	144:ef7eb2e8f9f7	3580	*/
<>	144:ef7eb2e8f9f7	3581	__STATIC_INLINE void LL_RCC_DisableRTC(void)
<>	144:ef7eb2e8f9f7	3582	{
<>	144:ef7eb2e8f9f7	3583	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	144:ef7eb2e8f9f7	3584	}
<>	144:ef7eb2e8f9f7	3585
<>	144:ef7eb2e8f9f7	3586	/**
<>	144:ef7eb2e8f9f7	3587	* @brief Check if RTC has been enabled or not
<>	144:ef7eb2e8f9f7	3588	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
<>	144:ef7eb2e8f9f7	3589	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3590	*/
<>	144:ef7eb2e8f9f7	3591	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
<>	144:ef7eb2e8f9f7	3592	{
<>	144:ef7eb2e8f9f7	3593	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
<>	144:ef7eb2e8f9f7	3594	}
<>	144:ef7eb2e8f9f7	3595
<>	144:ef7eb2e8f9f7	3596	/**
<>	144:ef7eb2e8f9f7	3597	* @brief Force the Backup domain reset
<>	144:ef7eb2e8f9f7	3598	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
<>	144:ef7eb2e8f9f7	3599	* @retval None
<>	144:ef7eb2e8f9f7	3600	*/
<>	144:ef7eb2e8f9f7	3601	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
<>	144:ef7eb2e8f9f7	3602	{
<>	144:ef7eb2e8f9f7	3603	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	144:ef7eb2e8f9f7	3604	}
<>	144:ef7eb2e8f9f7	3605
<>	144:ef7eb2e8f9f7	3606	/**
<>	144:ef7eb2e8f9f7	3607	* @brief Release the Backup domain reset
<>	144:ef7eb2e8f9f7	3608	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
<>	144:ef7eb2e8f9f7	3609	* @retval None
<>	144:ef7eb2e8f9f7	3610	*/
<>	144:ef7eb2e8f9f7	3611	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
<>	144:ef7eb2e8f9f7	3612	{
<>	144:ef7eb2e8f9f7	3613	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	144:ef7eb2e8f9f7	3614	}
<>	144:ef7eb2e8f9f7	3615
<>	144:ef7eb2e8f9f7	3616	/**
<>	144:ef7eb2e8f9f7	3617	* @}
<>	144:ef7eb2e8f9f7	3618	*/
<>	144:ef7eb2e8f9f7	3619
AnnaBridge	167:e84263d55307	3620
<>	144:ef7eb2e8f9f7	3621	/** @defgroup RCC_LL_EF_PLL PLL
<>	144:ef7eb2e8f9f7	3622	* @{
<>	144:ef7eb2e8f9f7	3623	*/
<>	144:ef7eb2e8f9f7	3624
<>	144:ef7eb2e8f9f7	3625	/**
<>	144:ef7eb2e8f9f7	3626	* @brief Enable PLL
<>	144:ef7eb2e8f9f7	3627	* @rmtoll CR PLLON LL_RCC_PLL_Enable
<>	144:ef7eb2e8f9f7	3628	* @retval None
<>	144:ef7eb2e8f9f7	3629	*/
<>	144:ef7eb2e8f9f7	3630	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
<>	144:ef7eb2e8f9f7	3631	{
<>	144:ef7eb2e8f9f7	3632	SET_BIT(RCC->CR, RCC_CR_PLLON);
<>	144:ef7eb2e8f9f7	3633	}
<>	144:ef7eb2e8f9f7	3634
<>	144:ef7eb2e8f9f7	3635	/**
<>	144:ef7eb2e8f9f7	3636	* @brief Disable PLL
<>	144:ef7eb2e8f9f7	3637	* @note Cannot be disabled if the PLL clock is used as the system clock
<>	144:ef7eb2e8f9f7	3638	* @rmtoll CR PLLON LL_RCC_PLL_Disable
<>	144:ef7eb2e8f9f7	3639	* @retval None
<>	144:ef7eb2e8f9f7	3640	*/
<>	144:ef7eb2e8f9f7	3641	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
<>	144:ef7eb2e8f9f7	3642	{
<>	144:ef7eb2e8f9f7	3643	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<>	144:ef7eb2e8f9f7	3644	}
<>	144:ef7eb2e8f9f7	3645
<>	144:ef7eb2e8f9f7	3646	/**
<>	144:ef7eb2e8f9f7	3647	* @brief Check if PLL Ready
<>	144:ef7eb2e8f9f7	3648	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
<>	144:ef7eb2e8f9f7	3649	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3650	*/
<>	144:ef7eb2e8f9f7	3651	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
<>	144:ef7eb2e8f9f7	3652	{
<>	144:ef7eb2e8f9f7	3653	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
<>	144:ef7eb2e8f9f7	3654	}
<>	144:ef7eb2e8f9f7	3655
<>	144:ef7eb2e8f9f7	3656	/**
<>	144:ef7eb2e8f9f7	3657	* @brief Configure PLL used for SYSCLK Domain
<>	144:ef7eb2e8f9f7	3658	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	3659	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	3660	* @note PLLN/PLLR can be written only when PLL is disabled.
<>	144:ef7eb2e8f9f7	3661	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<>	144:ef7eb2e8f9f7	3662	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
<>	144:ef7eb2e8f9f7	3663	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
<>	144:ef7eb2e8f9f7	3664	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
<>	144:ef7eb2e8f9f7	3665	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3666	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	3667	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	3668	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	3669	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	3670	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3671	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	3672	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	3673	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	3674	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	3675	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	3676	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	3677	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	3678	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	3679	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	181:57724642e740	3680	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	181:57724642e740	3681	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	181:57724642e740	3682	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	181:57724642e740	3683	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	181:57724642e740	3684	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	181:57724642e740	3685	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	181:57724642e740	3686	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	181:57724642e740	3687	*
AnnaBridge	181:57724642e740	3688	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3689	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	3690	* @param PLLR This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3691	* @arg @ref LL_RCC_PLLR_DIV_2
<>	144:ef7eb2e8f9f7	3692	* @arg @ref LL_RCC_PLLR_DIV_4
<>	144:ef7eb2e8f9f7	3693	* @arg @ref LL_RCC_PLLR_DIV_6
<>	144:ef7eb2e8f9f7	3694	* @arg @ref LL_RCC_PLLR_DIV_8
<>	144:ef7eb2e8f9f7	3695	* @retval None
<>	144:ef7eb2e8f9f7	3696	*/
<>	144:ef7eb2e8f9f7	3697	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
<>	144:ef7eb2e8f9f7	3698	{
<>	144:ef7eb2e8f9f7	3699	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	167:e84263d55307	3700	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
<>	144:ef7eb2e8f9f7	3701	}
<>	144:ef7eb2e8f9f7	3702
<>	144:ef7eb2e8f9f7	3703	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	3704	/**
<>	144:ef7eb2e8f9f7	3705	* @brief Configure PLL used for SAI domain clock
<>	144:ef7eb2e8f9f7	3706	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	3707	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	3708	* @note PLLN/PLLP can be written only when PLL is disabled.
<>	144:ef7eb2e8f9f7	3709	* @note This can be selected for SAI1 or SAI2 (*)
<>	144:ef7eb2e8f9f7	3710	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	3711	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	3712	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	3713	* PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
<>	144:ef7eb2e8f9f7	3714	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3715	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	3716	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	3717	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	3718	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	3719	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3720	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	3721	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	3722	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	3723	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	3724	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	3725	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	3726	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	3727	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	3728	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	181:57724642e740	3729	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	181:57724642e740	3730	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	181:57724642e740	3731	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	181:57724642e740	3732	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	181:57724642e740	3733	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	181:57724642e740	3734	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	181:57724642e740	3735	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	181:57724642e740	3736	*
AnnaBridge	181:57724642e740	3737	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3738	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	3739	* @param PLLP This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3740	* @arg @ref LL_RCC_PLLP_DIV_2
<>	144:ef7eb2e8f9f7	3741	* @arg @ref LL_RCC_PLLP_DIV_3
<>	144:ef7eb2e8f9f7	3742	* @arg @ref LL_RCC_PLLP_DIV_4
<>	144:ef7eb2e8f9f7	3743	* @arg @ref LL_RCC_PLLP_DIV_5
<>	144:ef7eb2e8f9f7	3744	* @arg @ref LL_RCC_PLLP_DIV_6
<>	144:ef7eb2e8f9f7	3745	* @arg @ref LL_RCC_PLLP_DIV_7
<>	144:ef7eb2e8f9f7	3746	* @arg @ref LL_RCC_PLLP_DIV_8
<>	144:ef7eb2e8f9f7	3747	* @arg @ref LL_RCC_PLLP_DIV_9
<>	144:ef7eb2e8f9f7	3748	* @arg @ref LL_RCC_PLLP_DIV_10
<>	144:ef7eb2e8f9f7	3749	* @arg @ref LL_RCC_PLLP_DIV_11
<>	144:ef7eb2e8f9f7	3750	* @arg @ref LL_RCC_PLLP_DIV_12
<>	144:ef7eb2e8f9f7	3751	* @arg @ref LL_RCC_PLLP_DIV_13
<>	144:ef7eb2e8f9f7	3752	* @arg @ref LL_RCC_PLLP_DIV_14
<>	144:ef7eb2e8f9f7	3753	* @arg @ref LL_RCC_PLLP_DIV_15
<>	144:ef7eb2e8f9f7	3754	* @arg @ref LL_RCC_PLLP_DIV_16
<>	144:ef7eb2e8f9f7	3755	* @arg @ref LL_RCC_PLLP_DIV_17
<>	144:ef7eb2e8f9f7	3756	* @arg @ref LL_RCC_PLLP_DIV_18
<>	144:ef7eb2e8f9f7	3757	* @arg @ref LL_RCC_PLLP_DIV_19
<>	144:ef7eb2e8f9f7	3758	* @arg @ref LL_RCC_PLLP_DIV_20
<>	144:ef7eb2e8f9f7	3759	* @arg @ref LL_RCC_PLLP_DIV_21
<>	144:ef7eb2e8f9f7	3760	* @arg @ref LL_RCC_PLLP_DIV_22
<>	144:ef7eb2e8f9f7	3761	* @arg @ref LL_RCC_PLLP_DIV_23
<>	144:ef7eb2e8f9f7	3762	* @arg @ref LL_RCC_PLLP_DIV_24
<>	144:ef7eb2e8f9f7	3763	* @arg @ref LL_RCC_PLLP_DIV_25
<>	144:ef7eb2e8f9f7	3764	* @arg @ref LL_RCC_PLLP_DIV_26
<>	144:ef7eb2e8f9f7	3765	* @arg @ref LL_RCC_PLLP_DIV_27
<>	144:ef7eb2e8f9f7	3766	* @arg @ref LL_RCC_PLLP_DIV_28
<>	144:ef7eb2e8f9f7	3767	* @arg @ref LL_RCC_PLLP_DIV_29
<>	144:ef7eb2e8f9f7	3768	* @arg @ref LL_RCC_PLLP_DIV_30
<>	144:ef7eb2e8f9f7	3769	* @arg @ref LL_RCC_PLLP_DIV_31
<>	144:ef7eb2e8f9f7	3770	* @retval None
<>	144:ef7eb2e8f9f7	3771	*/
<>	144:ef7eb2e8f9f7	3772	#else
<>	144:ef7eb2e8f9f7	3773	/**
<>	144:ef7eb2e8f9f7	3774	* @brief Configure PLL used for SAI domain clock
<>	144:ef7eb2e8f9f7	3775	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	3776	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	3777	* @note PLLN/PLLP can be written only when PLL is disabled.
<>	144:ef7eb2e8f9f7	3778	* @note This can be selected for SAI1 or SAI2 (*)
<>	144:ef7eb2e8f9f7	3779	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	3780	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	3781	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	3782	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
<>	144:ef7eb2e8f9f7	3783	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3784	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	3785	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	3786	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	3787	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	3788	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3789	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	3790	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	3791	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	3792	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	3793	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	3794	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	3795	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	3796	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	3797	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	3798	* @param PLLP This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3799	* @arg @ref LL_RCC_PLLP_DIV_7
<>	144:ef7eb2e8f9f7	3800	* @arg @ref LL_RCC_PLLP_DIV_17
<>	144:ef7eb2e8f9f7	3801	* @retval None
<>	144:ef7eb2e8f9f7	3802	*/
<>	144:ef7eb2e8f9f7	3803	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	3804	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
<>	144:ef7eb2e8f9f7	3805	{
<>	144:ef7eb2e8f9f7	3806	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	3807	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLPDIV,
AnnaBridge	167:e84263d55307	3808	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
<>	144:ef7eb2e8f9f7	3809	#else
<>	144:ef7eb2e8f9f7	3810	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
AnnaBridge	167:e84263d55307	3811	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
<>	144:ef7eb2e8f9f7	3812	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	3813	}
<>	144:ef7eb2e8f9f7	3814
<>	144:ef7eb2e8f9f7	3815	/**
<>	144:ef7eb2e8f9f7	3816	* @brief Configure PLL used for 48Mhz domain clock
<>	144:ef7eb2e8f9f7	3817	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	3818	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	3819	* @note PLLN/PLLQ can be written only when PLL is disabled.
<>	144:ef7eb2e8f9f7	3820	* @note This can be selected for USB, RNG, SDMMC
<>	144:ef7eb2e8f9f7	3821	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
<>	144:ef7eb2e8f9f7	3822	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
<>	144:ef7eb2e8f9f7	3823	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
<>	144:ef7eb2e8f9f7	3824	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
<>	144:ef7eb2e8f9f7	3825	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3826	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	3827	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	3828	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	3829	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	3830	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3831	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	3832	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	3833	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	3834	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	3835	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	3836	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	3837	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	3838	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	3839	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	181:57724642e740	3840	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	181:57724642e740	3841	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	181:57724642e740	3842	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	181:57724642e740	3843	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	181:57724642e740	3844	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	181:57724642e740	3845	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	181:57724642e740	3846	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	181:57724642e740	3847	*
AnnaBridge	181:57724642e740	3848	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	3849	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	3850	* @param PLLQ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3851	* @arg @ref LL_RCC_PLLQ_DIV_2
<>	144:ef7eb2e8f9f7	3852	* @arg @ref LL_RCC_PLLQ_DIV_4
<>	144:ef7eb2e8f9f7	3853	* @arg @ref LL_RCC_PLLQ_DIV_6
<>	144:ef7eb2e8f9f7	3854	* @arg @ref LL_RCC_PLLQ_DIV_8
<>	144:ef7eb2e8f9f7	3855	* @retval None
<>	144:ef7eb2e8f9f7	3856	*/
<>	144:ef7eb2e8f9f7	3857	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
<>	144:ef7eb2e8f9f7	3858	{
<>	144:ef7eb2e8f9f7	3859	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	167:e84263d55307	3860	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
<>	144:ef7eb2e8f9f7	3861	}
<>	144:ef7eb2e8f9f7	3862
<>	144:ef7eb2e8f9f7	3863	/**
AnnaBridge	181:57724642e740	3864	* @brief Configure PLL clock source
AnnaBridge	181:57724642e740	3865	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
AnnaBridge	181:57724642e740	3866	* @param PLLSource This parameter can be one of the following values:
AnnaBridge	181:57724642e740	3867	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	3868	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	3869	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	3870	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	3871	* @retval None
AnnaBridge	181:57724642e740	3872	*/
AnnaBridge	181:57724642e740	3873	__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
AnnaBridge	181:57724642e740	3874	{
AnnaBridge	181:57724642e740	3875	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
AnnaBridge	181:57724642e740	3876	}
AnnaBridge	181:57724642e740	3877
AnnaBridge	181:57724642e740	3878	/**
AnnaBridge	181:57724642e740	3879	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	181:57724642e740	3880	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	181:57724642e740	3881	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	3882	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	3883	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	3884	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	3885	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	3886	*/
AnnaBridge	181:57724642e740	3887	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	181:57724642e740	3888	{
AnnaBridge	181:57724642e740	3889	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	181:57724642e740	3890	}
AnnaBridge	181:57724642e740	3891
AnnaBridge	181:57724642e740	3892	/**
<>	144:ef7eb2e8f9f7	3893	* @brief Get Main PLL multiplication factor for VCO
<>	144:ef7eb2e8f9f7	3894	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
<>	144:ef7eb2e8f9f7	3895	* @retval Between 8 and 86
<>	144:ef7eb2e8f9f7	3896	*/
<>	144:ef7eb2e8f9f7	3897	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
<>	144:ef7eb2e8f9f7	3898	{
AnnaBridge	167:e84263d55307	3899	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
<>	144:ef7eb2e8f9f7	3900	}
<>	144:ef7eb2e8f9f7	3901
<>	144:ef7eb2e8f9f7	3902	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	3903	/**
<>	144:ef7eb2e8f9f7	3904	* @brief Get Main PLL division factor for PLLP
AnnaBridge	181:57724642e740	3905	* @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
<>	144:ef7eb2e8f9f7	3906	* @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
<>	144:ef7eb2e8f9f7	3907	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3908	* @arg @ref LL_RCC_PLLP_DIV_2
<>	144:ef7eb2e8f9f7	3909	* @arg @ref LL_RCC_PLLP_DIV_3
<>	144:ef7eb2e8f9f7	3910	* @arg @ref LL_RCC_PLLP_DIV_4
<>	144:ef7eb2e8f9f7	3911	* @arg @ref LL_RCC_PLLP_DIV_5
<>	144:ef7eb2e8f9f7	3912	* @arg @ref LL_RCC_PLLP_DIV_6
<>	144:ef7eb2e8f9f7	3913	* @arg @ref LL_RCC_PLLP_DIV_7
<>	144:ef7eb2e8f9f7	3914	* @arg @ref LL_RCC_PLLP_DIV_8
<>	144:ef7eb2e8f9f7	3915	* @arg @ref LL_RCC_PLLP_DIV_9
<>	144:ef7eb2e8f9f7	3916	* @arg @ref LL_RCC_PLLP_DIV_10
<>	144:ef7eb2e8f9f7	3917	* @arg @ref LL_RCC_PLLP_DIV_11
<>	144:ef7eb2e8f9f7	3918	* @arg @ref LL_RCC_PLLP_DIV_12
<>	144:ef7eb2e8f9f7	3919	* @arg @ref LL_RCC_PLLP_DIV_13
<>	144:ef7eb2e8f9f7	3920	* @arg @ref LL_RCC_PLLP_DIV_14
<>	144:ef7eb2e8f9f7	3921	* @arg @ref LL_RCC_PLLP_DIV_15
<>	144:ef7eb2e8f9f7	3922	* @arg @ref LL_RCC_PLLP_DIV_16
<>	144:ef7eb2e8f9f7	3923	* @arg @ref LL_RCC_PLLP_DIV_17
<>	144:ef7eb2e8f9f7	3924	* @arg @ref LL_RCC_PLLP_DIV_18
<>	144:ef7eb2e8f9f7	3925	* @arg @ref LL_RCC_PLLP_DIV_19
<>	144:ef7eb2e8f9f7	3926	* @arg @ref LL_RCC_PLLP_DIV_20
<>	144:ef7eb2e8f9f7	3927	* @arg @ref LL_RCC_PLLP_DIV_21
<>	144:ef7eb2e8f9f7	3928	* @arg @ref LL_RCC_PLLP_DIV_22
<>	144:ef7eb2e8f9f7	3929	* @arg @ref LL_RCC_PLLP_DIV_23
<>	144:ef7eb2e8f9f7	3930	* @arg @ref LL_RCC_PLLP_DIV_24
<>	144:ef7eb2e8f9f7	3931	* @arg @ref LL_RCC_PLLP_DIV_25
<>	144:ef7eb2e8f9f7	3932	* @arg @ref LL_RCC_PLLP_DIV_26
<>	144:ef7eb2e8f9f7	3933	* @arg @ref LL_RCC_PLLP_DIV_27
<>	144:ef7eb2e8f9f7	3934	* @arg @ref LL_RCC_PLLP_DIV_28
<>	144:ef7eb2e8f9f7	3935	* @arg @ref LL_RCC_PLLP_DIV_29
<>	144:ef7eb2e8f9f7	3936	* @arg @ref LL_RCC_PLLP_DIV_30
<>	144:ef7eb2e8f9f7	3937	* @arg @ref LL_RCC_PLLP_DIV_31
<>	144:ef7eb2e8f9f7	3938	*/
<>	144:ef7eb2e8f9f7	3939	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
<>	144:ef7eb2e8f9f7	3940	{
<>	144:ef7eb2e8f9f7	3941	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
<>	144:ef7eb2e8f9f7	3942	}
<>	144:ef7eb2e8f9f7	3943	#else
<>	144:ef7eb2e8f9f7	3944	/**
<>	144:ef7eb2e8f9f7	3945	* @brief Get Main PLL division factor for PLLP
AnnaBridge	181:57724642e740	3946	* @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
<>	144:ef7eb2e8f9f7	3947	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
<>	144:ef7eb2e8f9f7	3948	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3949	* @arg @ref LL_RCC_PLLP_DIV_7
<>	144:ef7eb2e8f9f7	3950	* @arg @ref LL_RCC_PLLP_DIV_17
<>	144:ef7eb2e8f9f7	3951	*/
<>	144:ef7eb2e8f9f7	3952	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
<>	144:ef7eb2e8f9f7	3953	{
<>	144:ef7eb2e8f9f7	3954	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
<>	144:ef7eb2e8f9f7	3955	}
<>	144:ef7eb2e8f9f7	3956	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	3957
<>	144:ef7eb2e8f9f7	3958	/**
<>	144:ef7eb2e8f9f7	3959	* @brief Get Main PLL division factor for PLLQ
AnnaBridge	181:57724642e740	3960	* @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
<>	144:ef7eb2e8f9f7	3961	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
<>	144:ef7eb2e8f9f7	3962	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3963	* @arg @ref LL_RCC_PLLQ_DIV_2
<>	144:ef7eb2e8f9f7	3964	* @arg @ref LL_RCC_PLLQ_DIV_4
<>	144:ef7eb2e8f9f7	3965	* @arg @ref LL_RCC_PLLQ_DIV_6
<>	144:ef7eb2e8f9f7	3966	* @arg @ref LL_RCC_PLLQ_DIV_8
<>	144:ef7eb2e8f9f7	3967	*/
<>	144:ef7eb2e8f9f7	3968	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
<>	144:ef7eb2e8f9f7	3969	{
<>	144:ef7eb2e8f9f7	3970	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
<>	144:ef7eb2e8f9f7	3971	}
<>	144:ef7eb2e8f9f7	3972
<>	144:ef7eb2e8f9f7	3973	/**
<>	144:ef7eb2e8f9f7	3974	* @brief Get Main PLL division factor for PLLR
AnnaBridge	181:57724642e740	3975	* @note Used for PLLCLK (system clock)
<>	144:ef7eb2e8f9f7	3976	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
<>	144:ef7eb2e8f9f7	3977	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3978	* @arg @ref LL_RCC_PLLR_DIV_2
<>	144:ef7eb2e8f9f7	3979	* @arg @ref LL_RCC_PLLR_DIV_4
<>	144:ef7eb2e8f9f7	3980	* @arg @ref LL_RCC_PLLR_DIV_6
<>	144:ef7eb2e8f9f7	3981	* @arg @ref LL_RCC_PLLR_DIV_8
<>	144:ef7eb2e8f9f7	3982	*/
<>	144:ef7eb2e8f9f7	3983	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
<>	144:ef7eb2e8f9f7	3984	{
<>	144:ef7eb2e8f9f7	3985	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
<>	144:ef7eb2e8f9f7	3986	}
<>	144:ef7eb2e8f9f7	3987
<>	144:ef7eb2e8f9f7	3988	/**
<>	144:ef7eb2e8f9f7	3989	* @brief Get Division factor for the main PLL and other PLL
<>	144:ef7eb2e8f9f7	3990	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
<>	144:ef7eb2e8f9f7	3991	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3992	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	3993	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	3994	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	3995	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	3996	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	3997	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	3998	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	3999	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	4000	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	181:57724642e740	4001	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	181:57724642e740	4002	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	181:57724642e740	4003	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	181:57724642e740	4004	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	181:57724642e740	4005	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	181:57724642e740	4006	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	181:57724642e740	4007	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	181:57724642e740	4008	*
AnnaBridge	181:57724642e740	4009	* (*) value not defined in all devices.
<>	144:ef7eb2e8f9f7	4010	*/
<>	144:ef7eb2e8f9f7	4011	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
<>	144:ef7eb2e8f9f7	4012	{
<>	144:ef7eb2e8f9f7	4013	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	4014	}
<>	144:ef7eb2e8f9f7	4015
<>	144:ef7eb2e8f9f7	4016	/**
<>	144:ef7eb2e8f9f7	4017	* @brief Enable PLL output mapped on SAI domain clock
<>	144:ef7eb2e8f9f7	4018	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
<>	144:ef7eb2e8f9f7	4019	* @retval None
<>	144:ef7eb2e8f9f7	4020	*/
<>	144:ef7eb2e8f9f7	4021	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
<>	144:ef7eb2e8f9f7	4022	{
<>	144:ef7eb2e8f9f7	4023	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
<>	144:ef7eb2e8f9f7	4024	}
<>	144:ef7eb2e8f9f7	4025
<>	144:ef7eb2e8f9f7	4026	/**
<>	144:ef7eb2e8f9f7	4027	* @brief Disable PLL output mapped on SAI domain clock
<>	144:ef7eb2e8f9f7	4028	* @note Cannot be disabled if the PLL clock is used as the system
<>	144:ef7eb2e8f9f7	4029	* clock
<>	144:ef7eb2e8f9f7	4030	* @note In order to save power, when the PLLCLK of the PLL is
<>	144:ef7eb2e8f9f7	4031	* not used, should be 0
<>	144:ef7eb2e8f9f7	4032	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
<>	144:ef7eb2e8f9f7	4033	* @retval None
<>	144:ef7eb2e8f9f7	4034	*/
<>	144:ef7eb2e8f9f7	4035	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
<>	144:ef7eb2e8f9f7	4036	{
<>	144:ef7eb2e8f9f7	4037	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
<>	144:ef7eb2e8f9f7	4038	}
<>	144:ef7eb2e8f9f7	4039
<>	144:ef7eb2e8f9f7	4040	/**
<>	144:ef7eb2e8f9f7	4041	* @brief Enable PLL output mapped on 48MHz domain clock
<>	144:ef7eb2e8f9f7	4042	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
<>	144:ef7eb2e8f9f7	4043	* @retval None
<>	144:ef7eb2e8f9f7	4044	*/
<>	144:ef7eb2e8f9f7	4045	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
<>	144:ef7eb2e8f9f7	4046	{
<>	144:ef7eb2e8f9f7	4047	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
<>	144:ef7eb2e8f9f7	4048	}
<>	144:ef7eb2e8f9f7	4049
<>	144:ef7eb2e8f9f7	4050	/**
<>	144:ef7eb2e8f9f7	4051	* @brief Disable PLL output mapped on 48MHz domain clock
<>	144:ef7eb2e8f9f7	4052	* @note Cannot be disabled if the PLL clock is used as the system
<>	144:ef7eb2e8f9f7	4053	* clock
<>	144:ef7eb2e8f9f7	4054	* @note In order to save power, when the PLLCLK of the PLL is
<>	144:ef7eb2e8f9f7	4055	* not used, should be 0
<>	144:ef7eb2e8f9f7	4056	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
<>	144:ef7eb2e8f9f7	4057	* @retval None
<>	144:ef7eb2e8f9f7	4058	*/
<>	144:ef7eb2e8f9f7	4059	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
<>	144:ef7eb2e8f9f7	4060	{
<>	144:ef7eb2e8f9f7	4061	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
<>	144:ef7eb2e8f9f7	4062	}
<>	144:ef7eb2e8f9f7	4063
<>	144:ef7eb2e8f9f7	4064	/**
<>	144:ef7eb2e8f9f7	4065	* @brief Enable PLL output mapped on SYSCLK domain
<>	144:ef7eb2e8f9f7	4066	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
<>	144:ef7eb2e8f9f7	4067	* @retval None
<>	144:ef7eb2e8f9f7	4068	*/
<>	144:ef7eb2e8f9f7	4069	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
<>	144:ef7eb2e8f9f7	4070	{
<>	144:ef7eb2e8f9f7	4071	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
<>	144:ef7eb2e8f9f7	4072	}
<>	144:ef7eb2e8f9f7	4073
<>	144:ef7eb2e8f9f7	4074	/**
<>	144:ef7eb2e8f9f7	4075	* @brief Disable PLL output mapped on SYSCLK domain
<>	144:ef7eb2e8f9f7	4076	* @note Cannot be disabled if the PLL clock is used as the system
<>	144:ef7eb2e8f9f7	4077	* clock
<>	144:ef7eb2e8f9f7	4078	* @note In order to save power, when the PLLCLK of the PLL is
<>	144:ef7eb2e8f9f7	4079	* not used, Main PLL should be 0
<>	144:ef7eb2e8f9f7	4080	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
<>	144:ef7eb2e8f9f7	4081	* @retval None
<>	144:ef7eb2e8f9f7	4082	*/
<>	144:ef7eb2e8f9f7	4083	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
<>	144:ef7eb2e8f9f7	4084	{
<>	144:ef7eb2e8f9f7	4085	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
<>	144:ef7eb2e8f9f7	4086	}
<>	144:ef7eb2e8f9f7	4087
<>	144:ef7eb2e8f9f7	4088	/**
<>	144:ef7eb2e8f9f7	4089	* @}
<>	144:ef7eb2e8f9f7	4090	*/
<>	144:ef7eb2e8f9f7	4091
<>	144:ef7eb2e8f9f7	4092	/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
<>	144:ef7eb2e8f9f7	4093	* @{
<>	144:ef7eb2e8f9f7	4094	*/
<>	144:ef7eb2e8f9f7	4095
<>	144:ef7eb2e8f9f7	4096	/**
<>	144:ef7eb2e8f9f7	4097	* @brief Enable PLLSAI1
<>	144:ef7eb2e8f9f7	4098	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
<>	144:ef7eb2e8f9f7	4099	* @retval None
<>	144:ef7eb2e8f9f7	4100	*/
<>	144:ef7eb2e8f9f7	4101	__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
<>	144:ef7eb2e8f9f7	4102	{
<>	144:ef7eb2e8f9f7	4103	SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
<>	144:ef7eb2e8f9f7	4104	}
<>	144:ef7eb2e8f9f7	4105
<>	144:ef7eb2e8f9f7	4106	/**
<>	144:ef7eb2e8f9f7	4107	* @brief Disable PLLSAI1
<>	144:ef7eb2e8f9f7	4108	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
<>	144:ef7eb2e8f9f7	4109	* @retval None
<>	144:ef7eb2e8f9f7	4110	*/
<>	144:ef7eb2e8f9f7	4111	__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
<>	144:ef7eb2e8f9f7	4112	{
<>	144:ef7eb2e8f9f7	4113	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
<>	144:ef7eb2e8f9f7	4114	}
<>	144:ef7eb2e8f9f7	4115
<>	144:ef7eb2e8f9f7	4116	/**
<>	144:ef7eb2e8f9f7	4117	* @brief Check if PLLSAI1 Ready
<>	144:ef7eb2e8f9f7	4118	* @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
<>	144:ef7eb2e8f9f7	4119	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4120	*/
<>	144:ef7eb2e8f9f7	4121	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
<>	144:ef7eb2e8f9f7	4122	{
<>	144:ef7eb2e8f9f7	4123	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
<>	144:ef7eb2e8f9f7	4124	}
<>	144:ef7eb2e8f9f7	4125
AnnaBridge	181:57724642e740	4126	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	4127	/**
AnnaBridge	181:57724642e740	4128	* @brief Configure PLLSAI1 used for 48Mhz domain clock
AnnaBridge	181:57724642e740	4129	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4130	* @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
AnnaBridge	181:57724642e740	4131	* @note This can be selected for USB, RNG, SDMMC
AnnaBridge	181:57724642e740	4132	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	181:57724642e740	4133	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	181:57724642e740	4134	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	181:57724642e740	4135	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
AnnaBridge	181:57724642e740	4136	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4137	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	4138	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	4139	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	4140	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	4141	* @param PLLM This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4142	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	181:57724642e740	4143	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	181:57724642e740	4144	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	181:57724642e740	4145	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	181:57724642e740	4146	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	181:57724642e740	4147	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	181:57724642e740	4148	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	181:57724642e740	4149	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	181:57724642e740	4150	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	181:57724642e740	4151	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	181:57724642e740	4152	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	181:57724642e740	4153	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	181:57724642e740	4154	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	181:57724642e740	4155	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	181:57724642e740	4156	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	181:57724642e740	4157	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	181:57724642e740	4158	* @param PLLN Between 8 and 86
AnnaBridge	181:57724642e740	4159	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4160	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	181:57724642e740	4161	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	181:57724642e740	4162	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	181:57724642e740	4163	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	181:57724642e740	4164	* @retval None
AnnaBridge	181:57724642e740	4165	*/
AnnaBridge	181:57724642e740	4166	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	181:57724642e740	4167	{
AnnaBridge	181:57724642e740	4168	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	181:57724642e740	4169	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q,
AnnaBridge	181:57724642e740	4170	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLQ);
AnnaBridge	181:57724642e740	4171	}
AnnaBridge	181:57724642e740	4172	#else
<>	144:ef7eb2e8f9f7	4173	/**
<>	144:ef7eb2e8f9f7	4174	* @brief Configure PLLSAI1 used for 48Mhz domain clock
<>	144:ef7eb2e8f9f7	4175	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	4176	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4177	* @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
<>	144:ef7eb2e8f9f7	4178	* @note This can be selected for USB, RNG, SDMMC
<>	144:ef7eb2e8f9f7	4179	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
<>	144:ef7eb2e8f9f7	4180	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
<>	144:ef7eb2e8f9f7	4181	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
<>	144:ef7eb2e8f9f7	4182	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
<>	144:ef7eb2e8f9f7	4183	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4184	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	4185	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	4186	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	4187	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	4188	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4189	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	4190	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	4191	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	4192	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	4193	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	4194	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	4195	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	4196	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	4197	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	4198	* @param PLLQ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4199	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
<>	144:ef7eb2e8f9f7	4200	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
<>	144:ef7eb2e8f9f7	4201	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
<>	144:ef7eb2e8f9f7	4202	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
<>	144:ef7eb2e8f9f7	4203	* @retval None
<>	144:ef7eb2e8f9f7	4204	*/
<>	144:ef7eb2e8f9f7	4205	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
<>	144:ef7eb2e8f9f7	4206	{
<>	144:ef7eb2e8f9f7	4207	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	167:e84263d55307	4208	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLQ);
<>	144:ef7eb2e8f9f7	4209	}
AnnaBridge	181:57724642e740	4210	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	181:57724642e740	4211
AnnaBridge	181:57724642e740	4212	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	181:57724642e740	4213	/**
AnnaBridge	181:57724642e740	4214	* @brief Configure PLLSAI1 used for SAI domain clock
AnnaBridge	181:57724642e740	4215	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4216	* @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
AnnaBridge	181:57724642e740	4217	* @note This can be selected for SAI1 or SAI2
AnnaBridge	181:57724642e740	4218	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4219	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4220	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4221	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
AnnaBridge	181:57724642e740	4222	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4223	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	4224	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	4225	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	4226	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	4227	* @param PLLM This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4228	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	181:57724642e740	4229	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	181:57724642e740	4230	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	181:57724642e740	4231	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	181:57724642e740	4232	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	181:57724642e740	4233	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	181:57724642e740	4234	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	181:57724642e740	4235	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	181:57724642e740	4236	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	181:57724642e740	4237	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	181:57724642e740	4238	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	181:57724642e740	4239	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	181:57724642e740	4240	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	181:57724642e740	4241	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	181:57724642e740	4242	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	181:57724642e740	4243	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	181:57724642e740	4244	* @param PLLN Between 8 and 86
AnnaBridge	181:57724642e740	4245	* @param PLLP This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4246	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	181:57724642e740	4247	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	181:57724642e740	4248	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	181:57724642e740	4249	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	181:57724642e740	4250	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	181:57724642e740	4251	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	181:57724642e740	4252	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	181:57724642e740	4253	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	181:57724642e740	4254	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	181:57724642e740	4255	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	181:57724642e740	4256	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	181:57724642e740	4257	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	181:57724642e740	4258	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	181:57724642e740	4259	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	181:57724642e740	4260	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	181:57724642e740	4261	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	181:57724642e740	4262	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	181:57724642e740	4263	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	181:57724642e740	4264	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	181:57724642e740	4265	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	181:57724642e740	4266	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	181:57724642e740	4267	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	181:57724642e740	4268	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	181:57724642e740	4269	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	181:57724642e740	4270	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	181:57724642e740	4271	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	181:57724642e740	4272	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	181:57724642e740	4273	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	181:57724642e740	4274	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	181:57724642e740	4275	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	181:57724642e740	4276	* @retval None
AnnaBridge	181:57724642e740	4277	*/
AnnaBridge	181:57724642e740	4278	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	181:57724642e740	4279	{
AnnaBridge	181:57724642e740	4280	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	181:57724642e740	4281	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
AnnaBridge	181:57724642e740	4282	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	181:57724642e740	4283	}
AnnaBridge	181:57724642e740	4284	#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	4285	/**
<>	144:ef7eb2e8f9f7	4286	* @brief Configure PLLSAI1 used for SAI domain clock
<>	144:ef7eb2e8f9f7	4287	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	4288	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4289	* @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
<>	144:ef7eb2e8f9f7	4290	* @note This can be selected for SAI1 or SAI2 (*)
<>	144:ef7eb2e8f9f7	4291	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4292	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4293	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4294	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
<>	144:ef7eb2e8f9f7	4295	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4296	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	4297	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	4298	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	4299	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	4300	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4301	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	4302	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	4303	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	4304	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	4305	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	4306	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	4307	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	4308	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	4309	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	4310	* @param PLLP This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4311	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
<>	144:ef7eb2e8f9f7	4312	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
<>	144:ef7eb2e8f9f7	4313	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
<>	144:ef7eb2e8f9f7	4314	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
<>	144:ef7eb2e8f9f7	4315	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
<>	144:ef7eb2e8f9f7	4316	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
<>	144:ef7eb2e8f9f7	4317	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
<>	144:ef7eb2e8f9f7	4318	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
<>	144:ef7eb2e8f9f7	4319	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
<>	144:ef7eb2e8f9f7	4320	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
<>	144:ef7eb2e8f9f7	4321	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
<>	144:ef7eb2e8f9f7	4322	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
<>	144:ef7eb2e8f9f7	4323	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
<>	144:ef7eb2e8f9f7	4324	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
<>	144:ef7eb2e8f9f7	4325	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
<>	144:ef7eb2e8f9f7	4326	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
<>	144:ef7eb2e8f9f7	4327	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
<>	144:ef7eb2e8f9f7	4328	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
<>	144:ef7eb2e8f9f7	4329	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
<>	144:ef7eb2e8f9f7	4330	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
<>	144:ef7eb2e8f9f7	4331	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
<>	144:ef7eb2e8f9f7	4332	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
<>	144:ef7eb2e8f9f7	4333	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
<>	144:ef7eb2e8f9f7	4334	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
<>	144:ef7eb2e8f9f7	4335	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
<>	144:ef7eb2e8f9f7	4336	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
<>	144:ef7eb2e8f9f7	4337	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
<>	144:ef7eb2e8f9f7	4338	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
<>	144:ef7eb2e8f9f7	4339	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
<>	144:ef7eb2e8f9f7	4340	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
<>	144:ef7eb2e8f9f7	4341	* @retval None
<>	144:ef7eb2e8f9f7	4342	*/
AnnaBridge	181:57724642e740	4343	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	181:57724642e740	4344	{
AnnaBridge	181:57724642e740	4345	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	181:57724642e740	4346	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
AnnaBridge	181:57724642e740	4347	PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	181:57724642e740	4348	}
<>	144:ef7eb2e8f9f7	4349	#else
<>	144:ef7eb2e8f9f7	4350	/**
<>	144:ef7eb2e8f9f7	4351	* @brief Configure PLLSAI1 used for SAI domain clock
<>	144:ef7eb2e8f9f7	4352	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	4353	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4354	* @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.
<>	144:ef7eb2e8f9f7	4355	* @note This can be selected for SAI1 or SAI2 (*)
<>	144:ef7eb2e8f9f7	4356	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4357	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4358	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4359	* PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
<>	144:ef7eb2e8f9f7	4360	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4361	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	4362	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	4363	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	4364	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	4365	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4366	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	4367	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	4368	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	4369	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	4370	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	4371	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	4372	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	4373	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	4374	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	4375	* @param PLLP This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4376	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
<>	144:ef7eb2e8f9f7	4377	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
<>	144:ef7eb2e8f9f7	4378	* @retval None
<>	144:ef7eb2e8f9f7	4379	*/
<>	144:ef7eb2e8f9f7	4380	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
<>	144:ef7eb2e8f9f7	4381	{
<>	144:ef7eb2e8f9f7	4382	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	181:57724642e740	4383	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	181:57724642e740	4384	}
AnnaBridge	181:57724642e740	4385	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	181:57724642e740	4386
AnnaBridge	181:57724642e740	4387	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	4388	/**
AnnaBridge	181:57724642e740	4389	* @brief Configure PLLSAI1 used for ADC domain clock
AnnaBridge	181:57724642e740	4390	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4391	* @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
AnnaBridge	181:57724642e740	4392	* @note This can be selected for ADC
AnnaBridge	181:57724642e740	4393	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	181:57724642e740	4394	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	181:57724642e740	4395	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	181:57724642e740	4396	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
AnnaBridge	181:57724642e740	4397	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4398	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	4399	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	4400	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	4401	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	4402	* @param PLLM This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4403	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	181:57724642e740	4404	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	181:57724642e740	4405	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	181:57724642e740	4406	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	181:57724642e740	4407	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	181:57724642e740	4408	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	181:57724642e740	4409	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	181:57724642e740	4410	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	181:57724642e740	4411	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	181:57724642e740	4412	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	181:57724642e740	4413	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	181:57724642e740	4414	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	181:57724642e740	4415	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	181:57724642e740	4416	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	181:57724642e740	4417	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	181:57724642e740	4418	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	181:57724642e740	4419	* @param PLLN Between 8 and 86
AnnaBridge	181:57724642e740	4420	* @param PLLR This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4421	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	181:57724642e740	4422	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	181:57724642e740	4423	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	181:57724642e740	4424	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	181:57724642e740	4425	* @retval None
AnnaBridge	181:57724642e740	4426	*/
AnnaBridge	181:57724642e740	4427	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	181:57724642e740	4428	{
AnnaBridge	181:57724642e740	4429	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	181:57724642e740	4430	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R,
AnnaBridge	181:57724642e740	4431	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLR);
AnnaBridge	181:57724642e740	4432	}
<>	144:ef7eb2e8f9f7	4433	#else
<>	144:ef7eb2e8f9f7	4434	/**
<>	144:ef7eb2e8f9f7	4435	* @brief Configure PLLSAI1 used for ADC domain clock
<>	144:ef7eb2e8f9f7	4436	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	4437	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4438	* @note PLLN/PLLR can be written only when PLLSAI1 is disabled.
<>	144:ef7eb2e8f9f7	4439	* @note This can be selected for ADC
<>	144:ef7eb2e8f9f7	4440	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
<>	144:ef7eb2e8f9f7	4441	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
<>	144:ef7eb2e8f9f7	4442	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
<>	144:ef7eb2e8f9f7	4443	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
<>	144:ef7eb2e8f9f7	4444	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4445	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	4446	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	4447	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	4448	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	4449	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4450	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	4451	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	4452	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	4453	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	4454	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	4455	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	4456	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	4457	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	4458	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	4459	* @param PLLR This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4460	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
<>	144:ef7eb2e8f9f7	4461	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
<>	144:ef7eb2e8f9f7	4462	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
<>	144:ef7eb2e8f9f7	4463	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
<>	144:ef7eb2e8f9f7	4464	* @retval None
<>	144:ef7eb2e8f9f7	4465	*/
<>	144:ef7eb2e8f9f7	4466	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
<>	144:ef7eb2e8f9f7	4467	{
<>	144:ef7eb2e8f9f7	4468	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	167:e84263d55307	4469	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLR);
<>	144:ef7eb2e8f9f7	4470	}
AnnaBridge	181:57724642e740	4471	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
<>	144:ef7eb2e8f9f7	4472
<>	144:ef7eb2e8f9f7	4473	/**
<>	144:ef7eb2e8f9f7	4474	* @brief Get SAI1PLL multiplication factor for VCO
<>	144:ef7eb2e8f9f7	4475	* @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
<>	144:ef7eb2e8f9f7	4476	* @retval Between 8 and 86
<>	144:ef7eb2e8f9f7	4477	*/
<>	144:ef7eb2e8f9f7	4478	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
<>	144:ef7eb2e8f9f7	4479	{
AnnaBridge	167:e84263d55307	4480	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
<>	144:ef7eb2e8f9f7	4481	}
<>	144:ef7eb2e8f9f7	4482
<>	144:ef7eb2e8f9f7	4483	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	4484	/**
<>	144:ef7eb2e8f9f7	4485	* @brief Get SAI1PLL division factor for PLLSAI1P
AnnaBridge	181:57724642e740	4486	* @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
<>	144:ef7eb2e8f9f7	4487	* @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
<>	144:ef7eb2e8f9f7	4488	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4489	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
<>	144:ef7eb2e8f9f7	4490	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
<>	144:ef7eb2e8f9f7	4491	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
<>	144:ef7eb2e8f9f7	4492	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
<>	144:ef7eb2e8f9f7	4493	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
<>	144:ef7eb2e8f9f7	4494	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
<>	144:ef7eb2e8f9f7	4495	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
<>	144:ef7eb2e8f9f7	4496	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
<>	144:ef7eb2e8f9f7	4497	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
<>	144:ef7eb2e8f9f7	4498	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
<>	144:ef7eb2e8f9f7	4499	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
<>	144:ef7eb2e8f9f7	4500	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
<>	144:ef7eb2e8f9f7	4501	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
<>	144:ef7eb2e8f9f7	4502	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
<>	144:ef7eb2e8f9f7	4503	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
<>	144:ef7eb2e8f9f7	4504	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
<>	144:ef7eb2e8f9f7	4505	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
<>	144:ef7eb2e8f9f7	4506	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
<>	144:ef7eb2e8f9f7	4507	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
<>	144:ef7eb2e8f9f7	4508	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
<>	144:ef7eb2e8f9f7	4509	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
<>	144:ef7eb2e8f9f7	4510	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
<>	144:ef7eb2e8f9f7	4511	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
<>	144:ef7eb2e8f9f7	4512	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
<>	144:ef7eb2e8f9f7	4513	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
<>	144:ef7eb2e8f9f7	4514	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
<>	144:ef7eb2e8f9f7	4515	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
<>	144:ef7eb2e8f9f7	4516	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
<>	144:ef7eb2e8f9f7	4517	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
<>	144:ef7eb2e8f9f7	4518	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
<>	144:ef7eb2e8f9f7	4519	*/
AnnaBridge	181:57724642e740	4520	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
AnnaBridge	181:57724642e740	4521	{
AnnaBridge	181:57724642e740	4522	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
AnnaBridge	181:57724642e740	4523	}
<>	144:ef7eb2e8f9f7	4524	#else
<>	144:ef7eb2e8f9f7	4525	/**
<>	144:ef7eb2e8f9f7	4526	* @brief Get SAI1PLL division factor for PLLSAI1P
AnnaBridge	181:57724642e740	4527	* @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
<>	144:ef7eb2e8f9f7	4528	* @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
<>	144:ef7eb2e8f9f7	4529	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4530	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
<>	144:ef7eb2e8f9f7	4531	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
<>	144:ef7eb2e8f9f7	4532	*/
AnnaBridge	181:57724642e740	4533	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
AnnaBridge	181:57724642e740	4534	{
AnnaBridge	181:57724642e740	4535	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
AnnaBridge	181:57724642e740	4536	}
<>	144:ef7eb2e8f9f7	4537	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
<>	144:ef7eb2e8f9f7	4538
<>	144:ef7eb2e8f9f7	4539	/**
<>	144:ef7eb2e8f9f7	4540	* @brief Get SAI1PLL division factor for PLLSAI1Q
AnnaBridge	181:57724642e740	4541	* @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
<>	144:ef7eb2e8f9f7	4542	* @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
<>	144:ef7eb2e8f9f7	4543	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4544	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
<>	144:ef7eb2e8f9f7	4545	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
<>	144:ef7eb2e8f9f7	4546	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
<>	144:ef7eb2e8f9f7	4547	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
<>	144:ef7eb2e8f9f7	4548	*/
<>	144:ef7eb2e8f9f7	4549	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
<>	144:ef7eb2e8f9f7	4550	{
<>	144:ef7eb2e8f9f7	4551	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
<>	144:ef7eb2e8f9f7	4552	}
<>	144:ef7eb2e8f9f7	4553
<>	144:ef7eb2e8f9f7	4554	/**
<>	144:ef7eb2e8f9f7	4555	* @brief Get PLLSAI1 division factor for PLLSAIR
AnnaBridge	181:57724642e740	4556	* @note Used for PLLADC1CLK (ADC clock)
<>	144:ef7eb2e8f9f7	4557	* @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
<>	144:ef7eb2e8f9f7	4558	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4559	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
<>	144:ef7eb2e8f9f7	4560	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
<>	144:ef7eb2e8f9f7	4561	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
<>	144:ef7eb2e8f9f7	4562	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
<>	144:ef7eb2e8f9f7	4563	*/
<>	144:ef7eb2e8f9f7	4564	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
<>	144:ef7eb2e8f9f7	4565	{
<>	144:ef7eb2e8f9f7	4566	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
<>	144:ef7eb2e8f9f7	4567	}
<>	144:ef7eb2e8f9f7	4568
AnnaBridge	181:57724642e740	4569	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	4570	/**
AnnaBridge	181:57724642e740	4571	* @brief Get Division factor for the PLLSAI1
AnnaBridge	181:57724642e740	4572	* @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
AnnaBridge	181:57724642e740	4573	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	4574	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	181:57724642e740	4575	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	181:57724642e740	4576	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	181:57724642e740	4577	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	181:57724642e740	4578	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	181:57724642e740	4579	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	181:57724642e740	4580	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	181:57724642e740	4581	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	181:57724642e740	4582	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	181:57724642e740	4583	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	181:57724642e740	4584	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	181:57724642e740	4585	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	181:57724642e740	4586	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	181:57724642e740	4587	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	181:57724642e740	4588	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	181:57724642e740	4589	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	181:57724642e740	4590	*/
AnnaBridge	181:57724642e740	4591	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
AnnaBridge	181:57724642e740	4592	{
AnnaBridge	181:57724642e740	4593	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
AnnaBridge	181:57724642e740	4594	}
AnnaBridge	181:57724642e740	4595	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	181:57724642e740	4596
<>	144:ef7eb2e8f9f7	4597	/**
<>	144:ef7eb2e8f9f7	4598	* @brief Enable PLLSAI1 output mapped on SAI domain clock
<>	144:ef7eb2e8f9f7	4599	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
<>	144:ef7eb2e8f9f7	4600	* @retval None
<>	144:ef7eb2e8f9f7	4601	*/
<>	144:ef7eb2e8f9f7	4602	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
<>	144:ef7eb2e8f9f7	4603	{
<>	144:ef7eb2e8f9f7	4604	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
<>	144:ef7eb2e8f9f7	4605	}
<>	144:ef7eb2e8f9f7	4606
<>	144:ef7eb2e8f9f7	4607	/**
<>	144:ef7eb2e8f9f7	4608	* @brief Disable PLLSAI1 output mapped on SAI domain clock
<>	144:ef7eb2e8f9f7	4609	* @note In order to save power, when of the PLLSAI1 is
<>	144:ef7eb2e8f9f7	4610	* not used, should be 0
<>	144:ef7eb2e8f9f7	4611	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
<>	144:ef7eb2e8f9f7	4612	* @retval None
<>	144:ef7eb2e8f9f7	4613	*/
<>	144:ef7eb2e8f9f7	4614	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
<>	144:ef7eb2e8f9f7	4615	{
<>	144:ef7eb2e8f9f7	4616	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
<>	144:ef7eb2e8f9f7	4617	}
<>	144:ef7eb2e8f9f7	4618
<>	144:ef7eb2e8f9f7	4619	/**
<>	144:ef7eb2e8f9f7	4620	* @brief Enable PLLSAI1 output mapped on 48MHz domain clock
<>	144:ef7eb2e8f9f7	4621	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
<>	144:ef7eb2e8f9f7	4622	* @retval None
<>	144:ef7eb2e8f9f7	4623	*/
<>	144:ef7eb2e8f9f7	4624	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
<>	144:ef7eb2e8f9f7	4625	{
<>	144:ef7eb2e8f9f7	4626	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
<>	144:ef7eb2e8f9f7	4627	}
<>	144:ef7eb2e8f9f7	4628
<>	144:ef7eb2e8f9f7	4629	/**
<>	144:ef7eb2e8f9f7	4630	* @brief Disable PLLSAI1 output mapped on 48MHz domain clock
<>	144:ef7eb2e8f9f7	4631	* @note In order to save power, when of the PLLSAI1 is
<>	144:ef7eb2e8f9f7	4632	* not used, should be 0
<>	144:ef7eb2e8f9f7	4633	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
<>	144:ef7eb2e8f9f7	4634	* @retval None
<>	144:ef7eb2e8f9f7	4635	*/
<>	144:ef7eb2e8f9f7	4636	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
<>	144:ef7eb2e8f9f7	4637	{
<>	144:ef7eb2e8f9f7	4638	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
<>	144:ef7eb2e8f9f7	4639	}
<>	144:ef7eb2e8f9f7	4640
<>	144:ef7eb2e8f9f7	4641	/**
<>	144:ef7eb2e8f9f7	4642	* @brief Enable PLLSAI1 output mapped on ADC domain clock
<>	144:ef7eb2e8f9f7	4643	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
<>	144:ef7eb2e8f9f7	4644	* @retval None
<>	144:ef7eb2e8f9f7	4645	*/
<>	144:ef7eb2e8f9f7	4646	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
<>	144:ef7eb2e8f9f7	4647	{
<>	144:ef7eb2e8f9f7	4648	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
<>	144:ef7eb2e8f9f7	4649	}
<>	144:ef7eb2e8f9f7	4650
<>	144:ef7eb2e8f9f7	4651	/**
<>	144:ef7eb2e8f9f7	4652	* @brief Disable PLLSAI1 output mapped on ADC domain clock
<>	144:ef7eb2e8f9f7	4653	* @note In order to save power, when of the PLLSAI1 is
<>	144:ef7eb2e8f9f7	4654	* not used, Main PLLSAI1 should be 0
<>	144:ef7eb2e8f9f7	4655	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
<>	144:ef7eb2e8f9f7	4656	* @retval None
<>	144:ef7eb2e8f9f7	4657	*/
<>	144:ef7eb2e8f9f7	4658	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
<>	144:ef7eb2e8f9f7	4659	{
<>	144:ef7eb2e8f9f7	4660	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
<>	144:ef7eb2e8f9f7	4661	}
<>	144:ef7eb2e8f9f7	4662
<>	144:ef7eb2e8f9f7	4663	/**
<>	144:ef7eb2e8f9f7	4664	* @}
<>	144:ef7eb2e8f9f7	4665	*/
<>	144:ef7eb2e8f9f7	4666
<>	144:ef7eb2e8f9f7	4667	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	4668	/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
<>	144:ef7eb2e8f9f7	4669	* @{
<>	144:ef7eb2e8f9f7	4670	*/
<>	144:ef7eb2e8f9f7	4671
<>	144:ef7eb2e8f9f7	4672	/**
<>	144:ef7eb2e8f9f7	4673	* @brief Enable PLLSAI2
<>	144:ef7eb2e8f9f7	4674	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
<>	144:ef7eb2e8f9f7	4675	* @retval None
<>	144:ef7eb2e8f9f7	4676	*/
<>	144:ef7eb2e8f9f7	4677	__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
<>	144:ef7eb2e8f9f7	4678	{
<>	144:ef7eb2e8f9f7	4679	SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
<>	144:ef7eb2e8f9f7	4680	}
<>	144:ef7eb2e8f9f7	4681
<>	144:ef7eb2e8f9f7	4682	/**
<>	144:ef7eb2e8f9f7	4683	* @brief Disable PLLSAI2
<>	144:ef7eb2e8f9f7	4684	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
<>	144:ef7eb2e8f9f7	4685	* @retval None
<>	144:ef7eb2e8f9f7	4686	*/
<>	144:ef7eb2e8f9f7	4687	__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
<>	144:ef7eb2e8f9f7	4688	{
<>	144:ef7eb2e8f9f7	4689	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
<>	144:ef7eb2e8f9f7	4690	}
<>	144:ef7eb2e8f9f7	4691
<>	144:ef7eb2e8f9f7	4692	/**
<>	144:ef7eb2e8f9f7	4693	* @brief Check if PLLSAI2 Ready
<>	144:ef7eb2e8f9f7	4694	* @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
<>	144:ef7eb2e8f9f7	4695	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4696	*/
<>	144:ef7eb2e8f9f7	4697	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
<>	144:ef7eb2e8f9f7	4698	{
<>	144:ef7eb2e8f9f7	4699	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
<>	144:ef7eb2e8f9f7	4700	}
<>	144:ef7eb2e8f9f7	4701
AnnaBridge	181:57724642e740	4702	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	181:57724642e740	4703	/**
AnnaBridge	181:57724642e740	4704	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	181:57724642e740	4705	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4706	* @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
AnnaBridge	181:57724642e740	4707	* @note This can be selected for SAI1 or SAI2
AnnaBridge	181:57724642e740	4708	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4709	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4710	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4711	* PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	181:57724642e740	4712	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4713	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	4714	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	4715	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	4716	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	4717	* @param PLLM This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4718	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	181:57724642e740	4719	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	181:57724642e740	4720	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	181:57724642e740	4721	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	181:57724642e740	4722	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	181:57724642e740	4723	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	181:57724642e740	4724	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	181:57724642e740	4725	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	181:57724642e740	4726	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	181:57724642e740	4727	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	181:57724642e740	4728	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	181:57724642e740	4729	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	181:57724642e740	4730	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	181:57724642e740	4731	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	181:57724642e740	4732	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	181:57724642e740	4733	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	181:57724642e740	4734	* @param PLLN Between 8 and 86
AnnaBridge	181:57724642e740	4735	* @param PLLP This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4736	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	181:57724642e740	4737	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	181:57724642e740	4738	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	181:57724642e740	4739	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	181:57724642e740	4740	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	181:57724642e740	4741	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	181:57724642e740	4742	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	181:57724642e740	4743	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	181:57724642e740	4744	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	181:57724642e740	4745	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	181:57724642e740	4746	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	181:57724642e740	4747	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	181:57724642e740	4748	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	181:57724642e740	4749	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	181:57724642e740	4750	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	181:57724642e740	4751	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	181:57724642e740	4752	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	181:57724642e740	4753	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	181:57724642e740	4754	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	181:57724642e740	4755	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	181:57724642e740	4756	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	181:57724642e740	4757	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	181:57724642e740	4758	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	181:57724642e740	4759	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	181:57724642e740	4760	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	181:57724642e740	4761	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	181:57724642e740	4762	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	181:57724642e740	4763	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	181:57724642e740	4764	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	181:57724642e740	4765	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	181:57724642e740	4766	* @retval None
AnnaBridge	181:57724642e740	4767	*/
AnnaBridge	181:57724642e740	4768	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	181:57724642e740	4769	{
AnnaBridge	181:57724642e740	4770	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	181:57724642e740	4771	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2PDIV,
AnnaBridge	181:57724642e740	4772	PLLM \| PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	181:57724642e740	4773	}
AnnaBridge	181:57724642e740	4774	#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	4775	/**
<>	144:ef7eb2e8f9f7	4776	* @brief Configure PLLSAI2 used for SAI domain clock
<>	144:ef7eb2e8f9f7	4777	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	4778	* PLLSAI1 and PLLSAI2 are disabled.
AnnaBridge	181:57724642e740	4779	* @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
AnnaBridge	181:57724642e740	4780	* @note This can be selected for SAI1 or SAI2
AnnaBridge	181:57724642e740	4781	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4782	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4783	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	181:57724642e740	4784	* PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	181:57724642e740	4785	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4786	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	4787	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	4788	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	4789	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	4790	* @param PLLM This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4791	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	181:57724642e740	4792	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	181:57724642e740	4793	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	181:57724642e740	4794	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	181:57724642e740	4795	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	181:57724642e740	4796	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	181:57724642e740	4797	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	181:57724642e740	4798	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	181:57724642e740	4799	* @param PLLN Between 8 and 86
AnnaBridge	181:57724642e740	4800	* @param PLLP This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4801	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	181:57724642e740	4802	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	181:57724642e740	4803	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	181:57724642e740	4804	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	181:57724642e740	4805	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	181:57724642e740	4806	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	181:57724642e740	4807	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	181:57724642e740	4808	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	181:57724642e740	4809	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	181:57724642e740	4810	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	181:57724642e740	4811	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	181:57724642e740	4812	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	181:57724642e740	4813	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	181:57724642e740	4814	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	181:57724642e740	4815	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	181:57724642e740	4816	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	181:57724642e740	4817	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	181:57724642e740	4818	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	181:57724642e740	4819	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	181:57724642e740	4820	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	181:57724642e740	4821	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	181:57724642e740	4822	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	181:57724642e740	4823	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	181:57724642e740	4824	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	181:57724642e740	4825	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	181:57724642e740	4826	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	181:57724642e740	4827	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	181:57724642e740	4828	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	181:57724642e740	4829	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	181:57724642e740	4830	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	181:57724642e740	4831	* @retval None
AnnaBridge	181:57724642e740	4832	*/
AnnaBridge	181:57724642e740	4833	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	181:57724642e740	4834	{
AnnaBridge	181:57724642e740	4835	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	181:57724642e740	4836	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	181:57724642e740	4837	}
AnnaBridge	181:57724642e740	4838	#else
AnnaBridge	181:57724642e740	4839	/**
AnnaBridge	181:57724642e740	4840	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	181:57724642e740	4841	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	4842	* PLLSAI2 and PLLSAI2 are disabled.
AnnaBridge	181:57724642e740	4843	* @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
<>	144:ef7eb2e8f9f7	4844	* @note This can be selected for SAI1 or SAI2
<>	144:ef7eb2e8f9f7	4845	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4846	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4847	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
<>	144:ef7eb2e8f9f7	4848	* PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
<>	144:ef7eb2e8f9f7	4849	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4850	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	4851	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	4852	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	4853	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	4854	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4855	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	4856	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	4857	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	4858	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	4859	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	4860	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	4861	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	4862	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	4863	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	4864	* @param PLLP This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4865	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
<>	144:ef7eb2e8f9f7	4866	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
<>	144:ef7eb2e8f9f7	4867	* @retval None
<>	144:ef7eb2e8f9f7	4868	*/
<>	144:ef7eb2e8f9f7	4869	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
<>	144:ef7eb2e8f9f7	4870	{
<>	144:ef7eb2e8f9f7	4871	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	167:e84263d55307	4872	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
<>	144:ef7eb2e8f9f7	4873	}
AnnaBridge	181:57724642e740	4874	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	181:57724642e740	4875
AnnaBridge	181:57724642e740	4876	#if defined(DSI)
AnnaBridge	181:57724642e740	4877	/**
AnnaBridge	181:57724642e740	4878	* @brief Configure PLLSAI2 used for DSI domain clock
AnnaBridge	181:57724642e740	4879	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4880	* @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
AnnaBridge	181:57724642e740	4881	* @note This can be selected for DSI
AnnaBridge	181:57724642e740	4882	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	181:57724642e740	4883	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	181:57724642e740	4884	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	181:57724642e740	4885	* PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
AnnaBridge	181:57724642e740	4886	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4887	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	4888	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	4889	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	4890	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	4891	* @param PLLM This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4892	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	181:57724642e740	4893	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	181:57724642e740	4894	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	181:57724642e740	4895	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	181:57724642e740	4896	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	181:57724642e740	4897	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	181:57724642e740	4898	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	181:57724642e740	4899	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	181:57724642e740	4900	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	181:57724642e740	4901	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	181:57724642e740	4902	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	181:57724642e740	4903	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	181:57724642e740	4904	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	181:57724642e740	4905	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	181:57724642e740	4906	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	181:57724642e740	4907	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	181:57724642e740	4908	* @param PLLN Between 8 and 86
AnnaBridge	181:57724642e740	4909	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4910	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	181:57724642e740	4911	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	181:57724642e740	4912	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	181:57724642e740	4913	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	181:57724642e740	4914	* @retval None
AnnaBridge	181:57724642e740	4915	*/
AnnaBridge	181:57724642e740	4916	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	181:57724642e740	4917	{
AnnaBridge	181:57724642e740	4918	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	181:57724642e740	4919	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLQ \| PLLM);
AnnaBridge	181:57724642e740	4920	}
AnnaBridge	181:57724642e740	4921	#endif /* DSI */
AnnaBridge	181:57724642e740	4922
AnnaBridge	181:57724642e740	4923	#if defined(LTDC)
AnnaBridge	181:57724642e740	4924	/**
AnnaBridge	181:57724642e740	4925	* @brief Configure PLLSAI2 used for LTDC domain clock
AnnaBridge	181:57724642e740	4926	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	181:57724642e740	4927	* @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
AnnaBridge	181:57724642e740	4928	* @note This can be selected for LTDC
AnnaBridge	181:57724642e740	4929	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	181:57724642e740	4930	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	181:57724642e740	4931	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	181:57724642e740	4932	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	181:57724642e740	4933	* CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
AnnaBridge	181:57724642e740	4934	* @param Source This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4935	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	181:57724642e740	4936	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	181:57724642e740	4937	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	181:57724642e740	4938	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	181:57724642e740	4939	* @param PLLM This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4940	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	181:57724642e740	4941	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	181:57724642e740	4942	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	181:57724642e740	4943	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	181:57724642e740	4944	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	181:57724642e740	4945	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	181:57724642e740	4946	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	181:57724642e740	4947	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	181:57724642e740	4948	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	181:57724642e740	4949	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	181:57724642e740	4950	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	181:57724642e740	4951	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	181:57724642e740	4952	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	181:57724642e740	4953	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	181:57724642e740	4954	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	181:57724642e740	4955	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	181:57724642e740	4956	* @param PLLN Between 8 and 86
AnnaBridge	181:57724642e740	4957	* @param PLLR This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4958	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	181:57724642e740	4959	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	181:57724642e740	4960	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	181:57724642e740	4961	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	181:57724642e740	4962	* @param PLLDIVR This parameter can be one of the following values:
AnnaBridge	181:57724642e740	4963	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	181:57724642e740	4964	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	181:57724642e740	4965	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	181:57724642e740	4966	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	181:57724642e740	4967	* @retval None
AnnaBridge	181:57724642e740	4968	*/
AnnaBridge	181:57724642e740	4969	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
AnnaBridge	181:57724642e740	4970	{
AnnaBridge	181:57724642e740	4971	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	181:57724642e740	4972	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLR \| PLLM);
AnnaBridge	181:57724642e740	4973	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
AnnaBridge	181:57724642e740	4974	}
AnnaBridge	181:57724642e740	4975	#else
<>	144:ef7eb2e8f9f7	4976	/**
<>	144:ef7eb2e8f9f7	4977	* @brief Configure PLLSAI2 used for ADC domain clock
<>	144:ef7eb2e8f9f7	4978	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	181:57724642e740	4979	* PLLSAI2 and PLLSAI2 are disabled.
AnnaBridge	181:57724642e740	4980	* @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
<>	144:ef7eb2e8f9f7	4981	* @note This can be selected for ADC
<>	144:ef7eb2e8f9f7	4982	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
<>	144:ef7eb2e8f9f7	4983	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
<>	144:ef7eb2e8f9f7	4984	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
<>	144:ef7eb2e8f9f7	4985	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
<>	144:ef7eb2e8f9f7	4986	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4987	* @arg @ref LL_RCC_PLLSOURCE_NONE
<>	144:ef7eb2e8f9f7	4988	* @arg @ref LL_RCC_PLLSOURCE_MSI
<>	144:ef7eb2e8f9f7	4989	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	144:ef7eb2e8f9f7	4990	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	144:ef7eb2e8f9f7	4991	* @param PLLM This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4992	* @arg @ref LL_RCC_PLLM_DIV_1
<>	144:ef7eb2e8f9f7	4993	* @arg @ref LL_RCC_PLLM_DIV_2
<>	144:ef7eb2e8f9f7	4994	* @arg @ref LL_RCC_PLLM_DIV_3
<>	144:ef7eb2e8f9f7	4995	* @arg @ref LL_RCC_PLLM_DIV_4
<>	144:ef7eb2e8f9f7	4996	* @arg @ref LL_RCC_PLLM_DIV_5
<>	144:ef7eb2e8f9f7	4997	* @arg @ref LL_RCC_PLLM_DIV_6
<>	144:ef7eb2e8f9f7	4998	* @arg @ref LL_RCC_PLLM_DIV_7
<>	144:ef7eb2e8f9f7	4999	* @arg @ref LL_RCC_PLLM_DIV_8
<>	144:ef7eb2e8f9f7	5000	* @param PLLN Between 8 and 86
<>	144:ef7eb2e8f9f7	5001	* @param PLLR This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5002	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
<>	144:ef7eb2e8f9f7	5003	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
<>	144:ef7eb2e8f9f7	5004	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
<>	144:ef7eb2e8f9f7	5005	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
<>	144:ef7eb2e8f9f7	5006	* @retval None
<>	144:ef7eb2e8f9f7	5007	*/
<>	144:ef7eb2e8f9f7	5008	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
<>	144:ef7eb2e8f9f7	5009	{
<>	144:ef7eb2e8f9f7	5010	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	167:e84263d55307	5011	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLR);
<>	144:ef7eb2e8f9f7	5012	}
AnnaBridge	181:57724642e740	5013	#endif /* LTDC */
<>	144:ef7eb2e8f9f7	5014
<>	144:ef7eb2e8f9f7	5015	/**
<>	144:ef7eb2e8f9f7	5016	* @brief Get SAI2PLL multiplication factor for VCO
<>	144:ef7eb2e8f9f7	5017	* @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
<>	144:ef7eb2e8f9f7	5018	* @retval Between 8 and 86
<>	144:ef7eb2e8f9f7	5019	*/
<>	144:ef7eb2e8f9f7	5020	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
<>	144:ef7eb2e8f9f7	5021	{
AnnaBridge	167:e84263d55307	5022	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
<>	144:ef7eb2e8f9f7	5023	}
<>	144:ef7eb2e8f9f7	5024
AnnaBridge	181:57724642e740	5025	#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
<>	144:ef7eb2e8f9f7	5026	/**
<>	144:ef7eb2e8f9f7	5027	* @brief Get SAI2PLL division factor for PLLSAI2P
AnnaBridge	181:57724642e740	5028	* @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
AnnaBridge	181:57724642e740	5029	* @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
AnnaBridge	181:57724642e740	5030	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	5031	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	181:57724642e740	5032	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	181:57724642e740	5033	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	181:57724642e740	5034	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	181:57724642e740	5035	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	181:57724642e740	5036	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	181:57724642e740	5037	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	181:57724642e740	5038	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	181:57724642e740	5039	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	181:57724642e740	5040	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	181:57724642e740	5041	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	181:57724642e740	5042	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	181:57724642e740	5043	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	181:57724642e740	5044	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	181:57724642e740	5045	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	181:57724642e740	5046	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	181:57724642e740	5047	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	181:57724642e740	5048	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	181:57724642e740	5049	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	181:57724642e740	5050	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	181:57724642e740	5051	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	181:57724642e740	5052	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	181:57724642e740	5053	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	181:57724642e740	5054	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	181:57724642e740	5055	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	181:57724642e740	5056	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	181:57724642e740	5057	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	181:57724642e740	5058	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	181:57724642e740	5059	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	181:57724642e740	5060	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	181:57724642e740	5061	*/
AnnaBridge	181:57724642e740	5062	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
AnnaBridge	181:57724642e740	5063	{
AnnaBridge	181:57724642e740	5064	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
AnnaBridge	181:57724642e740	5065	}
AnnaBridge	181:57724642e740	5066	#else
AnnaBridge	181:57724642e740	5067	/**
AnnaBridge	181:57724642e740	5068	* @brief Get SAI2PLL division factor for PLLSAI2P
AnnaBridge	181:57724642e740	5069	* @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
<>	144:ef7eb2e8f9f7	5070	* @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
<>	144:ef7eb2e8f9f7	5071	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	5072	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
<>	144:ef7eb2e8f9f7	5073	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
<>	144:ef7eb2e8f9f7	5074	*/
<>	144:ef7eb2e8f9f7	5075	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
<>	144:ef7eb2e8f9f7	5076	{
<>	144:ef7eb2e8f9f7	5077	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
<>	144:ef7eb2e8f9f7	5078	}
AnnaBridge	181:57724642e740	5079	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	181:57724642e740	5080
AnnaBridge	181:57724642e740	5081	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	181:57724642e740	5082	/**
AnnaBridge	181:57724642e740	5083	* @brief Get division factor for PLLSAI2Q
AnnaBridge	181:57724642e740	5084	* @note Used for PLLDSICLK (DSI clock)
AnnaBridge	181:57724642e740	5085	* @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
AnnaBridge	181:57724642e740	5086	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	5087	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	181:57724642e740	5088	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	181:57724642e740	5089	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	181:57724642e740	5090	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	181:57724642e740	5091	*/
AnnaBridge	181:57724642e740	5092	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
AnnaBridge	181:57724642e740	5093	{
AnnaBridge	181:57724642e740	5094	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
AnnaBridge	181:57724642e740	5095	}
AnnaBridge	181:57724642e740	5096	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
<>	144:ef7eb2e8f9f7	5097
<>	144:ef7eb2e8f9f7	5098	/**
<>	144:ef7eb2e8f9f7	5099	* @brief Get SAI2PLL division factor for PLLSAI2R
AnnaBridge	181:57724642e740	5100	* @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices
<>	144:ef7eb2e8f9f7	5101	* @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
<>	144:ef7eb2e8f9f7	5102	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	5103	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
<>	144:ef7eb2e8f9f7	5104	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
<>	144:ef7eb2e8f9f7	5105	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
<>	144:ef7eb2e8f9f7	5106	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
<>	144:ef7eb2e8f9f7	5107	*/
<>	144:ef7eb2e8f9f7	5108	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
<>	144:ef7eb2e8f9f7	5109	{
<>	144:ef7eb2e8f9f7	5110	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
<>	144:ef7eb2e8f9f7	5111	}
<>	144:ef7eb2e8f9f7	5112
AnnaBridge	181:57724642e740	5113	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	181:57724642e740	5114	/**
AnnaBridge	181:57724642e740	5115	* @brief Get Division factor for the PLLSAI2
AnnaBridge	181:57724642e740	5116	* @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
AnnaBridge	181:57724642e740	5117	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	5118	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	181:57724642e740	5119	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	181:57724642e740	5120	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	181:57724642e740	5121	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	181:57724642e740	5122	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	181:57724642e740	5123	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	181:57724642e740	5124	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	181:57724642e740	5125	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	181:57724642e740	5126	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	181:57724642e740	5127	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	181:57724642e740	5128	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	181:57724642e740	5129	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	181:57724642e740	5130	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	181:57724642e740	5131	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	181:57724642e740	5132	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	181:57724642e740	5133	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	181:57724642e740	5134	*/
AnnaBridge	181:57724642e740	5135	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
AnnaBridge	181:57724642e740	5136	{
AnnaBridge	181:57724642e740	5137	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
AnnaBridge	181:57724642e740	5138	}
AnnaBridge	181:57724642e740	5139	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	181:57724642e740	5140
AnnaBridge	181:57724642e740	5141	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	181:57724642e740	5142	/**
AnnaBridge	181:57724642e740	5143	* @brief Get PLLSAI2 division factor for PLLSAI2DIVR
AnnaBridge	181:57724642e740	5144	* @note Used for LTDC domain clock
AnnaBridge	181:57724642e740	5145	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
AnnaBridge	181:57724642e740	5146	* @retval Returned value can be one of the following values:
AnnaBridge	181:57724642e740	5147	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	181:57724642e740	5148	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	181:57724642e740	5149	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	181:57724642e740	5150	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	181:57724642e740	5151	*/
AnnaBridge	181:57724642e740	5152	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
AnnaBridge	181:57724642e740	5153	{
AnnaBridge	181:57724642e740	5154	return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
AnnaBridge	181:57724642e740	5155	}
AnnaBridge	181:57724642e740	5156	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
AnnaBridge	181:57724642e740	5157
<>	144:ef7eb2e8f9f7	5158	/**
<>	144:ef7eb2e8f9f7	5159	* @brief Enable PLLSAI2 output mapped on SAI domain clock
<>	144:ef7eb2e8f9f7	5160	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
<>	144:ef7eb2e8f9f7	5161	* @retval None
<>	144:ef7eb2e8f9f7	5162	*/
<>	144:ef7eb2e8f9f7	5163	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
<>	144:ef7eb2e8f9f7	5164	{
<>	144:ef7eb2e8f9f7	5165	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
<>	144:ef7eb2e8f9f7	5166	}
<>	144:ef7eb2e8f9f7	5167
<>	144:ef7eb2e8f9f7	5168	/**
<>	144:ef7eb2e8f9f7	5169	* @brief Disable PLLSAI2 output mapped on SAI domain clock
<>	144:ef7eb2e8f9f7	5170	* @note In order to save power, when of the PLLSAI2 is
<>	144:ef7eb2e8f9f7	5171	* not used, should be 0
<>	144:ef7eb2e8f9f7	5172	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
<>	144:ef7eb2e8f9f7	5173	* @retval None
<>	144:ef7eb2e8f9f7	5174	*/
<>	144:ef7eb2e8f9f7	5175	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
<>	144:ef7eb2e8f9f7	5176	{
<>	144:ef7eb2e8f9f7	5177	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
<>	144:ef7eb2e8f9f7	5178	}
<>	144:ef7eb2e8f9f7	5179
AnnaBridge	181:57724642e740	5180	#if defined(DSI)
AnnaBridge	181:57724642e740	5181	/**
AnnaBridge	181:57724642e740	5182	* @brief Enable PLLSAI2 output mapped on DSI domain clock
AnnaBridge	181:57724642e740	5183	* @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI
AnnaBridge	181:57724642e740	5184	* @retval None
AnnaBridge	181:57724642e740	5185	*/
AnnaBridge	181:57724642e740	5186	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
AnnaBridge	181:57724642e740	5187	{
AnnaBridge	181:57724642e740	5188	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
AnnaBridge	181:57724642e740	5189	}
AnnaBridge	181:57724642e740	5190
AnnaBridge	181:57724642e740	5191	/**
AnnaBridge	181:57724642e740	5192	* @brief Disable PLLSAI2 output mapped on DSI domain clock
AnnaBridge	181:57724642e740	5193	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	181:57724642e740	5194	* not used, Main PLLSAI2 should be 0
AnnaBridge	181:57724642e740	5195	* @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
AnnaBridge	181:57724642e740	5196	* @retval None
AnnaBridge	181:57724642e740	5197	*/
AnnaBridge	181:57724642e740	5198	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
AnnaBridge	181:57724642e740	5199	{
AnnaBridge	181:57724642e740	5200	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
AnnaBridge	181:57724642e740	5201	}
AnnaBridge	181:57724642e740	5202	#endif /* DSI */
AnnaBridge	181:57724642e740	5203
AnnaBridge	181:57724642e740	5204	#if defined(LTDC)
AnnaBridge	181:57724642e740	5205	/**
AnnaBridge	181:57724642e740	5206	* @brief Enable PLLSAI2 output mapped on LTDC domain clock
AnnaBridge	181:57724642e740	5207	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC
AnnaBridge	181:57724642e740	5208	* @retval None
AnnaBridge	181:57724642e740	5209	*/
AnnaBridge	181:57724642e740	5210	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
AnnaBridge	181:57724642e740	5211	{
AnnaBridge	181:57724642e740	5212	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	181:57724642e740	5213	}
AnnaBridge	181:57724642e740	5214
AnnaBridge	181:57724642e740	5215	/**
AnnaBridge	181:57724642e740	5216	* @brief Disable PLLSAI2 output mapped on LTDC domain clock
AnnaBridge	181:57724642e740	5217	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	181:57724642e740	5218	* not used, Main PLLSAI2 should be 0
AnnaBridge	181:57724642e740	5219	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
AnnaBridge	181:57724642e740	5220	* @retval None
AnnaBridge	181:57724642e740	5221	*/
AnnaBridge	181:57724642e740	5222	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
AnnaBridge	181:57724642e740	5223	{
AnnaBridge	181:57724642e740	5224	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	181:57724642e740	5225	}
AnnaBridge	181:57724642e740	5226	#else
<>	144:ef7eb2e8f9f7	5227	/**
<>	144:ef7eb2e8f9f7	5228	* @brief Enable PLLSAI2 output mapped on ADC domain clock
<>	144:ef7eb2e8f9f7	5229	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
<>	144:ef7eb2e8f9f7	5230	* @retval None
<>	144:ef7eb2e8f9f7	5231	*/
<>	144:ef7eb2e8f9f7	5232	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
<>	144:ef7eb2e8f9f7	5233	{
<>	144:ef7eb2e8f9f7	5234	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
<>	144:ef7eb2e8f9f7	5235	}
<>	144:ef7eb2e8f9f7	5236
<>	144:ef7eb2e8f9f7	5237	/**
<>	144:ef7eb2e8f9f7	5238	* @brief Disable PLLSAI2 output mapped on ADC domain clock
<>	144:ef7eb2e8f9f7	5239	* @note In order to save power, when of the PLLSAI2 is
<>	144:ef7eb2e8f9f7	5240	* not used, Main PLLSAI2 should be 0
<>	144:ef7eb2e8f9f7	5241	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
<>	144:ef7eb2e8f9f7	5242	* @retval None
<>	144:ef7eb2e8f9f7	5243	*/
<>	144:ef7eb2e8f9f7	5244	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
<>	144:ef7eb2e8f9f7	5245	{
<>	144:ef7eb2e8f9f7	5246	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
<>	144:ef7eb2e8f9f7	5247	}
AnnaBridge	181:57724642e740	5248	#endif /* LTDC */
<>	144:ef7eb2e8f9f7	5249
<>	144:ef7eb2e8f9f7	5250	/**
<>	144:ef7eb2e8f9f7	5251	* @}
<>	144:ef7eb2e8f9f7	5252	*/
<>	144:ef7eb2e8f9f7	5253	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	5254
AnnaBridge	181:57724642e740	5255
AnnaBridge	181:57724642e740	5256
<>	144:ef7eb2e8f9f7	5257	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
<>	144:ef7eb2e8f9f7	5258	* @{
<>	144:ef7eb2e8f9f7	5259	*/
<>	144:ef7eb2e8f9f7	5260
<>	144:ef7eb2e8f9f7	5261	/**
<>	144:ef7eb2e8f9f7	5262	* @brief Clear LSI ready interrupt flag
<>	144:ef7eb2e8f9f7	5263	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
<>	144:ef7eb2e8f9f7	5264	* @retval None
<>	144:ef7eb2e8f9f7	5265	*/
<>	144:ef7eb2e8f9f7	5266	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
<>	144:ef7eb2e8f9f7	5267	{
<>	144:ef7eb2e8f9f7	5268	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
<>	144:ef7eb2e8f9f7	5269	}
<>	144:ef7eb2e8f9f7	5270
<>	144:ef7eb2e8f9f7	5271	/**
<>	144:ef7eb2e8f9f7	5272	* @brief Clear LSE ready interrupt flag
<>	144:ef7eb2e8f9f7	5273	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
<>	144:ef7eb2e8f9f7	5274	* @retval None
<>	144:ef7eb2e8f9f7	5275	*/
<>	144:ef7eb2e8f9f7	5276	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
<>	144:ef7eb2e8f9f7	5277	{
<>	144:ef7eb2e8f9f7	5278	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
<>	144:ef7eb2e8f9f7	5279	}
<>	144:ef7eb2e8f9f7	5280
<>	144:ef7eb2e8f9f7	5281	/**
<>	144:ef7eb2e8f9f7	5282	* @brief Clear MSI ready interrupt flag
<>	144:ef7eb2e8f9f7	5283	* @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
<>	144:ef7eb2e8f9f7	5284	* @retval None
<>	144:ef7eb2e8f9f7	5285	*/
<>	144:ef7eb2e8f9f7	5286	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
<>	144:ef7eb2e8f9f7	5287	{
<>	144:ef7eb2e8f9f7	5288	SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
<>	144:ef7eb2e8f9f7	5289	}
<>	144:ef7eb2e8f9f7	5290
<>	144:ef7eb2e8f9f7	5291	/**
<>	144:ef7eb2e8f9f7	5292	* @brief Clear HSI ready interrupt flag
<>	144:ef7eb2e8f9f7	5293	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
<>	144:ef7eb2e8f9f7	5294	* @retval None
<>	144:ef7eb2e8f9f7	5295	*/
<>	144:ef7eb2e8f9f7	5296	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
<>	144:ef7eb2e8f9f7	5297	{
<>	144:ef7eb2e8f9f7	5298	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
<>	144:ef7eb2e8f9f7	5299	}
<>	144:ef7eb2e8f9f7	5300
<>	144:ef7eb2e8f9f7	5301	/**
<>	144:ef7eb2e8f9f7	5302	* @brief Clear HSE ready interrupt flag
<>	144:ef7eb2e8f9f7	5303	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
<>	144:ef7eb2e8f9f7	5304	* @retval None
<>	144:ef7eb2e8f9f7	5305	*/
<>	144:ef7eb2e8f9f7	5306	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
<>	144:ef7eb2e8f9f7	5307	{
<>	144:ef7eb2e8f9f7	5308	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
<>	144:ef7eb2e8f9f7	5309	}
<>	144:ef7eb2e8f9f7	5310
<>	144:ef7eb2e8f9f7	5311	/**
<>	144:ef7eb2e8f9f7	5312	* @brief Clear PLL ready interrupt flag
<>	144:ef7eb2e8f9f7	5313	* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
<>	144:ef7eb2e8f9f7	5314	* @retval None
<>	144:ef7eb2e8f9f7	5315	*/
<>	144:ef7eb2e8f9f7	5316	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
<>	144:ef7eb2e8f9f7	5317	{
<>	144:ef7eb2e8f9f7	5318	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
<>	144:ef7eb2e8f9f7	5319	}
<>	144:ef7eb2e8f9f7	5320
<>	144:ef7eb2e8f9f7	5321	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	5322	/**
<>	144:ef7eb2e8f9f7	5323	* @brief Clear HSI48 ready interrupt flag
<>	144:ef7eb2e8f9f7	5324	* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
<>	144:ef7eb2e8f9f7	5325	* @retval None
<>	144:ef7eb2e8f9f7	5326	*/
<>	144:ef7eb2e8f9f7	5327	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
<>	144:ef7eb2e8f9f7	5328	{
<>	144:ef7eb2e8f9f7	5329	SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
<>	144:ef7eb2e8f9f7	5330	}
<>	144:ef7eb2e8f9f7	5331	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	5332
<>	144:ef7eb2e8f9f7	5333	/**
<>	144:ef7eb2e8f9f7	5334	* @brief Clear PLLSAI1 ready interrupt flag
<>	144:ef7eb2e8f9f7	5335	* @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
<>	144:ef7eb2e8f9f7	5336	* @retval None
<>	144:ef7eb2e8f9f7	5337	*/
<>	144:ef7eb2e8f9f7	5338	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
<>	144:ef7eb2e8f9f7	5339	{
<>	144:ef7eb2e8f9f7	5340	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
<>	144:ef7eb2e8f9f7	5341	}
<>	144:ef7eb2e8f9f7	5342
<>	144:ef7eb2e8f9f7	5343	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	5344	/**
<>	144:ef7eb2e8f9f7	5345	* @brief Clear PLLSAI1 ready interrupt flag
<>	144:ef7eb2e8f9f7	5346	* @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
<>	144:ef7eb2e8f9f7	5347	* @retval None
<>	144:ef7eb2e8f9f7	5348	*/
<>	144:ef7eb2e8f9f7	5349	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
<>	144:ef7eb2e8f9f7	5350	{
<>	144:ef7eb2e8f9f7	5351	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
<>	144:ef7eb2e8f9f7	5352	}
<>	144:ef7eb2e8f9f7	5353	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	5354
<>	144:ef7eb2e8f9f7	5355	/**
<>	144:ef7eb2e8f9f7	5356	* @brief Clear Clock security system interrupt flag
<>	144:ef7eb2e8f9f7	5357	* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
<>	144:ef7eb2e8f9f7	5358	* @retval None
<>	144:ef7eb2e8f9f7	5359	*/
<>	144:ef7eb2e8f9f7	5360	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
<>	144:ef7eb2e8f9f7	5361	{
<>	144:ef7eb2e8f9f7	5362	SET_BIT(RCC->CICR, RCC_CICR_CSSC);
<>	144:ef7eb2e8f9f7	5363	}
<>	144:ef7eb2e8f9f7	5364
<>	144:ef7eb2e8f9f7	5365	/**
<>	144:ef7eb2e8f9f7	5366	* @brief Clear LSE Clock security system interrupt flag
<>	144:ef7eb2e8f9f7	5367	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
<>	144:ef7eb2e8f9f7	5368	* @retval None
<>	144:ef7eb2e8f9f7	5369	*/
<>	144:ef7eb2e8f9f7	5370	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
<>	144:ef7eb2e8f9f7	5371	{
<>	144:ef7eb2e8f9f7	5372	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
<>	144:ef7eb2e8f9f7	5373	}
<>	144:ef7eb2e8f9f7	5374
<>	144:ef7eb2e8f9f7	5375	/**
<>	144:ef7eb2e8f9f7	5376	* @brief Check if LSI ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5377	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
<>	144:ef7eb2e8f9f7	5378	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5379	*/
<>	144:ef7eb2e8f9f7	5380	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
<>	144:ef7eb2e8f9f7	5381	{
<>	144:ef7eb2e8f9f7	5382	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
<>	144:ef7eb2e8f9f7	5383	}
<>	144:ef7eb2e8f9f7	5384
<>	144:ef7eb2e8f9f7	5385	/**
<>	144:ef7eb2e8f9f7	5386	* @brief Check if LSE ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5387	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
<>	144:ef7eb2e8f9f7	5388	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5389	*/
<>	144:ef7eb2e8f9f7	5390	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
<>	144:ef7eb2e8f9f7	5391	{
<>	144:ef7eb2e8f9f7	5392	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
<>	144:ef7eb2e8f9f7	5393	}
<>	144:ef7eb2e8f9f7	5394
<>	144:ef7eb2e8f9f7	5395	/**
<>	144:ef7eb2e8f9f7	5396	* @brief Check if MSI ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5397	* @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
<>	144:ef7eb2e8f9f7	5398	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5399	*/
<>	144:ef7eb2e8f9f7	5400	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
<>	144:ef7eb2e8f9f7	5401	{
<>	144:ef7eb2e8f9f7	5402	return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
<>	144:ef7eb2e8f9f7	5403	}
<>	144:ef7eb2e8f9f7	5404
<>	144:ef7eb2e8f9f7	5405	/**
<>	144:ef7eb2e8f9f7	5406	* @brief Check if HSI ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5407	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
<>	144:ef7eb2e8f9f7	5408	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5409	*/
<>	144:ef7eb2e8f9f7	5410	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
<>	144:ef7eb2e8f9f7	5411	{
<>	144:ef7eb2e8f9f7	5412	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
<>	144:ef7eb2e8f9f7	5413	}
<>	144:ef7eb2e8f9f7	5414
<>	144:ef7eb2e8f9f7	5415	/**
<>	144:ef7eb2e8f9f7	5416	* @brief Check if HSE ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5417	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
<>	144:ef7eb2e8f9f7	5418	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5419	*/
<>	144:ef7eb2e8f9f7	5420	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
<>	144:ef7eb2e8f9f7	5421	{
<>	144:ef7eb2e8f9f7	5422	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
<>	144:ef7eb2e8f9f7	5423	}
<>	144:ef7eb2e8f9f7	5424
<>	144:ef7eb2e8f9f7	5425	/**
<>	144:ef7eb2e8f9f7	5426	* @brief Check if PLL ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5427	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
<>	144:ef7eb2e8f9f7	5428	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5429	*/
<>	144:ef7eb2e8f9f7	5430	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
<>	144:ef7eb2e8f9f7	5431	{
<>	144:ef7eb2e8f9f7	5432	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
<>	144:ef7eb2e8f9f7	5433	}
<>	144:ef7eb2e8f9f7	5434
<>	144:ef7eb2e8f9f7	5435	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	5436	/**
<>	144:ef7eb2e8f9f7	5437	* @brief Check if HSI48 ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5438	* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
<>	144:ef7eb2e8f9f7	5439	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5440	*/
<>	144:ef7eb2e8f9f7	5441	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
<>	144:ef7eb2e8f9f7	5442	{
<>	144:ef7eb2e8f9f7	5443	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
<>	144:ef7eb2e8f9f7	5444	}
<>	144:ef7eb2e8f9f7	5445	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	5446
<>	144:ef7eb2e8f9f7	5447	/**
<>	144:ef7eb2e8f9f7	5448	* @brief Check if PLLSAI1 ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5449	* @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
<>	144:ef7eb2e8f9f7	5450	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5451	*/
<>	144:ef7eb2e8f9f7	5452	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
<>	144:ef7eb2e8f9f7	5453	{
<>	144:ef7eb2e8f9f7	5454	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
<>	144:ef7eb2e8f9f7	5455	}
<>	144:ef7eb2e8f9f7	5456
<>	144:ef7eb2e8f9f7	5457	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	5458	/**
<>	144:ef7eb2e8f9f7	5459	* @brief Check if PLLSAI1 ready interrupt occurred or not
<>	144:ef7eb2e8f9f7	5460	* @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
<>	144:ef7eb2e8f9f7	5461	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5462	*/
<>	144:ef7eb2e8f9f7	5463	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
<>	144:ef7eb2e8f9f7	5464	{
<>	144:ef7eb2e8f9f7	5465	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
<>	144:ef7eb2e8f9f7	5466	}
<>	144:ef7eb2e8f9f7	5467	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	5468
<>	144:ef7eb2e8f9f7	5469	/**
<>	144:ef7eb2e8f9f7	5470	* @brief Check if Clock security system interrupt occurred or not
<>	144:ef7eb2e8f9f7	5471	* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
<>	144:ef7eb2e8f9f7	5472	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5473	*/
<>	144:ef7eb2e8f9f7	5474	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
<>	144:ef7eb2e8f9f7	5475	{
<>	144:ef7eb2e8f9f7	5476	return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
<>	144:ef7eb2e8f9f7	5477	}
<>	144:ef7eb2e8f9f7	5478
<>	144:ef7eb2e8f9f7	5479	/**
<>	144:ef7eb2e8f9f7	5480	* @brief Check if LSE Clock security system interrupt occurred or not
<>	144:ef7eb2e8f9f7	5481	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
<>	144:ef7eb2e8f9f7	5482	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5483	*/
<>	144:ef7eb2e8f9f7	5484	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
<>	144:ef7eb2e8f9f7	5485	{
<>	144:ef7eb2e8f9f7	5486	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
<>	144:ef7eb2e8f9f7	5487	}
<>	144:ef7eb2e8f9f7	5488
<>	144:ef7eb2e8f9f7	5489	/**
<>	144:ef7eb2e8f9f7	5490	* @brief Check if RCC flag FW reset is set or not.
<>	144:ef7eb2e8f9f7	5491	* @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
<>	144:ef7eb2e8f9f7	5492	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5493	*/
<>	144:ef7eb2e8f9f7	5494	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
<>	144:ef7eb2e8f9f7	5495	{
<>	144:ef7eb2e8f9f7	5496	return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
<>	144:ef7eb2e8f9f7	5497	}
<>	144:ef7eb2e8f9f7	5498
<>	144:ef7eb2e8f9f7	5499	/**
<>	144:ef7eb2e8f9f7	5500	* @brief Check if RCC flag Independent Watchdog reset is set or not.
<>	144:ef7eb2e8f9f7	5501	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
<>	144:ef7eb2e8f9f7	5502	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5503	*/
<>	144:ef7eb2e8f9f7	5504	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
<>	144:ef7eb2e8f9f7	5505	{
<>	144:ef7eb2e8f9f7	5506	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
<>	144:ef7eb2e8f9f7	5507	}
<>	144:ef7eb2e8f9f7	5508
<>	144:ef7eb2e8f9f7	5509	/**
<>	144:ef7eb2e8f9f7	5510	* @brief Check if RCC flag Low Power reset is set or not.
<>	144:ef7eb2e8f9f7	5511	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
<>	144:ef7eb2e8f9f7	5512	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5513	*/
<>	144:ef7eb2e8f9f7	5514	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
<>	144:ef7eb2e8f9f7	5515	{
<>	144:ef7eb2e8f9f7	5516	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
<>	144:ef7eb2e8f9f7	5517	}
<>	144:ef7eb2e8f9f7	5518
<>	144:ef7eb2e8f9f7	5519	/**
<>	144:ef7eb2e8f9f7	5520	* @brief Check if RCC flag is set or not.
<>	144:ef7eb2e8f9f7	5521	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
<>	144:ef7eb2e8f9f7	5522	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5523	*/
<>	144:ef7eb2e8f9f7	5524	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
<>	144:ef7eb2e8f9f7	5525	{
<>	144:ef7eb2e8f9f7	5526	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
<>	144:ef7eb2e8f9f7	5527	}
<>	144:ef7eb2e8f9f7	5528
<>	144:ef7eb2e8f9f7	5529	/**
<>	144:ef7eb2e8f9f7	5530	* @brief Check if RCC flag Pin reset is set or not.
<>	144:ef7eb2e8f9f7	5531	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
<>	144:ef7eb2e8f9f7	5532	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5533	*/
<>	144:ef7eb2e8f9f7	5534	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
<>	144:ef7eb2e8f9f7	5535	{
<>	144:ef7eb2e8f9f7	5536	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
<>	144:ef7eb2e8f9f7	5537	}
<>	144:ef7eb2e8f9f7	5538
<>	144:ef7eb2e8f9f7	5539	/**
<>	144:ef7eb2e8f9f7	5540	* @brief Check if RCC flag Software reset is set or not.
<>	144:ef7eb2e8f9f7	5541	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
<>	144:ef7eb2e8f9f7	5542	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5543	*/
<>	144:ef7eb2e8f9f7	5544	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
<>	144:ef7eb2e8f9f7	5545	{
<>	144:ef7eb2e8f9f7	5546	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
<>	144:ef7eb2e8f9f7	5547	}
<>	144:ef7eb2e8f9f7	5548
<>	144:ef7eb2e8f9f7	5549	/**
<>	144:ef7eb2e8f9f7	5550	* @brief Check if RCC flag Window Watchdog reset is set or not.
<>	144:ef7eb2e8f9f7	5551	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
<>	144:ef7eb2e8f9f7	5552	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5553	*/
<>	144:ef7eb2e8f9f7	5554	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
<>	144:ef7eb2e8f9f7	5555	{
<>	144:ef7eb2e8f9f7	5556	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
<>	144:ef7eb2e8f9f7	5557	}
<>	144:ef7eb2e8f9f7	5558
<>	144:ef7eb2e8f9f7	5559	/**
<>	144:ef7eb2e8f9f7	5560	* @brief Check if RCC flag BOR reset is set or not.
<>	144:ef7eb2e8f9f7	5561	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
<>	144:ef7eb2e8f9f7	5562	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5563	*/
<>	144:ef7eb2e8f9f7	5564	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
<>	144:ef7eb2e8f9f7	5565	{
<>	144:ef7eb2e8f9f7	5566	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
<>	144:ef7eb2e8f9f7	5567	}
<>	144:ef7eb2e8f9f7	5568
<>	144:ef7eb2e8f9f7	5569	/**
<>	144:ef7eb2e8f9f7	5570	* @brief Set RMVF bit to clear the reset flags.
<>	144:ef7eb2e8f9f7	5571	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
<>	144:ef7eb2e8f9f7	5572	* @retval None
<>	144:ef7eb2e8f9f7	5573	*/
<>	144:ef7eb2e8f9f7	5574	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
<>	144:ef7eb2e8f9f7	5575	{
<>	144:ef7eb2e8f9f7	5576	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<>	144:ef7eb2e8f9f7	5577	}
<>	144:ef7eb2e8f9f7	5578
<>	144:ef7eb2e8f9f7	5579	/**
<>	144:ef7eb2e8f9f7	5580	* @}
<>	144:ef7eb2e8f9f7	5581	*/
<>	144:ef7eb2e8f9f7	5582
<>	144:ef7eb2e8f9f7	5583	/** @defgroup RCC_LL_EF_IT_Management IT Management
<>	144:ef7eb2e8f9f7	5584	* @{
<>	144:ef7eb2e8f9f7	5585	*/
<>	144:ef7eb2e8f9f7	5586
<>	144:ef7eb2e8f9f7	5587	/**
<>	144:ef7eb2e8f9f7	5588	* @brief Enable LSI ready interrupt
<>	144:ef7eb2e8f9f7	5589	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
<>	144:ef7eb2e8f9f7	5590	* @retval None
<>	144:ef7eb2e8f9f7	5591	*/
<>	144:ef7eb2e8f9f7	5592	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
<>	144:ef7eb2e8f9f7	5593	{
<>	144:ef7eb2e8f9f7	5594	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
<>	144:ef7eb2e8f9f7	5595	}
<>	144:ef7eb2e8f9f7	5596
<>	144:ef7eb2e8f9f7	5597	/**
<>	144:ef7eb2e8f9f7	5598	* @brief Enable LSE ready interrupt
<>	144:ef7eb2e8f9f7	5599	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
<>	144:ef7eb2e8f9f7	5600	* @retval None
<>	144:ef7eb2e8f9f7	5601	*/
<>	144:ef7eb2e8f9f7	5602	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
<>	144:ef7eb2e8f9f7	5603	{
<>	144:ef7eb2e8f9f7	5604	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
<>	144:ef7eb2e8f9f7	5605	}
<>	144:ef7eb2e8f9f7	5606
<>	144:ef7eb2e8f9f7	5607	/**
<>	144:ef7eb2e8f9f7	5608	* @brief Enable MSI ready interrupt
<>	144:ef7eb2e8f9f7	5609	* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
<>	144:ef7eb2e8f9f7	5610	* @retval None
<>	144:ef7eb2e8f9f7	5611	*/
<>	144:ef7eb2e8f9f7	5612	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
<>	144:ef7eb2e8f9f7	5613	{
<>	144:ef7eb2e8f9f7	5614	SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
<>	144:ef7eb2e8f9f7	5615	}
<>	144:ef7eb2e8f9f7	5616
<>	144:ef7eb2e8f9f7	5617	/**
<>	144:ef7eb2e8f9f7	5618	* @brief Enable HSI ready interrupt
<>	144:ef7eb2e8f9f7	5619	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
<>	144:ef7eb2e8f9f7	5620	* @retval None
<>	144:ef7eb2e8f9f7	5621	*/
<>	144:ef7eb2e8f9f7	5622	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
<>	144:ef7eb2e8f9f7	5623	{
<>	144:ef7eb2e8f9f7	5624	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
<>	144:ef7eb2e8f9f7	5625	}
<>	144:ef7eb2e8f9f7	5626
<>	144:ef7eb2e8f9f7	5627	/**
<>	144:ef7eb2e8f9f7	5628	* @brief Enable HSE ready interrupt
<>	144:ef7eb2e8f9f7	5629	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
<>	144:ef7eb2e8f9f7	5630	* @retval None
<>	144:ef7eb2e8f9f7	5631	*/
<>	144:ef7eb2e8f9f7	5632	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
<>	144:ef7eb2e8f9f7	5633	{
<>	144:ef7eb2e8f9f7	5634	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
<>	144:ef7eb2e8f9f7	5635	}
<>	144:ef7eb2e8f9f7	5636
<>	144:ef7eb2e8f9f7	5637	/**
<>	144:ef7eb2e8f9f7	5638	* @brief Enable PLL ready interrupt
<>	144:ef7eb2e8f9f7	5639	* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
<>	144:ef7eb2e8f9f7	5640	* @retval None
<>	144:ef7eb2e8f9f7	5641	*/
<>	144:ef7eb2e8f9f7	5642	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
<>	144:ef7eb2e8f9f7	5643	{
<>	144:ef7eb2e8f9f7	5644	SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
<>	144:ef7eb2e8f9f7	5645	}
<>	144:ef7eb2e8f9f7	5646
<>	144:ef7eb2e8f9f7	5647	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	5648	/**
<>	144:ef7eb2e8f9f7	5649	* @brief Enable HSI48 ready interrupt
<>	144:ef7eb2e8f9f7	5650	* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
<>	144:ef7eb2e8f9f7	5651	* @retval None
<>	144:ef7eb2e8f9f7	5652	*/
<>	144:ef7eb2e8f9f7	5653	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
<>	144:ef7eb2e8f9f7	5654	{
<>	144:ef7eb2e8f9f7	5655	SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
<>	144:ef7eb2e8f9f7	5656	}
<>	144:ef7eb2e8f9f7	5657	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	5658
<>	144:ef7eb2e8f9f7	5659	/**
<>	144:ef7eb2e8f9f7	5660	* @brief Enable PLLSAI1 ready interrupt
<>	144:ef7eb2e8f9f7	5661	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
<>	144:ef7eb2e8f9f7	5662	* @retval None
<>	144:ef7eb2e8f9f7	5663	*/
<>	144:ef7eb2e8f9f7	5664	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
<>	144:ef7eb2e8f9f7	5665	{
<>	144:ef7eb2e8f9f7	5666	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
<>	144:ef7eb2e8f9f7	5667	}
<>	144:ef7eb2e8f9f7	5668
<>	144:ef7eb2e8f9f7	5669	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	5670	/**
<>	144:ef7eb2e8f9f7	5671	* @brief Enable PLLSAI2 ready interrupt
<>	144:ef7eb2e8f9f7	5672	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
<>	144:ef7eb2e8f9f7	5673	* @retval None
<>	144:ef7eb2e8f9f7	5674	*/
<>	144:ef7eb2e8f9f7	5675	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
<>	144:ef7eb2e8f9f7	5676	{
<>	144:ef7eb2e8f9f7	5677	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
<>	144:ef7eb2e8f9f7	5678	}
<>	144:ef7eb2e8f9f7	5679	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	5680
<>	144:ef7eb2e8f9f7	5681	/**
<>	144:ef7eb2e8f9f7	5682	* @brief Enable LSE clock security system interrupt
<>	144:ef7eb2e8f9f7	5683	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
<>	144:ef7eb2e8f9f7	5684	* @retval None
<>	144:ef7eb2e8f9f7	5685	*/
<>	144:ef7eb2e8f9f7	5686	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
<>	144:ef7eb2e8f9f7	5687	{
<>	144:ef7eb2e8f9f7	5688	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
<>	144:ef7eb2e8f9f7	5689	}
<>	144:ef7eb2e8f9f7	5690
<>	144:ef7eb2e8f9f7	5691	/**
<>	144:ef7eb2e8f9f7	5692	* @brief Disable LSI ready interrupt
<>	144:ef7eb2e8f9f7	5693	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
<>	144:ef7eb2e8f9f7	5694	* @retval None
<>	144:ef7eb2e8f9f7	5695	*/
<>	144:ef7eb2e8f9f7	5696	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
<>	144:ef7eb2e8f9f7	5697	{
<>	144:ef7eb2e8f9f7	5698	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
<>	144:ef7eb2e8f9f7	5699	}
<>	144:ef7eb2e8f9f7	5700
<>	144:ef7eb2e8f9f7	5701	/**
<>	144:ef7eb2e8f9f7	5702	* @brief Disable LSE ready interrupt
<>	144:ef7eb2e8f9f7	5703	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
<>	144:ef7eb2e8f9f7	5704	* @retval None
<>	144:ef7eb2e8f9f7	5705	*/
<>	144:ef7eb2e8f9f7	5706	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
<>	144:ef7eb2e8f9f7	5707	{
<>	144:ef7eb2e8f9f7	5708	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
<>	144:ef7eb2e8f9f7	5709	}
<>	144:ef7eb2e8f9f7	5710
<>	144:ef7eb2e8f9f7	5711	/**
<>	144:ef7eb2e8f9f7	5712	* @brief Disable MSI ready interrupt
<>	144:ef7eb2e8f9f7	5713	* @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
<>	144:ef7eb2e8f9f7	5714	* @retval None
<>	144:ef7eb2e8f9f7	5715	*/
<>	144:ef7eb2e8f9f7	5716	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
<>	144:ef7eb2e8f9f7	5717	{
<>	144:ef7eb2e8f9f7	5718	CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
<>	144:ef7eb2e8f9f7	5719	}
<>	144:ef7eb2e8f9f7	5720
<>	144:ef7eb2e8f9f7	5721	/**
<>	144:ef7eb2e8f9f7	5722	* @brief Disable HSI ready interrupt
<>	144:ef7eb2e8f9f7	5723	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
<>	144:ef7eb2e8f9f7	5724	* @retval None
<>	144:ef7eb2e8f9f7	5725	*/
<>	144:ef7eb2e8f9f7	5726	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
<>	144:ef7eb2e8f9f7	5727	{
<>	144:ef7eb2e8f9f7	5728	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
<>	144:ef7eb2e8f9f7	5729	}
<>	144:ef7eb2e8f9f7	5730
<>	144:ef7eb2e8f9f7	5731	/**
<>	144:ef7eb2e8f9f7	5732	* @brief Disable HSE ready interrupt
<>	144:ef7eb2e8f9f7	5733	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
<>	144:ef7eb2e8f9f7	5734	* @retval None
<>	144:ef7eb2e8f9f7	5735	*/
<>	144:ef7eb2e8f9f7	5736	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
<>	144:ef7eb2e8f9f7	5737	{
<>	144:ef7eb2e8f9f7	5738	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
<>	144:ef7eb2e8f9f7	5739	}
<>	144:ef7eb2e8f9f7	5740
<>	144:ef7eb2e8f9f7	5741	/**
<>	144:ef7eb2e8f9f7	5742	* @brief Disable PLL ready interrupt
<>	144:ef7eb2e8f9f7	5743	* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
<>	144:ef7eb2e8f9f7	5744	* @retval None
<>	144:ef7eb2e8f9f7	5745	*/
<>	144:ef7eb2e8f9f7	5746	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
<>	144:ef7eb2e8f9f7	5747	{
<>	144:ef7eb2e8f9f7	5748	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
<>	144:ef7eb2e8f9f7	5749	}
<>	144:ef7eb2e8f9f7	5750
<>	144:ef7eb2e8f9f7	5751	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	5752	/**
<>	144:ef7eb2e8f9f7	5753	* @brief Disable HSI48 ready interrupt
<>	144:ef7eb2e8f9f7	5754	* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
<>	144:ef7eb2e8f9f7	5755	* @retval None
<>	144:ef7eb2e8f9f7	5756	*/
<>	144:ef7eb2e8f9f7	5757	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
<>	144:ef7eb2e8f9f7	5758	{
<>	144:ef7eb2e8f9f7	5759	CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
<>	144:ef7eb2e8f9f7	5760	}
<>	144:ef7eb2e8f9f7	5761	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	5762
<>	144:ef7eb2e8f9f7	5763	/**
<>	144:ef7eb2e8f9f7	5764	* @brief Disable PLLSAI1 ready interrupt
<>	144:ef7eb2e8f9f7	5765	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
<>	144:ef7eb2e8f9f7	5766	* @retval None
<>	144:ef7eb2e8f9f7	5767	*/
<>	144:ef7eb2e8f9f7	5768	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
<>	144:ef7eb2e8f9f7	5769	{
<>	144:ef7eb2e8f9f7	5770	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
<>	144:ef7eb2e8f9f7	5771	}
<>	144:ef7eb2e8f9f7	5772
<>	144:ef7eb2e8f9f7	5773	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	5774	/**
<>	144:ef7eb2e8f9f7	5775	* @brief Disable PLLSAI2 ready interrupt
<>	144:ef7eb2e8f9f7	5776	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
<>	144:ef7eb2e8f9f7	5777	* @retval None
<>	144:ef7eb2e8f9f7	5778	*/
<>	144:ef7eb2e8f9f7	5779	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
<>	144:ef7eb2e8f9f7	5780	{
<>	144:ef7eb2e8f9f7	5781	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
<>	144:ef7eb2e8f9f7	5782	}
<>	144:ef7eb2e8f9f7	5783	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	5784
<>	144:ef7eb2e8f9f7	5785	/**
<>	144:ef7eb2e8f9f7	5786	* @brief Disable LSE clock security system interrupt
<>	144:ef7eb2e8f9f7	5787	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
<>	144:ef7eb2e8f9f7	5788	* @retval None
<>	144:ef7eb2e8f9f7	5789	*/
<>	144:ef7eb2e8f9f7	5790	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
<>	144:ef7eb2e8f9f7	5791	{
<>	144:ef7eb2e8f9f7	5792	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
<>	144:ef7eb2e8f9f7	5793	}
<>	144:ef7eb2e8f9f7	5794
<>	144:ef7eb2e8f9f7	5795	/**
<>	144:ef7eb2e8f9f7	5796	* @brief Checks if LSI ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5797	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
<>	144:ef7eb2e8f9f7	5798	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5799	*/
<>	144:ef7eb2e8f9f7	5800	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
<>	144:ef7eb2e8f9f7	5801	{
<>	144:ef7eb2e8f9f7	5802	return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
<>	144:ef7eb2e8f9f7	5803	}
<>	144:ef7eb2e8f9f7	5804
<>	144:ef7eb2e8f9f7	5805	/**
<>	144:ef7eb2e8f9f7	5806	* @brief Checks if LSE ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5807	* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
<>	144:ef7eb2e8f9f7	5808	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5809	*/
<>	144:ef7eb2e8f9f7	5810	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
<>	144:ef7eb2e8f9f7	5811	{
<>	144:ef7eb2e8f9f7	5812	return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
<>	144:ef7eb2e8f9f7	5813	}
<>	144:ef7eb2e8f9f7	5814
<>	144:ef7eb2e8f9f7	5815	/**
<>	144:ef7eb2e8f9f7	5816	* @brief Checks if MSI ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5817	* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
<>	144:ef7eb2e8f9f7	5818	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5819	*/
<>	144:ef7eb2e8f9f7	5820	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
<>	144:ef7eb2e8f9f7	5821	{
<>	144:ef7eb2e8f9f7	5822	return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
<>	144:ef7eb2e8f9f7	5823	}
<>	144:ef7eb2e8f9f7	5824
<>	144:ef7eb2e8f9f7	5825	/**
<>	144:ef7eb2e8f9f7	5826	* @brief Checks if HSI ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5827	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
<>	144:ef7eb2e8f9f7	5828	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5829	*/
<>	144:ef7eb2e8f9f7	5830	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
<>	144:ef7eb2e8f9f7	5831	{
<>	144:ef7eb2e8f9f7	5832	return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
<>	144:ef7eb2e8f9f7	5833	}
<>	144:ef7eb2e8f9f7	5834
<>	144:ef7eb2e8f9f7	5835	/**
<>	144:ef7eb2e8f9f7	5836	* @brief Checks if HSE ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5837	* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
<>	144:ef7eb2e8f9f7	5838	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5839	*/
<>	144:ef7eb2e8f9f7	5840	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
<>	144:ef7eb2e8f9f7	5841	{
<>	144:ef7eb2e8f9f7	5842	return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
<>	144:ef7eb2e8f9f7	5843	}
<>	144:ef7eb2e8f9f7	5844
<>	144:ef7eb2e8f9f7	5845	/**
<>	144:ef7eb2e8f9f7	5846	* @brief Checks if PLL ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5847	* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
<>	144:ef7eb2e8f9f7	5848	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5849	*/
<>	144:ef7eb2e8f9f7	5850	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
<>	144:ef7eb2e8f9f7	5851	{
<>	144:ef7eb2e8f9f7	5852	return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
<>	144:ef7eb2e8f9f7	5853	}
<>	144:ef7eb2e8f9f7	5854
<>	144:ef7eb2e8f9f7	5855	#if defined(RCC_HSI48_SUPPORT)
<>	144:ef7eb2e8f9f7	5856	/**
<>	144:ef7eb2e8f9f7	5857	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5858	* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
<>	144:ef7eb2e8f9f7	5859	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5860	*/
<>	144:ef7eb2e8f9f7	5861	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
<>	144:ef7eb2e8f9f7	5862	{
<>	144:ef7eb2e8f9f7	5863	return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
<>	144:ef7eb2e8f9f7	5864	}
<>	144:ef7eb2e8f9f7	5865	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	5866
<>	144:ef7eb2e8f9f7	5867	/**
<>	144:ef7eb2e8f9f7	5868	* @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5869	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
<>	144:ef7eb2e8f9f7	5870	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5871	*/
<>	144:ef7eb2e8f9f7	5872	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
<>	144:ef7eb2e8f9f7	5873	{
<>	144:ef7eb2e8f9f7	5874	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
<>	144:ef7eb2e8f9f7	5875	}
<>	144:ef7eb2e8f9f7	5876
<>	144:ef7eb2e8f9f7	5877	#if defined(RCC_PLLSAI2_SUPPORT)
<>	144:ef7eb2e8f9f7	5878	/**
<>	144:ef7eb2e8f9f7	5879	* @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5880	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
<>	144:ef7eb2e8f9f7	5881	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5882	*/
<>	144:ef7eb2e8f9f7	5883	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
<>	144:ef7eb2e8f9f7	5884	{
<>	144:ef7eb2e8f9f7	5885	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
<>	144:ef7eb2e8f9f7	5886	}
<>	144:ef7eb2e8f9f7	5887	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	167:e84263d55307	5888
<>	144:ef7eb2e8f9f7	5889	/**
<>	144:ef7eb2e8f9f7	5890	* @brief Checks if LSECSS interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	5891	* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
<>	144:ef7eb2e8f9f7	5892	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	5893	*/
<>	144:ef7eb2e8f9f7	5894	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
<>	144:ef7eb2e8f9f7	5895	{
<>	144:ef7eb2e8f9f7	5896	return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
<>	144:ef7eb2e8f9f7	5897	}
<>	144:ef7eb2e8f9f7	5898
<>	144:ef7eb2e8f9f7	5899	/**
<>	144:ef7eb2e8f9f7	5900	* @}
<>	144:ef7eb2e8f9f7	5901	*/
<>	144:ef7eb2e8f9f7	5902
<>	144:ef7eb2e8f9f7	5903	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	5904	/** @defgroup RCC_LL_EF_Init De-initialization function
<>	144:ef7eb2e8f9f7	5905	* @{
<>	144:ef7eb2e8f9f7	5906	*/
<>	144:ef7eb2e8f9f7	5907	ErrorStatus LL_RCC_DeInit(void);
<>	144:ef7eb2e8f9f7	5908	/**
<>	144:ef7eb2e8f9f7	5909	* @}
<>	144:ef7eb2e8f9f7	5910	*/
<>	144:ef7eb2e8f9f7	5911
<>	144:ef7eb2e8f9f7	5912	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
<>	144:ef7eb2e8f9f7	5913	* @{
<>	144:ef7eb2e8f9f7	5914	*/
<>	144:ef7eb2e8f9f7	5915	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
<>	144:ef7eb2e8f9f7	5916	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
<>	144:ef7eb2e8f9f7	5917	#if defined(UART4) \|\| defined(UART5)
<>	144:ef7eb2e8f9f7	5918	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
<>	144:ef7eb2e8f9f7	5919	#endif /* UART4 \|\| UART5 */
<>	144:ef7eb2e8f9f7	5920	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
<>	144:ef7eb2e8f9f7	5921	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
<>	144:ef7eb2e8f9f7	5922	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
<>	144:ef7eb2e8f9f7	5923	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
AnnaBridge	181:57724642e740	5924	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	181:57724642e740	5925	uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
AnnaBridge	181:57724642e740	5926	#endif
<>	144:ef7eb2e8f9f7	5927	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
<>	144:ef7eb2e8f9f7	5928	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
<>	144:ef7eb2e8f9f7	5929	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	144:ef7eb2e8f9f7	5930	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
<>	144:ef7eb2e8f9f7	5931	#endif /* USB_OTG_FS \|\| USB */
<>	144:ef7eb2e8f9f7	5932	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
AnnaBridge	167:e84263d55307	5933	#if defined(SWPMI1)
<>	144:ef7eb2e8f9f7	5934	uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
AnnaBridge	167:e84263d55307	5935	#endif /* SWPMI1 */
<>	144:ef7eb2e8f9f7	5936	#if defined(DFSDM1_Channel0)
<>	144:ef7eb2e8f9f7	5937	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
AnnaBridge	181:57724642e740	5938	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	181:57724642e740	5939	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
AnnaBridge	181:57724642e740	5940	#endif /* RCC_CCIPR2_DFSDM1SEL */
<>	144:ef7eb2e8f9f7	5941	#endif /* DFSDM1_Channel0 */
AnnaBridge	181:57724642e740	5942	#if defined(LTDC)
AnnaBridge	181:57724642e740	5943	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
AnnaBridge	181:57724642e740	5944	#endif /* LTDC */
AnnaBridge	181:57724642e740	5945	#if defined(DSI)
AnnaBridge	181:57724642e740	5946	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
AnnaBridge	181:57724642e740	5947	#endif /* DSI */
AnnaBridge	181:57724642e740	5948	#if defined(OCTOSPI1)
AnnaBridge	181:57724642e740	5949	uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
AnnaBridge	181:57724642e740	5950	#endif /* OCTOSPI1 */
<>	144:ef7eb2e8f9f7	5951	/**
<>	144:ef7eb2e8f9f7	5952	* @}
<>	144:ef7eb2e8f9f7	5953	*/
<>	144:ef7eb2e8f9f7	5954	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	5955
<>	144:ef7eb2e8f9f7	5956	/**
<>	144:ef7eb2e8f9f7	5957	* @}
<>	144:ef7eb2e8f9f7	5958	*/
<>	144:ef7eb2e8f9f7	5959
<>	144:ef7eb2e8f9f7	5960	/**
<>	144:ef7eb2e8f9f7	5961	* @}
<>	144:ef7eb2e8f9f7	5962	*/
<>	144:ef7eb2e8f9f7	5963
<>	144:ef7eb2e8f9f7	5964	#endif /* defined(RCC) */
<>	144:ef7eb2e8f9f7	5965
<>	144:ef7eb2e8f9f7	5966	/**
<>	144:ef7eb2e8f9f7	5967	* @}
<>	144:ef7eb2e8f9f7	5968	*/
<>	144:ef7eb2e8f9f7	5969
<>	144:ef7eb2e8f9f7	5970	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	5971	}
<>	144:ef7eb2e8f9f7	5972	#endif
<>	144:ef7eb2e8f9f7	5973
<>	144:ef7eb2e8f9f7	5974	#endif /* __STM32L4xx_LL_RCC_H */
<>	144:ef7eb2e8f9f7	5975
<>	144:ef7eb2e8f9f7	5976	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/