mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.h
- Revision:
- 184:08ed48f1de7f
- Parent:
- 149:156823d33999
--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.h Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.h Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
******************************************************************************
* @file stm32l1xx_ll_spi.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 01-July-2016
* @brief Header file of SPI LL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -141,7 +139,6 @@
#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
-#define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */
#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
@@ -165,7 +162,7 @@
* @{
*/
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
-#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
/**
* @}
*/
@@ -174,7 +171,7 @@
/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
* @{
*/
-#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
/**
* @}
@@ -184,7 +181,7 @@
/** @defgroup SPI_LL_EC_PHASE Clock Phase
* @{
*/
-#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
/**
* @}
@@ -193,7 +190,7 @@
/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
* @{
*/
-#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
/**
* @}
@@ -202,7 +199,7 @@
/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
* @{
*/
-#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
@@ -218,7 +215,7 @@
* @{
*/
#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/received with the MSB first */
+#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
/**
* @}
*/
@@ -226,7 +223,7 @@
/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
* @{
*/
-#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
@@ -238,7 +235,7 @@
* @{
*/
#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
-#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
/**
* @}
@@ -247,7 +244,7 @@
/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
* @{
*/
-#define LL_SPI_DATAWIDTH_8BIT ((uint32_t)0x00000000U) /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
/**
* @}
@@ -257,7 +254,7 @@
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
* @{
*/
-#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
/**
* @}
@@ -1122,7 +1119,8 @@
*/
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
- *((__IO uint8_t *)&SPIx->DR) = TxData;
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
}
/**
@@ -1134,7 +1132,8 @@
*/
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
- *((__IO uint16_t *)&SPIx->DR) = TxData;
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
}
/**
@@ -1236,7 +1235,7 @@
#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
-#define LL_I2S_SR_UDR LL_SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
/**
@@ -1257,7 +1256,7 @@
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
* @{
*/
-#define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
@@ -1268,7 +1267,7 @@
/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
* @{
*/
-#define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock steady state is low level */
+#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
/**
* @}
@@ -1277,7 +1276,7 @@
/** @defgroup I2S_LL_EC_STANDARD I2s Standard
* @{
*/
-#define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /*!< I2S standard philips */
+#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
@@ -1289,7 +1288,7 @@
/** @defgroup I2S_LL_EC_MODE Operation Mode
* @{
*/
-#define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
@@ -1300,7 +1299,7 @@
/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
* @{
*/
-#define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
/**
* @}
@@ -1311,7 +1310,7 @@
/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
* @{
*/
-#define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
/**
* @}
@@ -1321,16 +1320,16 @@
* @{
*/
-#define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /*!< Audio Frequency configuration 192000 Hz */
-#define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /*!< Audio Frequency configuration 96000 Hz */
-#define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /*!< Audio Frequency configuration 48000 Hz */
-#define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /*!< Audio Frequency configuration 44100 Hz */
-#define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /*!< Audio Frequency configuration 32000 Hz */
-#define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /*!< Audio Frequency configuration 22050 Hz */
-#define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /*!< Audio Frequency configuration 16000 Hz */
-#define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /*!< Audio Frequency configuration 11025 Hz */
-#define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /*!< Audio Frequency configuration 8000 Hz */
-#define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /*!< Audio Freq not specified. Register I2SDIV = 2 */
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
/**
* @}
*/
@@ -1419,7 +1418,7 @@
}
/**
- * @brief Set I2S Data frame length
+ * @brief Set I2S data frame length
* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
* I2SCFGR CHLEN LL_I2S_SetDataFormat
* @param SPIx SPI Instance
@@ -1436,7 +1435,7 @@
}
/**
- * @brief Get I2S Data frame length
+ * @brief Get I2S data frame length
* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
* I2SCFGR CHLEN LL_I2S_GetDataFormat
* @param SPIx SPI Instance
@@ -1479,7 +1478,7 @@
}
/**
- * @brief Set I2S Standard Protocol
+ * @brief Set I2S standard protocol
* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
* I2SCFGR PCMSYNC LL_I2S_SetStandard
* @param SPIx SPI Instance
@@ -1497,7 +1496,7 @@
}
/**
- * @brief Get I2S Standard Protocol
+ * @brief Get I2S standard protocol
* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
* I2SCFGR PCMSYNC LL_I2S_GetStandard
* @param SPIx SPI Instance
@@ -1514,7 +1513,7 @@
}
/**
- * @brief Set I2S Transfer Mode
+ * @brief Set I2S transfer mode
* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
* @param SPIx SPI Instance
* @param Mode This parameter can be one of the following values:
@@ -1530,7 +1529,7 @@
}
/**
- * @brief Get I2S Transfer Mode
+ * @brief Get I2S transfer mode
* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
@@ -1595,7 +1594,7 @@
}
/**
- * @brief Enable the Master Clock Ouput (Pin MCK)
+ * @brief Enable the master clock ouput (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
* @param SPIx SPI Instance
* @retval None
@@ -1606,7 +1605,7 @@
}
/**
- * @brief Disable the Master Clock Ouput (Pin MCK)
+ * @brief Disable the master clock ouput (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
* @param SPIx SPI Instance
* @retval None
@@ -1617,7 +1616,7 @@
}
/**
- * @brief Check if the Master Clock Ouput (Pin MCK) is enabled
+ * @brief Check if the master clock ouput (Pin MCK) is enabled
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
@@ -1658,7 +1657,7 @@
}
/**
- * @brief Get Busy flag
+ * @brief Get busy flag
* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
@@ -1669,7 +1668,7 @@
}
/**
- * @brief Get Overrun error flag
+ * @brief Get overrun error flag
* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
@@ -1680,7 +1679,7 @@
}
/**
- * @brief Get Underrun error flag
+ * @brief Get underrun error flag
* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
@@ -1691,7 +1690,7 @@
}
/**
- * @brief Get Frame format error flag
+ * @brief Get frame format error flag
* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
@@ -1702,7 +1701,7 @@
}
/**
- * @brief Get Channel side flag.
+ * @brief Get channel side flag.
* @note 0: Channel Left has to be transmitted or has been received\n
* 1: Channel Right has to be transmitted or has been received\n
* It has no significance in PCM mode.
@@ -1716,7 +1715,7 @@
}
/**
- * @brief Clear Overrun error flag
+ * @brief Clear overrun error flag
* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
* @param SPIx SPI Instance
* @retval None
@@ -1727,7 +1726,7 @@
}
/**
- * @brief Clear Underrun error flag
+ * @brief Clear underrun error flag
* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
* @param SPIx SPI Instance
* @retval None
@@ -1740,7 +1739,7 @@
}
/**
- * @brief Clear Frame format error flag
+ * @brief Clear frame format error flag
* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
* @param SPIx SPI Instance
* @retval None
@@ -1793,7 +1792,7 @@
}
/**
- * @brief Disable Error IT
+ * @brief Disable error IT
* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
* @param SPIx SPI Instance
