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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:: <>
Date:: Thu Feb 02 17:01:33 2017 +0000
Revision:: 157:ff67d9f36b67
Child:: 186:707f6e361f3e

This updates the lib to the mbed lib v135

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	157:ff67d9f36b67	1	/**
<>	157:ff67d9f36b67	2	******************************************************************************
<>	157:ff67d9f36b67	3	* @file stm32f3xx_ll_dma.h
<>	157:ff67d9f36b67	4	* @author MCD Application Team
<>	157:ff67d9f36b67	5	* @version V1.4.0
<>	157:ff67d9f36b67	6	* @date 16-December-2016
<>	157:ff67d9f36b67	7	* @brief Header file of DMA LL module.
<>	157:ff67d9f36b67	8	******************************************************************************
<>	157:ff67d9f36b67	9	* @attention
<>	157:ff67d9f36b67	10	*
<>	157:ff67d9f36b67	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	157:ff67d9f36b67	12	*
<>	157:ff67d9f36b67	13	* Redistribution and use in source and binary forms, with or without modification,
<>	157:ff67d9f36b67	14	* are permitted provided that the following conditions are met:
<>	157:ff67d9f36b67	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	157:ff67d9f36b67	16	* this list of conditions and the following disclaimer.
<>	157:ff67d9f36b67	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	157:ff67d9f36b67	18	* this list of conditions and the following disclaimer in the documentation
<>	157:ff67d9f36b67	19	* and/or other materials provided with the distribution.
<>	157:ff67d9f36b67	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	157:ff67d9f36b67	21	* may be used to endorse or promote products derived from this software
<>	157:ff67d9f36b67	22	* without specific prior written permission.
<>	157:ff67d9f36b67	23	*
<>	157:ff67d9f36b67	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	157:ff67d9f36b67	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	157:ff67d9f36b67	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	157:ff67d9f36b67	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	157:ff67d9f36b67	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	157:ff67d9f36b67	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	157:ff67d9f36b67	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	157:ff67d9f36b67	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	157:ff67d9f36b67	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	157:ff67d9f36b67	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	157:ff67d9f36b67	34	*
<>	157:ff67d9f36b67	35	******************************************************************************
<>	157:ff67d9f36b67	36	*/
<>	157:ff67d9f36b67	37
<>	157:ff67d9f36b67	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	157:ff67d9f36b67	39	#ifndef __STM32F3xx_LL_DMA_H
<>	157:ff67d9f36b67	40	#define __STM32F3xx_LL_DMA_H
<>	157:ff67d9f36b67	41
<>	157:ff67d9f36b67	42	#ifdef __cplusplus
<>	157:ff67d9f36b67	43	extern "C" {
<>	157:ff67d9f36b67	44	#endif
<>	157:ff67d9f36b67	45
<>	157:ff67d9f36b67	46	/* Includes ------------------------------------------------------------------*/
<>	157:ff67d9f36b67	47	#include "stm32f3xx.h"
<>	157:ff67d9f36b67	48
<>	157:ff67d9f36b67	49	/** @addtogroup STM32F3xx_LL_Driver
<>	157:ff67d9f36b67	50	* @{
<>	157:ff67d9f36b67	51	*/
<>	157:ff67d9f36b67	52
<>	157:ff67d9f36b67	53	#if defined (DMA1) \|\| defined (DMA2)
<>	157:ff67d9f36b67	54
<>	157:ff67d9f36b67	55	/** @defgroup DMA_LL DMA
<>	157:ff67d9f36b67	56	* @{
<>	157:ff67d9f36b67	57	*/
<>	157:ff67d9f36b67	58
<>	157:ff67d9f36b67	59	/* Private types -------------------------------------------------------------*/
<>	157:ff67d9f36b67	60	/* Private variables ---------------------------------------------------------*/
<>	157:ff67d9f36b67	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
<>	157:ff67d9f36b67	62	* @{
<>	157:ff67d9f36b67	63	*/
<>	157:ff67d9f36b67	64	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<>	157:ff67d9f36b67	65	static const uint8_t CHANNEL_OFFSET_TAB[] =
<>	157:ff67d9f36b67	66	{
<>	157:ff67d9f36b67	67	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<>	157:ff67d9f36b67	68	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<>	157:ff67d9f36b67	69	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<>	157:ff67d9f36b67	70	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<>	157:ff67d9f36b67	71	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<>	157:ff67d9f36b67	72	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<>	157:ff67d9f36b67	73	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<>	157:ff67d9f36b67	74	};
<>	157:ff67d9f36b67	75	/**
<>	157:ff67d9f36b67	76	* @}
<>	157:ff67d9f36b67	77	*/
<>	157:ff67d9f36b67	78
<>	157:ff67d9f36b67	79	/* Private constants ---------------------------------------------------------*/
<>	157:ff67d9f36b67	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
<>	157:ff67d9f36b67	81	* @{
<>	157:ff67d9f36b67	82	*/
<>	157:ff67d9f36b67	83	/* Define used to get CSELR register offset */
<>	157:ff67d9f36b67	84	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
<>	157:ff67d9f36b67	85
<>	157:ff67d9f36b67	86	/* Defines used for the bit position in the register and perform offsets */
<>	157:ff67d9f36b67	87	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
<>	157:ff67d9f36b67	88	/**
<>	157:ff67d9f36b67	89	* @}
<>	157:ff67d9f36b67	90	*/
<>	157:ff67d9f36b67	91
<>	157:ff67d9f36b67	92	/* Private macros ------------------------------------------------------------*/
<>	157:ff67d9f36b67	93	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	94	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
<>	157:ff67d9f36b67	95	* @{
<>	157:ff67d9f36b67	96	*/
<>	157:ff67d9f36b67	97	/**
<>	157:ff67d9f36b67	98	* @}
<>	157:ff67d9f36b67	99	*/
<>	157:ff67d9f36b67	100	#endif /USE_FULL_LL_DRIVER/
<>	157:ff67d9f36b67	101
<>	157:ff67d9f36b67	102	/* Exported types ------------------------------------------------------------*/
<>	157:ff67d9f36b67	103	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	104	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<>	157:ff67d9f36b67	105	* @{
<>	157:ff67d9f36b67	106	*/
<>	157:ff67d9f36b67	107	typedef struct
<>	157:ff67d9f36b67	108	{
<>	157:ff67d9f36b67	109	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<>	157:ff67d9f36b67	110	or as Source base address in case of memory to memory transfer direction.
<>	157:ff67d9f36b67	111
<>	157:ff67d9f36b67	112	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	157:ff67d9f36b67	113
<>	157:ff67d9f36b67	114	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<>	157:ff67d9f36b67	115	or as Destination base address in case of memory to memory transfer direction.
<>	157:ff67d9f36b67	116
<>	157:ff67d9f36b67	117	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	157:ff67d9f36b67	118
<>	157:ff67d9f36b67	119	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<>	157:ff67d9f36b67	120	from memory to memory or from peripheral to memory.
<>	157:ff67d9f36b67	121	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<>	157:ff67d9f36b67	122
<>	157:ff67d9f36b67	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<>	157:ff67d9f36b67	124
<>	157:ff67d9f36b67	125	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<>	157:ff67d9f36b67	126	This parameter can be a value of @ref DMA_LL_EC_MODE
<>	157:ff67d9f36b67	127	@note: The circular buffer mode cannot be used if the memory to memory
<>	157:ff67d9f36b67	128	data transfer direction is configured on the selected Channel
<>	157:ff67d9f36b67	129
<>	157:ff67d9f36b67	130	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<>	157:ff67d9f36b67	131
<>	157:ff67d9f36b67	132	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<>	157:ff67d9f36b67	133	is incremented or not.
<>	157:ff67d9f36b67	134	This parameter can be a value of @ref DMA_LL_EC_PERIPH
<>	157:ff67d9f36b67	135
<>	157:ff67d9f36b67	136	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<>	157:ff67d9f36b67	137
<>	157:ff67d9f36b67	138	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<>	157:ff67d9f36b67	139	is incremented or not.
<>	157:ff67d9f36b67	140	This parameter can be a value of @ref DMA_LL_EC_MEMORY
<>	157:ff67d9f36b67	141
<>	157:ff67d9f36b67	142	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<>	157:ff67d9f36b67	143
<>	157:ff67d9f36b67	144	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<>	157:ff67d9f36b67	145	in case of memory to memory transfer direction.
<>	157:ff67d9f36b67	146	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<>	157:ff67d9f36b67	147
<>	157:ff67d9f36b67	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<>	157:ff67d9f36b67	149
<>	157:ff67d9f36b67	150	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<>	157:ff67d9f36b67	151	in case of memory to memory transfer direction.
<>	157:ff67d9f36b67	152	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<>	157:ff67d9f36b67	153
<>	157:ff67d9f36b67	154	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<>	157:ff67d9f36b67	155
<>	157:ff67d9f36b67	156	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<>	157:ff67d9f36b67	157	The data unit is equal to the source buffer configuration set in PeripheralSize
<>	157:ff67d9f36b67	158	or MemorySize parameters depending in the transfer direction.
<>	157:ff67d9f36b67	159	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	157:ff67d9f36b67	160
<>	157:ff67d9f36b67	161	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<>	157:ff67d9f36b67	162
<>	157:ff67d9f36b67	163	uint32_t Priority; /*!< Specifies the channel priority level.
<>	157:ff67d9f36b67	164	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<>	157:ff67d9f36b67	165
<>	157:ff67d9f36b67	166	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<>	157:ff67d9f36b67	167
<>	157:ff67d9f36b67	168	} LL_DMA_InitTypeDef;
<>	157:ff67d9f36b67	169	/**
<>	157:ff67d9f36b67	170	* @}
<>	157:ff67d9f36b67	171	*/
<>	157:ff67d9f36b67	172	#endif /USE_FULL_LL_DRIVER/
<>	157:ff67d9f36b67	173
<>	157:ff67d9f36b67	174	/* Exported constants --------------------------------------------------------*/
<>	157:ff67d9f36b67	175	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<>	157:ff67d9f36b67	176	* @{
<>	157:ff67d9f36b67	177	*/
<>	157:ff67d9f36b67	178	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	157:ff67d9f36b67	179	* @brief Flags defines which can be used with LL_DMA_WriteReg function
<>	157:ff67d9f36b67	180	* @{
<>	157:ff67d9f36b67	181	*/
<>	157:ff67d9f36b67	182	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
<>	157:ff67d9f36b67	183	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
<>	157:ff67d9f36b67	184	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
<>	157:ff67d9f36b67	185	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
<>	157:ff67d9f36b67	186	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
<>	157:ff67d9f36b67	187	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
<>	157:ff67d9f36b67	188	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
<>	157:ff67d9f36b67	189	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
<>	157:ff67d9f36b67	190	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
<>	157:ff67d9f36b67	191	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
<>	157:ff67d9f36b67	192	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
<>	157:ff67d9f36b67	193	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
<>	157:ff67d9f36b67	194	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
<>	157:ff67d9f36b67	195	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
<>	157:ff67d9f36b67	196	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
<>	157:ff67d9f36b67	197	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
<>	157:ff67d9f36b67	198	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
<>	157:ff67d9f36b67	199	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
<>	157:ff67d9f36b67	200	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
<>	157:ff67d9f36b67	201	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
<>	157:ff67d9f36b67	202	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
<>	157:ff67d9f36b67	203	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
<>	157:ff67d9f36b67	204	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
<>	157:ff67d9f36b67	205	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
<>	157:ff67d9f36b67	206	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
<>	157:ff67d9f36b67	207	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
<>	157:ff67d9f36b67	208	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
<>	157:ff67d9f36b67	209	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
<>	157:ff67d9f36b67	210	/**
<>	157:ff67d9f36b67	211	* @}
<>	157:ff67d9f36b67	212	*/
<>	157:ff67d9f36b67	213
<>	157:ff67d9f36b67	214	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<>	157:ff67d9f36b67	215	* @brief Flags defines which can be used with LL_DMA_ReadReg function
<>	157:ff67d9f36b67	216	* @{
<>	157:ff67d9f36b67	217	*/
<>	157:ff67d9f36b67	218	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
<>	157:ff67d9f36b67	219	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
<>	157:ff67d9f36b67	220	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
<>	157:ff67d9f36b67	221	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
<>	157:ff67d9f36b67	222	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
<>	157:ff67d9f36b67	223	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
<>	157:ff67d9f36b67	224	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
<>	157:ff67d9f36b67	225	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
<>	157:ff67d9f36b67	226	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
<>	157:ff67d9f36b67	227	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
<>	157:ff67d9f36b67	228	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
<>	157:ff67d9f36b67	229	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
<>	157:ff67d9f36b67	230	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
<>	157:ff67d9f36b67	231	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
<>	157:ff67d9f36b67	232	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
<>	157:ff67d9f36b67	233	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
<>	157:ff67d9f36b67	234	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
<>	157:ff67d9f36b67	235	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
<>	157:ff67d9f36b67	236	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
<>	157:ff67d9f36b67	237	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
<>	157:ff67d9f36b67	238	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
<>	157:ff67d9f36b67	239	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
<>	157:ff67d9f36b67	240	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
<>	157:ff67d9f36b67	241	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
<>	157:ff67d9f36b67	242	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
<>	157:ff67d9f36b67	243	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
<>	157:ff67d9f36b67	244	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
<>	157:ff67d9f36b67	245	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
<>	157:ff67d9f36b67	246	/**
<>	157:ff67d9f36b67	247	* @}
<>	157:ff67d9f36b67	248	*/
<>	157:ff67d9f36b67	249
<>	157:ff67d9f36b67	250	/** @defgroup DMA_LL_EC_IT IT Defines
<>	157:ff67d9f36b67	251	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<>	157:ff67d9f36b67	252	* @{
<>	157:ff67d9f36b67	253	*/
<>	157:ff67d9f36b67	254	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
<>	157:ff67d9f36b67	255	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
<>	157:ff67d9f36b67	256	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
<>	157:ff67d9f36b67	257	/**
<>	157:ff67d9f36b67	258	* @}
<>	157:ff67d9f36b67	259	*/
<>	157:ff67d9f36b67	260
<>	157:ff67d9f36b67	261	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<>	157:ff67d9f36b67	262	* @{
<>	157:ff67d9f36b67	263	*/
<>	157:ff67d9f36b67	264	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
<>	157:ff67d9f36b67	265	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
<>	157:ff67d9f36b67	266	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
<>	157:ff67d9f36b67	267	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
<>	157:ff67d9f36b67	268	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
<>	157:ff67d9f36b67	269	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
<>	157:ff67d9f36b67	270	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
<>	157:ff67d9f36b67	271	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	272	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
<>	157:ff67d9f36b67	273	#endif /USE_FULL_LL_DRIVER/
<>	157:ff67d9f36b67	274	/**
<>	157:ff67d9f36b67	275	* @}
<>	157:ff67d9f36b67	276	*/
<>	157:ff67d9f36b67	277
<>	157:ff67d9f36b67	278	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<>	157:ff67d9f36b67	279	* @{
<>	157:ff67d9f36b67	280	*/
<>	157:ff67d9f36b67	281	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
<>	157:ff67d9f36b67	282	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
<>	157:ff67d9f36b67	283	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
<>	157:ff67d9f36b67	284	/**
<>	157:ff67d9f36b67	285	* @}
<>	157:ff67d9f36b67	286	*/
<>	157:ff67d9f36b67	287
<>	157:ff67d9f36b67	288	/** @defgroup DMA_LL_EC_MODE Transfer mode
<>	157:ff67d9f36b67	289	* @{
<>	157:ff67d9f36b67	290	*/
<>	157:ff67d9f36b67	291	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
<>	157:ff67d9f36b67	292	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
<>	157:ff67d9f36b67	293	/**
<>	157:ff67d9f36b67	294	* @}
<>	157:ff67d9f36b67	295	*/
<>	157:ff67d9f36b67	296
<>	157:ff67d9f36b67	297	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<>	157:ff67d9f36b67	298	* @{
<>	157:ff67d9f36b67	299	*/
<>	157:ff67d9f36b67	300	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
<>	157:ff67d9f36b67	301	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
<>	157:ff67d9f36b67	302	/**
<>	157:ff67d9f36b67	303	* @}
<>	157:ff67d9f36b67	304	*/
<>	157:ff67d9f36b67	305
<>	157:ff67d9f36b67	306	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<>	157:ff67d9f36b67	307	* @{
<>	157:ff67d9f36b67	308	*/
<>	157:ff67d9f36b67	309	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
<>	157:ff67d9f36b67	310	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
<>	157:ff67d9f36b67	311	/**
<>	157:ff67d9f36b67	312	* @}
<>	157:ff67d9f36b67	313	*/
<>	157:ff67d9f36b67	314
<>	157:ff67d9f36b67	315	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<>	157:ff67d9f36b67	316	* @{
<>	157:ff67d9f36b67	317	*/
<>	157:ff67d9f36b67	318	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
<>	157:ff67d9f36b67	319	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
<>	157:ff67d9f36b67	320	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
<>	157:ff67d9f36b67	321	/**
<>	157:ff67d9f36b67	322	* @}
<>	157:ff67d9f36b67	323	*/
<>	157:ff67d9f36b67	324
<>	157:ff67d9f36b67	325	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<>	157:ff67d9f36b67	326	* @{
<>	157:ff67d9f36b67	327	*/
<>	157:ff67d9f36b67	328	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
<>	157:ff67d9f36b67	329	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
<>	157:ff67d9f36b67	330	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
<>	157:ff67d9f36b67	331	/**
<>	157:ff67d9f36b67	332	* @}
<>	157:ff67d9f36b67	333	*/
<>	157:ff67d9f36b67	334
<>	157:ff67d9f36b67	335	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<>	157:ff67d9f36b67	336	* @{
<>	157:ff67d9f36b67	337	*/
<>	157:ff67d9f36b67	338	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
<>	157:ff67d9f36b67	339	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
<>	157:ff67d9f36b67	340	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
<>	157:ff67d9f36b67	341	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
<>	157:ff67d9f36b67	342	/**
<>	157:ff67d9f36b67	343	* @}
<>	157:ff67d9f36b67	344	*/
<>	157:ff67d9f36b67	345
<>	157:ff67d9f36b67	346
<>	157:ff67d9f36b67	347	/**
<>	157:ff67d9f36b67	348	* @}
<>	157:ff67d9f36b67	349	*/
<>	157:ff67d9f36b67	350
<>	157:ff67d9f36b67	351	/* Exported macro ------------------------------------------------------------*/
<>	157:ff67d9f36b67	352	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<>	157:ff67d9f36b67	353	* @{
<>	157:ff67d9f36b67	354	*/
<>	157:ff67d9f36b67	355
<>	157:ff67d9f36b67	356	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<>	157:ff67d9f36b67	357	* @{
<>	157:ff67d9f36b67	358	*/
<>	157:ff67d9f36b67	359	/**
<>	157:ff67d9f36b67	360	* @brief Write a value in DMA register
<>	157:ff67d9f36b67	361	* @param __INSTANCE__ DMA Instance
<>	157:ff67d9f36b67	362	* @param __REG__ Register to be written
<>	157:ff67d9f36b67	363	* @param __VALUE__ Value to be written in the register
<>	157:ff67d9f36b67	364	* @retval None
<>	157:ff67d9f36b67	365	*/
<>	157:ff67d9f36b67	366	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	157:ff67d9f36b67	367
<>	157:ff67d9f36b67	368	/**
<>	157:ff67d9f36b67	369	* @brief Read a value in DMA register
<>	157:ff67d9f36b67	370	* @param __INSTANCE__ DMA Instance
<>	157:ff67d9f36b67	371	* @param __REG__ Register to be read
<>	157:ff67d9f36b67	372	* @retval Register value
<>	157:ff67d9f36b67	373	*/
<>	157:ff67d9f36b67	374	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	157:ff67d9f36b67	375	/**
<>	157:ff67d9f36b67	376	* @}
<>	157:ff67d9f36b67	377	*/
<>	157:ff67d9f36b67	378
<>	157:ff67d9f36b67	379	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<>	157:ff67d9f36b67	380	* @{
<>	157:ff67d9f36b67	381	*/
<>	157:ff67d9f36b67	382	/**
<>	157:ff67d9f36b67	383	* @brief Convert DMAx_Channely into DMAx
<>	157:ff67d9f36b67	384	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	157:ff67d9f36b67	385	* @retval DMAx
<>	157:ff67d9f36b67	386	*/
<>	157:ff67d9f36b67	387	#if defined(DMA2)
<>	157:ff67d9f36b67	388	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<>	157:ff67d9f36b67	389	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<>	157:ff67d9f36b67	390	#else
<>	157:ff67d9f36b67	391	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<>	157:ff67d9f36b67	392	#endif
<>	157:ff67d9f36b67	393
<>	157:ff67d9f36b67	394	/**
<>	157:ff67d9f36b67	395	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<>	157:ff67d9f36b67	396	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	157:ff67d9f36b67	397	* @retval LL_DMA_CHANNEL_y
<>	157:ff67d9f36b67	398	*/
<>	157:ff67d9f36b67	399	#if defined (DMA2)
<>	157:ff67d9f36b67	400	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	157:ff67d9f36b67	401	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	157:ff67d9f36b67	402	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	157:ff67d9f36b67	403	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	157:ff67d9f36b67	404	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	157:ff67d9f36b67	405	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	157:ff67d9f36b67	406	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	157:ff67d9f36b67	407	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	157:ff67d9f36b67	408	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	157:ff67d9f36b67	409	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	157:ff67d9f36b67	410	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	157:ff67d9f36b67	411	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	157:ff67d9f36b67	412	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	157:ff67d9f36b67	413	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	157:ff67d9f36b67	414	LL_DMA_CHANNEL_7)
<>	157:ff67d9f36b67	415	#else
<>	157:ff67d9f36b67	416	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	157:ff67d9f36b67	417	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	157:ff67d9f36b67	418	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	157:ff67d9f36b67	419	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	157:ff67d9f36b67	420	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	157:ff67d9f36b67	421	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	157:ff67d9f36b67	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	157:ff67d9f36b67	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	157:ff67d9f36b67	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	157:ff67d9f36b67	425	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	157:ff67d9f36b67	426	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	157:ff67d9f36b67	427	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	157:ff67d9f36b67	428	LL_DMA_CHANNEL_7)
<>	157:ff67d9f36b67	429	#endif
<>	157:ff67d9f36b67	430	#else
<>	157:ff67d9f36b67	431	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	157:ff67d9f36b67	432	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	157:ff67d9f36b67	433	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	157:ff67d9f36b67	434	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	157:ff67d9f36b67	435	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	157:ff67d9f36b67	436	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	157:ff67d9f36b67	437	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	157:ff67d9f36b67	438	LL_DMA_CHANNEL_7)
<>	157:ff67d9f36b67	439	#endif
<>	157:ff67d9f36b67	440
<>	157:ff67d9f36b67	441	/**
<>	157:ff67d9f36b67	442	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<>	157:ff67d9f36b67	443	* @param __DMA_INSTANCE__ DMAx
<>	157:ff67d9f36b67	444	* @param __CHANNEL__ LL_DMA_CHANNEL_y
<>	157:ff67d9f36b67	445	* @retval DMAx_Channely
<>	157:ff67d9f36b67	446	*/
<>	157:ff67d9f36b67	447	#if defined (DMA2)
<>	157:ff67d9f36b67	448	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	157:ff67d9f36b67	449	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	157:ff67d9f36b67	450	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	157:ff67d9f36b67	451	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	157:ff67d9f36b67	452	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	157:ff67d9f36b67	453	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	157:ff67d9f36b67	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	157:ff67d9f36b67	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	157:ff67d9f36b67	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	157:ff67d9f36b67	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	157:ff67d9f36b67	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	157:ff67d9f36b67	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	157:ff67d9f36b67	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	157:ff67d9f36b67	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<>	157:ff67d9f36b67	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<>	157:ff67d9f36b67	463	DMA2_Channel7)
<>	157:ff67d9f36b67	464	#else
<>	157:ff67d9f36b67	465	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	157:ff67d9f36b67	466	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	157:ff67d9f36b67	467	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	157:ff67d9f36b67	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	157:ff67d9f36b67	469	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	157:ff67d9f36b67	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	157:ff67d9f36b67	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	157:ff67d9f36b67	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	157:ff67d9f36b67	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	157:ff67d9f36b67	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	157:ff67d9f36b67	475	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	157:ff67d9f36b67	476	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	157:ff67d9f36b67	477	DMA1_Channel7)
<>	157:ff67d9f36b67	478	#endif
<>	157:ff67d9f36b67	479	#else
<>	157:ff67d9f36b67	480	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	157:ff67d9f36b67	481	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	157:ff67d9f36b67	482	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	157:ff67d9f36b67	483	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	157:ff67d9f36b67	484	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	157:ff67d9f36b67	485	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	157:ff67d9f36b67	486	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	157:ff67d9f36b67	487	DMA1_Channel7)
<>	157:ff67d9f36b67	488	#endif
<>	157:ff67d9f36b67	489
<>	157:ff67d9f36b67	490	/**
<>	157:ff67d9f36b67	491	* @}
<>	157:ff67d9f36b67	492	*/
<>	157:ff67d9f36b67	493
<>	157:ff67d9f36b67	494	/**
<>	157:ff67d9f36b67	495	* @}
<>	157:ff67d9f36b67	496	*/
<>	157:ff67d9f36b67	497
<>	157:ff67d9f36b67	498	/* Exported functions --------------------------------------------------------*/
<>	157:ff67d9f36b67	499	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<>	157:ff67d9f36b67	500	* @{
<>	157:ff67d9f36b67	501	*/
<>	157:ff67d9f36b67	502
<>	157:ff67d9f36b67	503	/** @defgroup DMA_LL_EF_Configuration Configuration
<>	157:ff67d9f36b67	504	* @{
<>	157:ff67d9f36b67	505	*/
<>	157:ff67d9f36b67	506	/**
<>	157:ff67d9f36b67	507	* @brief Enable DMA channel.
<>	157:ff67d9f36b67	508	* @rmtoll CCR EN LL_DMA_EnableChannel
<>	157:ff67d9f36b67	509	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	510	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	511	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	512	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	513	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	514	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	515	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	516	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	517	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	518	* @retval None
<>	157:ff67d9f36b67	519	*/
<>	157:ff67d9f36b67	520	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	521	{
<>	157:ff67d9f36b67	522	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	157:ff67d9f36b67	523	}
<>	157:ff67d9f36b67	524
<>	157:ff67d9f36b67	525	/**
<>	157:ff67d9f36b67	526	* @brief Disable DMA channel.
<>	157:ff67d9f36b67	527	* @rmtoll CCR EN LL_DMA_DisableChannel
<>	157:ff67d9f36b67	528	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	529	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	530	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	531	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	532	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	533	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	534	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	535	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	536	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	537	* @retval None
<>	157:ff67d9f36b67	538	*/
<>	157:ff67d9f36b67	539	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	540	{
<>	157:ff67d9f36b67	541	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	157:ff67d9f36b67	542	}
<>	157:ff67d9f36b67	543
<>	157:ff67d9f36b67	544	/**
<>	157:ff67d9f36b67	545	* @brief Check if DMA channel is enabled or disabled.
<>	157:ff67d9f36b67	546	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
<>	157:ff67d9f36b67	547	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	548	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	549	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	550	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	551	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	552	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	553	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	554	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	555	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	556	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	557	*/
<>	157:ff67d9f36b67	558	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	559	{
<>	157:ff67d9f36b67	560	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	561	DMA_CCR_EN) == (DMA_CCR_EN));
<>	157:ff67d9f36b67	562	}
<>	157:ff67d9f36b67	563
<>	157:ff67d9f36b67	564	/**
<>	157:ff67d9f36b67	565	* @brief Configure all parameters link to DMA transfer.
<>	157:ff67d9f36b67	566	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<>	157:ff67d9f36b67	567	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
<>	157:ff67d9f36b67	568	* CCR CIRC LL_DMA_ConfigTransfer\n
<>	157:ff67d9f36b67	569	* CCR PINC LL_DMA_ConfigTransfer\n
<>	157:ff67d9f36b67	570	* CCR MINC LL_DMA_ConfigTransfer\n
<>	157:ff67d9f36b67	571	* CCR PSIZE LL_DMA_ConfigTransfer\n
<>	157:ff67d9f36b67	572	* CCR MSIZE LL_DMA_ConfigTransfer\n
<>	157:ff67d9f36b67	573	* CCR PL LL_DMA_ConfigTransfer
<>	157:ff67d9f36b67	574	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	575	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	576	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	577	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	578	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	579	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	580	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	581	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	582	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	583	* @param Configuration This parameter must be a combination of all the following values:
<>	157:ff67d9f36b67	584	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	157:ff67d9f36b67	585	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<>	157:ff67d9f36b67	586	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<>	157:ff67d9f36b67	587	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<>	157:ff67d9f36b67	588	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<>	157:ff67d9f36b67	589	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<>	157:ff67d9f36b67	590	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<>	157:ff67d9f36b67	591	* @retval None
<>	157:ff67d9f36b67	592	*/
<>	157:ff67d9f36b67	593	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<>	157:ff67d9f36b67	594	{
<>	157:ff67d9f36b67	595	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	596	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
<>	157:ff67d9f36b67	597	Configuration);
<>	157:ff67d9f36b67	598	}
<>	157:ff67d9f36b67	599
<>	157:ff67d9f36b67	600	/**
<>	157:ff67d9f36b67	601	* @brief Set Data transfer direction (read from peripheral or from memory).
<>	157:ff67d9f36b67	602	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<>	157:ff67d9f36b67	603	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
<>	157:ff67d9f36b67	604	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	605	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	606	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	607	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	608	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	609	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	610	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	611	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	612	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	613	* @param Direction This parameter can be one of the following values:
<>	157:ff67d9f36b67	614	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	157:ff67d9f36b67	615	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	157:ff67d9f36b67	616	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	157:ff67d9f36b67	617	* @retval None
<>	157:ff67d9f36b67	618	*/
<>	157:ff67d9f36b67	619	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<>	157:ff67d9f36b67	620	{
<>	157:ff67d9f36b67	621	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	622	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
<>	157:ff67d9f36b67	623	}
<>	157:ff67d9f36b67	624
<>	157:ff67d9f36b67	625	/**
<>	157:ff67d9f36b67	626	* @brief Get Data transfer direction (read from peripheral or from memory).
<>	157:ff67d9f36b67	627	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<>	157:ff67d9f36b67	628	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
<>	157:ff67d9f36b67	629	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	630	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	631	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	632	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	633	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	634	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	635	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	636	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	637	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	638	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	639	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	157:ff67d9f36b67	640	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	157:ff67d9f36b67	641	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	157:ff67d9f36b67	642	*/
<>	157:ff67d9f36b67	643	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	644	{
<>	157:ff67d9f36b67	645	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	646	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
<>	157:ff67d9f36b67	647	}
<>	157:ff67d9f36b67	648
<>	157:ff67d9f36b67	649	/**
<>	157:ff67d9f36b67	650	* @brief Set DMA mode circular or normal.
<>	157:ff67d9f36b67	651	* @note The circular buffer mode cannot be used if the memory-to-memory
<>	157:ff67d9f36b67	652	* data transfer is configured on the selected Channel.
<>	157:ff67d9f36b67	653	* @rmtoll CCR CIRC LL_DMA_SetMode
<>	157:ff67d9f36b67	654	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	655	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	656	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	657	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	658	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	659	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	660	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	661	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	662	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	663	* @param Mode This parameter can be one of the following values:
<>	157:ff67d9f36b67	664	* @arg @ref LL_DMA_MODE_NORMAL
<>	157:ff67d9f36b67	665	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	157:ff67d9f36b67	666	* @retval None
<>	157:ff67d9f36b67	667	*/
<>	157:ff67d9f36b67	668	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<>	157:ff67d9f36b67	669	{
<>	157:ff67d9f36b67	670	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<>	157:ff67d9f36b67	671	Mode);
<>	157:ff67d9f36b67	672	}
<>	157:ff67d9f36b67	673
<>	157:ff67d9f36b67	674	/**
<>	157:ff67d9f36b67	675	* @brief Get DMA mode circular or normal.
<>	157:ff67d9f36b67	676	* @rmtoll CCR CIRC LL_DMA_GetMode
<>	157:ff67d9f36b67	677	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	678	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	679	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	680	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	681	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	682	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	683	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	684	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	685	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	686	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	687	* @arg @ref LL_DMA_MODE_NORMAL
<>	157:ff67d9f36b67	688	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	157:ff67d9f36b67	689	*/
<>	157:ff67d9f36b67	690	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	691	{
<>	157:ff67d9f36b67	692	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	693	DMA_CCR_CIRC));
<>	157:ff67d9f36b67	694	}
<>	157:ff67d9f36b67	695
<>	157:ff67d9f36b67	696	/**
<>	157:ff67d9f36b67	697	* @brief Set Peripheral increment mode.
<>	157:ff67d9f36b67	698	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<>	157:ff67d9f36b67	699	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	700	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	701	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	702	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	703	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	704	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	705	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	706	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	707	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	708	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<>	157:ff67d9f36b67	709	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	157:ff67d9f36b67	710	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	157:ff67d9f36b67	711	* @retval None
<>	157:ff67d9f36b67	712	*/
<>	157:ff67d9f36b67	713	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<>	157:ff67d9f36b67	714	{
<>	157:ff67d9f36b67	715	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<>	157:ff67d9f36b67	716	PeriphOrM2MSrcIncMode);
<>	157:ff67d9f36b67	717	}
<>	157:ff67d9f36b67	718
<>	157:ff67d9f36b67	719	/**
<>	157:ff67d9f36b67	720	* @brief Get Peripheral increment mode.
<>	157:ff67d9f36b67	721	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<>	157:ff67d9f36b67	722	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	723	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	724	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	725	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	726	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	727	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	728	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	729	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	730	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	731	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	732	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	157:ff67d9f36b67	733	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	157:ff67d9f36b67	734	*/
<>	157:ff67d9f36b67	735	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	736	{
<>	157:ff67d9f36b67	737	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	738	DMA_CCR_PINC));
<>	157:ff67d9f36b67	739	}
<>	157:ff67d9f36b67	740
<>	157:ff67d9f36b67	741	/**
<>	157:ff67d9f36b67	742	* @brief Set Memory increment mode.
<>	157:ff67d9f36b67	743	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<>	157:ff67d9f36b67	744	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	745	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	746	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	747	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	748	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	749	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	750	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	751	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	752	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	753	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<>	157:ff67d9f36b67	754	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	157:ff67d9f36b67	755	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	157:ff67d9f36b67	756	* @retval None
<>	157:ff67d9f36b67	757	*/
<>	157:ff67d9f36b67	758	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<>	157:ff67d9f36b67	759	{
<>	157:ff67d9f36b67	760	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<>	157:ff67d9f36b67	761	MemoryOrM2MDstIncMode);
<>	157:ff67d9f36b67	762	}
<>	157:ff67d9f36b67	763
<>	157:ff67d9f36b67	764	/**
<>	157:ff67d9f36b67	765	* @brief Get Memory increment mode.
<>	157:ff67d9f36b67	766	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<>	157:ff67d9f36b67	767	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	768	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	769	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	770	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	771	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	772	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	773	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	774	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	775	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	776	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	777	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	157:ff67d9f36b67	778	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	157:ff67d9f36b67	779	*/
<>	157:ff67d9f36b67	780	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	781	{
<>	157:ff67d9f36b67	782	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	783	DMA_CCR_MINC));
<>	157:ff67d9f36b67	784	}
<>	157:ff67d9f36b67	785
<>	157:ff67d9f36b67	786	/**
<>	157:ff67d9f36b67	787	* @brief Set Peripheral size.
<>	157:ff67d9f36b67	788	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<>	157:ff67d9f36b67	789	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	790	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	791	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	792	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	793	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	794	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	795	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	796	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	797	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	798	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<>	157:ff67d9f36b67	799	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	157:ff67d9f36b67	800	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	157:ff67d9f36b67	801	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	157:ff67d9f36b67	802	* @retval None
<>	157:ff67d9f36b67	803	*/
<>	157:ff67d9f36b67	804	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<>	157:ff67d9f36b67	805	{
<>	157:ff67d9f36b67	806	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<>	157:ff67d9f36b67	807	PeriphOrM2MSrcDataSize);
<>	157:ff67d9f36b67	808	}
<>	157:ff67d9f36b67	809
<>	157:ff67d9f36b67	810	/**
<>	157:ff67d9f36b67	811	* @brief Get Peripheral size.
<>	157:ff67d9f36b67	812	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<>	157:ff67d9f36b67	813	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	814	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	815	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	816	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	817	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	818	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	819	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	820	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	821	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	822	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	823	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	157:ff67d9f36b67	824	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	157:ff67d9f36b67	825	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	157:ff67d9f36b67	826	*/
<>	157:ff67d9f36b67	827	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	828	{
<>	157:ff67d9f36b67	829	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	830	DMA_CCR_PSIZE));
<>	157:ff67d9f36b67	831	}
<>	157:ff67d9f36b67	832
<>	157:ff67d9f36b67	833	/**
<>	157:ff67d9f36b67	834	* @brief Set Memory size.
<>	157:ff67d9f36b67	835	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<>	157:ff67d9f36b67	836	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	837	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	838	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	839	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	840	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	841	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	842	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	843	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	844	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	845	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<>	157:ff67d9f36b67	846	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	157:ff67d9f36b67	847	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	157:ff67d9f36b67	848	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	157:ff67d9f36b67	849	* @retval None
<>	157:ff67d9f36b67	850	*/
<>	157:ff67d9f36b67	851	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<>	157:ff67d9f36b67	852	{
<>	157:ff67d9f36b67	853	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<>	157:ff67d9f36b67	854	MemoryOrM2MDstDataSize);
<>	157:ff67d9f36b67	855	}
<>	157:ff67d9f36b67	856
<>	157:ff67d9f36b67	857	/**
<>	157:ff67d9f36b67	858	* @brief Get Memory size.
<>	157:ff67d9f36b67	859	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<>	157:ff67d9f36b67	860	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	861	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	862	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	863	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	864	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	865	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	866	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	867	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	868	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	869	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	870	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	157:ff67d9f36b67	871	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	157:ff67d9f36b67	872	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	157:ff67d9f36b67	873	*/
<>	157:ff67d9f36b67	874	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	875	{
<>	157:ff67d9f36b67	876	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	877	DMA_CCR_MSIZE));
<>	157:ff67d9f36b67	878	}
<>	157:ff67d9f36b67	879
<>	157:ff67d9f36b67	880	/**
<>	157:ff67d9f36b67	881	* @brief Set Channel priority level.
<>	157:ff67d9f36b67	882	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<>	157:ff67d9f36b67	883	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	884	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	885	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	886	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	887	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	888	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	889	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	890	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	891	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	892	* @param Priority This parameter can be one of the following values:
<>	157:ff67d9f36b67	893	* @arg @ref LL_DMA_PRIORITY_LOW
<>	157:ff67d9f36b67	894	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	157:ff67d9f36b67	895	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	157:ff67d9f36b67	896	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	157:ff67d9f36b67	897	* @retval None
<>	157:ff67d9f36b67	898	*/
<>	157:ff67d9f36b67	899	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<>	157:ff67d9f36b67	900	{
<>	157:ff67d9f36b67	901	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<>	157:ff67d9f36b67	902	Priority);
<>	157:ff67d9f36b67	903	}
<>	157:ff67d9f36b67	904
<>	157:ff67d9f36b67	905	/**
<>	157:ff67d9f36b67	906	* @brief Get Channel priority level.
<>	157:ff67d9f36b67	907	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<>	157:ff67d9f36b67	908	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	909	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	910	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	911	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	912	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	913	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	914	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	915	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	916	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	917	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	918	* @arg @ref LL_DMA_PRIORITY_LOW
<>	157:ff67d9f36b67	919	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	157:ff67d9f36b67	920	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	157:ff67d9f36b67	921	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	157:ff67d9f36b67	922	*/
<>	157:ff67d9f36b67	923	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	924	{
<>	157:ff67d9f36b67	925	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	926	DMA_CCR_PL));
<>	157:ff67d9f36b67	927	}
<>	157:ff67d9f36b67	928
<>	157:ff67d9f36b67	929	/**
<>	157:ff67d9f36b67	930	* @brief Set Number of data to transfer.
<>	157:ff67d9f36b67	931	* @note This action has no effect if
<>	157:ff67d9f36b67	932	* channel is enabled.
<>	157:ff67d9f36b67	933	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
<>	157:ff67d9f36b67	934	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	935	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	936	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	937	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	938	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	939	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	940	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	941	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	942	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	943	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	157:ff67d9f36b67	944	* @retval None
<>	157:ff67d9f36b67	945	*/
<>	157:ff67d9f36b67	946	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<>	157:ff67d9f36b67	947	{
<>	157:ff67d9f36b67	948	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	157:ff67d9f36b67	949	DMA_CNDTR_NDT, NbData);
<>	157:ff67d9f36b67	950	}
<>	157:ff67d9f36b67	951
<>	157:ff67d9f36b67	952	/**
<>	157:ff67d9f36b67	953	* @brief Get Number of data to transfer.
<>	157:ff67d9f36b67	954	* @note Once the channel is enabled, the return value indicate the
<>	157:ff67d9f36b67	955	* remaining bytes to be transmitted.
<>	157:ff67d9f36b67	956	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
<>	157:ff67d9f36b67	957	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	958	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	959	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	960	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	961	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	962	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	963	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	964	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	965	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	966	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	967	*/
<>	157:ff67d9f36b67	968	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	969	{
<>	157:ff67d9f36b67	970	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	157:ff67d9f36b67	971	DMA_CNDTR_NDT));
<>	157:ff67d9f36b67	972	}
<>	157:ff67d9f36b67	973
<>	157:ff67d9f36b67	974	/**
<>	157:ff67d9f36b67	975	* @brief Configure the Source and Destination addresses.
<>	157:ff67d9f36b67	976	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
<>	157:ff67d9f36b67	977	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<>	157:ff67d9f36b67	978	* CMAR MA LL_DMA_ConfigAddresses
<>	157:ff67d9f36b67	979	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	980	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	981	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	982	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	983	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	984	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	985	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	986	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	987	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	988	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	989	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	990	* @param Direction This parameter can be one of the following values:
<>	157:ff67d9f36b67	991	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	157:ff67d9f36b67	992	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	157:ff67d9f36b67	993	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	157:ff67d9f36b67	994	* @retval None
<>	157:ff67d9f36b67	995	*/
<>	157:ff67d9f36b67	996	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<>	157:ff67d9f36b67	997	uint32_t DstAddress, uint32_t Direction)
<>	157:ff67d9f36b67	998	{
<>	157:ff67d9f36b67	999	/* Direction Memory to Periph */
<>	157:ff67d9f36b67	1000	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<>	157:ff67d9f36b67	1001	{
<>	157:ff67d9f36b67	1002	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	157:ff67d9f36b67	1003	SrcAddress);
<>	157:ff67d9f36b67	1004	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	157:ff67d9f36b67	1005	DstAddress);
<>	157:ff67d9f36b67	1006	}
<>	157:ff67d9f36b67	1007	/* Direction Periph to Memory and Memory to Memory */
<>	157:ff67d9f36b67	1008	else
<>	157:ff67d9f36b67	1009	{
<>	157:ff67d9f36b67	1010	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	157:ff67d9f36b67	1011	SrcAddress);
<>	157:ff67d9f36b67	1012	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	157:ff67d9f36b67	1013	DstAddress);
<>	157:ff67d9f36b67	1014	}
<>	157:ff67d9f36b67	1015	}
<>	157:ff67d9f36b67	1016
<>	157:ff67d9f36b67	1017	/**
<>	157:ff67d9f36b67	1018	* @brief Set the Memory address.
<>	157:ff67d9f36b67	1019	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	157:ff67d9f36b67	1020	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<>	157:ff67d9f36b67	1021	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1022	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1023	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1024	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1025	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1026	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1027	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1028	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1029	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1030	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1031	* @retval None
<>	157:ff67d9f36b67	1032	*/
<>	157:ff67d9f36b67	1033	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	157:ff67d9f36b67	1034	{
<>	157:ff67d9f36b67	1035	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	157:ff67d9f36b67	1036	MemoryAddress);
<>	157:ff67d9f36b67	1037	}
<>	157:ff67d9f36b67	1038
<>	157:ff67d9f36b67	1039	/**
<>	157:ff67d9f36b67	1040	* @brief Set the Peripheral address.
<>	157:ff67d9f36b67	1041	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	157:ff67d9f36b67	1042	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<>	157:ff67d9f36b67	1043	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1044	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1045	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1046	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1047	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1048	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1049	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1050	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1051	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1052	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1053	* @retval None
<>	157:ff67d9f36b67	1054	*/
<>	157:ff67d9f36b67	1055	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<>	157:ff67d9f36b67	1056	{
<>	157:ff67d9f36b67	1057	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	157:ff67d9f36b67	1058	PeriphAddress);
<>	157:ff67d9f36b67	1059	}
<>	157:ff67d9f36b67	1060
<>	157:ff67d9f36b67	1061	/**
<>	157:ff67d9f36b67	1062	* @brief Get Memory address.
<>	157:ff67d9f36b67	1063	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	157:ff67d9f36b67	1064	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<>	157:ff67d9f36b67	1065	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1066	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1067	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1068	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1069	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1070	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1071	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1072	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1073	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1074	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1075	*/
<>	157:ff67d9f36b67	1076	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1077	{
<>	157:ff67d9f36b67	1078	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	157:ff67d9f36b67	1079	DMA_CMAR_MA));
<>	157:ff67d9f36b67	1080	}
<>	157:ff67d9f36b67	1081
<>	157:ff67d9f36b67	1082	/**
<>	157:ff67d9f36b67	1083	* @brief Get Peripheral address.
<>	157:ff67d9f36b67	1084	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	157:ff67d9f36b67	1085	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<>	157:ff67d9f36b67	1086	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1087	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1088	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1089	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1090	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1091	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1092	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1093	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1094	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1095	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1096	*/
<>	157:ff67d9f36b67	1097	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1098	{
<>	157:ff67d9f36b67	1099	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	157:ff67d9f36b67	1100	DMA_CPAR_PA));
<>	157:ff67d9f36b67	1101	}
<>	157:ff67d9f36b67	1102
<>	157:ff67d9f36b67	1103	/**
<>	157:ff67d9f36b67	1104	* @brief Set the Memory to Memory Source address.
<>	157:ff67d9f36b67	1105	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	157:ff67d9f36b67	1106	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<>	157:ff67d9f36b67	1107	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1108	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1109	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1110	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1111	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1112	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1113	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1114	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1115	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1116	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1117	* @retval None
<>	157:ff67d9f36b67	1118	*/
<>	157:ff67d9f36b67	1119	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	157:ff67d9f36b67	1120	{
<>	157:ff67d9f36b67	1121	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	157:ff67d9f36b67	1122	MemoryAddress);
<>	157:ff67d9f36b67	1123	}
<>	157:ff67d9f36b67	1124
<>	157:ff67d9f36b67	1125	/**
<>	157:ff67d9f36b67	1126	* @brief Set the Memory to Memory Destination address.
<>	157:ff67d9f36b67	1127	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	157:ff67d9f36b67	1128	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<>	157:ff67d9f36b67	1129	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1130	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1131	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1132	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1133	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1134	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1135	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1136	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1137	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1138	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1139	* @retval None
<>	157:ff67d9f36b67	1140	*/
<>	157:ff67d9f36b67	1141	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	157:ff67d9f36b67	1142	{
<>	157:ff67d9f36b67	1143	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	157:ff67d9f36b67	1144	MemoryAddress);
<>	157:ff67d9f36b67	1145	}
<>	157:ff67d9f36b67	1146
<>	157:ff67d9f36b67	1147	/**
<>	157:ff67d9f36b67	1148	* @brief Get the Memory to Memory Source address.
<>	157:ff67d9f36b67	1149	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	157:ff67d9f36b67	1150	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<>	157:ff67d9f36b67	1151	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1152	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1153	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1154	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1155	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1156	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1157	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1158	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1159	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1160	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1161	*/
<>	157:ff67d9f36b67	1162	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1163	{
<>	157:ff67d9f36b67	1164	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	157:ff67d9f36b67	1165	DMA_CPAR_PA));
<>	157:ff67d9f36b67	1166	}
<>	157:ff67d9f36b67	1167
<>	157:ff67d9f36b67	1168	/**
<>	157:ff67d9f36b67	1169	* @brief Get the Memory to Memory Destination address.
<>	157:ff67d9f36b67	1170	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	157:ff67d9f36b67	1171	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<>	157:ff67d9f36b67	1172	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1173	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1174	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1175	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1176	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1177	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1178	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1179	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1180	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1181	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	157:ff67d9f36b67	1182	*/
<>	157:ff67d9f36b67	1183	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1184	{
<>	157:ff67d9f36b67	1185	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	157:ff67d9f36b67	1186	DMA_CMAR_MA));
<>	157:ff67d9f36b67	1187	}
<>	157:ff67d9f36b67	1188
<>	157:ff67d9f36b67	1189
<>	157:ff67d9f36b67	1190	/**
<>	157:ff67d9f36b67	1191	* @}
<>	157:ff67d9f36b67	1192	*/
<>	157:ff67d9f36b67	1193
<>	157:ff67d9f36b67	1194	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<>	157:ff67d9f36b67	1195	* @{
<>	157:ff67d9f36b67	1196	*/
<>	157:ff67d9f36b67	1197
<>	157:ff67d9f36b67	1198	/**
<>	157:ff67d9f36b67	1199	* @brief Get Channel 1 global interrupt flag.
<>	157:ff67d9f36b67	1200	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<>	157:ff67d9f36b67	1201	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1202	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1203	*/
<>	157:ff67d9f36b67	1204	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1205	{
<>	157:ff67d9f36b67	1206	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<>	157:ff67d9f36b67	1207	}
<>	157:ff67d9f36b67	1208
<>	157:ff67d9f36b67	1209	/**
<>	157:ff67d9f36b67	1210	* @brief Get Channel 2 global interrupt flag.
<>	157:ff67d9f36b67	1211	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<>	157:ff67d9f36b67	1212	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1213	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1214	*/
<>	157:ff67d9f36b67	1215	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1216	{
<>	157:ff67d9f36b67	1217	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<>	157:ff67d9f36b67	1218	}
<>	157:ff67d9f36b67	1219
<>	157:ff67d9f36b67	1220	/**
<>	157:ff67d9f36b67	1221	* @brief Get Channel 3 global interrupt flag.
<>	157:ff67d9f36b67	1222	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<>	157:ff67d9f36b67	1223	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1224	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1225	*/
<>	157:ff67d9f36b67	1226	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1227	{
<>	157:ff67d9f36b67	1228	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<>	157:ff67d9f36b67	1229	}
<>	157:ff67d9f36b67	1230
<>	157:ff67d9f36b67	1231	/**
<>	157:ff67d9f36b67	1232	* @brief Get Channel 4 global interrupt flag.
<>	157:ff67d9f36b67	1233	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<>	157:ff67d9f36b67	1234	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1235	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1236	*/
<>	157:ff67d9f36b67	1237	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1238	{
<>	157:ff67d9f36b67	1239	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<>	157:ff67d9f36b67	1240	}
<>	157:ff67d9f36b67	1241
<>	157:ff67d9f36b67	1242	/**
<>	157:ff67d9f36b67	1243	* @brief Get Channel 5 global interrupt flag.
<>	157:ff67d9f36b67	1244	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<>	157:ff67d9f36b67	1245	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1246	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1247	*/
<>	157:ff67d9f36b67	1248	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1249	{
<>	157:ff67d9f36b67	1250	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<>	157:ff67d9f36b67	1251	}
<>	157:ff67d9f36b67	1252
<>	157:ff67d9f36b67	1253	/**
<>	157:ff67d9f36b67	1254	* @brief Get Channel 6 global interrupt flag.
<>	157:ff67d9f36b67	1255	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<>	157:ff67d9f36b67	1256	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1257	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1258	*/
<>	157:ff67d9f36b67	1259	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1260	{
<>	157:ff67d9f36b67	1261	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<>	157:ff67d9f36b67	1262	}
<>	157:ff67d9f36b67	1263
<>	157:ff67d9f36b67	1264	/**
<>	157:ff67d9f36b67	1265	* @brief Get Channel 7 global interrupt flag.
<>	157:ff67d9f36b67	1266	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<>	157:ff67d9f36b67	1267	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1268	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1269	*/
<>	157:ff67d9f36b67	1270	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1271	{
<>	157:ff67d9f36b67	1272	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<>	157:ff67d9f36b67	1273	}
<>	157:ff67d9f36b67	1274
<>	157:ff67d9f36b67	1275	/**
<>	157:ff67d9f36b67	1276	* @brief Get Channel 1 transfer complete flag.
<>	157:ff67d9f36b67	1277	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<>	157:ff67d9f36b67	1278	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1279	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1280	*/
<>	157:ff67d9f36b67	1281	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1282	{
<>	157:ff67d9f36b67	1283	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<>	157:ff67d9f36b67	1284	}
<>	157:ff67d9f36b67	1285
<>	157:ff67d9f36b67	1286	/**
<>	157:ff67d9f36b67	1287	* @brief Get Channel 2 transfer complete flag.
<>	157:ff67d9f36b67	1288	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<>	157:ff67d9f36b67	1289	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1290	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1291	*/
<>	157:ff67d9f36b67	1292	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1293	{
<>	157:ff67d9f36b67	1294	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<>	157:ff67d9f36b67	1295	}
<>	157:ff67d9f36b67	1296
<>	157:ff67d9f36b67	1297	/**
<>	157:ff67d9f36b67	1298	* @brief Get Channel 3 transfer complete flag.
<>	157:ff67d9f36b67	1299	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<>	157:ff67d9f36b67	1300	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1301	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1302	*/
<>	157:ff67d9f36b67	1303	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1304	{
<>	157:ff67d9f36b67	1305	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<>	157:ff67d9f36b67	1306	}
<>	157:ff67d9f36b67	1307
<>	157:ff67d9f36b67	1308	/**
<>	157:ff67d9f36b67	1309	* @brief Get Channel 4 transfer complete flag.
<>	157:ff67d9f36b67	1310	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<>	157:ff67d9f36b67	1311	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1312	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1313	*/
<>	157:ff67d9f36b67	1314	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1315	{
<>	157:ff67d9f36b67	1316	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<>	157:ff67d9f36b67	1317	}
<>	157:ff67d9f36b67	1318
<>	157:ff67d9f36b67	1319	/**
<>	157:ff67d9f36b67	1320	* @brief Get Channel 5 transfer complete flag.
<>	157:ff67d9f36b67	1321	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<>	157:ff67d9f36b67	1322	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1323	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1324	*/
<>	157:ff67d9f36b67	1325	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1326	{
<>	157:ff67d9f36b67	1327	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<>	157:ff67d9f36b67	1328	}
<>	157:ff67d9f36b67	1329
<>	157:ff67d9f36b67	1330	/**
<>	157:ff67d9f36b67	1331	* @brief Get Channel 6 transfer complete flag.
<>	157:ff67d9f36b67	1332	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<>	157:ff67d9f36b67	1333	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1334	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1335	*/
<>	157:ff67d9f36b67	1336	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1337	{
<>	157:ff67d9f36b67	1338	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<>	157:ff67d9f36b67	1339	}
<>	157:ff67d9f36b67	1340
<>	157:ff67d9f36b67	1341	/**
<>	157:ff67d9f36b67	1342	* @brief Get Channel 7 transfer complete flag.
<>	157:ff67d9f36b67	1343	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<>	157:ff67d9f36b67	1344	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1345	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1346	*/
<>	157:ff67d9f36b67	1347	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1348	{
<>	157:ff67d9f36b67	1349	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<>	157:ff67d9f36b67	1350	}
<>	157:ff67d9f36b67	1351
<>	157:ff67d9f36b67	1352	/**
<>	157:ff67d9f36b67	1353	* @brief Get Channel 1 half transfer flag.
<>	157:ff67d9f36b67	1354	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<>	157:ff67d9f36b67	1355	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1356	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1357	*/
<>	157:ff67d9f36b67	1358	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1359	{
<>	157:ff67d9f36b67	1360	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<>	157:ff67d9f36b67	1361	}
<>	157:ff67d9f36b67	1362
<>	157:ff67d9f36b67	1363	/**
<>	157:ff67d9f36b67	1364	* @brief Get Channel 2 half transfer flag.
<>	157:ff67d9f36b67	1365	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<>	157:ff67d9f36b67	1366	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1367	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1368	*/
<>	157:ff67d9f36b67	1369	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1370	{
<>	157:ff67d9f36b67	1371	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<>	157:ff67d9f36b67	1372	}
<>	157:ff67d9f36b67	1373
<>	157:ff67d9f36b67	1374	/**
<>	157:ff67d9f36b67	1375	* @brief Get Channel 3 half transfer flag.
<>	157:ff67d9f36b67	1376	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<>	157:ff67d9f36b67	1377	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1378	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1379	*/
<>	157:ff67d9f36b67	1380	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1381	{
<>	157:ff67d9f36b67	1382	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<>	157:ff67d9f36b67	1383	}
<>	157:ff67d9f36b67	1384
<>	157:ff67d9f36b67	1385	/**
<>	157:ff67d9f36b67	1386	* @brief Get Channel 4 half transfer flag.
<>	157:ff67d9f36b67	1387	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<>	157:ff67d9f36b67	1388	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1389	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1390	*/
<>	157:ff67d9f36b67	1391	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1392	{
<>	157:ff67d9f36b67	1393	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<>	157:ff67d9f36b67	1394	}
<>	157:ff67d9f36b67	1395
<>	157:ff67d9f36b67	1396	/**
<>	157:ff67d9f36b67	1397	* @brief Get Channel 5 half transfer flag.
<>	157:ff67d9f36b67	1398	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<>	157:ff67d9f36b67	1399	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1400	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1401	*/
<>	157:ff67d9f36b67	1402	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1403	{
<>	157:ff67d9f36b67	1404	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<>	157:ff67d9f36b67	1405	}
<>	157:ff67d9f36b67	1406
<>	157:ff67d9f36b67	1407	/**
<>	157:ff67d9f36b67	1408	* @brief Get Channel 6 half transfer flag.
<>	157:ff67d9f36b67	1409	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<>	157:ff67d9f36b67	1410	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1411	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1412	*/
<>	157:ff67d9f36b67	1413	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1414	{
<>	157:ff67d9f36b67	1415	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<>	157:ff67d9f36b67	1416	}
<>	157:ff67d9f36b67	1417
<>	157:ff67d9f36b67	1418	/**
<>	157:ff67d9f36b67	1419	* @brief Get Channel 7 half transfer flag.
<>	157:ff67d9f36b67	1420	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<>	157:ff67d9f36b67	1421	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1422	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1423	*/
<>	157:ff67d9f36b67	1424	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1425	{
<>	157:ff67d9f36b67	1426	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<>	157:ff67d9f36b67	1427	}
<>	157:ff67d9f36b67	1428
<>	157:ff67d9f36b67	1429	/**
<>	157:ff67d9f36b67	1430	* @brief Get Channel 1 transfer error flag.
<>	157:ff67d9f36b67	1431	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<>	157:ff67d9f36b67	1432	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1433	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1434	*/
<>	157:ff67d9f36b67	1435	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1436	{
<>	157:ff67d9f36b67	1437	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<>	157:ff67d9f36b67	1438	}
<>	157:ff67d9f36b67	1439
<>	157:ff67d9f36b67	1440	/**
<>	157:ff67d9f36b67	1441	* @brief Get Channel 2 transfer error flag.
<>	157:ff67d9f36b67	1442	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<>	157:ff67d9f36b67	1443	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1444	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1445	*/
<>	157:ff67d9f36b67	1446	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1447	{
<>	157:ff67d9f36b67	1448	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<>	157:ff67d9f36b67	1449	}
<>	157:ff67d9f36b67	1450
<>	157:ff67d9f36b67	1451	/**
<>	157:ff67d9f36b67	1452	* @brief Get Channel 3 transfer error flag.
<>	157:ff67d9f36b67	1453	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<>	157:ff67d9f36b67	1454	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1455	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1456	*/
<>	157:ff67d9f36b67	1457	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1458	{
<>	157:ff67d9f36b67	1459	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<>	157:ff67d9f36b67	1460	}
<>	157:ff67d9f36b67	1461
<>	157:ff67d9f36b67	1462	/**
<>	157:ff67d9f36b67	1463	* @brief Get Channel 4 transfer error flag.
<>	157:ff67d9f36b67	1464	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<>	157:ff67d9f36b67	1465	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1466	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1467	*/
<>	157:ff67d9f36b67	1468	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1469	{
<>	157:ff67d9f36b67	1470	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<>	157:ff67d9f36b67	1471	}
<>	157:ff67d9f36b67	1472
<>	157:ff67d9f36b67	1473	/**
<>	157:ff67d9f36b67	1474	* @brief Get Channel 5 transfer error flag.
<>	157:ff67d9f36b67	1475	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<>	157:ff67d9f36b67	1476	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1477	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1478	*/
<>	157:ff67d9f36b67	1479	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1480	{
<>	157:ff67d9f36b67	1481	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<>	157:ff67d9f36b67	1482	}
<>	157:ff67d9f36b67	1483
<>	157:ff67d9f36b67	1484	/**
<>	157:ff67d9f36b67	1485	* @brief Get Channel 6 transfer error flag.
<>	157:ff67d9f36b67	1486	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<>	157:ff67d9f36b67	1487	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1488	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1489	*/
<>	157:ff67d9f36b67	1490	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1491	{
<>	157:ff67d9f36b67	1492	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<>	157:ff67d9f36b67	1493	}
<>	157:ff67d9f36b67	1494
<>	157:ff67d9f36b67	1495	/**
<>	157:ff67d9f36b67	1496	* @brief Get Channel 7 transfer error flag.
<>	157:ff67d9f36b67	1497	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<>	157:ff67d9f36b67	1498	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1499	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1500	*/
<>	157:ff67d9f36b67	1501	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1502	{
<>	157:ff67d9f36b67	1503	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<>	157:ff67d9f36b67	1504	}
<>	157:ff67d9f36b67	1505
<>	157:ff67d9f36b67	1506	/**
<>	157:ff67d9f36b67	1507	* @brief Clear Channel 1 global interrupt flag.
<>	157:ff67d9f36b67	1508	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<>	157:ff67d9f36b67	1509	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1510	* @retval None
<>	157:ff67d9f36b67	1511	*/
<>	157:ff67d9f36b67	1512	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1513	{
<>	157:ff67d9f36b67	1514	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
<>	157:ff67d9f36b67	1515	}
<>	157:ff67d9f36b67	1516
<>	157:ff67d9f36b67	1517	/**
<>	157:ff67d9f36b67	1518	* @brief Clear Channel 2 global interrupt flag.
<>	157:ff67d9f36b67	1519	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<>	157:ff67d9f36b67	1520	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1521	* @retval None
<>	157:ff67d9f36b67	1522	*/
<>	157:ff67d9f36b67	1523	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1524	{
<>	157:ff67d9f36b67	1525	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
<>	157:ff67d9f36b67	1526	}
<>	157:ff67d9f36b67	1527
<>	157:ff67d9f36b67	1528	/**
<>	157:ff67d9f36b67	1529	* @brief Clear Channel 3 global interrupt flag.
<>	157:ff67d9f36b67	1530	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<>	157:ff67d9f36b67	1531	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1532	* @retval None
<>	157:ff67d9f36b67	1533	*/
<>	157:ff67d9f36b67	1534	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1535	{
<>	157:ff67d9f36b67	1536	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
<>	157:ff67d9f36b67	1537	}
<>	157:ff67d9f36b67	1538
<>	157:ff67d9f36b67	1539	/**
<>	157:ff67d9f36b67	1540	* @brief Clear Channel 4 global interrupt flag.
<>	157:ff67d9f36b67	1541	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<>	157:ff67d9f36b67	1542	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1543	* @retval None
<>	157:ff67d9f36b67	1544	*/
<>	157:ff67d9f36b67	1545	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1546	{
<>	157:ff67d9f36b67	1547	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
<>	157:ff67d9f36b67	1548	}
<>	157:ff67d9f36b67	1549
<>	157:ff67d9f36b67	1550	/**
<>	157:ff67d9f36b67	1551	* @brief Clear Channel 5 global interrupt flag.
<>	157:ff67d9f36b67	1552	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<>	157:ff67d9f36b67	1553	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1554	* @retval None
<>	157:ff67d9f36b67	1555	*/
<>	157:ff67d9f36b67	1556	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1557	{
<>	157:ff67d9f36b67	1558	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
<>	157:ff67d9f36b67	1559	}
<>	157:ff67d9f36b67	1560
<>	157:ff67d9f36b67	1561	/**
<>	157:ff67d9f36b67	1562	* @brief Clear Channel 6 global interrupt flag.
<>	157:ff67d9f36b67	1563	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<>	157:ff67d9f36b67	1564	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1565	* @retval None
<>	157:ff67d9f36b67	1566	*/
<>	157:ff67d9f36b67	1567	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1568	{
<>	157:ff67d9f36b67	1569	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
<>	157:ff67d9f36b67	1570	}
<>	157:ff67d9f36b67	1571
<>	157:ff67d9f36b67	1572	/**
<>	157:ff67d9f36b67	1573	* @brief Clear Channel 7 global interrupt flag.
<>	157:ff67d9f36b67	1574	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<>	157:ff67d9f36b67	1575	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1576	* @retval None
<>	157:ff67d9f36b67	1577	*/
<>	157:ff67d9f36b67	1578	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1579	{
<>	157:ff67d9f36b67	1580	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
<>	157:ff67d9f36b67	1581	}
<>	157:ff67d9f36b67	1582
<>	157:ff67d9f36b67	1583	/**
<>	157:ff67d9f36b67	1584	* @brief Clear Channel 1 transfer complete flag.
<>	157:ff67d9f36b67	1585	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<>	157:ff67d9f36b67	1586	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1587	* @retval None
<>	157:ff67d9f36b67	1588	*/
<>	157:ff67d9f36b67	1589	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1590	{
<>	157:ff67d9f36b67	1591	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
<>	157:ff67d9f36b67	1592	}
<>	157:ff67d9f36b67	1593
<>	157:ff67d9f36b67	1594	/**
<>	157:ff67d9f36b67	1595	* @brief Clear Channel 2 transfer complete flag.
<>	157:ff67d9f36b67	1596	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<>	157:ff67d9f36b67	1597	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1598	* @retval None
<>	157:ff67d9f36b67	1599	*/
<>	157:ff67d9f36b67	1600	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1601	{
<>	157:ff67d9f36b67	1602	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
<>	157:ff67d9f36b67	1603	}
<>	157:ff67d9f36b67	1604
<>	157:ff67d9f36b67	1605	/**
<>	157:ff67d9f36b67	1606	* @brief Clear Channel 3 transfer complete flag.
<>	157:ff67d9f36b67	1607	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<>	157:ff67d9f36b67	1608	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1609	* @retval None
<>	157:ff67d9f36b67	1610	*/
<>	157:ff67d9f36b67	1611	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1612	{
<>	157:ff67d9f36b67	1613	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
<>	157:ff67d9f36b67	1614	}
<>	157:ff67d9f36b67	1615
<>	157:ff67d9f36b67	1616	/**
<>	157:ff67d9f36b67	1617	* @brief Clear Channel 4 transfer complete flag.
<>	157:ff67d9f36b67	1618	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<>	157:ff67d9f36b67	1619	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1620	* @retval None
<>	157:ff67d9f36b67	1621	*/
<>	157:ff67d9f36b67	1622	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1623	{
<>	157:ff67d9f36b67	1624	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
<>	157:ff67d9f36b67	1625	}
<>	157:ff67d9f36b67	1626
<>	157:ff67d9f36b67	1627	/**
<>	157:ff67d9f36b67	1628	* @brief Clear Channel 5 transfer complete flag.
<>	157:ff67d9f36b67	1629	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<>	157:ff67d9f36b67	1630	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1631	* @retval None
<>	157:ff67d9f36b67	1632	*/
<>	157:ff67d9f36b67	1633	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1634	{
<>	157:ff67d9f36b67	1635	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
<>	157:ff67d9f36b67	1636	}
<>	157:ff67d9f36b67	1637
<>	157:ff67d9f36b67	1638	/**
<>	157:ff67d9f36b67	1639	* @brief Clear Channel 6 transfer complete flag.
<>	157:ff67d9f36b67	1640	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<>	157:ff67d9f36b67	1641	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1642	* @retval None
<>	157:ff67d9f36b67	1643	*/
<>	157:ff67d9f36b67	1644	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1645	{
<>	157:ff67d9f36b67	1646	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
<>	157:ff67d9f36b67	1647	}
<>	157:ff67d9f36b67	1648
<>	157:ff67d9f36b67	1649	/**
<>	157:ff67d9f36b67	1650	* @brief Clear Channel 7 transfer complete flag.
<>	157:ff67d9f36b67	1651	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<>	157:ff67d9f36b67	1652	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1653	* @retval None
<>	157:ff67d9f36b67	1654	*/
<>	157:ff67d9f36b67	1655	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1656	{
<>	157:ff67d9f36b67	1657	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
<>	157:ff67d9f36b67	1658	}
<>	157:ff67d9f36b67	1659
<>	157:ff67d9f36b67	1660	/**
<>	157:ff67d9f36b67	1661	* @brief Clear Channel 1 half transfer flag.
<>	157:ff67d9f36b67	1662	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<>	157:ff67d9f36b67	1663	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1664	* @retval None
<>	157:ff67d9f36b67	1665	*/
<>	157:ff67d9f36b67	1666	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1667	{
<>	157:ff67d9f36b67	1668	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
<>	157:ff67d9f36b67	1669	}
<>	157:ff67d9f36b67	1670
<>	157:ff67d9f36b67	1671	/**
<>	157:ff67d9f36b67	1672	* @brief Clear Channel 2 half transfer flag.
<>	157:ff67d9f36b67	1673	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<>	157:ff67d9f36b67	1674	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1675	* @retval None
<>	157:ff67d9f36b67	1676	*/
<>	157:ff67d9f36b67	1677	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1678	{
<>	157:ff67d9f36b67	1679	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
<>	157:ff67d9f36b67	1680	}
<>	157:ff67d9f36b67	1681
<>	157:ff67d9f36b67	1682	/**
<>	157:ff67d9f36b67	1683	* @brief Clear Channel 3 half transfer flag.
<>	157:ff67d9f36b67	1684	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<>	157:ff67d9f36b67	1685	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1686	* @retval None
<>	157:ff67d9f36b67	1687	*/
<>	157:ff67d9f36b67	1688	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1689	{
<>	157:ff67d9f36b67	1690	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
<>	157:ff67d9f36b67	1691	}
<>	157:ff67d9f36b67	1692
<>	157:ff67d9f36b67	1693	/**
<>	157:ff67d9f36b67	1694	* @brief Clear Channel 4 half transfer flag.
<>	157:ff67d9f36b67	1695	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<>	157:ff67d9f36b67	1696	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1697	* @retval None
<>	157:ff67d9f36b67	1698	*/
<>	157:ff67d9f36b67	1699	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1700	{
<>	157:ff67d9f36b67	1701	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
<>	157:ff67d9f36b67	1702	}
<>	157:ff67d9f36b67	1703
<>	157:ff67d9f36b67	1704	/**
<>	157:ff67d9f36b67	1705	* @brief Clear Channel 5 half transfer flag.
<>	157:ff67d9f36b67	1706	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<>	157:ff67d9f36b67	1707	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1708	* @retval None
<>	157:ff67d9f36b67	1709	*/
<>	157:ff67d9f36b67	1710	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1711	{
<>	157:ff67d9f36b67	1712	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
<>	157:ff67d9f36b67	1713	}
<>	157:ff67d9f36b67	1714
<>	157:ff67d9f36b67	1715	/**
<>	157:ff67d9f36b67	1716	* @brief Clear Channel 6 half transfer flag.
<>	157:ff67d9f36b67	1717	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<>	157:ff67d9f36b67	1718	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1719	* @retval None
<>	157:ff67d9f36b67	1720	*/
<>	157:ff67d9f36b67	1721	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1722	{
<>	157:ff67d9f36b67	1723	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
<>	157:ff67d9f36b67	1724	}
<>	157:ff67d9f36b67	1725
<>	157:ff67d9f36b67	1726	/**
<>	157:ff67d9f36b67	1727	* @brief Clear Channel 7 half transfer flag.
<>	157:ff67d9f36b67	1728	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<>	157:ff67d9f36b67	1729	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1730	* @retval None
<>	157:ff67d9f36b67	1731	*/
<>	157:ff67d9f36b67	1732	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1733	{
<>	157:ff67d9f36b67	1734	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
<>	157:ff67d9f36b67	1735	}
<>	157:ff67d9f36b67	1736
<>	157:ff67d9f36b67	1737	/**
<>	157:ff67d9f36b67	1738	* @brief Clear Channel 1 transfer error flag.
<>	157:ff67d9f36b67	1739	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<>	157:ff67d9f36b67	1740	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1741	* @retval None
<>	157:ff67d9f36b67	1742	*/
<>	157:ff67d9f36b67	1743	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1744	{
<>	157:ff67d9f36b67	1745	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
<>	157:ff67d9f36b67	1746	}
<>	157:ff67d9f36b67	1747
<>	157:ff67d9f36b67	1748	/**
<>	157:ff67d9f36b67	1749	* @brief Clear Channel 2 transfer error flag.
<>	157:ff67d9f36b67	1750	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<>	157:ff67d9f36b67	1751	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1752	* @retval None
<>	157:ff67d9f36b67	1753	*/
<>	157:ff67d9f36b67	1754	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1755	{
<>	157:ff67d9f36b67	1756	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
<>	157:ff67d9f36b67	1757	}
<>	157:ff67d9f36b67	1758
<>	157:ff67d9f36b67	1759	/**
<>	157:ff67d9f36b67	1760	* @brief Clear Channel 3 transfer error flag.
<>	157:ff67d9f36b67	1761	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<>	157:ff67d9f36b67	1762	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1763	* @retval None
<>	157:ff67d9f36b67	1764	*/
<>	157:ff67d9f36b67	1765	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1766	{
<>	157:ff67d9f36b67	1767	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
<>	157:ff67d9f36b67	1768	}
<>	157:ff67d9f36b67	1769
<>	157:ff67d9f36b67	1770	/**
<>	157:ff67d9f36b67	1771	* @brief Clear Channel 4 transfer error flag.
<>	157:ff67d9f36b67	1772	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<>	157:ff67d9f36b67	1773	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1774	* @retval None
<>	157:ff67d9f36b67	1775	*/
<>	157:ff67d9f36b67	1776	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1777	{
<>	157:ff67d9f36b67	1778	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
<>	157:ff67d9f36b67	1779	}
<>	157:ff67d9f36b67	1780
<>	157:ff67d9f36b67	1781	/**
<>	157:ff67d9f36b67	1782	* @brief Clear Channel 5 transfer error flag.
<>	157:ff67d9f36b67	1783	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<>	157:ff67d9f36b67	1784	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1785	* @retval None
<>	157:ff67d9f36b67	1786	*/
<>	157:ff67d9f36b67	1787	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1788	{
<>	157:ff67d9f36b67	1789	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
<>	157:ff67d9f36b67	1790	}
<>	157:ff67d9f36b67	1791
<>	157:ff67d9f36b67	1792	/**
<>	157:ff67d9f36b67	1793	* @brief Clear Channel 6 transfer error flag.
<>	157:ff67d9f36b67	1794	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<>	157:ff67d9f36b67	1795	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1796	* @retval None
<>	157:ff67d9f36b67	1797	*/
<>	157:ff67d9f36b67	1798	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1799	{
<>	157:ff67d9f36b67	1800	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
<>	157:ff67d9f36b67	1801	}
<>	157:ff67d9f36b67	1802
<>	157:ff67d9f36b67	1803	/**
<>	157:ff67d9f36b67	1804	* @brief Clear Channel 7 transfer error flag.
<>	157:ff67d9f36b67	1805	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<>	157:ff67d9f36b67	1806	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1807	* @retval None
<>	157:ff67d9f36b67	1808	*/
<>	157:ff67d9f36b67	1809	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<>	157:ff67d9f36b67	1810	{
<>	157:ff67d9f36b67	1811	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
<>	157:ff67d9f36b67	1812	}
<>	157:ff67d9f36b67	1813
<>	157:ff67d9f36b67	1814	/**
<>	157:ff67d9f36b67	1815	* @}
<>	157:ff67d9f36b67	1816	*/
<>	157:ff67d9f36b67	1817
<>	157:ff67d9f36b67	1818	/** @defgroup DMA_LL_EF_IT_Management IT_Management
<>	157:ff67d9f36b67	1819	* @{
<>	157:ff67d9f36b67	1820	*/
<>	157:ff67d9f36b67	1821	/**
<>	157:ff67d9f36b67	1822	* @brief Enable Transfer complete interrupt.
<>	157:ff67d9f36b67	1823	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<>	157:ff67d9f36b67	1824	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1825	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1826	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1827	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1828	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1829	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1830	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1831	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1832	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1833	* @retval None
<>	157:ff67d9f36b67	1834	*/
<>	157:ff67d9f36b67	1835	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1836	{
<>	157:ff67d9f36b67	1837	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	157:ff67d9f36b67	1838	}
<>	157:ff67d9f36b67	1839
<>	157:ff67d9f36b67	1840	/**
<>	157:ff67d9f36b67	1841	* @brief Enable Half transfer interrupt.
<>	157:ff67d9f36b67	1842	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<>	157:ff67d9f36b67	1843	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1844	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1845	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1846	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1847	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1848	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1849	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1850	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1851	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1852	* @retval None
<>	157:ff67d9f36b67	1853	*/
<>	157:ff67d9f36b67	1854	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1855	{
<>	157:ff67d9f36b67	1856	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	157:ff67d9f36b67	1857	}
<>	157:ff67d9f36b67	1858
<>	157:ff67d9f36b67	1859	/**
<>	157:ff67d9f36b67	1860	* @brief Enable Transfer error interrupt.
<>	157:ff67d9f36b67	1861	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<>	157:ff67d9f36b67	1862	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1863	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1864	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1865	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1866	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1867	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1868	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1869	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1870	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1871	* @retval None
<>	157:ff67d9f36b67	1872	*/
<>	157:ff67d9f36b67	1873	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1874	{
<>	157:ff67d9f36b67	1875	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	157:ff67d9f36b67	1876	}
<>	157:ff67d9f36b67	1877
<>	157:ff67d9f36b67	1878	/**
<>	157:ff67d9f36b67	1879	* @brief Disable Transfer complete interrupt.
<>	157:ff67d9f36b67	1880	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<>	157:ff67d9f36b67	1881	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1882	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1883	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1884	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1885	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1886	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1887	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1888	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1889	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1890	* @retval None
<>	157:ff67d9f36b67	1891	*/
<>	157:ff67d9f36b67	1892	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1893	{
<>	157:ff67d9f36b67	1894	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	157:ff67d9f36b67	1895	}
<>	157:ff67d9f36b67	1896
<>	157:ff67d9f36b67	1897	/**
<>	157:ff67d9f36b67	1898	* @brief Disable Half transfer interrupt.
<>	157:ff67d9f36b67	1899	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<>	157:ff67d9f36b67	1900	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1901	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1902	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1903	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1904	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1905	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1906	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1907	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1908	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1909	* @retval None
<>	157:ff67d9f36b67	1910	*/
<>	157:ff67d9f36b67	1911	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1912	{
<>	157:ff67d9f36b67	1913	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	157:ff67d9f36b67	1914	}
<>	157:ff67d9f36b67	1915
<>	157:ff67d9f36b67	1916	/**
<>	157:ff67d9f36b67	1917	* @brief Disable Transfer error interrupt.
<>	157:ff67d9f36b67	1918	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<>	157:ff67d9f36b67	1919	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1920	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1921	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1922	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1923	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1924	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1925	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1926	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1927	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1928	* @retval None
<>	157:ff67d9f36b67	1929	*/
<>	157:ff67d9f36b67	1930	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1931	{
<>	157:ff67d9f36b67	1932	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	157:ff67d9f36b67	1933	}
<>	157:ff67d9f36b67	1934
<>	157:ff67d9f36b67	1935	/**
<>	157:ff67d9f36b67	1936	* @brief Check if Transfer complete Interrupt is enabled.
<>	157:ff67d9f36b67	1937	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<>	157:ff67d9f36b67	1938	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1939	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1940	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1941	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1942	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1943	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1944	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1945	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1946	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1947	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1948	*/
<>	157:ff67d9f36b67	1949	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1950	{
<>	157:ff67d9f36b67	1951	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	1952	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<>	157:ff67d9f36b67	1953	}
<>	157:ff67d9f36b67	1954
<>	157:ff67d9f36b67	1955	/**
<>	157:ff67d9f36b67	1956	* @brief Check if Half transfer Interrupt is enabled.
<>	157:ff67d9f36b67	1957	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<>	157:ff67d9f36b67	1958	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1959	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1960	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1961	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1962	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1963	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1964	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1965	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1966	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1967	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1968	*/
<>	157:ff67d9f36b67	1969	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1970	{
<>	157:ff67d9f36b67	1971	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	1972	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<>	157:ff67d9f36b67	1973	}
<>	157:ff67d9f36b67	1974
<>	157:ff67d9f36b67	1975	/**
<>	157:ff67d9f36b67	1976	* @brief Check if Transfer error Interrupt is enabled.
<>	157:ff67d9f36b67	1977	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<>	157:ff67d9f36b67	1978	* @param DMAx DMAx Instance
<>	157:ff67d9f36b67	1979	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1980	* @arg @ref LL_DMA_CHANNEL_1
<>	157:ff67d9f36b67	1981	* @arg @ref LL_DMA_CHANNEL_2
<>	157:ff67d9f36b67	1982	* @arg @ref LL_DMA_CHANNEL_3
<>	157:ff67d9f36b67	1983	* @arg @ref LL_DMA_CHANNEL_4
<>	157:ff67d9f36b67	1984	* @arg @ref LL_DMA_CHANNEL_5
<>	157:ff67d9f36b67	1985	* @arg @ref LL_DMA_CHANNEL_6
<>	157:ff67d9f36b67	1986	* @arg @ref LL_DMA_CHANNEL_7
<>	157:ff67d9f36b67	1987	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1988	*/
<>	157:ff67d9f36b67	1989	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	157:ff67d9f36b67	1990	{
<>	157:ff67d9f36b67	1991	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	157:ff67d9f36b67	1992	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<>	157:ff67d9f36b67	1993	}
<>	157:ff67d9f36b67	1994
<>	157:ff67d9f36b67	1995	/**
<>	157:ff67d9f36b67	1996	* @}
<>	157:ff67d9f36b67	1997	*/
<>	157:ff67d9f36b67	1998
<>	157:ff67d9f36b67	1999	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	2000	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<>	157:ff67d9f36b67	2001	* @{
<>	157:ff67d9f36b67	2002	*/
<>	157:ff67d9f36b67	2003
<>	157:ff67d9f36b67	2004	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
<>	157:ff67d9f36b67	2005	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<>	157:ff67d9f36b67	2006	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<>	157:ff67d9f36b67	2007
<>	157:ff67d9f36b67	2008	/**
<>	157:ff67d9f36b67	2009	* @}
<>	157:ff67d9f36b67	2010	*/
<>	157:ff67d9f36b67	2011	#endif /* USE_FULL_LL_DRIVER */
<>	157:ff67d9f36b67	2012
<>	157:ff67d9f36b67	2013	/**
<>	157:ff67d9f36b67	2014	* @}
<>	157:ff67d9f36b67	2015	*/
<>	157:ff67d9f36b67	2016
<>	157:ff67d9f36b67	2017	/**
<>	157:ff67d9f36b67	2018	* @}
<>	157:ff67d9f36b67	2019	*/
<>	157:ff67d9f36b67	2020
<>	157:ff67d9f36b67	2021	#endif /* DMA1 \|\| DMA2 */
<>	157:ff67d9f36b67	2022
<>	157:ff67d9f36b67	2023	/**
<>	157:ff67d9f36b67	2024	* @}
<>	157:ff67d9f36b67	2025	*/
<>	157:ff67d9f36b67	2026
<>	157:ff67d9f36b67	2027	#ifdef __cplusplus
<>	157:ff67d9f36b67	2028	}
<>	157:ff67d9f36b67	2029	#endif
<>	157:ff67d9f36b67	2030
<>	157:ff67d9f36b67	2031	#endif /* __STM32F3xx_LL_DMA_H */
<>	157:ff67d9f36b67	2032
<>	157:ff67d9f36b67	2033	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/