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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
181:57724642e740 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief CORTEX HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 8 * + Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 9 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15
<> 144:ef7eb2e8f9f7 16 [..]
<> 144:ef7eb2e8f9f7 17 *** How to configure Interrupts using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 18 ===========================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 21 The Cortex-M4 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
<> 144:ef7eb2e8f9f7 24 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
<> 144:ef7eb2e8f9f7 25 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 28 The pending IRQ priority will be managed only by the sub priority.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 -@- IRQ priority order (sorted by highest to lowest priority):
<> 144:ef7eb2e8f9f7 31 (+@) Lowest pre-emption priority
<> 144:ef7eb2e8f9f7 32 (+@) Lowest sub priority
<> 144:ef7eb2e8f9f7 33 (+@) Lowest hardware priority (IRQ number)
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 [..]
<> 144:ef7eb2e8f9f7 36 *** How to configure SysTick using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 37 ========================================================
<> 144:ef7eb2e8f9f7 38 [..]
<> 144:ef7eb2e8f9f7 39 Setup SysTick Timer for time base.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 42 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 43 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 144:ef7eb2e8f9f7 44 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
<> 144:ef7eb2e8f9f7 45 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 46 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 47 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 48 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
<> 144:ef7eb2e8f9f7 51 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 144:ef7eb2e8f9f7 52 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
<> 144:ef7eb2e8f9f7 53 inside the stm32l4xx_hal_cortex.h file.
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 56 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 57 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 62 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 63 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 @endverbatim
<> 144:ef7eb2e8f9f7 66 ******************************************************************************
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 The table below gives the allowed values of the pre-emption priority and subpriority according
<> 144:ef7eb2e8f9f7 69 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 72 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
<> 144:ef7eb2e8f9f7 73 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 74 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
<> 144:ef7eb2e8f9f7 75 | | | 4 bits for subpriority
<> 144:ef7eb2e8f9f7 76 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 77 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
<> 144:ef7eb2e8f9f7 78 | | | 3 bits for subpriority
<> 144:ef7eb2e8f9f7 79 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 80 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 81 | | | 2 bits for subpriority
<> 144:ef7eb2e8f9f7 82 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 83 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 84 | | | 1 bit for subpriority
<> 144:ef7eb2e8f9f7 85 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 86 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 87 | | | 0 bit for subpriority
<> 144:ef7eb2e8f9f7 88 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 ******************************************************************************
<> 144:ef7eb2e8f9f7 91 * @attention
<> 144:ef7eb2e8f9f7 92 *
AnnaBridge 167:e84263d55307 93 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 96 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 97 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 98 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 99 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 100 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 101 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 102 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 103 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 104 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 107 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 108 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 109 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 110 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 111 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 112 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 113 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 114 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 115 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 ******************************************************************************
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** @addtogroup CORTEX
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 134 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 135 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 136 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @addtogroup CORTEX_Exported_Functions
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @addtogroup CORTEX_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 146 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 147 *
<> 144:ef7eb2e8f9f7 148 @verbatim
<> 144:ef7eb2e8f9f7 149 ==============================================================================
<> 144:ef7eb2e8f9f7 150 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 151 ==============================================================================
<> 144:ef7eb2e8f9f7 152 [..]
<> 144:ef7eb2e8f9f7 153 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 154 SysTick functionalities
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 @endverbatim
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief Set the priority grouping field (pre-emption priority and subpriority)
<> 144:ef7eb2e8f9f7 163 * using the required unlock sequence.
<> 144:ef7eb2e8f9f7 164 * @param PriorityGroup: The priority grouping bits length.
<> 144:ef7eb2e8f9f7 165 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 166 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 167 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 168 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 169 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 170 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 171 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 172 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 173 * 1 bit for subpriority
<> 144:ef7eb2e8f9f7 174 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 175 * 0 bit for subpriority
<> 144:ef7eb2e8f9f7 176 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 177 * The pending IRQ priority will be managed only by the subpriority.
<> 144:ef7eb2e8f9f7 178 * @retval None
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 /* Check the parameters */
<> 144:ef7eb2e8f9f7 183 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
<> 144:ef7eb2e8f9f7 186 NVIC_SetPriorityGrouping(PriorityGroup);
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @brief Set the priority of an interrupt.
<> 144:ef7eb2e8f9f7 191 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 192 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 193 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 194 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 195 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 196 * A lower priority value indicates a higher priority
<> 144:ef7eb2e8f9f7 197 * @param SubPriority: the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 198 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 199 * A lower priority value indicates a higher priority.
<> 144:ef7eb2e8f9f7 200 * @retval None
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 uint32_t prioritygroup = 0x00;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Check the parameters */
<> 144:ef7eb2e8f9f7 207 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
<> 144:ef7eb2e8f9f7 208 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 prioritygroup = NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 217 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 218 * function should be called before.
<> 144:ef7eb2e8f9f7 219 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 220 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 221 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 222 * @retval None
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* Check the parameters */
<> 144:ef7eb2e8f9f7 227 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 230 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 235 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 236 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 237 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 238 * @retval None
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 /* Check the parameters */
<> 144:ef7eb2e8f9f7 243 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 246 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @brief Initiate a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 251 * @retval None
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 /* System Reset */
<> 144:ef7eb2e8f9f7 256 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
<> 144:ef7eb2e8f9f7 261 * Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 262 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 263 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 264 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @}
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /** @addtogroup CORTEX_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 275 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 276 *
<> 144:ef7eb2e8f9f7 277 @verbatim
<> 144:ef7eb2e8f9f7 278 ==============================================================================
<> 144:ef7eb2e8f9f7 279 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 280 ==============================================================================
<> 144:ef7eb2e8f9f7 281 [..]
<> 144:ef7eb2e8f9f7 282 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 283 (NVIC, SYSTICK, MPU) functionalities.
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 @endverbatim
<> 144:ef7eb2e8f9f7 287 * @{
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
<> 144:ef7eb2e8f9f7 292 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 uint32_t HAL_NVIC_GetPriorityGrouping(void)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 /* Get the PRIGROUP[10:8] field value */
<> 144:ef7eb2e8f9f7 297 return NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @brief Get the priority of an interrupt.
<> 144:ef7eb2e8f9f7 302 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 303 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 304 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 305 * @param PriorityGroup: the priority grouping bits length.
<> 144:ef7eb2e8f9f7 306 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 307 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 308 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 309 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 310 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 311 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 312 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 313 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 314 * 1 bit for subpriority
<> 144:ef7eb2e8f9f7 315 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 316 * 0 bit for subpriority
<> 144:ef7eb2e8f9f7 317 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
<> 144:ef7eb2e8f9f7 318 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
<> 144:ef7eb2e8f9f7 319 * @retval None
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Check the parameters */
<> 144:ef7eb2e8f9f7 324 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 325 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 326 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Set Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 331 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 332 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 333 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 334 * @retval None
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 337 {
AnnaBridge 181:57724642e740 338 /* Check the parameters */
AnnaBridge 181:57724642e740 339 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
AnnaBridge 181:57724642e740 340
<> 144:ef7eb2e8f9f7 341 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 342 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @brief Get Pending Interrupt (read the pending register in the NVIC
<> 144:ef7eb2e8f9f7 347 * and return the pending bit for the specified interrupt).
<> 144:ef7eb2e8f9f7 348 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 349 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 350 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 351 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 352 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 355 {
AnnaBridge 181:57724642e740 356 /* Check the parameters */
AnnaBridge 181:57724642e740 357 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
AnnaBridge 181:57724642e740 358
<> 144:ef7eb2e8f9f7 359 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 360 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @brief Clear the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 365 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 366 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 367 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 371 {
AnnaBridge 181:57724642e740 372 /* Check the parameters */
AnnaBridge 181:57724642e740 373 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
AnnaBridge 181:57724642e740 374
<> 144:ef7eb2e8f9f7 375 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 376 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
<> 144:ef7eb2e8f9f7 381 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 382 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 383 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 384 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 385 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Return 1 if active else 0 */
<> 144:ef7eb2e8f9f7 390 return NVIC_GetActive(IRQn);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @brief Configure the SysTick clock source.
<> 144:ef7eb2e8f9f7 395 * @param CLKSource: specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 396 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 397 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 398 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 399 * @retval None
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 /* Check the parameters */
<> 144:ef7eb2e8f9f7 404 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 405 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409 else
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief Handle SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 417 * @retval None
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 426 * @retval None
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 431 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 436 /**
AnnaBridge 181:57724642e740 437 * @brief Disable the MPU.
AnnaBridge 181:57724642e740 438 * @retval None
AnnaBridge 181:57724642e740 439 */
AnnaBridge 181:57724642e740 440 void HAL_MPU_Disable(void)
AnnaBridge 181:57724642e740 441 {
AnnaBridge 181:57724642e740 442 /* Make sure outstanding transfers are done */
AnnaBridge 181:57724642e740 443 __DMB();
AnnaBridge 181:57724642e740 444
AnnaBridge 181:57724642e740 445 /* Disable fault exceptions */
AnnaBridge 181:57724642e740 446 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 181:57724642e740 447
AnnaBridge 181:57724642e740 448 /* Disable the MPU and clear the control register*/
AnnaBridge 181:57724642e740 449 MPU->CTRL = 0U;
AnnaBridge 181:57724642e740 450 }
AnnaBridge 181:57724642e740 451
AnnaBridge 181:57724642e740 452 /**
AnnaBridge 181:57724642e740 453 * @brief Enable the MPU.
AnnaBridge 181:57724642e740 454 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
AnnaBridge 181:57724642e740 455 * NMI, FAULTMASK and privileged accessto the default memory
AnnaBridge 181:57724642e740 456 * This parameter can be one of the following values:
AnnaBridge 181:57724642e740 457 * @arg MPU_HFNMI_PRIVDEF_NONE
AnnaBridge 181:57724642e740 458 * @arg MPU_HARDFAULT_NMI
AnnaBridge 181:57724642e740 459 * @arg MPU_PRIVILEGED_DEFAULT
AnnaBridge 181:57724642e740 460 * @arg MPU_HFNMI_PRIVDEF
AnnaBridge 181:57724642e740 461 * @retval None
AnnaBridge 181:57724642e740 462 */
AnnaBridge 181:57724642e740 463 void HAL_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 181:57724642e740 464 {
AnnaBridge 181:57724642e740 465 /* Enable the MPU */
AnnaBridge 181:57724642e740 466 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 181:57724642e740 467
AnnaBridge 181:57724642e740 468 /* Enable fault exceptions */
AnnaBridge 181:57724642e740 469 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 181:57724642e740 470
AnnaBridge 181:57724642e740 471 /* Ensure MPU settings take effects */
AnnaBridge 181:57724642e740 472 __DSB();
AnnaBridge 181:57724642e740 473 __ISB();
AnnaBridge 181:57724642e740 474 }
AnnaBridge 181:57724642e740 475
AnnaBridge 181:57724642e740 476 /**
<> 144:ef7eb2e8f9f7 477 * @brief Initialize and configure the Region and the memory to be protected.
<> 144:ef7eb2e8f9f7 478 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 479 * the initialization and configuration information.
<> 144:ef7eb2e8f9f7 480 * @retval None
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 /* Check the parameters */
<> 144:ef7eb2e8f9f7 485 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
<> 144:ef7eb2e8f9f7 486 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Set the Region number */
<> 144:ef7eb2e8f9f7 489 MPU->RNR = MPU_Init->Number;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 if ((MPU_Init->Enable) != RESET)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 /* Check the parameters */
<> 144:ef7eb2e8f9f7 494 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
<> 144:ef7eb2e8f9f7 495 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
<> 144:ef7eb2e8f9f7 496 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
<> 144:ef7eb2e8f9f7 497 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
<> 144:ef7eb2e8f9f7 498 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
<> 144:ef7eb2e8f9f7 499 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
<> 144:ef7eb2e8f9f7 500 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
<> 144:ef7eb2e8f9f7 501 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 MPU->RBAR = MPU_Init->BaseAddress;
<> 144:ef7eb2e8f9f7 504 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
<> 144:ef7eb2e8f9f7 505 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
<> 144:ef7eb2e8f9f7 506 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
<> 144:ef7eb2e8f9f7 507 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
<> 144:ef7eb2e8f9f7 508 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
<> 144:ef7eb2e8f9f7 509 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
<> 144:ef7eb2e8f9f7 510 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
<> 144:ef7eb2e8f9f7 511 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
<> 144:ef7eb2e8f9f7 512 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514 else
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 MPU->RBAR = 0x00;
<> 144:ef7eb2e8f9f7 517 MPU->RASR = 0x00;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @}
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @}
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @}
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /**
<> 144:ef7eb2e8f9f7 536 * @}
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/