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mbed library sources. Supersedes mbed-src.

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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_cortex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief CORTEX HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 10 * + Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 *** How to configure Interrupts using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 20 ===========================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 23 The Cortex-M4 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
<> 144:ef7eb2e8f9f7 26 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
<> 144:ef7eb2e8f9f7 27 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 30 The pending IRQ priority will be managed only by the sub priority.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 -@- IRQ priority order (sorted by highest to lowest priority):
<> 144:ef7eb2e8f9f7 33 (+@) Lowest pre-emption priority
<> 144:ef7eb2e8f9f7 34 (+@) Lowest sub priority
<> 144:ef7eb2e8f9f7 35 (+@) Lowest hardware priority (IRQ number)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 *** How to configure SysTick using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 39 ========================================================
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 Setup SysTick Timer for time base.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 44 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 45 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 144:ef7eb2e8f9f7 46 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
<> 144:ef7eb2e8f9f7 47 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 48 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 49 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 50 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
<> 144:ef7eb2e8f9f7 53 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 144:ef7eb2e8f9f7 54 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
<> 144:ef7eb2e8f9f7 55 inside the stm32l4xx_hal_cortex.h file.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 58 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 59 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 64 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 65 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 The table below gives the allowed values of the pre-emption priority and subpriority according
<> 144:ef7eb2e8f9f7 71 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 74 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
<> 144:ef7eb2e8f9f7 75 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 76 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
<> 144:ef7eb2e8f9f7 77 | | | 4 bits for subpriority
<> 144:ef7eb2e8f9f7 78 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 79 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
<> 144:ef7eb2e8f9f7 80 | | | 3 bits for subpriority
<> 144:ef7eb2e8f9f7 81 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 82 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 83 | | | 2 bits for subpriority
<> 144:ef7eb2e8f9f7 84 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 85 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 86 | | | 1 bit for subpriority
<> 144:ef7eb2e8f9f7 87 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 88 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 89 | | | 0 bit for subpriority
<> 144:ef7eb2e8f9f7 90 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 ******************************************************************************
<> 144:ef7eb2e8f9f7 93 * @attention
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 98 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 99 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 100 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 101 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 102 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 103 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 104 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 105 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 106 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 107 *
<> 144:ef7eb2e8f9f7 108 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 109 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 110 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 111 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 112 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 113 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 114 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 115 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 116 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 117 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 118 *
<> 144:ef7eb2e8f9f7 119 ******************************************************************************
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 126 * @{
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @addtogroup CORTEX
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 136 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @addtogroup CORTEX_Exported_Functions
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @addtogroup CORTEX_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 148 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 149 *
<> 144:ef7eb2e8f9f7 150 @verbatim
<> 144:ef7eb2e8f9f7 151 ==============================================================================
<> 144:ef7eb2e8f9f7 152 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 153 ==============================================================================
<> 144:ef7eb2e8f9f7 154 [..]
<> 144:ef7eb2e8f9f7 155 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 156 SysTick functionalities
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 @endverbatim
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief Set the priority grouping field (pre-emption priority and subpriority)
<> 144:ef7eb2e8f9f7 165 * using the required unlock sequence.
<> 144:ef7eb2e8f9f7 166 * @param PriorityGroup: The priority grouping bits length.
<> 144:ef7eb2e8f9f7 167 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 168 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 169 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 170 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 171 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 172 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 173 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 174 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 175 * 1 bit for subpriority
<> 144:ef7eb2e8f9f7 176 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 177 * 0 bit for subpriority
<> 144:ef7eb2e8f9f7 178 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 179 * The pending IRQ priority will be managed only by the subpriority.
<> 144:ef7eb2e8f9f7 180 * @retval None
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 /* Check the parameters */
<> 144:ef7eb2e8f9f7 185 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
<> 144:ef7eb2e8f9f7 188 NVIC_SetPriorityGrouping(PriorityGroup);
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief Set the priority of an interrupt.
<> 144:ef7eb2e8f9f7 193 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 194 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 195 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 196 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 197 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 198 * A lower priority value indicates a higher priority
<> 144:ef7eb2e8f9f7 199 * @param SubPriority: the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 200 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 201 * A lower priority value indicates a higher priority.
<> 144:ef7eb2e8f9f7 202 * @retval None
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 uint32_t prioritygroup = 0x00;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Check the parameters */
<> 144:ef7eb2e8f9f7 209 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
<> 144:ef7eb2e8f9f7 210 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 prioritygroup = NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 219 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 220 * function should be called before.
<> 144:ef7eb2e8f9f7 221 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 222 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 223 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 224 * @retval None
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 /* Check the parameters */
<> 144:ef7eb2e8f9f7 229 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 232 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 237 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 238 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 239 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 240 * @retval None
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 /* Check the parameters */
<> 144:ef7eb2e8f9f7 245 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 248 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @brief Initiate a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 253 * @retval None
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 /* System Reset */
<> 144:ef7eb2e8f9f7 258 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 259 }
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
<> 144:ef7eb2e8f9f7 263 * Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 264 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 265 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 266 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @}
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /** @addtogroup CORTEX_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 277 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 278 *
<> 144:ef7eb2e8f9f7 279 @verbatim
<> 144:ef7eb2e8f9f7 280 ==============================================================================
<> 144:ef7eb2e8f9f7 281 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 282 ==============================================================================
<> 144:ef7eb2e8f9f7 283 [..]
<> 144:ef7eb2e8f9f7 284 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 285 (NVIC, SYSTICK, MPU) functionalities.
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 @endverbatim
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
<> 144:ef7eb2e8f9f7 294 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 uint32_t HAL_NVIC_GetPriorityGrouping(void)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Get the PRIGROUP[10:8] field value */
<> 144:ef7eb2e8f9f7 299 return NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @brief Get the priority of an interrupt.
<> 144:ef7eb2e8f9f7 304 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 305 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 306 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 307 * @param PriorityGroup: the priority grouping bits length.
<> 144:ef7eb2e8f9f7 308 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 309 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 310 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 311 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
<> 144:ef7eb2e8f9f7 312 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 313 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 314 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 315 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 316 * 1 bit for subpriority
<> 144:ef7eb2e8f9f7 317 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
<> 144:ef7eb2e8f9f7 318 * 0 bit for subpriority
<> 144:ef7eb2e8f9f7 319 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
<> 144:ef7eb2e8f9f7 320 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
<> 144:ef7eb2e8f9f7 321 * @retval None
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 /* Check the parameters */
<> 144:ef7eb2e8f9f7 326 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 327 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 328 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Set Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 333 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 334 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 335 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 336 * @retval None
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 341 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Get Pending Interrupt (read the pending register in the NVIC
<> 144:ef7eb2e8f9f7 346 * and return the pending bit for the specified interrupt).
<> 144:ef7eb2e8f9f7 347 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 348 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 349 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 350 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 351 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 356 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @brief Clear the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 361 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 362 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 363 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 364 * @retval None
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 369 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 370 }
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /**
<> 144:ef7eb2e8f9f7 373 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
<> 144:ef7eb2e8f9f7 374 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 375 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 376 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
<> 144:ef7eb2e8f9f7 377 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 378 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 /* Return 1 if active else 0 */
<> 144:ef7eb2e8f9f7 383 return NVIC_GetActive(IRQn);
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @brief Configure the SysTick clock source.
<> 144:ef7eb2e8f9f7 388 * @param CLKSource: specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 389 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 390 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 391 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 392 * @retval None
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 /* Check the parameters */
<> 144:ef7eb2e8f9f7 397 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 398 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402 else
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @brief Handle SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 410 * @retval None
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 419 * @retval None
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 422 {
<> 144:ef7eb2e8f9f7 423 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 424 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Initialize and configure the Region and the memory to be protected.
<> 144:ef7eb2e8f9f7 431 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 432 * the initialization and configuration information.
<> 144:ef7eb2e8f9f7 433 * @retval None
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 /* Check the parameters */
<> 144:ef7eb2e8f9f7 438 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
<> 144:ef7eb2e8f9f7 439 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Set the Region number */
<> 144:ef7eb2e8f9f7 442 MPU->RNR = MPU_Init->Number;
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 if ((MPU_Init->Enable) != RESET)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 /* Check the parameters */
<> 144:ef7eb2e8f9f7 447 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
<> 144:ef7eb2e8f9f7 448 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
<> 144:ef7eb2e8f9f7 449 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
<> 144:ef7eb2e8f9f7 450 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
<> 144:ef7eb2e8f9f7 451 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
<> 144:ef7eb2e8f9f7 452 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
<> 144:ef7eb2e8f9f7 453 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
<> 144:ef7eb2e8f9f7 454 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 MPU->RBAR = MPU_Init->BaseAddress;
<> 144:ef7eb2e8f9f7 457 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
<> 144:ef7eb2e8f9f7 458 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
<> 144:ef7eb2e8f9f7 459 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
<> 144:ef7eb2e8f9f7 460 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
<> 144:ef7eb2e8f9f7 461 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
<> 144:ef7eb2e8f9f7 462 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
<> 144:ef7eb2e8f9f7 463 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
<> 144:ef7eb2e8f9f7 464 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
<> 144:ef7eb2e8f9f7 465 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467 else
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 MPU->RBAR = 0x00;
<> 144:ef7eb2e8f9f7 470 MPU->RASR = 0x00;
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /**
<> 144:ef7eb2e8f9f7 476 * @}
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @}
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @}
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @}
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/