mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 184:08ed48f1de7f

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_ll_dma.h
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @brief Header file of DMA LL module.
<>	149:156823d33999	6	******************************************************************************
<>	149:156823d33999	7	* @attention
<>	149:156823d33999	8	*
AnnaBridge	184:08ed48f1de7f	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	149:156823d33999	10	*
<>	149:156823d33999	11	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	12	* are permitted provided that the following conditions are met:
<>	149:156823d33999	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	14	* this list of conditions and the following disclaimer.
<>	149:156823d33999	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	16	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	17	* and/or other materials provided with the distribution.
<>	149:156823d33999	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	19	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	20	* without specific prior written permission.
<>	149:156823d33999	21	*
<>	149:156823d33999	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	32	*
<>	149:156823d33999	33	******************************************************************************
<>	149:156823d33999	34	*/
<>	149:156823d33999	35
<>	149:156823d33999	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	149:156823d33999	37	#ifndef __STM32L1xx_LL_DMA_H
<>	149:156823d33999	38	#define __STM32L1xx_LL_DMA_H
<>	149:156823d33999	39
<>	149:156823d33999	40	#ifdef __cplusplus
<>	149:156823d33999	41	extern "C" {
<>	149:156823d33999	42	#endif
<>	149:156823d33999	43
<>	149:156823d33999	44	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	45	#include "stm32l1xx.h"
<>	149:156823d33999	46
<>	149:156823d33999	47	/** @addtogroup STM32L1xx_LL_Driver
<>	149:156823d33999	48	* @{
<>	149:156823d33999	49	*/
<>	149:156823d33999	50
<>	149:156823d33999	51	#if defined (DMA1) \|\| defined (DMA2)
<>	149:156823d33999	52
<>	149:156823d33999	53	/** @defgroup DMA_LL DMA
<>	149:156823d33999	54	* @{
<>	149:156823d33999	55	*/
<>	149:156823d33999	56
<>	149:156823d33999	57	/* Private types -------------------------------------------------------------*/
<>	149:156823d33999	58	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	59	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
<>	149:156823d33999	60	* @{
<>	149:156823d33999	61	*/
<>	149:156823d33999	62	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<>	149:156823d33999	63	static const uint8_t CHANNEL_OFFSET_TAB[] =
<>	149:156823d33999	64	{
<>	149:156823d33999	65	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<>	149:156823d33999	66	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<>	149:156823d33999	67	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<>	149:156823d33999	68	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<>	149:156823d33999	69	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<>	149:156823d33999	70	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<>	149:156823d33999	71	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<>	149:156823d33999	72	};
<>	149:156823d33999	73	/**
<>	149:156823d33999	74	* @}
<>	149:156823d33999	75	*/
<>	149:156823d33999	76
<>	149:156823d33999	77	/* Private constants ---------------------------------------------------------*/
<>	149:156823d33999	78
<>	149:156823d33999	79	/* Private macros ------------------------------------------------------------*/
<>	149:156823d33999	80	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	81	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
<>	149:156823d33999	82	* @{
<>	149:156823d33999	83	*/
<>	149:156823d33999	84	/**
<>	149:156823d33999	85	* @}
<>	149:156823d33999	86	*/
<>	149:156823d33999	87	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	88
<>	149:156823d33999	89	/* Exported types ------------------------------------------------------------*/
<>	149:156823d33999	90	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	91	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<>	149:156823d33999	92	* @{
<>	149:156823d33999	93	*/
<>	149:156823d33999	94	typedef struct
<>	149:156823d33999	95	{
<>	149:156823d33999	96	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<>	149:156823d33999	97	or as Source base address in case of memory to memory transfer direction.
<>	149:156823d33999	98
<>	149:156823d33999	99	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	149:156823d33999	100
<>	149:156823d33999	101	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<>	149:156823d33999	102	or as Destination base address in case of memory to memory transfer direction.
<>	149:156823d33999	103
<>	149:156823d33999	104	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	149:156823d33999	105
<>	149:156823d33999	106	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<>	149:156823d33999	107	from memory to memory or from peripheral to memory.
<>	149:156823d33999	108	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<>	149:156823d33999	109
<>	149:156823d33999	110	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<>	149:156823d33999	111
<>	149:156823d33999	112	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<>	149:156823d33999	113	This parameter can be a value of @ref DMA_LL_EC_MODE
<>	149:156823d33999	114	@note: The circular buffer mode cannot be used if the memory to memory
<>	149:156823d33999	115	data transfer direction is configured on the selected Channel
<>	149:156823d33999	116
<>	149:156823d33999	117	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<>	149:156823d33999	118
<>	149:156823d33999	119	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<>	149:156823d33999	120	is incremented or not.
<>	149:156823d33999	121	This parameter can be a value of @ref DMA_LL_EC_PERIPH
<>	149:156823d33999	122
<>	149:156823d33999	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<>	149:156823d33999	124
<>	149:156823d33999	125	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<>	149:156823d33999	126	is incremented or not.
<>	149:156823d33999	127	This parameter can be a value of @ref DMA_LL_EC_MEMORY
<>	149:156823d33999	128
<>	149:156823d33999	129	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<>	149:156823d33999	130
<>	149:156823d33999	131	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<>	149:156823d33999	132	in case of memory to memory transfer direction.
<>	149:156823d33999	133	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<>	149:156823d33999	134
<>	149:156823d33999	135	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<>	149:156823d33999	136
<>	149:156823d33999	137	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<>	149:156823d33999	138	in case of memory to memory transfer direction.
<>	149:156823d33999	139	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<>	149:156823d33999	140
<>	149:156823d33999	141	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<>	149:156823d33999	142
<>	149:156823d33999	143	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<>	149:156823d33999	144	The data unit is equal to the source buffer configuration set in PeripheralSize
<>	149:156823d33999	145	or MemorySize parameters depending in the transfer direction.
<>	149:156823d33999	146	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	149:156823d33999	147
<>	149:156823d33999	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<>	149:156823d33999	149
<>	149:156823d33999	150	uint32_t Priority; /*!< Specifies the channel priority level.
<>	149:156823d33999	151	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<>	149:156823d33999	152
<>	149:156823d33999	153	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<>	149:156823d33999	154
<>	149:156823d33999	155	} LL_DMA_InitTypeDef;
<>	149:156823d33999	156	/**
<>	149:156823d33999	157	* @}
<>	149:156823d33999	158	*/
<>	149:156823d33999	159	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	160
<>	149:156823d33999	161	/* Exported constants --------------------------------------------------------*/
<>	149:156823d33999	162	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<>	149:156823d33999	163	* @{
<>	149:156823d33999	164	*/
<>	149:156823d33999	165	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	149:156823d33999	166	* @brief Flags defines which can be used with LL_DMA_WriteReg function
<>	149:156823d33999	167	* @{
<>	149:156823d33999	168	*/
<>	149:156823d33999	169	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
<>	149:156823d33999	170	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
<>	149:156823d33999	171	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
<>	149:156823d33999	172	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
<>	149:156823d33999	173	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
<>	149:156823d33999	174	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
<>	149:156823d33999	175	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
<>	149:156823d33999	176	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
<>	149:156823d33999	177	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
<>	149:156823d33999	178	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
<>	149:156823d33999	179	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
<>	149:156823d33999	180	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
<>	149:156823d33999	181	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
<>	149:156823d33999	182	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
<>	149:156823d33999	183	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
<>	149:156823d33999	184	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
<>	149:156823d33999	185	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
<>	149:156823d33999	186	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
<>	149:156823d33999	187	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
<>	149:156823d33999	188	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
<>	149:156823d33999	189	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
<>	149:156823d33999	190	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
<>	149:156823d33999	191	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
<>	149:156823d33999	192	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
<>	149:156823d33999	193	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
<>	149:156823d33999	194	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
<>	149:156823d33999	195	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
<>	149:156823d33999	196	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
<>	149:156823d33999	197	/**
<>	149:156823d33999	198	* @}
<>	149:156823d33999	199	*/
<>	149:156823d33999	200
<>	149:156823d33999	201	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<>	149:156823d33999	202	* @brief Flags defines which can be used with LL_DMA_ReadReg function
<>	149:156823d33999	203	* @{
<>	149:156823d33999	204	*/
<>	149:156823d33999	205	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
<>	149:156823d33999	206	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
<>	149:156823d33999	207	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
<>	149:156823d33999	208	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
<>	149:156823d33999	209	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
<>	149:156823d33999	210	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
<>	149:156823d33999	211	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
<>	149:156823d33999	212	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
<>	149:156823d33999	213	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
<>	149:156823d33999	214	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
<>	149:156823d33999	215	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
<>	149:156823d33999	216	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
<>	149:156823d33999	217	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
<>	149:156823d33999	218	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
<>	149:156823d33999	219	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
<>	149:156823d33999	220	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
<>	149:156823d33999	221	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
<>	149:156823d33999	222	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
<>	149:156823d33999	223	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
<>	149:156823d33999	224	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
<>	149:156823d33999	225	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
<>	149:156823d33999	226	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
<>	149:156823d33999	227	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
<>	149:156823d33999	228	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
<>	149:156823d33999	229	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
<>	149:156823d33999	230	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
<>	149:156823d33999	231	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
<>	149:156823d33999	232	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
<>	149:156823d33999	233	/**
<>	149:156823d33999	234	* @}
<>	149:156823d33999	235	*/
<>	149:156823d33999	236
<>	149:156823d33999	237	/** @defgroup DMA_LL_EC_IT IT Defines
<>	149:156823d33999	238	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<>	149:156823d33999	239	* @{
<>	149:156823d33999	240	*/
<>	149:156823d33999	241	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
<>	149:156823d33999	242	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
<>	149:156823d33999	243	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
<>	149:156823d33999	244	/**
<>	149:156823d33999	245	* @}
<>	149:156823d33999	246	*/
<>	149:156823d33999	247
<>	149:156823d33999	248	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<>	149:156823d33999	249	* @{
<>	149:156823d33999	250	*/
AnnaBridge	184:08ed48f1de7f	251	#define LL_DMA_CHANNEL_1 0x00000001U /!< DMA Channel 1 /
AnnaBridge	184:08ed48f1de7f	252	#define LL_DMA_CHANNEL_2 0x00000002U /!< DMA Channel 2 /
AnnaBridge	184:08ed48f1de7f	253	#define LL_DMA_CHANNEL_3 0x00000003U /!< DMA Channel 3 /
AnnaBridge	184:08ed48f1de7f	254	#define LL_DMA_CHANNEL_4 0x00000004U /!< DMA Channel 4 /
AnnaBridge	184:08ed48f1de7f	255	#define LL_DMA_CHANNEL_5 0x00000005U /!< DMA Channel 5 /
AnnaBridge	184:08ed48f1de7f	256	#define LL_DMA_CHANNEL_6 0x00000006U /!< DMA Channel 6 /
AnnaBridge	184:08ed48f1de7f	257	#define LL_DMA_CHANNEL_7 0x00000007U /!< DMA Channel 7 /
<>	149:156823d33999	258	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	184:08ed48f1de7f	259	#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
<>	149:156823d33999	260	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	261	/**
<>	149:156823d33999	262	* @}
<>	149:156823d33999	263	*/
<>	149:156823d33999	264
<>	149:156823d33999	265	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<>	149:156823d33999	266	* @{
<>	149:156823d33999	267	*/
AnnaBridge	184:08ed48f1de7f	268	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
<>	149:156823d33999	269	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
<>	149:156823d33999	270	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
<>	149:156823d33999	271	/**
<>	149:156823d33999	272	* @}
<>	149:156823d33999	273	*/
<>	149:156823d33999	274
<>	149:156823d33999	275	/** @defgroup DMA_LL_EC_MODE Transfer mode
<>	149:156823d33999	276	* @{
<>	149:156823d33999	277	*/
AnnaBridge	184:08ed48f1de7f	278	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
<>	149:156823d33999	279	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
<>	149:156823d33999	280	/**
<>	149:156823d33999	281	* @}
<>	149:156823d33999	282	*/
<>	149:156823d33999	283
<>	149:156823d33999	284	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<>	149:156823d33999	285	* @{
<>	149:156823d33999	286	*/
<>	149:156823d33999	287	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	184:08ed48f1de7f	288	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
<>	149:156823d33999	289	/**
<>	149:156823d33999	290	* @}
<>	149:156823d33999	291	*/
<>	149:156823d33999	292
<>	149:156823d33999	293	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<>	149:156823d33999	294	* @{
<>	149:156823d33999	295	*/
<>	149:156823d33999	296	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	184:08ed48f1de7f	297	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
<>	149:156823d33999	298	/**
<>	149:156823d33999	299	* @}
<>	149:156823d33999	300	*/
<>	149:156823d33999	301
<>	149:156823d33999	302	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<>	149:156823d33999	303	* @{
<>	149:156823d33999	304	*/
AnnaBridge	184:08ed48f1de7f	305	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
<>	149:156823d33999	306	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
<>	149:156823d33999	307	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
<>	149:156823d33999	308	/**
<>	149:156823d33999	309	* @}
<>	149:156823d33999	310	*/
<>	149:156823d33999	311
<>	149:156823d33999	312	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<>	149:156823d33999	313	* @{
<>	149:156823d33999	314	*/
AnnaBridge	184:08ed48f1de7f	315	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
<>	149:156823d33999	316	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
<>	149:156823d33999	317	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
<>	149:156823d33999	318	/**
<>	149:156823d33999	319	* @}
<>	149:156823d33999	320	*/
<>	149:156823d33999	321
<>	149:156823d33999	322	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<>	149:156823d33999	323	* @{
<>	149:156823d33999	324	*/
AnnaBridge	184:08ed48f1de7f	325	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
<>	149:156823d33999	326	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
<>	149:156823d33999	327	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
<>	149:156823d33999	328	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
<>	149:156823d33999	329	/**
<>	149:156823d33999	330	* @}
<>	149:156823d33999	331	*/
<>	149:156823d33999	332
<>	149:156823d33999	333
<>	149:156823d33999	334	/**
<>	149:156823d33999	335	* @}
<>	149:156823d33999	336	*/
<>	149:156823d33999	337
<>	149:156823d33999	338	/* Exported macro ------------------------------------------------------------*/
<>	149:156823d33999	339	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<>	149:156823d33999	340	* @{
<>	149:156823d33999	341	*/
<>	149:156823d33999	342
<>	149:156823d33999	343	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<>	149:156823d33999	344	* @{
<>	149:156823d33999	345	*/
<>	149:156823d33999	346	/**
<>	149:156823d33999	347	* @brief Write a value in DMA register
<>	149:156823d33999	348	* @param __INSTANCE__ DMA Instance
<>	149:156823d33999	349	* @param __REG__ Register to be written
<>	149:156823d33999	350	* @param __VALUE__ Value to be written in the register
<>	149:156823d33999	351	* @retval None
<>	149:156823d33999	352	*/
<>	149:156823d33999	353	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	149:156823d33999	354
<>	149:156823d33999	355	/**
<>	149:156823d33999	356	* @brief Read a value in DMA register
<>	149:156823d33999	357	* @param __INSTANCE__ DMA Instance
<>	149:156823d33999	358	* @param __REG__ Register to be read
<>	149:156823d33999	359	* @retval Register value
<>	149:156823d33999	360	*/
<>	149:156823d33999	361	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	149:156823d33999	362	/**
<>	149:156823d33999	363	* @}
<>	149:156823d33999	364	*/
<>	149:156823d33999	365
<>	149:156823d33999	366	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<>	149:156823d33999	367	* @{
<>	149:156823d33999	368	*/
<>	149:156823d33999	369	/**
<>	149:156823d33999	370	* @brief Convert DMAx_Channely into DMAx
<>	149:156823d33999	371	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	149:156823d33999	372	* @retval DMAx
<>	149:156823d33999	373	*/
<>	149:156823d33999	374	#if defined(DMA2)
<>	149:156823d33999	375	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	376	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<>	149:156823d33999	377	#else
<>	149:156823d33999	378	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<>	149:156823d33999	379	#endif
<>	149:156823d33999	380
<>	149:156823d33999	381	/**
<>	149:156823d33999	382	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<>	149:156823d33999	383	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	149:156823d33999	384	* @retval LL_DMA_CHANNEL_y
<>	149:156823d33999	385	*/
<>	149:156823d33999	386	#if defined (DMA2)
<>	149:156823d33999	387	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	149:156823d33999	388	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	389	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	390	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	391	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	392	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	393	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	394	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	395	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	396	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	397	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	398	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	399	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	400	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	401	LL_DMA_CHANNEL_7)
<>	149:156823d33999	402	#else
<>	149:156823d33999	403	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	404	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	405	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	406	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	407	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	408	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	409	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	410	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	411	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	412	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	413	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	414	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	415	LL_DMA_CHANNEL_7)
<>	149:156823d33999	416	#endif
<>	149:156823d33999	417	#else
<>	149:156823d33999	418	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	419	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	420	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	421	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	425	LL_DMA_CHANNEL_7)
<>	149:156823d33999	426	#endif
<>	149:156823d33999	427
<>	149:156823d33999	428	/**
<>	149:156823d33999	429	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<>	149:156823d33999	430	* @param __DMA_INSTANCE__ DMAx
<>	149:156823d33999	431	* @param __CHANNEL__ LL_DMA_CHANNEL_y
<>	149:156823d33999	432	* @retval DMAx_Channely
<>	149:156823d33999	433	*/
<>	149:156823d33999	434	#if defined (DMA2)
<>	149:156823d33999	435	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	149:156823d33999	436	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	149:156823d33999	437	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	149:156823d33999	438	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	149:156823d33999	439	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	149:156823d33999	440	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	149:156823d33999	441	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	149:156823d33999	442	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	149:156823d33999	443	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	149:156823d33999	444	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	149:156823d33999	445	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	149:156823d33999	446	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	149:156823d33999	447	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	149:156823d33999	448	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<>	149:156823d33999	449	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<>	149:156823d33999	450	DMA2_Channel7)
<>	149:156823d33999	451	#else
<>	149:156823d33999	452	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	149:156823d33999	453	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	149:156823d33999	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	149:156823d33999	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	149:156823d33999	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	149:156823d33999	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	149:156823d33999	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	149:156823d33999	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	149:156823d33999	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	149:156823d33999	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	149:156823d33999	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	149:156823d33999	463	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	149:156823d33999	464	DMA1_Channel7)
<>	149:156823d33999	465	#endif
<>	149:156823d33999	466	#else
<>	149:156823d33999	467	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	149:156823d33999	468	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	149:156823d33999	469	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	149:156823d33999	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	149:156823d33999	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	149:156823d33999	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	149:156823d33999	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	149:156823d33999	474	DMA1_Channel7)
<>	149:156823d33999	475	#endif
<>	149:156823d33999	476
<>	149:156823d33999	477	/**
<>	149:156823d33999	478	* @}
<>	149:156823d33999	479	*/
<>	149:156823d33999	480
<>	149:156823d33999	481	/**
<>	149:156823d33999	482	* @}
<>	149:156823d33999	483	*/
<>	149:156823d33999	484
<>	149:156823d33999	485	/* Exported functions --------------------------------------------------------*/
<>	149:156823d33999	486	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<>	149:156823d33999	487	* @{
<>	149:156823d33999	488	*/
<>	149:156823d33999	489
<>	149:156823d33999	490	/** @defgroup DMA_LL_EF_Configuration Configuration
<>	149:156823d33999	491	* @{
<>	149:156823d33999	492	*/
<>	149:156823d33999	493	/**
<>	149:156823d33999	494	* @brief Enable DMA channel.
<>	149:156823d33999	495	* @rmtoll CCR EN LL_DMA_EnableChannel
<>	149:156823d33999	496	* @param DMAx DMAx Instance
<>	149:156823d33999	497	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	498	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	499	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	500	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	501	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	502	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	503	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	504	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	505	* @retval None
<>	149:156823d33999	506	*/
<>	149:156823d33999	507	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	508	{
<>	149:156823d33999	509	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	149:156823d33999	510	}
<>	149:156823d33999	511
<>	149:156823d33999	512	/**
<>	149:156823d33999	513	* @brief Disable DMA channel.
<>	149:156823d33999	514	* @rmtoll CCR EN LL_DMA_DisableChannel
<>	149:156823d33999	515	* @param DMAx DMAx Instance
<>	149:156823d33999	516	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	517	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	518	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	519	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	520	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	521	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	522	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	523	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	524	* @retval None
<>	149:156823d33999	525	*/
<>	149:156823d33999	526	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	527	{
<>	149:156823d33999	528	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	149:156823d33999	529	}
<>	149:156823d33999	530
<>	149:156823d33999	531	/**
<>	149:156823d33999	532	* @brief Check if DMA channel is enabled or disabled.
<>	149:156823d33999	533	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
<>	149:156823d33999	534	* @param DMAx DMAx Instance
<>	149:156823d33999	535	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	536	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	537	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	538	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	539	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	540	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	541	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	542	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	543	* @retval State of bit (1 or 0).
<>	149:156823d33999	544	*/
<>	149:156823d33999	545	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	546	{
<>	149:156823d33999	547	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	548	DMA_CCR_EN) == (DMA_CCR_EN));
<>	149:156823d33999	549	}
<>	149:156823d33999	550
<>	149:156823d33999	551	/**
<>	149:156823d33999	552	* @brief Configure all parameters link to DMA transfer.
<>	149:156823d33999	553	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<>	149:156823d33999	554	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
<>	149:156823d33999	555	* CCR CIRC LL_DMA_ConfigTransfer\n
<>	149:156823d33999	556	* CCR PINC LL_DMA_ConfigTransfer\n
<>	149:156823d33999	557	* CCR MINC LL_DMA_ConfigTransfer\n
<>	149:156823d33999	558	* CCR PSIZE LL_DMA_ConfigTransfer\n
<>	149:156823d33999	559	* CCR MSIZE LL_DMA_ConfigTransfer\n
<>	149:156823d33999	560	* CCR PL LL_DMA_ConfigTransfer
<>	149:156823d33999	561	* @param DMAx DMAx Instance
<>	149:156823d33999	562	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	563	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	564	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	565	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	566	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	567	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	568	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	569	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	570	* @param Configuration This parameter must be a combination of all the following values:
<>	149:156823d33999	571	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	572	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<>	149:156823d33999	573	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<>	149:156823d33999	574	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<>	149:156823d33999	575	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<>	149:156823d33999	576	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<>	149:156823d33999	577	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<>	149:156823d33999	578	* @retval None
<>	149:156823d33999	579	*/
<>	149:156823d33999	580	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<>	149:156823d33999	581	{
<>	149:156823d33999	582	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	583	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
<>	149:156823d33999	584	Configuration);
<>	149:156823d33999	585	}
<>	149:156823d33999	586
<>	149:156823d33999	587	/**
<>	149:156823d33999	588	* @brief Set Data transfer direction (read from peripheral or from memory).
<>	149:156823d33999	589	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<>	149:156823d33999	590	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
<>	149:156823d33999	591	* @param DMAx DMAx Instance
<>	149:156823d33999	592	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	593	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	594	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	595	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	596	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	597	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	598	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	599	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	600	* @param Direction This parameter can be one of the following values:
<>	149:156823d33999	601	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	149:156823d33999	602	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	149:156823d33999	603	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	604	* @retval None
<>	149:156823d33999	605	*/
<>	149:156823d33999	606	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<>	149:156823d33999	607	{
<>	149:156823d33999	608	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	609	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
<>	149:156823d33999	610	}
<>	149:156823d33999	611
<>	149:156823d33999	612	/**
<>	149:156823d33999	613	* @brief Get Data transfer direction (read from peripheral or from memory).
<>	149:156823d33999	614	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<>	149:156823d33999	615	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
<>	149:156823d33999	616	* @param DMAx DMAx Instance
<>	149:156823d33999	617	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	618	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	619	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	620	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	621	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	622	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	623	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	624	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	625	* @retval Returned value can be one of the following values:
<>	149:156823d33999	626	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	149:156823d33999	627	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	149:156823d33999	628	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	629	*/
<>	149:156823d33999	630	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	631	{
<>	149:156823d33999	632	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	633	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
<>	149:156823d33999	634	}
<>	149:156823d33999	635
<>	149:156823d33999	636	/**
<>	149:156823d33999	637	* @brief Set DMA mode circular or normal.
<>	149:156823d33999	638	* @note The circular buffer mode cannot be used if the memory-to-memory
<>	149:156823d33999	639	* data transfer is configured on the selected Channel.
<>	149:156823d33999	640	* @rmtoll CCR CIRC LL_DMA_SetMode
<>	149:156823d33999	641	* @param DMAx DMAx Instance
<>	149:156823d33999	642	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	643	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	644	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	645	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	646	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	647	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	648	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	649	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	650	* @param Mode This parameter can be one of the following values:
<>	149:156823d33999	651	* @arg @ref LL_DMA_MODE_NORMAL
<>	149:156823d33999	652	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	149:156823d33999	653	* @retval None
<>	149:156823d33999	654	*/
<>	149:156823d33999	655	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<>	149:156823d33999	656	{
<>	149:156823d33999	657	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<>	149:156823d33999	658	Mode);
<>	149:156823d33999	659	}
<>	149:156823d33999	660
<>	149:156823d33999	661	/**
<>	149:156823d33999	662	* @brief Get DMA mode circular or normal.
<>	149:156823d33999	663	* @rmtoll CCR CIRC LL_DMA_GetMode
<>	149:156823d33999	664	* @param DMAx DMAx Instance
<>	149:156823d33999	665	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	666	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	667	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	668	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	669	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	670	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	671	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	672	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	673	* @retval Returned value can be one of the following values:
<>	149:156823d33999	674	* @arg @ref LL_DMA_MODE_NORMAL
<>	149:156823d33999	675	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	149:156823d33999	676	*/
<>	149:156823d33999	677	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	678	{
<>	149:156823d33999	679	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	680	DMA_CCR_CIRC));
<>	149:156823d33999	681	}
<>	149:156823d33999	682
<>	149:156823d33999	683	/**
<>	149:156823d33999	684	* @brief Set Peripheral increment mode.
<>	149:156823d33999	685	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<>	149:156823d33999	686	* @param DMAx DMAx Instance
<>	149:156823d33999	687	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	688	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	689	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	690	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	691	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	692	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	693	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	694	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	695	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<>	149:156823d33999	696	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	149:156823d33999	697	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	149:156823d33999	698	* @retval None
<>	149:156823d33999	699	*/
<>	149:156823d33999	700	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<>	149:156823d33999	701	{
<>	149:156823d33999	702	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<>	149:156823d33999	703	PeriphOrM2MSrcIncMode);
<>	149:156823d33999	704	}
<>	149:156823d33999	705
<>	149:156823d33999	706	/**
<>	149:156823d33999	707	* @brief Get Peripheral increment mode.
<>	149:156823d33999	708	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<>	149:156823d33999	709	* @param DMAx DMAx Instance
<>	149:156823d33999	710	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	711	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	712	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	713	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	714	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	715	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	716	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	717	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	718	* @retval Returned value can be one of the following values:
<>	149:156823d33999	719	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	149:156823d33999	720	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	149:156823d33999	721	*/
<>	149:156823d33999	722	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	723	{
<>	149:156823d33999	724	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	725	DMA_CCR_PINC));
<>	149:156823d33999	726	}
<>	149:156823d33999	727
<>	149:156823d33999	728	/**
<>	149:156823d33999	729	* @brief Set Memory increment mode.
<>	149:156823d33999	730	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<>	149:156823d33999	731	* @param DMAx DMAx Instance
<>	149:156823d33999	732	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	733	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	734	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	735	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	736	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	737	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	738	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	739	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	740	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<>	149:156823d33999	741	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	149:156823d33999	742	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	149:156823d33999	743	* @retval None
<>	149:156823d33999	744	*/
<>	149:156823d33999	745	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<>	149:156823d33999	746	{
<>	149:156823d33999	747	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<>	149:156823d33999	748	MemoryOrM2MDstIncMode);
<>	149:156823d33999	749	}
<>	149:156823d33999	750
<>	149:156823d33999	751	/**
<>	149:156823d33999	752	* @brief Get Memory increment mode.
<>	149:156823d33999	753	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<>	149:156823d33999	754	* @param DMAx DMAx Instance
<>	149:156823d33999	755	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	756	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	757	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	758	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	759	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	760	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	761	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	762	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	763	* @retval Returned value can be one of the following values:
<>	149:156823d33999	764	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	149:156823d33999	765	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	149:156823d33999	766	*/
<>	149:156823d33999	767	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	768	{
<>	149:156823d33999	769	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	770	DMA_CCR_MINC));
<>	149:156823d33999	771	}
<>	149:156823d33999	772
<>	149:156823d33999	773	/**
<>	149:156823d33999	774	* @brief Set Peripheral size.
<>	149:156823d33999	775	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<>	149:156823d33999	776	* @param DMAx DMAx Instance
<>	149:156823d33999	777	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	778	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	779	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	780	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	781	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	782	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	783	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	784	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	785	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<>	149:156823d33999	786	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	149:156823d33999	787	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	149:156823d33999	788	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	149:156823d33999	789	* @retval None
<>	149:156823d33999	790	*/
<>	149:156823d33999	791	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<>	149:156823d33999	792	{
<>	149:156823d33999	793	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<>	149:156823d33999	794	PeriphOrM2MSrcDataSize);
<>	149:156823d33999	795	}
<>	149:156823d33999	796
<>	149:156823d33999	797	/**
<>	149:156823d33999	798	* @brief Get Peripheral size.
<>	149:156823d33999	799	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<>	149:156823d33999	800	* @param DMAx DMAx Instance
<>	149:156823d33999	801	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	802	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	803	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	804	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	805	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	806	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	807	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	808	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	809	* @retval Returned value can be one of the following values:
<>	149:156823d33999	810	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	149:156823d33999	811	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	149:156823d33999	812	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	149:156823d33999	813	*/
<>	149:156823d33999	814	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	815	{
<>	149:156823d33999	816	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	817	DMA_CCR_PSIZE));
<>	149:156823d33999	818	}
<>	149:156823d33999	819
<>	149:156823d33999	820	/**
<>	149:156823d33999	821	* @brief Set Memory size.
<>	149:156823d33999	822	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<>	149:156823d33999	823	* @param DMAx DMAx Instance
<>	149:156823d33999	824	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	825	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	826	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	827	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	828	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	829	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	830	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	831	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	832	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<>	149:156823d33999	833	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	149:156823d33999	834	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	149:156823d33999	835	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	149:156823d33999	836	* @retval None
<>	149:156823d33999	837	*/
<>	149:156823d33999	838	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<>	149:156823d33999	839	{
<>	149:156823d33999	840	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<>	149:156823d33999	841	MemoryOrM2MDstDataSize);
<>	149:156823d33999	842	}
<>	149:156823d33999	843
<>	149:156823d33999	844	/**
<>	149:156823d33999	845	* @brief Get Memory size.
<>	149:156823d33999	846	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<>	149:156823d33999	847	* @param DMAx DMAx Instance
<>	149:156823d33999	848	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	849	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	850	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	851	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	852	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	853	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	854	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	855	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	856	* @retval Returned value can be one of the following values:
<>	149:156823d33999	857	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	149:156823d33999	858	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	149:156823d33999	859	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	149:156823d33999	860	*/
<>	149:156823d33999	861	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	862	{
<>	149:156823d33999	863	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	864	DMA_CCR_MSIZE));
<>	149:156823d33999	865	}
<>	149:156823d33999	866
<>	149:156823d33999	867	/**
<>	149:156823d33999	868	* @brief Set Channel priority level.
<>	149:156823d33999	869	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<>	149:156823d33999	870	* @param DMAx DMAx Instance
<>	149:156823d33999	871	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	872	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	873	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	874	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	875	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	876	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	877	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	878	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	879	* @param Priority This parameter can be one of the following values:
<>	149:156823d33999	880	* @arg @ref LL_DMA_PRIORITY_LOW
<>	149:156823d33999	881	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	149:156823d33999	882	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	149:156823d33999	883	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	149:156823d33999	884	* @retval None
<>	149:156823d33999	885	*/
<>	149:156823d33999	886	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<>	149:156823d33999	887	{
<>	149:156823d33999	888	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<>	149:156823d33999	889	Priority);
<>	149:156823d33999	890	}
<>	149:156823d33999	891
<>	149:156823d33999	892	/**
<>	149:156823d33999	893	* @brief Get Channel priority level.
<>	149:156823d33999	894	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<>	149:156823d33999	895	* @param DMAx DMAx Instance
<>	149:156823d33999	896	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	897	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	898	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	899	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	900	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	901	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	902	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	903	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	904	* @retval Returned value can be one of the following values:
<>	149:156823d33999	905	* @arg @ref LL_DMA_PRIORITY_LOW
<>	149:156823d33999	906	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	149:156823d33999	907	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	149:156823d33999	908	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	149:156823d33999	909	*/
<>	149:156823d33999	910	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	911	{
<>	149:156823d33999	912	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	913	DMA_CCR_PL));
<>	149:156823d33999	914	}
<>	149:156823d33999	915
<>	149:156823d33999	916	/**
<>	149:156823d33999	917	* @brief Set Number of data to transfer.
<>	149:156823d33999	918	* @note This action has no effect if
<>	149:156823d33999	919	* channel is enabled.
<>	149:156823d33999	920	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
<>	149:156823d33999	921	* @param DMAx DMAx Instance
<>	149:156823d33999	922	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	923	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	924	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	925	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	926	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	927	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	928	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	929	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	930	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	149:156823d33999	931	* @retval None
<>	149:156823d33999	932	*/
<>	149:156823d33999	933	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<>	149:156823d33999	934	{
<>	149:156823d33999	935	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	149:156823d33999	936	DMA_CNDTR_NDT, NbData);
<>	149:156823d33999	937	}
<>	149:156823d33999	938
<>	149:156823d33999	939	/**
<>	149:156823d33999	940	* @brief Get Number of data to transfer.
<>	149:156823d33999	941	* @note Once the channel is enabled, the return value indicate the
<>	149:156823d33999	942	* remaining bytes to be transmitted.
<>	149:156823d33999	943	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
<>	149:156823d33999	944	* @param DMAx DMAx Instance
<>	149:156823d33999	945	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	946	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	947	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	948	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	949	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	950	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	951	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	952	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	953	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	954	*/
<>	149:156823d33999	955	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	956	{
<>	149:156823d33999	957	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	149:156823d33999	958	DMA_CNDTR_NDT));
<>	149:156823d33999	959	}
<>	149:156823d33999	960
<>	149:156823d33999	961	/**
<>	149:156823d33999	962	* @brief Configure the Source and Destination addresses.
AnnaBridge	184:08ed48f1de7f	963	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	184:08ed48f1de7f	964	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
<>	149:156823d33999	965	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<>	149:156823d33999	966	* CMAR MA LL_DMA_ConfigAddresses
<>	149:156823d33999	967	* @param DMAx DMAx Instance
<>	149:156823d33999	968	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	969	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	970	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	971	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	972	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	973	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	974	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	975	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	976	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	977	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	978	* @param Direction This parameter can be one of the following values:
<>	149:156823d33999	979	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	149:156823d33999	980	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	149:156823d33999	981	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	982	* @retval None
<>	149:156823d33999	983	*/
<>	149:156823d33999	984	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<>	149:156823d33999	985	uint32_t DstAddress, uint32_t Direction)
<>	149:156823d33999	986	{
<>	149:156823d33999	987	/* Direction Memory to Periph */
<>	149:156823d33999	988	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<>	149:156823d33999	989	{
AnnaBridge	184:08ed48f1de7f	990	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	184:08ed48f1de7f	991	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
<>	149:156823d33999	992	}
<>	149:156823d33999	993	/* Direction Periph to Memory and Memory to Memory */
<>	149:156823d33999	994	else
<>	149:156823d33999	995	{
AnnaBridge	184:08ed48f1de7f	996	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	184:08ed48f1de7f	997	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
<>	149:156823d33999	998	}
<>	149:156823d33999	999	}
<>	149:156823d33999	1000
<>	149:156823d33999	1001	/**
<>	149:156823d33999	1002	* @brief Set the Memory address.
<>	149:156823d33999	1003	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	184:08ed48f1de7f	1004	* @note This API must not be called when the DMA channel is enabled.
<>	149:156823d33999	1005	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<>	149:156823d33999	1006	* @param DMAx DMAx Instance
<>	149:156823d33999	1007	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1008	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1009	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1010	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1011	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1012	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1013	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1014	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1015	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1016	* @retval None
<>	149:156823d33999	1017	*/
<>	149:156823d33999	1018	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	149:156823d33999	1019	{
AnnaBridge	184:08ed48f1de7f	1020	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
<>	149:156823d33999	1021	}
<>	149:156823d33999	1022
<>	149:156823d33999	1023	/**
<>	149:156823d33999	1024	* @brief Set the Peripheral address.
<>	149:156823d33999	1025	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	184:08ed48f1de7f	1026	* @note This API must not be called when the DMA channel is enabled.
<>	149:156823d33999	1027	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<>	149:156823d33999	1028	* @param DMAx DMAx Instance
<>	149:156823d33999	1029	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1030	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1031	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1032	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1033	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1034	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1035	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1036	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1037	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1038	* @retval None
<>	149:156823d33999	1039	*/
<>	149:156823d33999	1040	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<>	149:156823d33999	1041	{
AnnaBridge	184:08ed48f1de7f	1042	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
<>	149:156823d33999	1043	}
<>	149:156823d33999	1044
<>	149:156823d33999	1045	/**
<>	149:156823d33999	1046	* @brief Get Memory address.
<>	149:156823d33999	1047	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	149:156823d33999	1048	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<>	149:156823d33999	1049	* @param DMAx DMAx Instance
<>	149:156823d33999	1050	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1051	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1052	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1053	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1054	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1055	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1056	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1057	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1058	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1059	*/
<>	149:156823d33999	1060	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1061	{
AnnaBridge	184:08ed48f1de7f	1062	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
<>	149:156823d33999	1063	}
<>	149:156823d33999	1064
<>	149:156823d33999	1065	/**
<>	149:156823d33999	1066	* @brief Get Peripheral address.
<>	149:156823d33999	1067	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	149:156823d33999	1068	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<>	149:156823d33999	1069	* @param DMAx DMAx Instance
<>	149:156823d33999	1070	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1071	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1072	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1073	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1074	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1075	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1076	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1077	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1078	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1079	*/
<>	149:156823d33999	1080	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1081	{
AnnaBridge	184:08ed48f1de7f	1082	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
<>	149:156823d33999	1083	}
<>	149:156823d33999	1084
<>	149:156823d33999	1085	/**
<>	149:156823d33999	1086	* @brief Set the Memory to Memory Source address.
<>	149:156823d33999	1087	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	184:08ed48f1de7f	1088	* @note This API must not be called when the DMA channel is enabled.
<>	149:156823d33999	1089	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<>	149:156823d33999	1090	* @param DMAx DMAx Instance
<>	149:156823d33999	1091	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1092	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1093	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1094	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1095	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1096	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1097	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1098	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1099	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1100	* @retval None
<>	149:156823d33999	1101	*/
<>	149:156823d33999	1102	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	149:156823d33999	1103	{
AnnaBridge	184:08ed48f1de7f	1104	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
<>	149:156823d33999	1105	}
<>	149:156823d33999	1106
<>	149:156823d33999	1107	/**
<>	149:156823d33999	1108	* @brief Set the Memory to Memory Destination address.
<>	149:156823d33999	1109	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	184:08ed48f1de7f	1110	* @note This API must not be called when the DMA channel is enabled.
<>	149:156823d33999	1111	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<>	149:156823d33999	1112	* @param DMAx DMAx Instance
<>	149:156823d33999	1113	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1114	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1115	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1116	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1117	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1118	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1119	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1120	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1121	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1122	* @retval None
<>	149:156823d33999	1123	*/
<>	149:156823d33999	1124	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	149:156823d33999	1125	{
AnnaBridge	184:08ed48f1de7f	1126	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
<>	149:156823d33999	1127	}
<>	149:156823d33999	1128
<>	149:156823d33999	1129	/**
<>	149:156823d33999	1130	* @brief Get the Memory to Memory Source address.
<>	149:156823d33999	1131	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	149:156823d33999	1132	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<>	149:156823d33999	1133	* @param DMAx DMAx Instance
<>	149:156823d33999	1134	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1135	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1136	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1137	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1138	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1139	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1140	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1141	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1142	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1143	*/
<>	149:156823d33999	1144	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1145	{
AnnaBridge	184:08ed48f1de7f	1146	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
<>	149:156823d33999	1147	}
<>	149:156823d33999	1148
<>	149:156823d33999	1149	/**
<>	149:156823d33999	1150	* @brief Get the Memory to Memory Destination address.
<>	149:156823d33999	1151	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	149:156823d33999	1152	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<>	149:156823d33999	1153	* @param DMAx DMAx Instance
<>	149:156823d33999	1154	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1155	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1156	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1157	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1158	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1159	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1160	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1161	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1162	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1163	*/
<>	149:156823d33999	1164	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1165	{
AnnaBridge	184:08ed48f1de7f	1166	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
<>	149:156823d33999	1167	}
<>	149:156823d33999	1168
<>	149:156823d33999	1169
<>	149:156823d33999	1170	/**
<>	149:156823d33999	1171	* @}
<>	149:156823d33999	1172	*/
<>	149:156823d33999	1173
<>	149:156823d33999	1174	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<>	149:156823d33999	1175	* @{
<>	149:156823d33999	1176	*/
<>	149:156823d33999	1177
<>	149:156823d33999	1178	/**
<>	149:156823d33999	1179	* @brief Get Channel 1 global interrupt flag.
<>	149:156823d33999	1180	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<>	149:156823d33999	1181	* @param DMAx DMAx Instance
<>	149:156823d33999	1182	* @retval State of bit (1 or 0).
<>	149:156823d33999	1183	*/
<>	149:156823d33999	1184	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1185	{
<>	149:156823d33999	1186	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<>	149:156823d33999	1187	}
<>	149:156823d33999	1188
<>	149:156823d33999	1189	/**
<>	149:156823d33999	1190	* @brief Get Channel 2 global interrupt flag.
<>	149:156823d33999	1191	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<>	149:156823d33999	1192	* @param DMAx DMAx Instance
<>	149:156823d33999	1193	* @retval State of bit (1 or 0).
<>	149:156823d33999	1194	*/
<>	149:156823d33999	1195	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1196	{
<>	149:156823d33999	1197	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<>	149:156823d33999	1198	}
<>	149:156823d33999	1199
<>	149:156823d33999	1200	/**
<>	149:156823d33999	1201	* @brief Get Channel 3 global interrupt flag.
<>	149:156823d33999	1202	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<>	149:156823d33999	1203	* @param DMAx DMAx Instance
<>	149:156823d33999	1204	* @retval State of bit (1 or 0).
<>	149:156823d33999	1205	*/
<>	149:156823d33999	1206	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1207	{
<>	149:156823d33999	1208	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<>	149:156823d33999	1209	}
<>	149:156823d33999	1210
<>	149:156823d33999	1211	/**
<>	149:156823d33999	1212	* @brief Get Channel 4 global interrupt flag.
<>	149:156823d33999	1213	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<>	149:156823d33999	1214	* @param DMAx DMAx Instance
<>	149:156823d33999	1215	* @retval State of bit (1 or 0).
<>	149:156823d33999	1216	*/
<>	149:156823d33999	1217	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1218	{
<>	149:156823d33999	1219	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<>	149:156823d33999	1220	}
<>	149:156823d33999	1221
<>	149:156823d33999	1222	/**
<>	149:156823d33999	1223	* @brief Get Channel 5 global interrupt flag.
<>	149:156823d33999	1224	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<>	149:156823d33999	1225	* @param DMAx DMAx Instance
<>	149:156823d33999	1226	* @retval State of bit (1 or 0).
<>	149:156823d33999	1227	*/
<>	149:156823d33999	1228	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1229	{
<>	149:156823d33999	1230	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<>	149:156823d33999	1231	}
<>	149:156823d33999	1232
<>	149:156823d33999	1233	/**
<>	149:156823d33999	1234	* @brief Get Channel 6 global interrupt flag.
<>	149:156823d33999	1235	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<>	149:156823d33999	1236	* @param DMAx DMAx Instance
<>	149:156823d33999	1237	* @retval State of bit (1 or 0).
<>	149:156823d33999	1238	*/
<>	149:156823d33999	1239	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1240	{
<>	149:156823d33999	1241	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<>	149:156823d33999	1242	}
<>	149:156823d33999	1243
<>	149:156823d33999	1244	/**
<>	149:156823d33999	1245	* @brief Get Channel 7 global interrupt flag.
<>	149:156823d33999	1246	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<>	149:156823d33999	1247	* @param DMAx DMAx Instance
<>	149:156823d33999	1248	* @retval State of bit (1 or 0).
<>	149:156823d33999	1249	*/
<>	149:156823d33999	1250	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1251	{
<>	149:156823d33999	1252	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<>	149:156823d33999	1253	}
<>	149:156823d33999	1254
<>	149:156823d33999	1255	/**
<>	149:156823d33999	1256	* @brief Get Channel 1 transfer complete flag.
<>	149:156823d33999	1257	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<>	149:156823d33999	1258	* @param DMAx DMAx Instance
<>	149:156823d33999	1259	* @retval State of bit (1 or 0).
<>	149:156823d33999	1260	*/
<>	149:156823d33999	1261	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1262	{
<>	149:156823d33999	1263	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<>	149:156823d33999	1264	}
<>	149:156823d33999	1265
<>	149:156823d33999	1266	/**
<>	149:156823d33999	1267	* @brief Get Channel 2 transfer complete flag.
<>	149:156823d33999	1268	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<>	149:156823d33999	1269	* @param DMAx DMAx Instance
<>	149:156823d33999	1270	* @retval State of bit (1 or 0).
<>	149:156823d33999	1271	*/
<>	149:156823d33999	1272	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1273	{
<>	149:156823d33999	1274	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<>	149:156823d33999	1275	}
<>	149:156823d33999	1276
<>	149:156823d33999	1277	/**
<>	149:156823d33999	1278	* @brief Get Channel 3 transfer complete flag.
<>	149:156823d33999	1279	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<>	149:156823d33999	1280	* @param DMAx DMAx Instance
<>	149:156823d33999	1281	* @retval State of bit (1 or 0).
<>	149:156823d33999	1282	*/
<>	149:156823d33999	1283	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1284	{
<>	149:156823d33999	1285	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<>	149:156823d33999	1286	}
<>	149:156823d33999	1287
<>	149:156823d33999	1288	/**
<>	149:156823d33999	1289	* @brief Get Channel 4 transfer complete flag.
<>	149:156823d33999	1290	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<>	149:156823d33999	1291	* @param DMAx DMAx Instance
<>	149:156823d33999	1292	* @retval State of bit (1 or 0).
<>	149:156823d33999	1293	*/
<>	149:156823d33999	1294	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1295	{
<>	149:156823d33999	1296	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<>	149:156823d33999	1297	}
<>	149:156823d33999	1298
<>	149:156823d33999	1299	/**
<>	149:156823d33999	1300	* @brief Get Channel 5 transfer complete flag.
<>	149:156823d33999	1301	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<>	149:156823d33999	1302	* @param DMAx DMAx Instance
<>	149:156823d33999	1303	* @retval State of bit (1 or 0).
<>	149:156823d33999	1304	*/
<>	149:156823d33999	1305	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1306	{
<>	149:156823d33999	1307	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<>	149:156823d33999	1308	}
<>	149:156823d33999	1309
<>	149:156823d33999	1310	/**
<>	149:156823d33999	1311	* @brief Get Channel 6 transfer complete flag.
<>	149:156823d33999	1312	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<>	149:156823d33999	1313	* @param DMAx DMAx Instance
<>	149:156823d33999	1314	* @retval State of bit (1 or 0).
<>	149:156823d33999	1315	*/
<>	149:156823d33999	1316	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1317	{
<>	149:156823d33999	1318	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<>	149:156823d33999	1319	}
<>	149:156823d33999	1320
<>	149:156823d33999	1321	/**
<>	149:156823d33999	1322	* @brief Get Channel 7 transfer complete flag.
<>	149:156823d33999	1323	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<>	149:156823d33999	1324	* @param DMAx DMAx Instance
<>	149:156823d33999	1325	* @retval State of bit (1 or 0).
<>	149:156823d33999	1326	*/
<>	149:156823d33999	1327	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1328	{
<>	149:156823d33999	1329	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<>	149:156823d33999	1330	}
<>	149:156823d33999	1331
<>	149:156823d33999	1332	/**
<>	149:156823d33999	1333	* @brief Get Channel 1 half transfer flag.
<>	149:156823d33999	1334	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<>	149:156823d33999	1335	* @param DMAx DMAx Instance
<>	149:156823d33999	1336	* @retval State of bit (1 or 0).
<>	149:156823d33999	1337	*/
<>	149:156823d33999	1338	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1339	{
<>	149:156823d33999	1340	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<>	149:156823d33999	1341	}
<>	149:156823d33999	1342
<>	149:156823d33999	1343	/**
<>	149:156823d33999	1344	* @brief Get Channel 2 half transfer flag.
<>	149:156823d33999	1345	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<>	149:156823d33999	1346	* @param DMAx DMAx Instance
<>	149:156823d33999	1347	* @retval State of bit (1 or 0).
<>	149:156823d33999	1348	*/
<>	149:156823d33999	1349	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1350	{
<>	149:156823d33999	1351	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<>	149:156823d33999	1352	}
<>	149:156823d33999	1353
<>	149:156823d33999	1354	/**
<>	149:156823d33999	1355	* @brief Get Channel 3 half transfer flag.
<>	149:156823d33999	1356	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<>	149:156823d33999	1357	* @param DMAx DMAx Instance
<>	149:156823d33999	1358	* @retval State of bit (1 or 0).
<>	149:156823d33999	1359	*/
<>	149:156823d33999	1360	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1361	{
<>	149:156823d33999	1362	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<>	149:156823d33999	1363	}
<>	149:156823d33999	1364
<>	149:156823d33999	1365	/**
<>	149:156823d33999	1366	* @brief Get Channel 4 half transfer flag.
<>	149:156823d33999	1367	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<>	149:156823d33999	1368	* @param DMAx DMAx Instance
<>	149:156823d33999	1369	* @retval State of bit (1 or 0).
<>	149:156823d33999	1370	*/
<>	149:156823d33999	1371	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1372	{
<>	149:156823d33999	1373	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<>	149:156823d33999	1374	}
<>	149:156823d33999	1375
<>	149:156823d33999	1376	/**
<>	149:156823d33999	1377	* @brief Get Channel 5 half transfer flag.
<>	149:156823d33999	1378	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<>	149:156823d33999	1379	* @param DMAx DMAx Instance
<>	149:156823d33999	1380	* @retval State of bit (1 or 0).
<>	149:156823d33999	1381	*/
<>	149:156823d33999	1382	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1383	{
<>	149:156823d33999	1384	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<>	149:156823d33999	1385	}
<>	149:156823d33999	1386
<>	149:156823d33999	1387	/**
<>	149:156823d33999	1388	* @brief Get Channel 6 half transfer flag.
<>	149:156823d33999	1389	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<>	149:156823d33999	1390	* @param DMAx DMAx Instance
<>	149:156823d33999	1391	* @retval State of bit (1 or 0).
<>	149:156823d33999	1392	*/
<>	149:156823d33999	1393	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1394	{
<>	149:156823d33999	1395	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<>	149:156823d33999	1396	}
<>	149:156823d33999	1397
<>	149:156823d33999	1398	/**
<>	149:156823d33999	1399	* @brief Get Channel 7 half transfer flag.
<>	149:156823d33999	1400	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<>	149:156823d33999	1401	* @param DMAx DMAx Instance
<>	149:156823d33999	1402	* @retval State of bit (1 or 0).
<>	149:156823d33999	1403	*/
<>	149:156823d33999	1404	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1405	{
<>	149:156823d33999	1406	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<>	149:156823d33999	1407	}
<>	149:156823d33999	1408
<>	149:156823d33999	1409	/**
<>	149:156823d33999	1410	* @brief Get Channel 1 transfer error flag.
<>	149:156823d33999	1411	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<>	149:156823d33999	1412	* @param DMAx DMAx Instance
<>	149:156823d33999	1413	* @retval State of bit (1 or 0).
<>	149:156823d33999	1414	*/
<>	149:156823d33999	1415	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1416	{
<>	149:156823d33999	1417	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<>	149:156823d33999	1418	}
<>	149:156823d33999	1419
<>	149:156823d33999	1420	/**
<>	149:156823d33999	1421	* @brief Get Channel 2 transfer error flag.
<>	149:156823d33999	1422	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<>	149:156823d33999	1423	* @param DMAx DMAx Instance
<>	149:156823d33999	1424	* @retval State of bit (1 or 0).
<>	149:156823d33999	1425	*/
<>	149:156823d33999	1426	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1427	{
<>	149:156823d33999	1428	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<>	149:156823d33999	1429	}
<>	149:156823d33999	1430
<>	149:156823d33999	1431	/**
<>	149:156823d33999	1432	* @brief Get Channel 3 transfer error flag.
<>	149:156823d33999	1433	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<>	149:156823d33999	1434	* @param DMAx DMAx Instance
<>	149:156823d33999	1435	* @retval State of bit (1 or 0).
<>	149:156823d33999	1436	*/
<>	149:156823d33999	1437	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1438	{
<>	149:156823d33999	1439	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<>	149:156823d33999	1440	}
<>	149:156823d33999	1441
<>	149:156823d33999	1442	/**
<>	149:156823d33999	1443	* @brief Get Channel 4 transfer error flag.
<>	149:156823d33999	1444	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<>	149:156823d33999	1445	* @param DMAx DMAx Instance
<>	149:156823d33999	1446	* @retval State of bit (1 or 0).
<>	149:156823d33999	1447	*/
<>	149:156823d33999	1448	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1449	{
<>	149:156823d33999	1450	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<>	149:156823d33999	1451	}
<>	149:156823d33999	1452
<>	149:156823d33999	1453	/**
<>	149:156823d33999	1454	* @brief Get Channel 5 transfer error flag.
<>	149:156823d33999	1455	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<>	149:156823d33999	1456	* @param DMAx DMAx Instance
<>	149:156823d33999	1457	* @retval State of bit (1 or 0).
<>	149:156823d33999	1458	*/
<>	149:156823d33999	1459	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1460	{
<>	149:156823d33999	1461	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<>	149:156823d33999	1462	}
<>	149:156823d33999	1463
<>	149:156823d33999	1464	/**
<>	149:156823d33999	1465	* @brief Get Channel 6 transfer error flag.
<>	149:156823d33999	1466	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<>	149:156823d33999	1467	* @param DMAx DMAx Instance
<>	149:156823d33999	1468	* @retval State of bit (1 or 0).
<>	149:156823d33999	1469	*/
<>	149:156823d33999	1470	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1471	{
<>	149:156823d33999	1472	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<>	149:156823d33999	1473	}
<>	149:156823d33999	1474
<>	149:156823d33999	1475	/**
<>	149:156823d33999	1476	* @brief Get Channel 7 transfer error flag.
<>	149:156823d33999	1477	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<>	149:156823d33999	1478	* @param DMAx DMAx Instance
<>	149:156823d33999	1479	* @retval State of bit (1 or 0).
<>	149:156823d33999	1480	*/
<>	149:156823d33999	1481	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1482	{
<>	149:156823d33999	1483	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<>	149:156823d33999	1484	}
<>	149:156823d33999	1485
<>	149:156823d33999	1486	/**
<>	149:156823d33999	1487	* @brief Clear Channel 1 global interrupt flag.
<>	149:156823d33999	1488	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<>	149:156823d33999	1489	* @param DMAx DMAx Instance
<>	149:156823d33999	1490	* @retval None
<>	149:156823d33999	1491	*/
<>	149:156823d33999	1492	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1493	{
<>	149:156823d33999	1494	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
<>	149:156823d33999	1495	}
<>	149:156823d33999	1496
<>	149:156823d33999	1497	/**
<>	149:156823d33999	1498	* @brief Clear Channel 2 global interrupt flag.
<>	149:156823d33999	1499	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<>	149:156823d33999	1500	* @param DMAx DMAx Instance
<>	149:156823d33999	1501	* @retval None
<>	149:156823d33999	1502	*/
<>	149:156823d33999	1503	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1504	{
<>	149:156823d33999	1505	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
<>	149:156823d33999	1506	}
<>	149:156823d33999	1507
<>	149:156823d33999	1508	/**
<>	149:156823d33999	1509	* @brief Clear Channel 3 global interrupt flag.
<>	149:156823d33999	1510	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<>	149:156823d33999	1511	* @param DMAx DMAx Instance
<>	149:156823d33999	1512	* @retval None
<>	149:156823d33999	1513	*/
<>	149:156823d33999	1514	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1515	{
<>	149:156823d33999	1516	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
<>	149:156823d33999	1517	}
<>	149:156823d33999	1518
<>	149:156823d33999	1519	/**
<>	149:156823d33999	1520	* @brief Clear Channel 4 global interrupt flag.
<>	149:156823d33999	1521	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<>	149:156823d33999	1522	* @param DMAx DMAx Instance
<>	149:156823d33999	1523	* @retval None
<>	149:156823d33999	1524	*/
<>	149:156823d33999	1525	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1526	{
<>	149:156823d33999	1527	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
<>	149:156823d33999	1528	}
<>	149:156823d33999	1529
<>	149:156823d33999	1530	/**
<>	149:156823d33999	1531	* @brief Clear Channel 5 global interrupt flag.
<>	149:156823d33999	1532	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<>	149:156823d33999	1533	* @param DMAx DMAx Instance
<>	149:156823d33999	1534	* @retval None
<>	149:156823d33999	1535	*/
<>	149:156823d33999	1536	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1537	{
<>	149:156823d33999	1538	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
<>	149:156823d33999	1539	}
<>	149:156823d33999	1540
<>	149:156823d33999	1541	/**
<>	149:156823d33999	1542	* @brief Clear Channel 6 global interrupt flag.
<>	149:156823d33999	1543	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<>	149:156823d33999	1544	* @param DMAx DMAx Instance
<>	149:156823d33999	1545	* @retval None
<>	149:156823d33999	1546	*/
<>	149:156823d33999	1547	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1548	{
<>	149:156823d33999	1549	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
<>	149:156823d33999	1550	}
<>	149:156823d33999	1551
<>	149:156823d33999	1552	/**
<>	149:156823d33999	1553	* @brief Clear Channel 7 global interrupt flag.
<>	149:156823d33999	1554	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<>	149:156823d33999	1555	* @param DMAx DMAx Instance
<>	149:156823d33999	1556	* @retval None
<>	149:156823d33999	1557	*/
<>	149:156823d33999	1558	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1559	{
<>	149:156823d33999	1560	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
<>	149:156823d33999	1561	}
<>	149:156823d33999	1562
<>	149:156823d33999	1563	/**
<>	149:156823d33999	1564	* @brief Clear Channel 1 transfer complete flag.
<>	149:156823d33999	1565	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<>	149:156823d33999	1566	* @param DMAx DMAx Instance
<>	149:156823d33999	1567	* @retval None
<>	149:156823d33999	1568	*/
<>	149:156823d33999	1569	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1570	{
<>	149:156823d33999	1571	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
<>	149:156823d33999	1572	}
<>	149:156823d33999	1573
<>	149:156823d33999	1574	/**
<>	149:156823d33999	1575	* @brief Clear Channel 2 transfer complete flag.
<>	149:156823d33999	1576	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<>	149:156823d33999	1577	* @param DMAx DMAx Instance
<>	149:156823d33999	1578	* @retval None
<>	149:156823d33999	1579	*/
<>	149:156823d33999	1580	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1581	{
<>	149:156823d33999	1582	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
<>	149:156823d33999	1583	}
<>	149:156823d33999	1584
<>	149:156823d33999	1585	/**
<>	149:156823d33999	1586	* @brief Clear Channel 3 transfer complete flag.
<>	149:156823d33999	1587	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<>	149:156823d33999	1588	* @param DMAx DMAx Instance
<>	149:156823d33999	1589	* @retval None
<>	149:156823d33999	1590	*/
<>	149:156823d33999	1591	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1592	{
<>	149:156823d33999	1593	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
<>	149:156823d33999	1594	}
<>	149:156823d33999	1595
<>	149:156823d33999	1596	/**
<>	149:156823d33999	1597	* @brief Clear Channel 4 transfer complete flag.
<>	149:156823d33999	1598	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<>	149:156823d33999	1599	* @param DMAx DMAx Instance
<>	149:156823d33999	1600	* @retval None
<>	149:156823d33999	1601	*/
<>	149:156823d33999	1602	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1603	{
<>	149:156823d33999	1604	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
<>	149:156823d33999	1605	}
<>	149:156823d33999	1606
<>	149:156823d33999	1607	/**
<>	149:156823d33999	1608	* @brief Clear Channel 5 transfer complete flag.
<>	149:156823d33999	1609	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<>	149:156823d33999	1610	* @param DMAx DMAx Instance
<>	149:156823d33999	1611	* @retval None
<>	149:156823d33999	1612	*/
<>	149:156823d33999	1613	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1614	{
<>	149:156823d33999	1615	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
<>	149:156823d33999	1616	}
<>	149:156823d33999	1617
<>	149:156823d33999	1618	/**
<>	149:156823d33999	1619	* @brief Clear Channel 6 transfer complete flag.
<>	149:156823d33999	1620	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<>	149:156823d33999	1621	* @param DMAx DMAx Instance
<>	149:156823d33999	1622	* @retval None
<>	149:156823d33999	1623	*/
<>	149:156823d33999	1624	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1625	{
<>	149:156823d33999	1626	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
<>	149:156823d33999	1627	}
<>	149:156823d33999	1628
<>	149:156823d33999	1629	/**
<>	149:156823d33999	1630	* @brief Clear Channel 7 transfer complete flag.
<>	149:156823d33999	1631	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<>	149:156823d33999	1632	* @param DMAx DMAx Instance
<>	149:156823d33999	1633	* @retval None
<>	149:156823d33999	1634	*/
<>	149:156823d33999	1635	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1636	{
<>	149:156823d33999	1637	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
<>	149:156823d33999	1638	}
<>	149:156823d33999	1639
<>	149:156823d33999	1640	/**
<>	149:156823d33999	1641	* @brief Clear Channel 1 half transfer flag.
<>	149:156823d33999	1642	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<>	149:156823d33999	1643	* @param DMAx DMAx Instance
<>	149:156823d33999	1644	* @retval None
<>	149:156823d33999	1645	*/
<>	149:156823d33999	1646	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1647	{
<>	149:156823d33999	1648	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
<>	149:156823d33999	1649	}
<>	149:156823d33999	1650
<>	149:156823d33999	1651	/**
<>	149:156823d33999	1652	* @brief Clear Channel 2 half transfer flag.
<>	149:156823d33999	1653	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<>	149:156823d33999	1654	* @param DMAx DMAx Instance
<>	149:156823d33999	1655	* @retval None
<>	149:156823d33999	1656	*/
<>	149:156823d33999	1657	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1658	{
<>	149:156823d33999	1659	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
<>	149:156823d33999	1660	}
<>	149:156823d33999	1661
<>	149:156823d33999	1662	/**
<>	149:156823d33999	1663	* @brief Clear Channel 3 half transfer flag.
<>	149:156823d33999	1664	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<>	149:156823d33999	1665	* @param DMAx DMAx Instance
<>	149:156823d33999	1666	* @retval None
<>	149:156823d33999	1667	*/
<>	149:156823d33999	1668	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1669	{
<>	149:156823d33999	1670	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
<>	149:156823d33999	1671	}
<>	149:156823d33999	1672
<>	149:156823d33999	1673	/**
<>	149:156823d33999	1674	* @brief Clear Channel 4 half transfer flag.
<>	149:156823d33999	1675	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<>	149:156823d33999	1676	* @param DMAx DMAx Instance
<>	149:156823d33999	1677	* @retval None
<>	149:156823d33999	1678	*/
<>	149:156823d33999	1679	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1680	{
<>	149:156823d33999	1681	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
<>	149:156823d33999	1682	}
<>	149:156823d33999	1683
<>	149:156823d33999	1684	/**
<>	149:156823d33999	1685	* @brief Clear Channel 5 half transfer flag.
<>	149:156823d33999	1686	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<>	149:156823d33999	1687	* @param DMAx DMAx Instance
<>	149:156823d33999	1688	* @retval None
<>	149:156823d33999	1689	*/
<>	149:156823d33999	1690	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1691	{
<>	149:156823d33999	1692	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
<>	149:156823d33999	1693	}
<>	149:156823d33999	1694
<>	149:156823d33999	1695	/**
<>	149:156823d33999	1696	* @brief Clear Channel 6 half transfer flag.
<>	149:156823d33999	1697	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<>	149:156823d33999	1698	* @param DMAx DMAx Instance
<>	149:156823d33999	1699	* @retval None
<>	149:156823d33999	1700	*/
<>	149:156823d33999	1701	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1702	{
<>	149:156823d33999	1703	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
<>	149:156823d33999	1704	}
<>	149:156823d33999	1705
<>	149:156823d33999	1706	/**
<>	149:156823d33999	1707	* @brief Clear Channel 7 half transfer flag.
<>	149:156823d33999	1708	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<>	149:156823d33999	1709	* @param DMAx DMAx Instance
<>	149:156823d33999	1710	* @retval None
<>	149:156823d33999	1711	*/
<>	149:156823d33999	1712	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1713	{
<>	149:156823d33999	1714	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
<>	149:156823d33999	1715	}
<>	149:156823d33999	1716
<>	149:156823d33999	1717	/**
<>	149:156823d33999	1718	* @brief Clear Channel 1 transfer error flag.
<>	149:156823d33999	1719	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<>	149:156823d33999	1720	* @param DMAx DMAx Instance
<>	149:156823d33999	1721	* @retval None
<>	149:156823d33999	1722	*/
<>	149:156823d33999	1723	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1724	{
<>	149:156823d33999	1725	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
<>	149:156823d33999	1726	}
<>	149:156823d33999	1727
<>	149:156823d33999	1728	/**
<>	149:156823d33999	1729	* @brief Clear Channel 2 transfer error flag.
<>	149:156823d33999	1730	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<>	149:156823d33999	1731	* @param DMAx DMAx Instance
<>	149:156823d33999	1732	* @retval None
<>	149:156823d33999	1733	*/
<>	149:156823d33999	1734	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1735	{
<>	149:156823d33999	1736	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
<>	149:156823d33999	1737	}
<>	149:156823d33999	1738
<>	149:156823d33999	1739	/**
<>	149:156823d33999	1740	* @brief Clear Channel 3 transfer error flag.
<>	149:156823d33999	1741	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<>	149:156823d33999	1742	* @param DMAx DMAx Instance
<>	149:156823d33999	1743	* @retval None
<>	149:156823d33999	1744	*/
<>	149:156823d33999	1745	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1746	{
<>	149:156823d33999	1747	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
<>	149:156823d33999	1748	}
<>	149:156823d33999	1749
<>	149:156823d33999	1750	/**
<>	149:156823d33999	1751	* @brief Clear Channel 4 transfer error flag.
<>	149:156823d33999	1752	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<>	149:156823d33999	1753	* @param DMAx DMAx Instance
<>	149:156823d33999	1754	* @retval None
<>	149:156823d33999	1755	*/
<>	149:156823d33999	1756	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1757	{
<>	149:156823d33999	1758	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
<>	149:156823d33999	1759	}
<>	149:156823d33999	1760
<>	149:156823d33999	1761	/**
<>	149:156823d33999	1762	* @brief Clear Channel 5 transfer error flag.
<>	149:156823d33999	1763	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<>	149:156823d33999	1764	* @param DMAx DMAx Instance
<>	149:156823d33999	1765	* @retval None
<>	149:156823d33999	1766	*/
<>	149:156823d33999	1767	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1768	{
<>	149:156823d33999	1769	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
<>	149:156823d33999	1770	}
<>	149:156823d33999	1771
<>	149:156823d33999	1772	/**
<>	149:156823d33999	1773	* @brief Clear Channel 6 transfer error flag.
<>	149:156823d33999	1774	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<>	149:156823d33999	1775	* @param DMAx DMAx Instance
<>	149:156823d33999	1776	* @retval None
<>	149:156823d33999	1777	*/
<>	149:156823d33999	1778	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1779	{
<>	149:156823d33999	1780	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
<>	149:156823d33999	1781	}
<>	149:156823d33999	1782
<>	149:156823d33999	1783	/**
<>	149:156823d33999	1784	* @brief Clear Channel 7 transfer error flag.
<>	149:156823d33999	1785	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<>	149:156823d33999	1786	* @param DMAx DMAx Instance
<>	149:156823d33999	1787	* @retval None
<>	149:156823d33999	1788	*/
<>	149:156823d33999	1789	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1790	{
<>	149:156823d33999	1791	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
<>	149:156823d33999	1792	}
<>	149:156823d33999	1793
<>	149:156823d33999	1794	/**
<>	149:156823d33999	1795	* @}
<>	149:156823d33999	1796	*/
<>	149:156823d33999	1797
<>	149:156823d33999	1798	/** @defgroup DMA_LL_EF_IT_Management IT_Management
<>	149:156823d33999	1799	* @{
<>	149:156823d33999	1800	*/
<>	149:156823d33999	1801	/**
<>	149:156823d33999	1802	* @brief Enable Transfer complete interrupt.
<>	149:156823d33999	1803	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<>	149:156823d33999	1804	* @param DMAx DMAx Instance
<>	149:156823d33999	1805	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1806	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1807	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1808	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1809	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1810	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1811	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1812	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1813	* @retval None
<>	149:156823d33999	1814	*/
<>	149:156823d33999	1815	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1816	{
<>	149:156823d33999	1817	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	149:156823d33999	1818	}
<>	149:156823d33999	1819
<>	149:156823d33999	1820	/**
<>	149:156823d33999	1821	* @brief Enable Half transfer interrupt.
<>	149:156823d33999	1822	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<>	149:156823d33999	1823	* @param DMAx DMAx Instance
<>	149:156823d33999	1824	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1825	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1826	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1827	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1828	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1829	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1830	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1831	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1832	* @retval None
<>	149:156823d33999	1833	*/
<>	149:156823d33999	1834	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1835	{
<>	149:156823d33999	1836	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	149:156823d33999	1837	}
<>	149:156823d33999	1838
<>	149:156823d33999	1839	/**
<>	149:156823d33999	1840	* @brief Enable Transfer error interrupt.
<>	149:156823d33999	1841	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<>	149:156823d33999	1842	* @param DMAx DMAx Instance
<>	149:156823d33999	1843	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1844	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1845	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1846	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1847	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1848	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1849	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1850	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1851	* @retval None
<>	149:156823d33999	1852	*/
<>	149:156823d33999	1853	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1854	{
<>	149:156823d33999	1855	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	149:156823d33999	1856	}
<>	149:156823d33999	1857
<>	149:156823d33999	1858	/**
<>	149:156823d33999	1859	* @brief Disable Transfer complete interrupt.
<>	149:156823d33999	1860	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<>	149:156823d33999	1861	* @param DMAx DMAx Instance
<>	149:156823d33999	1862	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1863	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1864	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1865	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1866	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1867	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1868	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1869	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1870	* @retval None
<>	149:156823d33999	1871	*/
<>	149:156823d33999	1872	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1873	{
<>	149:156823d33999	1874	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	149:156823d33999	1875	}
<>	149:156823d33999	1876
<>	149:156823d33999	1877	/**
<>	149:156823d33999	1878	* @brief Disable Half transfer interrupt.
<>	149:156823d33999	1879	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<>	149:156823d33999	1880	* @param DMAx DMAx Instance
<>	149:156823d33999	1881	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1882	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1883	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1884	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1885	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1886	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1887	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1888	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1889	* @retval None
<>	149:156823d33999	1890	*/
<>	149:156823d33999	1891	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1892	{
<>	149:156823d33999	1893	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	149:156823d33999	1894	}
<>	149:156823d33999	1895
<>	149:156823d33999	1896	/**
<>	149:156823d33999	1897	* @brief Disable Transfer error interrupt.
<>	149:156823d33999	1898	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<>	149:156823d33999	1899	* @param DMAx DMAx Instance
<>	149:156823d33999	1900	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1901	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1902	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1903	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1904	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1905	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1906	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1907	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1908	* @retval None
<>	149:156823d33999	1909	*/
<>	149:156823d33999	1910	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1911	{
<>	149:156823d33999	1912	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	149:156823d33999	1913	}
<>	149:156823d33999	1914
<>	149:156823d33999	1915	/**
<>	149:156823d33999	1916	* @brief Check if Transfer complete Interrupt is enabled.
<>	149:156823d33999	1917	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<>	149:156823d33999	1918	* @param DMAx DMAx Instance
<>	149:156823d33999	1919	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1920	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1921	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1922	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1923	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1924	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1925	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1926	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1927	* @retval State of bit (1 or 0).
<>	149:156823d33999	1928	*/
<>	149:156823d33999	1929	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1930	{
<>	149:156823d33999	1931	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	1932	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<>	149:156823d33999	1933	}
<>	149:156823d33999	1934
<>	149:156823d33999	1935	/**
<>	149:156823d33999	1936	* @brief Check if Half transfer Interrupt is enabled.
<>	149:156823d33999	1937	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<>	149:156823d33999	1938	* @param DMAx DMAx Instance
<>	149:156823d33999	1939	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1940	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1941	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1942	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1943	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1944	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1945	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1946	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1947	* @retval State of bit (1 or 0).
<>	149:156823d33999	1948	*/
<>	149:156823d33999	1949	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1950	{
<>	149:156823d33999	1951	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	1952	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<>	149:156823d33999	1953	}
<>	149:156823d33999	1954
<>	149:156823d33999	1955	/**
<>	149:156823d33999	1956	* @brief Check if Transfer error Interrupt is enabled.
<>	149:156823d33999	1957	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<>	149:156823d33999	1958	* @param DMAx DMAx Instance
<>	149:156823d33999	1959	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1960	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1961	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1962	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1963	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1964	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1965	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1966	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1967	* @retval State of bit (1 or 0).
<>	149:156823d33999	1968	*/
<>	149:156823d33999	1969	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1970	{
<>	149:156823d33999	1971	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	1972	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<>	149:156823d33999	1973	}
<>	149:156823d33999	1974
<>	149:156823d33999	1975	/**
<>	149:156823d33999	1976	* @}
<>	149:156823d33999	1977	*/
<>	149:156823d33999	1978
<>	149:156823d33999	1979	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	1980	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<>	149:156823d33999	1981	* @{
<>	149:156823d33999	1982	*/
<>	149:156823d33999	1983
<>	149:156823d33999	1984	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
<>	149:156823d33999	1985	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<>	149:156823d33999	1986	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<>	149:156823d33999	1987
<>	149:156823d33999	1988	/**
<>	149:156823d33999	1989	* @}
<>	149:156823d33999	1990	*/
<>	149:156823d33999	1991	#endif /* USE_FULL_LL_DRIVER */
<>	149:156823d33999	1992
<>	149:156823d33999	1993	/**
<>	149:156823d33999	1994	* @}
<>	149:156823d33999	1995	*/
<>	149:156823d33999	1996
<>	149:156823d33999	1997	/**
<>	149:156823d33999	1998	* @}
<>	149:156823d33999	1999	*/
<>	149:156823d33999	2000
<>	149:156823d33999	2001	#endif /* DMA1 \|\| DMA2 */
<>	149:156823d33999	2002
<>	149:156823d33999	2003	/**
<>	149:156823d33999	2004	* @}
<>	149:156823d33999	2005	*/
<>	149:156823d33999	2006
<>	149:156823d33999	2007	#ifdef __cplusplus
<>	149:156823d33999	2008	}
<>	149:156823d33999	2009	#endif
<>	149:156823d33999	2010
<>	149:156823d33999	2011	#endif /* __STM32L1xx_LL_DMA_H */
<>	149:156823d33999	2012
<>	149:156823d33999	2013	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/