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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dma.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Child:: 184:08ed48f1de7f

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_ll_dma.h
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @version V1.2.0
<>	149:156823d33999	6	* @date 01-July-2016
<>	149:156823d33999	7	* @brief Header file of DMA LL module.
<>	149:156823d33999	8	******************************************************************************
<>	149:156823d33999	9	* @attention
<>	149:156823d33999	10	*
<>	149:156823d33999	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	149:156823d33999	12	*
<>	149:156823d33999	13	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	14	* are permitted provided that the following conditions are met:
<>	149:156823d33999	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	16	* this list of conditions and the following disclaimer.
<>	149:156823d33999	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	18	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	19	* and/or other materials provided with the distribution.
<>	149:156823d33999	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	21	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	22	* without specific prior written permission.
<>	149:156823d33999	23	*
<>	149:156823d33999	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	34	*
<>	149:156823d33999	35	******************************************************************************
<>	149:156823d33999	36	*/
<>	149:156823d33999	37
<>	149:156823d33999	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	149:156823d33999	39	#ifndef __STM32L1xx_LL_DMA_H
<>	149:156823d33999	40	#define __STM32L1xx_LL_DMA_H
<>	149:156823d33999	41
<>	149:156823d33999	42	#ifdef __cplusplus
<>	149:156823d33999	43	extern "C" {
<>	149:156823d33999	44	#endif
<>	149:156823d33999	45
<>	149:156823d33999	46	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	47	#include "stm32l1xx.h"
<>	149:156823d33999	48
<>	149:156823d33999	49	/** @addtogroup STM32L1xx_LL_Driver
<>	149:156823d33999	50	* @{
<>	149:156823d33999	51	*/
<>	149:156823d33999	52
<>	149:156823d33999	53	#if defined (DMA1) \|\| defined (DMA2)
<>	149:156823d33999	54
<>	149:156823d33999	55	/** @defgroup DMA_LL DMA
<>	149:156823d33999	56	* @{
<>	149:156823d33999	57	*/
<>	149:156823d33999	58
<>	149:156823d33999	59	/* Private types -------------------------------------------------------------*/
<>	149:156823d33999	60	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
<>	149:156823d33999	62	* @{
<>	149:156823d33999	63	*/
<>	149:156823d33999	64	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<>	149:156823d33999	65	static const uint8_t CHANNEL_OFFSET_TAB[] =
<>	149:156823d33999	66	{
<>	149:156823d33999	67	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<>	149:156823d33999	68	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<>	149:156823d33999	69	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<>	149:156823d33999	70	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<>	149:156823d33999	71	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<>	149:156823d33999	72	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<>	149:156823d33999	73	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<>	149:156823d33999	74	};
<>	149:156823d33999	75	/**
<>	149:156823d33999	76	* @}
<>	149:156823d33999	77	*/
<>	149:156823d33999	78
<>	149:156823d33999	79	/* Private constants ---------------------------------------------------------*/
<>	149:156823d33999	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
<>	149:156823d33999	81	* @{
<>	149:156823d33999	82	*/
<>	149:156823d33999	83	/* Define used to get CSELR register offset */
<>	149:156823d33999	84	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
<>	149:156823d33999	85
<>	149:156823d33999	86	/* Defines used for the bit position in the register and perform offsets */
<>	149:156823d33999	87	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
<>	149:156823d33999	88	/**
<>	149:156823d33999	89	* @}
<>	149:156823d33999	90	*/
<>	149:156823d33999	91
<>	149:156823d33999	92	/* Private macros ------------------------------------------------------------*/
<>	149:156823d33999	93	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	94	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
<>	149:156823d33999	95	* @{
<>	149:156823d33999	96	*/
<>	149:156823d33999	97	/**
<>	149:156823d33999	98	* @}
<>	149:156823d33999	99	*/
<>	149:156823d33999	100	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	101
<>	149:156823d33999	102	/* Exported types ------------------------------------------------------------*/
<>	149:156823d33999	103	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	104	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<>	149:156823d33999	105	* @{
<>	149:156823d33999	106	*/
<>	149:156823d33999	107	typedef struct
<>	149:156823d33999	108	{
<>	149:156823d33999	109	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<>	149:156823d33999	110	or as Source base address in case of memory to memory transfer direction.
<>	149:156823d33999	111
<>	149:156823d33999	112	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	149:156823d33999	113
<>	149:156823d33999	114	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<>	149:156823d33999	115	or as Destination base address in case of memory to memory transfer direction.
<>	149:156823d33999	116
<>	149:156823d33999	117	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	149:156823d33999	118
<>	149:156823d33999	119	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<>	149:156823d33999	120	from memory to memory or from peripheral to memory.
<>	149:156823d33999	121	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<>	149:156823d33999	122
<>	149:156823d33999	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<>	149:156823d33999	124
<>	149:156823d33999	125	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<>	149:156823d33999	126	This parameter can be a value of @ref DMA_LL_EC_MODE
<>	149:156823d33999	127	@note: The circular buffer mode cannot be used if the memory to memory
<>	149:156823d33999	128	data transfer direction is configured on the selected Channel
<>	149:156823d33999	129
<>	149:156823d33999	130	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<>	149:156823d33999	131
<>	149:156823d33999	132	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<>	149:156823d33999	133	is incremented or not.
<>	149:156823d33999	134	This parameter can be a value of @ref DMA_LL_EC_PERIPH
<>	149:156823d33999	135
<>	149:156823d33999	136	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<>	149:156823d33999	137
<>	149:156823d33999	138	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<>	149:156823d33999	139	is incremented or not.
<>	149:156823d33999	140	This parameter can be a value of @ref DMA_LL_EC_MEMORY
<>	149:156823d33999	141
<>	149:156823d33999	142	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<>	149:156823d33999	143
<>	149:156823d33999	144	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<>	149:156823d33999	145	in case of memory to memory transfer direction.
<>	149:156823d33999	146	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<>	149:156823d33999	147
<>	149:156823d33999	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<>	149:156823d33999	149
<>	149:156823d33999	150	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<>	149:156823d33999	151	in case of memory to memory transfer direction.
<>	149:156823d33999	152	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<>	149:156823d33999	153
<>	149:156823d33999	154	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<>	149:156823d33999	155
<>	149:156823d33999	156	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<>	149:156823d33999	157	The data unit is equal to the source buffer configuration set in PeripheralSize
<>	149:156823d33999	158	or MemorySize parameters depending in the transfer direction.
<>	149:156823d33999	159	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	149:156823d33999	160
<>	149:156823d33999	161	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<>	149:156823d33999	162
<>	149:156823d33999	163	uint32_t Priority; /*!< Specifies the channel priority level.
<>	149:156823d33999	164	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<>	149:156823d33999	165
<>	149:156823d33999	166	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<>	149:156823d33999	167
<>	149:156823d33999	168	} LL_DMA_InitTypeDef;
<>	149:156823d33999	169	/**
<>	149:156823d33999	170	* @}
<>	149:156823d33999	171	*/
<>	149:156823d33999	172	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	173
<>	149:156823d33999	174	/* Exported constants --------------------------------------------------------*/
<>	149:156823d33999	175	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<>	149:156823d33999	176	* @{
<>	149:156823d33999	177	*/
<>	149:156823d33999	178	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	149:156823d33999	179	* @brief Flags defines which can be used with LL_DMA_WriteReg function
<>	149:156823d33999	180	* @{
<>	149:156823d33999	181	*/
<>	149:156823d33999	182	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
<>	149:156823d33999	183	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
<>	149:156823d33999	184	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
<>	149:156823d33999	185	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
<>	149:156823d33999	186	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
<>	149:156823d33999	187	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
<>	149:156823d33999	188	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
<>	149:156823d33999	189	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
<>	149:156823d33999	190	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
<>	149:156823d33999	191	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
<>	149:156823d33999	192	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
<>	149:156823d33999	193	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
<>	149:156823d33999	194	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
<>	149:156823d33999	195	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
<>	149:156823d33999	196	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
<>	149:156823d33999	197	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
<>	149:156823d33999	198	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
<>	149:156823d33999	199	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
<>	149:156823d33999	200	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
<>	149:156823d33999	201	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
<>	149:156823d33999	202	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
<>	149:156823d33999	203	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
<>	149:156823d33999	204	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
<>	149:156823d33999	205	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
<>	149:156823d33999	206	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
<>	149:156823d33999	207	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
<>	149:156823d33999	208	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
<>	149:156823d33999	209	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
<>	149:156823d33999	210	/**
<>	149:156823d33999	211	* @}
<>	149:156823d33999	212	*/
<>	149:156823d33999	213
<>	149:156823d33999	214	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<>	149:156823d33999	215	* @brief Flags defines which can be used with LL_DMA_ReadReg function
<>	149:156823d33999	216	* @{
<>	149:156823d33999	217	*/
<>	149:156823d33999	218	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
<>	149:156823d33999	219	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
<>	149:156823d33999	220	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
<>	149:156823d33999	221	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
<>	149:156823d33999	222	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
<>	149:156823d33999	223	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
<>	149:156823d33999	224	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
<>	149:156823d33999	225	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
<>	149:156823d33999	226	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
<>	149:156823d33999	227	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
<>	149:156823d33999	228	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
<>	149:156823d33999	229	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
<>	149:156823d33999	230	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
<>	149:156823d33999	231	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
<>	149:156823d33999	232	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
<>	149:156823d33999	233	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
<>	149:156823d33999	234	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
<>	149:156823d33999	235	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
<>	149:156823d33999	236	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
<>	149:156823d33999	237	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
<>	149:156823d33999	238	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
<>	149:156823d33999	239	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
<>	149:156823d33999	240	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
<>	149:156823d33999	241	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
<>	149:156823d33999	242	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
<>	149:156823d33999	243	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
<>	149:156823d33999	244	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
<>	149:156823d33999	245	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
<>	149:156823d33999	246	/**
<>	149:156823d33999	247	* @}
<>	149:156823d33999	248	*/
<>	149:156823d33999	249
<>	149:156823d33999	250	/** @defgroup DMA_LL_EC_IT IT Defines
<>	149:156823d33999	251	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<>	149:156823d33999	252	* @{
<>	149:156823d33999	253	*/
<>	149:156823d33999	254	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
<>	149:156823d33999	255	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
<>	149:156823d33999	256	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
<>	149:156823d33999	257	/**
<>	149:156823d33999	258	* @}
<>	149:156823d33999	259	*/
<>	149:156823d33999	260
<>	149:156823d33999	261	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<>	149:156823d33999	262	* @{
<>	149:156823d33999	263	*/
<>	149:156823d33999	264	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
<>	149:156823d33999	265	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
<>	149:156823d33999	266	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
<>	149:156823d33999	267	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
<>	149:156823d33999	268	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
<>	149:156823d33999	269	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
<>	149:156823d33999	270	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
<>	149:156823d33999	271	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	272	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
<>	149:156823d33999	273	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	274	/**
<>	149:156823d33999	275	* @}
<>	149:156823d33999	276	*/
<>	149:156823d33999	277
<>	149:156823d33999	278	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<>	149:156823d33999	279	* @{
<>	149:156823d33999	280	*/
<>	149:156823d33999	281	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
<>	149:156823d33999	282	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
<>	149:156823d33999	283	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
<>	149:156823d33999	284	/**
<>	149:156823d33999	285	* @}
<>	149:156823d33999	286	*/
<>	149:156823d33999	287
<>	149:156823d33999	288	/** @defgroup DMA_LL_EC_MODE Transfer mode
<>	149:156823d33999	289	* @{
<>	149:156823d33999	290	*/
<>	149:156823d33999	291	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
<>	149:156823d33999	292	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
<>	149:156823d33999	293	/**
<>	149:156823d33999	294	* @}
<>	149:156823d33999	295	*/
<>	149:156823d33999	296
<>	149:156823d33999	297	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<>	149:156823d33999	298	* @{
<>	149:156823d33999	299	*/
<>	149:156823d33999	300	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
<>	149:156823d33999	301	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
<>	149:156823d33999	302	/**
<>	149:156823d33999	303	* @}
<>	149:156823d33999	304	*/
<>	149:156823d33999	305
<>	149:156823d33999	306	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<>	149:156823d33999	307	* @{
<>	149:156823d33999	308	*/
<>	149:156823d33999	309	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
<>	149:156823d33999	310	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
<>	149:156823d33999	311	/**
<>	149:156823d33999	312	* @}
<>	149:156823d33999	313	*/
<>	149:156823d33999	314
<>	149:156823d33999	315	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<>	149:156823d33999	316	* @{
<>	149:156823d33999	317	*/
<>	149:156823d33999	318	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
<>	149:156823d33999	319	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
<>	149:156823d33999	320	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
<>	149:156823d33999	321	/**
<>	149:156823d33999	322	* @}
<>	149:156823d33999	323	*/
<>	149:156823d33999	324
<>	149:156823d33999	325	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<>	149:156823d33999	326	* @{
<>	149:156823d33999	327	*/
<>	149:156823d33999	328	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
<>	149:156823d33999	329	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
<>	149:156823d33999	330	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
<>	149:156823d33999	331	/**
<>	149:156823d33999	332	* @}
<>	149:156823d33999	333	*/
<>	149:156823d33999	334
<>	149:156823d33999	335	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<>	149:156823d33999	336	* @{
<>	149:156823d33999	337	*/
<>	149:156823d33999	338	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
<>	149:156823d33999	339	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
<>	149:156823d33999	340	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
<>	149:156823d33999	341	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
<>	149:156823d33999	342	/**
<>	149:156823d33999	343	* @}
<>	149:156823d33999	344	*/
<>	149:156823d33999	345
<>	149:156823d33999	346
<>	149:156823d33999	347	/**
<>	149:156823d33999	348	* @}
<>	149:156823d33999	349	*/
<>	149:156823d33999	350
<>	149:156823d33999	351	/* Exported macro ------------------------------------------------------------*/
<>	149:156823d33999	352	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<>	149:156823d33999	353	* @{
<>	149:156823d33999	354	*/
<>	149:156823d33999	355
<>	149:156823d33999	356	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<>	149:156823d33999	357	* @{
<>	149:156823d33999	358	*/
<>	149:156823d33999	359	/**
<>	149:156823d33999	360	* @brief Write a value in DMA register
<>	149:156823d33999	361	* @param __INSTANCE__ DMA Instance
<>	149:156823d33999	362	* @param __REG__ Register to be written
<>	149:156823d33999	363	* @param __VALUE__ Value to be written in the register
<>	149:156823d33999	364	* @retval None
<>	149:156823d33999	365	*/
<>	149:156823d33999	366	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	149:156823d33999	367
<>	149:156823d33999	368	/**
<>	149:156823d33999	369	* @brief Read a value in DMA register
<>	149:156823d33999	370	* @param __INSTANCE__ DMA Instance
<>	149:156823d33999	371	* @param __REG__ Register to be read
<>	149:156823d33999	372	* @retval Register value
<>	149:156823d33999	373	*/
<>	149:156823d33999	374	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	149:156823d33999	375	/**
<>	149:156823d33999	376	* @}
<>	149:156823d33999	377	*/
<>	149:156823d33999	378
<>	149:156823d33999	379	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<>	149:156823d33999	380	* @{
<>	149:156823d33999	381	*/
<>	149:156823d33999	382	/**
<>	149:156823d33999	383	* @brief Convert DMAx_Channely into DMAx
<>	149:156823d33999	384	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	149:156823d33999	385	* @retval DMAx
<>	149:156823d33999	386	*/
<>	149:156823d33999	387	#if defined(DMA2)
<>	149:156823d33999	388	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	389	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<>	149:156823d33999	390	#else
<>	149:156823d33999	391	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<>	149:156823d33999	392	#endif
<>	149:156823d33999	393
<>	149:156823d33999	394	/**
<>	149:156823d33999	395	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<>	149:156823d33999	396	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	149:156823d33999	397	* @retval LL_DMA_CHANNEL_y
<>	149:156823d33999	398	*/
<>	149:156823d33999	399	#if defined (DMA2)
<>	149:156823d33999	400	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	149:156823d33999	401	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	402	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	403	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	404	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	405	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	406	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	407	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	408	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	409	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	410	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	411	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	412	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	413	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	414	LL_DMA_CHANNEL_7)
<>	149:156823d33999	415	#else
<>	149:156823d33999	416	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	417	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	418	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	419	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	420	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	421	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	425	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	426	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	427	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	428	LL_DMA_CHANNEL_7)
<>	149:156823d33999	429	#endif
<>	149:156823d33999	430	#else
<>	149:156823d33999	431	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	149:156823d33999	432	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	149:156823d33999	433	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	149:156823d33999	434	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	149:156823d33999	435	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	149:156823d33999	436	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	149:156823d33999	437	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	149:156823d33999	438	LL_DMA_CHANNEL_7)
<>	149:156823d33999	439	#endif
<>	149:156823d33999	440
<>	149:156823d33999	441	/**
<>	149:156823d33999	442	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<>	149:156823d33999	443	* @param __DMA_INSTANCE__ DMAx
<>	149:156823d33999	444	* @param __CHANNEL__ LL_DMA_CHANNEL_y
<>	149:156823d33999	445	* @retval DMAx_Channely
<>	149:156823d33999	446	*/
<>	149:156823d33999	447	#if defined (DMA2)
<>	149:156823d33999	448	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	149:156823d33999	449	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	149:156823d33999	450	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	149:156823d33999	451	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	149:156823d33999	452	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	149:156823d33999	453	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	149:156823d33999	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	149:156823d33999	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	149:156823d33999	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	149:156823d33999	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	149:156823d33999	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	149:156823d33999	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	149:156823d33999	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	149:156823d33999	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<>	149:156823d33999	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<>	149:156823d33999	463	DMA2_Channel7)
<>	149:156823d33999	464	#else
<>	149:156823d33999	465	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	149:156823d33999	466	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	149:156823d33999	467	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	149:156823d33999	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	149:156823d33999	469	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	149:156823d33999	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	149:156823d33999	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	149:156823d33999	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	149:156823d33999	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	149:156823d33999	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	149:156823d33999	475	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	149:156823d33999	476	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	149:156823d33999	477	DMA1_Channel7)
<>	149:156823d33999	478	#endif
<>	149:156823d33999	479	#else
<>	149:156823d33999	480	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	149:156823d33999	481	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	149:156823d33999	482	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	149:156823d33999	483	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	149:156823d33999	484	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	149:156823d33999	485	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	149:156823d33999	486	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	149:156823d33999	487	DMA1_Channel7)
<>	149:156823d33999	488	#endif
<>	149:156823d33999	489
<>	149:156823d33999	490	/**
<>	149:156823d33999	491	* @}
<>	149:156823d33999	492	*/
<>	149:156823d33999	493
<>	149:156823d33999	494	/**
<>	149:156823d33999	495	* @}
<>	149:156823d33999	496	*/
<>	149:156823d33999	497
<>	149:156823d33999	498	/* Exported functions --------------------------------------------------------*/
<>	149:156823d33999	499	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<>	149:156823d33999	500	* @{
<>	149:156823d33999	501	*/
<>	149:156823d33999	502
<>	149:156823d33999	503	/** @defgroup DMA_LL_EF_Configuration Configuration
<>	149:156823d33999	504	* @{
<>	149:156823d33999	505	*/
<>	149:156823d33999	506	/**
<>	149:156823d33999	507	* @brief Enable DMA channel.
<>	149:156823d33999	508	* @rmtoll CCR EN LL_DMA_EnableChannel
<>	149:156823d33999	509	* @param DMAx DMAx Instance
<>	149:156823d33999	510	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	511	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	512	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	513	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	514	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	515	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	516	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	517	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	518	* @retval None
<>	149:156823d33999	519	*/
<>	149:156823d33999	520	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	521	{
<>	149:156823d33999	522	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	149:156823d33999	523	}
<>	149:156823d33999	524
<>	149:156823d33999	525	/**
<>	149:156823d33999	526	* @brief Disable DMA channel.
<>	149:156823d33999	527	* @rmtoll CCR EN LL_DMA_DisableChannel
<>	149:156823d33999	528	* @param DMAx DMAx Instance
<>	149:156823d33999	529	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	530	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	531	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	532	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	533	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	534	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	535	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	536	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	537	* @retval None
<>	149:156823d33999	538	*/
<>	149:156823d33999	539	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	540	{
<>	149:156823d33999	541	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	149:156823d33999	542	}
<>	149:156823d33999	543
<>	149:156823d33999	544	/**
<>	149:156823d33999	545	* @brief Check if DMA channel is enabled or disabled.
<>	149:156823d33999	546	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
<>	149:156823d33999	547	* @param DMAx DMAx Instance
<>	149:156823d33999	548	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	549	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	550	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	551	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	552	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	553	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	554	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	555	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	556	* @retval State of bit (1 or 0).
<>	149:156823d33999	557	*/
<>	149:156823d33999	558	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	559	{
<>	149:156823d33999	560	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	561	DMA_CCR_EN) == (DMA_CCR_EN));
<>	149:156823d33999	562	}
<>	149:156823d33999	563
<>	149:156823d33999	564	/**
<>	149:156823d33999	565	* @brief Configure all parameters link to DMA transfer.
<>	149:156823d33999	566	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<>	149:156823d33999	567	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
<>	149:156823d33999	568	* CCR CIRC LL_DMA_ConfigTransfer\n
<>	149:156823d33999	569	* CCR PINC LL_DMA_ConfigTransfer\n
<>	149:156823d33999	570	* CCR MINC LL_DMA_ConfigTransfer\n
<>	149:156823d33999	571	* CCR PSIZE LL_DMA_ConfigTransfer\n
<>	149:156823d33999	572	* CCR MSIZE LL_DMA_ConfigTransfer\n
<>	149:156823d33999	573	* CCR PL LL_DMA_ConfigTransfer
<>	149:156823d33999	574	* @param DMAx DMAx Instance
<>	149:156823d33999	575	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	576	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	577	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	578	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	579	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	580	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	581	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	582	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	583	* @param Configuration This parameter must be a combination of all the following values:
<>	149:156823d33999	584	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	585	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<>	149:156823d33999	586	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<>	149:156823d33999	587	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<>	149:156823d33999	588	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<>	149:156823d33999	589	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<>	149:156823d33999	590	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<>	149:156823d33999	591	* @retval None
<>	149:156823d33999	592	*/
<>	149:156823d33999	593	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<>	149:156823d33999	594	{
<>	149:156823d33999	595	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	596	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
<>	149:156823d33999	597	Configuration);
<>	149:156823d33999	598	}
<>	149:156823d33999	599
<>	149:156823d33999	600	/**
<>	149:156823d33999	601	* @brief Set Data transfer direction (read from peripheral or from memory).
<>	149:156823d33999	602	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<>	149:156823d33999	603	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
<>	149:156823d33999	604	* @param DMAx DMAx Instance
<>	149:156823d33999	605	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	606	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	607	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	608	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	609	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	610	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	611	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	612	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	613	* @param Direction This parameter can be one of the following values:
<>	149:156823d33999	614	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	149:156823d33999	615	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	149:156823d33999	616	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	617	* @retval None
<>	149:156823d33999	618	*/
<>	149:156823d33999	619	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<>	149:156823d33999	620	{
<>	149:156823d33999	621	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	622	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
<>	149:156823d33999	623	}
<>	149:156823d33999	624
<>	149:156823d33999	625	/**
<>	149:156823d33999	626	* @brief Get Data transfer direction (read from peripheral or from memory).
<>	149:156823d33999	627	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<>	149:156823d33999	628	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
<>	149:156823d33999	629	* @param DMAx DMAx Instance
<>	149:156823d33999	630	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	631	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	632	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	633	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	634	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	635	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	636	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	637	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	638	* @retval Returned value can be one of the following values:
<>	149:156823d33999	639	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	149:156823d33999	640	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	149:156823d33999	641	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	642	*/
<>	149:156823d33999	643	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	644	{
<>	149:156823d33999	645	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	646	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
<>	149:156823d33999	647	}
<>	149:156823d33999	648
<>	149:156823d33999	649	/**
<>	149:156823d33999	650	* @brief Set DMA mode circular or normal.
<>	149:156823d33999	651	* @note The circular buffer mode cannot be used if the memory-to-memory
<>	149:156823d33999	652	* data transfer is configured on the selected Channel.
<>	149:156823d33999	653	* @rmtoll CCR CIRC LL_DMA_SetMode
<>	149:156823d33999	654	* @param DMAx DMAx Instance
<>	149:156823d33999	655	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	656	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	657	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	658	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	659	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	660	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	661	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	662	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	663	* @param Mode This parameter can be one of the following values:
<>	149:156823d33999	664	* @arg @ref LL_DMA_MODE_NORMAL
<>	149:156823d33999	665	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	149:156823d33999	666	* @retval None
<>	149:156823d33999	667	*/
<>	149:156823d33999	668	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<>	149:156823d33999	669	{
<>	149:156823d33999	670	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<>	149:156823d33999	671	Mode);
<>	149:156823d33999	672	}
<>	149:156823d33999	673
<>	149:156823d33999	674	/**
<>	149:156823d33999	675	* @brief Get DMA mode circular or normal.
<>	149:156823d33999	676	* @rmtoll CCR CIRC LL_DMA_GetMode
<>	149:156823d33999	677	* @param DMAx DMAx Instance
<>	149:156823d33999	678	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	679	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	680	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	681	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	682	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	683	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	684	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	685	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	686	* @retval Returned value can be one of the following values:
<>	149:156823d33999	687	* @arg @ref LL_DMA_MODE_NORMAL
<>	149:156823d33999	688	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	149:156823d33999	689	*/
<>	149:156823d33999	690	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	691	{
<>	149:156823d33999	692	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	693	DMA_CCR_CIRC));
<>	149:156823d33999	694	}
<>	149:156823d33999	695
<>	149:156823d33999	696	/**
<>	149:156823d33999	697	* @brief Set Peripheral increment mode.
<>	149:156823d33999	698	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<>	149:156823d33999	699	* @param DMAx DMAx Instance
<>	149:156823d33999	700	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	701	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	702	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	703	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	704	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	705	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	706	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	707	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	708	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<>	149:156823d33999	709	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	149:156823d33999	710	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	149:156823d33999	711	* @retval None
<>	149:156823d33999	712	*/
<>	149:156823d33999	713	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<>	149:156823d33999	714	{
<>	149:156823d33999	715	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<>	149:156823d33999	716	PeriphOrM2MSrcIncMode);
<>	149:156823d33999	717	}
<>	149:156823d33999	718
<>	149:156823d33999	719	/**
<>	149:156823d33999	720	* @brief Get Peripheral increment mode.
<>	149:156823d33999	721	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<>	149:156823d33999	722	* @param DMAx DMAx Instance
<>	149:156823d33999	723	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	724	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	725	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	726	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	727	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	728	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	729	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	730	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	731	* @retval Returned value can be one of the following values:
<>	149:156823d33999	732	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	149:156823d33999	733	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	149:156823d33999	734	*/
<>	149:156823d33999	735	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	736	{
<>	149:156823d33999	737	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	738	DMA_CCR_PINC));
<>	149:156823d33999	739	}
<>	149:156823d33999	740
<>	149:156823d33999	741	/**
<>	149:156823d33999	742	* @brief Set Memory increment mode.
<>	149:156823d33999	743	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<>	149:156823d33999	744	* @param DMAx DMAx Instance
<>	149:156823d33999	745	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	746	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	747	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	748	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	749	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	750	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	751	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	752	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	753	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<>	149:156823d33999	754	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	149:156823d33999	755	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	149:156823d33999	756	* @retval None
<>	149:156823d33999	757	*/
<>	149:156823d33999	758	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<>	149:156823d33999	759	{
<>	149:156823d33999	760	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<>	149:156823d33999	761	MemoryOrM2MDstIncMode);
<>	149:156823d33999	762	}
<>	149:156823d33999	763
<>	149:156823d33999	764	/**
<>	149:156823d33999	765	* @brief Get Memory increment mode.
<>	149:156823d33999	766	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<>	149:156823d33999	767	* @param DMAx DMAx Instance
<>	149:156823d33999	768	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	769	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	770	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	771	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	772	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	773	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	774	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	775	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	776	* @retval Returned value can be one of the following values:
<>	149:156823d33999	777	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	149:156823d33999	778	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	149:156823d33999	779	*/
<>	149:156823d33999	780	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	781	{
<>	149:156823d33999	782	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	783	DMA_CCR_MINC));
<>	149:156823d33999	784	}
<>	149:156823d33999	785
<>	149:156823d33999	786	/**
<>	149:156823d33999	787	* @brief Set Peripheral size.
<>	149:156823d33999	788	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<>	149:156823d33999	789	* @param DMAx DMAx Instance
<>	149:156823d33999	790	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	791	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	792	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	793	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	794	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	795	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	796	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	797	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	798	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<>	149:156823d33999	799	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	149:156823d33999	800	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	149:156823d33999	801	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	149:156823d33999	802	* @retval None
<>	149:156823d33999	803	*/
<>	149:156823d33999	804	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<>	149:156823d33999	805	{
<>	149:156823d33999	806	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<>	149:156823d33999	807	PeriphOrM2MSrcDataSize);
<>	149:156823d33999	808	}
<>	149:156823d33999	809
<>	149:156823d33999	810	/**
<>	149:156823d33999	811	* @brief Get Peripheral size.
<>	149:156823d33999	812	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<>	149:156823d33999	813	* @param DMAx DMAx Instance
<>	149:156823d33999	814	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	815	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	816	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	817	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	818	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	819	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	820	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	821	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	822	* @retval Returned value can be one of the following values:
<>	149:156823d33999	823	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	149:156823d33999	824	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	149:156823d33999	825	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	149:156823d33999	826	*/
<>	149:156823d33999	827	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	828	{
<>	149:156823d33999	829	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	830	DMA_CCR_PSIZE));
<>	149:156823d33999	831	}
<>	149:156823d33999	832
<>	149:156823d33999	833	/**
<>	149:156823d33999	834	* @brief Set Memory size.
<>	149:156823d33999	835	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<>	149:156823d33999	836	* @param DMAx DMAx Instance
<>	149:156823d33999	837	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	838	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	839	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	840	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	841	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	842	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	843	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	844	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	845	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<>	149:156823d33999	846	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	149:156823d33999	847	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	149:156823d33999	848	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	149:156823d33999	849	* @retval None
<>	149:156823d33999	850	*/
<>	149:156823d33999	851	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<>	149:156823d33999	852	{
<>	149:156823d33999	853	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<>	149:156823d33999	854	MemoryOrM2MDstDataSize);
<>	149:156823d33999	855	}
<>	149:156823d33999	856
<>	149:156823d33999	857	/**
<>	149:156823d33999	858	* @brief Get Memory size.
<>	149:156823d33999	859	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<>	149:156823d33999	860	* @param DMAx DMAx Instance
<>	149:156823d33999	861	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	862	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	863	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	864	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	865	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	866	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	867	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	868	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	869	* @retval Returned value can be one of the following values:
<>	149:156823d33999	870	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	149:156823d33999	871	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	149:156823d33999	872	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	149:156823d33999	873	*/
<>	149:156823d33999	874	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	875	{
<>	149:156823d33999	876	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	877	DMA_CCR_MSIZE));
<>	149:156823d33999	878	}
<>	149:156823d33999	879
<>	149:156823d33999	880	/**
<>	149:156823d33999	881	* @brief Set Channel priority level.
<>	149:156823d33999	882	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<>	149:156823d33999	883	* @param DMAx DMAx Instance
<>	149:156823d33999	884	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	885	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	886	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	887	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	888	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	889	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	890	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	891	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	892	* @param Priority This parameter can be one of the following values:
<>	149:156823d33999	893	* @arg @ref LL_DMA_PRIORITY_LOW
<>	149:156823d33999	894	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	149:156823d33999	895	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	149:156823d33999	896	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	149:156823d33999	897	* @retval None
<>	149:156823d33999	898	*/
<>	149:156823d33999	899	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<>	149:156823d33999	900	{
<>	149:156823d33999	901	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<>	149:156823d33999	902	Priority);
<>	149:156823d33999	903	}
<>	149:156823d33999	904
<>	149:156823d33999	905	/**
<>	149:156823d33999	906	* @brief Get Channel priority level.
<>	149:156823d33999	907	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<>	149:156823d33999	908	* @param DMAx DMAx Instance
<>	149:156823d33999	909	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	910	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	911	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	912	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	913	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	914	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	915	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	916	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	917	* @retval Returned value can be one of the following values:
<>	149:156823d33999	918	* @arg @ref LL_DMA_PRIORITY_LOW
<>	149:156823d33999	919	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	149:156823d33999	920	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	149:156823d33999	921	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	149:156823d33999	922	*/
<>	149:156823d33999	923	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	924	{
<>	149:156823d33999	925	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	926	DMA_CCR_PL));
<>	149:156823d33999	927	}
<>	149:156823d33999	928
<>	149:156823d33999	929	/**
<>	149:156823d33999	930	* @brief Set Number of data to transfer.
<>	149:156823d33999	931	* @note This action has no effect if
<>	149:156823d33999	932	* channel is enabled.
<>	149:156823d33999	933	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
<>	149:156823d33999	934	* @param DMAx DMAx Instance
<>	149:156823d33999	935	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	936	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	937	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	938	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	939	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	940	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	941	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	942	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	943	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	149:156823d33999	944	* @retval None
<>	149:156823d33999	945	*/
<>	149:156823d33999	946	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<>	149:156823d33999	947	{
<>	149:156823d33999	948	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	149:156823d33999	949	DMA_CNDTR_NDT, NbData);
<>	149:156823d33999	950	}
<>	149:156823d33999	951
<>	149:156823d33999	952	/**
<>	149:156823d33999	953	* @brief Get Number of data to transfer.
<>	149:156823d33999	954	* @note Once the channel is enabled, the return value indicate the
<>	149:156823d33999	955	* remaining bytes to be transmitted.
<>	149:156823d33999	956	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
<>	149:156823d33999	957	* @param DMAx DMAx Instance
<>	149:156823d33999	958	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	959	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	960	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	961	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	962	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	963	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	964	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	965	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	966	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	967	*/
<>	149:156823d33999	968	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	969	{
<>	149:156823d33999	970	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	149:156823d33999	971	DMA_CNDTR_NDT));
<>	149:156823d33999	972	}
<>	149:156823d33999	973
<>	149:156823d33999	974	/**
<>	149:156823d33999	975	* @brief Configure the Source and Destination addresses.
<>	149:156823d33999	976	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
<>	149:156823d33999	977	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<>	149:156823d33999	978	* CMAR MA LL_DMA_ConfigAddresses
<>	149:156823d33999	979	* @param DMAx DMAx Instance
<>	149:156823d33999	980	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	981	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	982	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	983	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	984	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	985	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	986	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	987	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	988	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	989	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	990	* @param Direction This parameter can be one of the following values:
<>	149:156823d33999	991	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	149:156823d33999	992	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	149:156823d33999	993	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	149:156823d33999	994	* @retval None
<>	149:156823d33999	995	*/
<>	149:156823d33999	996	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<>	149:156823d33999	997	uint32_t DstAddress, uint32_t Direction)
<>	149:156823d33999	998	{
<>	149:156823d33999	999	/* Direction Memory to Periph */
<>	149:156823d33999	1000	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<>	149:156823d33999	1001	{
<>	149:156823d33999	1002	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	149:156823d33999	1003	SrcAddress);
<>	149:156823d33999	1004	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	149:156823d33999	1005	DstAddress);
<>	149:156823d33999	1006	}
<>	149:156823d33999	1007	/* Direction Periph to Memory and Memory to Memory */
<>	149:156823d33999	1008	else
<>	149:156823d33999	1009	{
<>	149:156823d33999	1010	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	149:156823d33999	1011	SrcAddress);
<>	149:156823d33999	1012	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	149:156823d33999	1013	DstAddress);
<>	149:156823d33999	1014	}
<>	149:156823d33999	1015	}
<>	149:156823d33999	1016
<>	149:156823d33999	1017	/**
<>	149:156823d33999	1018	* @brief Set the Memory address.
<>	149:156823d33999	1019	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	149:156823d33999	1020	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<>	149:156823d33999	1021	* @param DMAx DMAx Instance
<>	149:156823d33999	1022	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1023	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1024	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1025	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1026	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1027	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1028	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1029	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1030	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1031	* @retval None
<>	149:156823d33999	1032	*/
<>	149:156823d33999	1033	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	149:156823d33999	1034	{
<>	149:156823d33999	1035	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	149:156823d33999	1036	MemoryAddress);
<>	149:156823d33999	1037	}
<>	149:156823d33999	1038
<>	149:156823d33999	1039	/**
<>	149:156823d33999	1040	* @brief Set the Peripheral address.
<>	149:156823d33999	1041	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	149:156823d33999	1042	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<>	149:156823d33999	1043	* @param DMAx DMAx Instance
<>	149:156823d33999	1044	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1045	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1046	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1047	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1048	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1049	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1050	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1051	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1052	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1053	* @retval None
<>	149:156823d33999	1054	*/
<>	149:156823d33999	1055	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<>	149:156823d33999	1056	{
<>	149:156823d33999	1057	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	149:156823d33999	1058	PeriphAddress);
<>	149:156823d33999	1059	}
<>	149:156823d33999	1060
<>	149:156823d33999	1061	/**
<>	149:156823d33999	1062	* @brief Get Memory address.
<>	149:156823d33999	1063	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	149:156823d33999	1064	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<>	149:156823d33999	1065	* @param DMAx DMAx Instance
<>	149:156823d33999	1066	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1067	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1068	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1069	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1070	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1071	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1072	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1073	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1074	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1075	*/
<>	149:156823d33999	1076	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1077	{
<>	149:156823d33999	1078	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	149:156823d33999	1079	DMA_CMAR_MA));
<>	149:156823d33999	1080	}
<>	149:156823d33999	1081
<>	149:156823d33999	1082	/**
<>	149:156823d33999	1083	* @brief Get Peripheral address.
<>	149:156823d33999	1084	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	149:156823d33999	1085	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<>	149:156823d33999	1086	* @param DMAx DMAx Instance
<>	149:156823d33999	1087	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1088	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1089	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1090	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1091	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1092	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1093	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1094	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1095	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1096	*/
<>	149:156823d33999	1097	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1098	{
<>	149:156823d33999	1099	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	149:156823d33999	1100	DMA_CPAR_PA));
<>	149:156823d33999	1101	}
<>	149:156823d33999	1102
<>	149:156823d33999	1103	/**
<>	149:156823d33999	1104	* @brief Set the Memory to Memory Source address.
<>	149:156823d33999	1105	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	149:156823d33999	1106	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<>	149:156823d33999	1107	* @param DMAx DMAx Instance
<>	149:156823d33999	1108	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1109	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1110	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1111	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1112	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1113	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1114	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1115	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1116	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1117	* @retval None
<>	149:156823d33999	1118	*/
<>	149:156823d33999	1119	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	149:156823d33999	1120	{
<>	149:156823d33999	1121	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	149:156823d33999	1122	MemoryAddress);
<>	149:156823d33999	1123	}
<>	149:156823d33999	1124
<>	149:156823d33999	1125	/**
<>	149:156823d33999	1126	* @brief Set the Memory to Memory Destination address.
<>	149:156823d33999	1127	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	149:156823d33999	1128	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<>	149:156823d33999	1129	* @param DMAx DMAx Instance
<>	149:156823d33999	1130	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1131	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1132	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1133	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1134	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1135	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1136	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1137	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1138	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1139	* @retval None
<>	149:156823d33999	1140	*/
<>	149:156823d33999	1141	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	149:156823d33999	1142	{
<>	149:156823d33999	1143	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	149:156823d33999	1144	MemoryAddress);
<>	149:156823d33999	1145	}
<>	149:156823d33999	1146
<>	149:156823d33999	1147	/**
<>	149:156823d33999	1148	* @brief Get the Memory to Memory Source address.
<>	149:156823d33999	1149	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	149:156823d33999	1150	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<>	149:156823d33999	1151	* @param DMAx DMAx Instance
<>	149:156823d33999	1152	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1153	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1154	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1155	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1156	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1157	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1158	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1159	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1160	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1161	*/
<>	149:156823d33999	1162	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1163	{
<>	149:156823d33999	1164	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	149:156823d33999	1165	DMA_CPAR_PA));
<>	149:156823d33999	1166	}
<>	149:156823d33999	1167
<>	149:156823d33999	1168	/**
<>	149:156823d33999	1169	* @brief Get the Memory to Memory Destination address.
<>	149:156823d33999	1170	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	149:156823d33999	1171	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<>	149:156823d33999	1172	* @param DMAx DMAx Instance
<>	149:156823d33999	1173	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1174	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1175	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1176	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1177	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1178	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1179	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1180	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1181	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	149:156823d33999	1182	*/
<>	149:156823d33999	1183	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1184	{
<>	149:156823d33999	1185	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	149:156823d33999	1186	DMA_CMAR_MA));
<>	149:156823d33999	1187	}
<>	149:156823d33999	1188
<>	149:156823d33999	1189
<>	149:156823d33999	1190	/**
<>	149:156823d33999	1191	* @}
<>	149:156823d33999	1192	*/
<>	149:156823d33999	1193
<>	149:156823d33999	1194	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<>	149:156823d33999	1195	* @{
<>	149:156823d33999	1196	*/
<>	149:156823d33999	1197
<>	149:156823d33999	1198	/**
<>	149:156823d33999	1199	* @brief Get Channel 1 global interrupt flag.
<>	149:156823d33999	1200	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<>	149:156823d33999	1201	* @param DMAx DMAx Instance
<>	149:156823d33999	1202	* @retval State of bit (1 or 0).
<>	149:156823d33999	1203	*/
<>	149:156823d33999	1204	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1205	{
<>	149:156823d33999	1206	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<>	149:156823d33999	1207	}
<>	149:156823d33999	1208
<>	149:156823d33999	1209	/**
<>	149:156823d33999	1210	* @brief Get Channel 2 global interrupt flag.
<>	149:156823d33999	1211	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<>	149:156823d33999	1212	* @param DMAx DMAx Instance
<>	149:156823d33999	1213	* @retval State of bit (1 or 0).
<>	149:156823d33999	1214	*/
<>	149:156823d33999	1215	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1216	{
<>	149:156823d33999	1217	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<>	149:156823d33999	1218	}
<>	149:156823d33999	1219
<>	149:156823d33999	1220	/**
<>	149:156823d33999	1221	* @brief Get Channel 3 global interrupt flag.
<>	149:156823d33999	1222	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<>	149:156823d33999	1223	* @param DMAx DMAx Instance
<>	149:156823d33999	1224	* @retval State of bit (1 or 0).
<>	149:156823d33999	1225	*/
<>	149:156823d33999	1226	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1227	{
<>	149:156823d33999	1228	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<>	149:156823d33999	1229	}
<>	149:156823d33999	1230
<>	149:156823d33999	1231	/**
<>	149:156823d33999	1232	* @brief Get Channel 4 global interrupt flag.
<>	149:156823d33999	1233	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<>	149:156823d33999	1234	* @param DMAx DMAx Instance
<>	149:156823d33999	1235	* @retval State of bit (1 or 0).
<>	149:156823d33999	1236	*/
<>	149:156823d33999	1237	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1238	{
<>	149:156823d33999	1239	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<>	149:156823d33999	1240	}
<>	149:156823d33999	1241
<>	149:156823d33999	1242	/**
<>	149:156823d33999	1243	* @brief Get Channel 5 global interrupt flag.
<>	149:156823d33999	1244	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<>	149:156823d33999	1245	* @param DMAx DMAx Instance
<>	149:156823d33999	1246	* @retval State of bit (1 or 0).
<>	149:156823d33999	1247	*/
<>	149:156823d33999	1248	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1249	{
<>	149:156823d33999	1250	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<>	149:156823d33999	1251	}
<>	149:156823d33999	1252
<>	149:156823d33999	1253	/**
<>	149:156823d33999	1254	* @brief Get Channel 6 global interrupt flag.
<>	149:156823d33999	1255	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<>	149:156823d33999	1256	* @param DMAx DMAx Instance
<>	149:156823d33999	1257	* @retval State of bit (1 or 0).
<>	149:156823d33999	1258	*/
<>	149:156823d33999	1259	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1260	{
<>	149:156823d33999	1261	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<>	149:156823d33999	1262	}
<>	149:156823d33999	1263
<>	149:156823d33999	1264	/**
<>	149:156823d33999	1265	* @brief Get Channel 7 global interrupt flag.
<>	149:156823d33999	1266	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<>	149:156823d33999	1267	* @param DMAx DMAx Instance
<>	149:156823d33999	1268	* @retval State of bit (1 or 0).
<>	149:156823d33999	1269	*/
<>	149:156823d33999	1270	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1271	{
<>	149:156823d33999	1272	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<>	149:156823d33999	1273	}
<>	149:156823d33999	1274
<>	149:156823d33999	1275	/**
<>	149:156823d33999	1276	* @brief Get Channel 1 transfer complete flag.
<>	149:156823d33999	1277	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<>	149:156823d33999	1278	* @param DMAx DMAx Instance
<>	149:156823d33999	1279	* @retval State of bit (1 or 0).
<>	149:156823d33999	1280	*/
<>	149:156823d33999	1281	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1282	{
<>	149:156823d33999	1283	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<>	149:156823d33999	1284	}
<>	149:156823d33999	1285
<>	149:156823d33999	1286	/**
<>	149:156823d33999	1287	* @brief Get Channel 2 transfer complete flag.
<>	149:156823d33999	1288	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<>	149:156823d33999	1289	* @param DMAx DMAx Instance
<>	149:156823d33999	1290	* @retval State of bit (1 or 0).
<>	149:156823d33999	1291	*/
<>	149:156823d33999	1292	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1293	{
<>	149:156823d33999	1294	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<>	149:156823d33999	1295	}
<>	149:156823d33999	1296
<>	149:156823d33999	1297	/**
<>	149:156823d33999	1298	* @brief Get Channel 3 transfer complete flag.
<>	149:156823d33999	1299	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<>	149:156823d33999	1300	* @param DMAx DMAx Instance
<>	149:156823d33999	1301	* @retval State of bit (1 or 0).
<>	149:156823d33999	1302	*/
<>	149:156823d33999	1303	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1304	{
<>	149:156823d33999	1305	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<>	149:156823d33999	1306	}
<>	149:156823d33999	1307
<>	149:156823d33999	1308	/**
<>	149:156823d33999	1309	* @brief Get Channel 4 transfer complete flag.
<>	149:156823d33999	1310	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<>	149:156823d33999	1311	* @param DMAx DMAx Instance
<>	149:156823d33999	1312	* @retval State of bit (1 or 0).
<>	149:156823d33999	1313	*/
<>	149:156823d33999	1314	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1315	{
<>	149:156823d33999	1316	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<>	149:156823d33999	1317	}
<>	149:156823d33999	1318
<>	149:156823d33999	1319	/**
<>	149:156823d33999	1320	* @brief Get Channel 5 transfer complete flag.
<>	149:156823d33999	1321	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<>	149:156823d33999	1322	* @param DMAx DMAx Instance
<>	149:156823d33999	1323	* @retval State of bit (1 or 0).
<>	149:156823d33999	1324	*/
<>	149:156823d33999	1325	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1326	{
<>	149:156823d33999	1327	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<>	149:156823d33999	1328	}
<>	149:156823d33999	1329
<>	149:156823d33999	1330	/**
<>	149:156823d33999	1331	* @brief Get Channel 6 transfer complete flag.
<>	149:156823d33999	1332	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<>	149:156823d33999	1333	* @param DMAx DMAx Instance
<>	149:156823d33999	1334	* @retval State of bit (1 or 0).
<>	149:156823d33999	1335	*/
<>	149:156823d33999	1336	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1337	{
<>	149:156823d33999	1338	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<>	149:156823d33999	1339	}
<>	149:156823d33999	1340
<>	149:156823d33999	1341	/**
<>	149:156823d33999	1342	* @brief Get Channel 7 transfer complete flag.
<>	149:156823d33999	1343	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<>	149:156823d33999	1344	* @param DMAx DMAx Instance
<>	149:156823d33999	1345	* @retval State of bit (1 or 0).
<>	149:156823d33999	1346	*/
<>	149:156823d33999	1347	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1348	{
<>	149:156823d33999	1349	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<>	149:156823d33999	1350	}
<>	149:156823d33999	1351
<>	149:156823d33999	1352	/**
<>	149:156823d33999	1353	* @brief Get Channel 1 half transfer flag.
<>	149:156823d33999	1354	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<>	149:156823d33999	1355	* @param DMAx DMAx Instance
<>	149:156823d33999	1356	* @retval State of bit (1 or 0).
<>	149:156823d33999	1357	*/
<>	149:156823d33999	1358	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1359	{
<>	149:156823d33999	1360	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<>	149:156823d33999	1361	}
<>	149:156823d33999	1362
<>	149:156823d33999	1363	/**
<>	149:156823d33999	1364	* @brief Get Channel 2 half transfer flag.
<>	149:156823d33999	1365	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<>	149:156823d33999	1366	* @param DMAx DMAx Instance
<>	149:156823d33999	1367	* @retval State of bit (1 or 0).
<>	149:156823d33999	1368	*/
<>	149:156823d33999	1369	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1370	{
<>	149:156823d33999	1371	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<>	149:156823d33999	1372	}
<>	149:156823d33999	1373
<>	149:156823d33999	1374	/**
<>	149:156823d33999	1375	* @brief Get Channel 3 half transfer flag.
<>	149:156823d33999	1376	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<>	149:156823d33999	1377	* @param DMAx DMAx Instance
<>	149:156823d33999	1378	* @retval State of bit (1 or 0).
<>	149:156823d33999	1379	*/
<>	149:156823d33999	1380	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1381	{
<>	149:156823d33999	1382	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<>	149:156823d33999	1383	}
<>	149:156823d33999	1384
<>	149:156823d33999	1385	/**
<>	149:156823d33999	1386	* @brief Get Channel 4 half transfer flag.
<>	149:156823d33999	1387	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<>	149:156823d33999	1388	* @param DMAx DMAx Instance
<>	149:156823d33999	1389	* @retval State of bit (1 or 0).
<>	149:156823d33999	1390	*/
<>	149:156823d33999	1391	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1392	{
<>	149:156823d33999	1393	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<>	149:156823d33999	1394	}
<>	149:156823d33999	1395
<>	149:156823d33999	1396	/**
<>	149:156823d33999	1397	* @brief Get Channel 5 half transfer flag.
<>	149:156823d33999	1398	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<>	149:156823d33999	1399	* @param DMAx DMAx Instance
<>	149:156823d33999	1400	* @retval State of bit (1 or 0).
<>	149:156823d33999	1401	*/
<>	149:156823d33999	1402	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1403	{
<>	149:156823d33999	1404	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<>	149:156823d33999	1405	}
<>	149:156823d33999	1406
<>	149:156823d33999	1407	/**
<>	149:156823d33999	1408	* @brief Get Channel 6 half transfer flag.
<>	149:156823d33999	1409	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<>	149:156823d33999	1410	* @param DMAx DMAx Instance
<>	149:156823d33999	1411	* @retval State of bit (1 or 0).
<>	149:156823d33999	1412	*/
<>	149:156823d33999	1413	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1414	{
<>	149:156823d33999	1415	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<>	149:156823d33999	1416	}
<>	149:156823d33999	1417
<>	149:156823d33999	1418	/**
<>	149:156823d33999	1419	* @brief Get Channel 7 half transfer flag.
<>	149:156823d33999	1420	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<>	149:156823d33999	1421	* @param DMAx DMAx Instance
<>	149:156823d33999	1422	* @retval State of bit (1 or 0).
<>	149:156823d33999	1423	*/
<>	149:156823d33999	1424	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1425	{
<>	149:156823d33999	1426	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<>	149:156823d33999	1427	}
<>	149:156823d33999	1428
<>	149:156823d33999	1429	/**
<>	149:156823d33999	1430	* @brief Get Channel 1 transfer error flag.
<>	149:156823d33999	1431	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<>	149:156823d33999	1432	* @param DMAx DMAx Instance
<>	149:156823d33999	1433	* @retval State of bit (1 or 0).
<>	149:156823d33999	1434	*/
<>	149:156823d33999	1435	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1436	{
<>	149:156823d33999	1437	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<>	149:156823d33999	1438	}
<>	149:156823d33999	1439
<>	149:156823d33999	1440	/**
<>	149:156823d33999	1441	* @brief Get Channel 2 transfer error flag.
<>	149:156823d33999	1442	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<>	149:156823d33999	1443	* @param DMAx DMAx Instance
<>	149:156823d33999	1444	* @retval State of bit (1 or 0).
<>	149:156823d33999	1445	*/
<>	149:156823d33999	1446	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1447	{
<>	149:156823d33999	1448	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<>	149:156823d33999	1449	}
<>	149:156823d33999	1450
<>	149:156823d33999	1451	/**
<>	149:156823d33999	1452	* @brief Get Channel 3 transfer error flag.
<>	149:156823d33999	1453	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<>	149:156823d33999	1454	* @param DMAx DMAx Instance
<>	149:156823d33999	1455	* @retval State of bit (1 or 0).
<>	149:156823d33999	1456	*/
<>	149:156823d33999	1457	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1458	{
<>	149:156823d33999	1459	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<>	149:156823d33999	1460	}
<>	149:156823d33999	1461
<>	149:156823d33999	1462	/**
<>	149:156823d33999	1463	* @brief Get Channel 4 transfer error flag.
<>	149:156823d33999	1464	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<>	149:156823d33999	1465	* @param DMAx DMAx Instance
<>	149:156823d33999	1466	* @retval State of bit (1 or 0).
<>	149:156823d33999	1467	*/
<>	149:156823d33999	1468	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1469	{
<>	149:156823d33999	1470	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<>	149:156823d33999	1471	}
<>	149:156823d33999	1472
<>	149:156823d33999	1473	/**
<>	149:156823d33999	1474	* @brief Get Channel 5 transfer error flag.
<>	149:156823d33999	1475	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<>	149:156823d33999	1476	* @param DMAx DMAx Instance
<>	149:156823d33999	1477	* @retval State of bit (1 or 0).
<>	149:156823d33999	1478	*/
<>	149:156823d33999	1479	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1480	{
<>	149:156823d33999	1481	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<>	149:156823d33999	1482	}
<>	149:156823d33999	1483
<>	149:156823d33999	1484	/**
<>	149:156823d33999	1485	* @brief Get Channel 6 transfer error flag.
<>	149:156823d33999	1486	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<>	149:156823d33999	1487	* @param DMAx DMAx Instance
<>	149:156823d33999	1488	* @retval State of bit (1 or 0).
<>	149:156823d33999	1489	*/
<>	149:156823d33999	1490	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1491	{
<>	149:156823d33999	1492	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<>	149:156823d33999	1493	}
<>	149:156823d33999	1494
<>	149:156823d33999	1495	/**
<>	149:156823d33999	1496	* @brief Get Channel 7 transfer error flag.
<>	149:156823d33999	1497	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<>	149:156823d33999	1498	* @param DMAx DMAx Instance
<>	149:156823d33999	1499	* @retval State of bit (1 or 0).
<>	149:156823d33999	1500	*/
<>	149:156823d33999	1501	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1502	{
<>	149:156823d33999	1503	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<>	149:156823d33999	1504	}
<>	149:156823d33999	1505
<>	149:156823d33999	1506	/**
<>	149:156823d33999	1507	* @brief Clear Channel 1 global interrupt flag.
<>	149:156823d33999	1508	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<>	149:156823d33999	1509	* @param DMAx DMAx Instance
<>	149:156823d33999	1510	* @retval None
<>	149:156823d33999	1511	*/
<>	149:156823d33999	1512	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1513	{
<>	149:156823d33999	1514	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
<>	149:156823d33999	1515	}
<>	149:156823d33999	1516
<>	149:156823d33999	1517	/**
<>	149:156823d33999	1518	* @brief Clear Channel 2 global interrupt flag.
<>	149:156823d33999	1519	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<>	149:156823d33999	1520	* @param DMAx DMAx Instance
<>	149:156823d33999	1521	* @retval None
<>	149:156823d33999	1522	*/
<>	149:156823d33999	1523	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1524	{
<>	149:156823d33999	1525	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
<>	149:156823d33999	1526	}
<>	149:156823d33999	1527
<>	149:156823d33999	1528	/**
<>	149:156823d33999	1529	* @brief Clear Channel 3 global interrupt flag.
<>	149:156823d33999	1530	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<>	149:156823d33999	1531	* @param DMAx DMAx Instance
<>	149:156823d33999	1532	* @retval None
<>	149:156823d33999	1533	*/
<>	149:156823d33999	1534	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1535	{
<>	149:156823d33999	1536	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
<>	149:156823d33999	1537	}
<>	149:156823d33999	1538
<>	149:156823d33999	1539	/**
<>	149:156823d33999	1540	* @brief Clear Channel 4 global interrupt flag.
<>	149:156823d33999	1541	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<>	149:156823d33999	1542	* @param DMAx DMAx Instance
<>	149:156823d33999	1543	* @retval None
<>	149:156823d33999	1544	*/
<>	149:156823d33999	1545	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1546	{
<>	149:156823d33999	1547	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
<>	149:156823d33999	1548	}
<>	149:156823d33999	1549
<>	149:156823d33999	1550	/**
<>	149:156823d33999	1551	* @brief Clear Channel 5 global interrupt flag.
<>	149:156823d33999	1552	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<>	149:156823d33999	1553	* @param DMAx DMAx Instance
<>	149:156823d33999	1554	* @retval None
<>	149:156823d33999	1555	*/
<>	149:156823d33999	1556	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1557	{
<>	149:156823d33999	1558	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
<>	149:156823d33999	1559	}
<>	149:156823d33999	1560
<>	149:156823d33999	1561	/**
<>	149:156823d33999	1562	* @brief Clear Channel 6 global interrupt flag.
<>	149:156823d33999	1563	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<>	149:156823d33999	1564	* @param DMAx DMAx Instance
<>	149:156823d33999	1565	* @retval None
<>	149:156823d33999	1566	*/
<>	149:156823d33999	1567	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1568	{
<>	149:156823d33999	1569	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
<>	149:156823d33999	1570	}
<>	149:156823d33999	1571
<>	149:156823d33999	1572	/**
<>	149:156823d33999	1573	* @brief Clear Channel 7 global interrupt flag.
<>	149:156823d33999	1574	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<>	149:156823d33999	1575	* @param DMAx DMAx Instance
<>	149:156823d33999	1576	* @retval None
<>	149:156823d33999	1577	*/
<>	149:156823d33999	1578	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1579	{
<>	149:156823d33999	1580	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
<>	149:156823d33999	1581	}
<>	149:156823d33999	1582
<>	149:156823d33999	1583	/**
<>	149:156823d33999	1584	* @brief Clear Channel 1 transfer complete flag.
<>	149:156823d33999	1585	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<>	149:156823d33999	1586	* @param DMAx DMAx Instance
<>	149:156823d33999	1587	* @retval None
<>	149:156823d33999	1588	*/
<>	149:156823d33999	1589	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1590	{
<>	149:156823d33999	1591	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
<>	149:156823d33999	1592	}
<>	149:156823d33999	1593
<>	149:156823d33999	1594	/**
<>	149:156823d33999	1595	* @brief Clear Channel 2 transfer complete flag.
<>	149:156823d33999	1596	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<>	149:156823d33999	1597	* @param DMAx DMAx Instance
<>	149:156823d33999	1598	* @retval None
<>	149:156823d33999	1599	*/
<>	149:156823d33999	1600	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1601	{
<>	149:156823d33999	1602	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
<>	149:156823d33999	1603	}
<>	149:156823d33999	1604
<>	149:156823d33999	1605	/**
<>	149:156823d33999	1606	* @brief Clear Channel 3 transfer complete flag.
<>	149:156823d33999	1607	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<>	149:156823d33999	1608	* @param DMAx DMAx Instance
<>	149:156823d33999	1609	* @retval None
<>	149:156823d33999	1610	*/
<>	149:156823d33999	1611	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1612	{
<>	149:156823d33999	1613	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
<>	149:156823d33999	1614	}
<>	149:156823d33999	1615
<>	149:156823d33999	1616	/**
<>	149:156823d33999	1617	* @brief Clear Channel 4 transfer complete flag.
<>	149:156823d33999	1618	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<>	149:156823d33999	1619	* @param DMAx DMAx Instance
<>	149:156823d33999	1620	* @retval None
<>	149:156823d33999	1621	*/
<>	149:156823d33999	1622	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1623	{
<>	149:156823d33999	1624	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
<>	149:156823d33999	1625	}
<>	149:156823d33999	1626
<>	149:156823d33999	1627	/**
<>	149:156823d33999	1628	* @brief Clear Channel 5 transfer complete flag.
<>	149:156823d33999	1629	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<>	149:156823d33999	1630	* @param DMAx DMAx Instance
<>	149:156823d33999	1631	* @retval None
<>	149:156823d33999	1632	*/
<>	149:156823d33999	1633	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1634	{
<>	149:156823d33999	1635	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
<>	149:156823d33999	1636	}
<>	149:156823d33999	1637
<>	149:156823d33999	1638	/**
<>	149:156823d33999	1639	* @brief Clear Channel 6 transfer complete flag.
<>	149:156823d33999	1640	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<>	149:156823d33999	1641	* @param DMAx DMAx Instance
<>	149:156823d33999	1642	* @retval None
<>	149:156823d33999	1643	*/
<>	149:156823d33999	1644	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1645	{
<>	149:156823d33999	1646	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
<>	149:156823d33999	1647	}
<>	149:156823d33999	1648
<>	149:156823d33999	1649	/**
<>	149:156823d33999	1650	* @brief Clear Channel 7 transfer complete flag.
<>	149:156823d33999	1651	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<>	149:156823d33999	1652	* @param DMAx DMAx Instance
<>	149:156823d33999	1653	* @retval None
<>	149:156823d33999	1654	*/
<>	149:156823d33999	1655	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1656	{
<>	149:156823d33999	1657	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
<>	149:156823d33999	1658	}
<>	149:156823d33999	1659
<>	149:156823d33999	1660	/**
<>	149:156823d33999	1661	* @brief Clear Channel 1 half transfer flag.
<>	149:156823d33999	1662	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<>	149:156823d33999	1663	* @param DMAx DMAx Instance
<>	149:156823d33999	1664	* @retval None
<>	149:156823d33999	1665	*/
<>	149:156823d33999	1666	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1667	{
<>	149:156823d33999	1668	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
<>	149:156823d33999	1669	}
<>	149:156823d33999	1670
<>	149:156823d33999	1671	/**
<>	149:156823d33999	1672	* @brief Clear Channel 2 half transfer flag.
<>	149:156823d33999	1673	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<>	149:156823d33999	1674	* @param DMAx DMAx Instance
<>	149:156823d33999	1675	* @retval None
<>	149:156823d33999	1676	*/
<>	149:156823d33999	1677	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1678	{
<>	149:156823d33999	1679	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
<>	149:156823d33999	1680	}
<>	149:156823d33999	1681
<>	149:156823d33999	1682	/**
<>	149:156823d33999	1683	* @brief Clear Channel 3 half transfer flag.
<>	149:156823d33999	1684	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<>	149:156823d33999	1685	* @param DMAx DMAx Instance
<>	149:156823d33999	1686	* @retval None
<>	149:156823d33999	1687	*/
<>	149:156823d33999	1688	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1689	{
<>	149:156823d33999	1690	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
<>	149:156823d33999	1691	}
<>	149:156823d33999	1692
<>	149:156823d33999	1693	/**
<>	149:156823d33999	1694	* @brief Clear Channel 4 half transfer flag.
<>	149:156823d33999	1695	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<>	149:156823d33999	1696	* @param DMAx DMAx Instance
<>	149:156823d33999	1697	* @retval None
<>	149:156823d33999	1698	*/
<>	149:156823d33999	1699	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1700	{
<>	149:156823d33999	1701	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
<>	149:156823d33999	1702	}
<>	149:156823d33999	1703
<>	149:156823d33999	1704	/**
<>	149:156823d33999	1705	* @brief Clear Channel 5 half transfer flag.
<>	149:156823d33999	1706	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<>	149:156823d33999	1707	* @param DMAx DMAx Instance
<>	149:156823d33999	1708	* @retval None
<>	149:156823d33999	1709	*/
<>	149:156823d33999	1710	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1711	{
<>	149:156823d33999	1712	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
<>	149:156823d33999	1713	}
<>	149:156823d33999	1714
<>	149:156823d33999	1715	/**
<>	149:156823d33999	1716	* @brief Clear Channel 6 half transfer flag.
<>	149:156823d33999	1717	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<>	149:156823d33999	1718	* @param DMAx DMAx Instance
<>	149:156823d33999	1719	* @retval None
<>	149:156823d33999	1720	*/
<>	149:156823d33999	1721	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1722	{
<>	149:156823d33999	1723	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
<>	149:156823d33999	1724	}
<>	149:156823d33999	1725
<>	149:156823d33999	1726	/**
<>	149:156823d33999	1727	* @brief Clear Channel 7 half transfer flag.
<>	149:156823d33999	1728	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<>	149:156823d33999	1729	* @param DMAx DMAx Instance
<>	149:156823d33999	1730	* @retval None
<>	149:156823d33999	1731	*/
<>	149:156823d33999	1732	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1733	{
<>	149:156823d33999	1734	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
<>	149:156823d33999	1735	}
<>	149:156823d33999	1736
<>	149:156823d33999	1737	/**
<>	149:156823d33999	1738	* @brief Clear Channel 1 transfer error flag.
<>	149:156823d33999	1739	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<>	149:156823d33999	1740	* @param DMAx DMAx Instance
<>	149:156823d33999	1741	* @retval None
<>	149:156823d33999	1742	*/
<>	149:156823d33999	1743	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<>	149:156823d33999	1744	{
<>	149:156823d33999	1745	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
<>	149:156823d33999	1746	}
<>	149:156823d33999	1747
<>	149:156823d33999	1748	/**
<>	149:156823d33999	1749	* @brief Clear Channel 2 transfer error flag.
<>	149:156823d33999	1750	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<>	149:156823d33999	1751	* @param DMAx DMAx Instance
<>	149:156823d33999	1752	* @retval None
<>	149:156823d33999	1753	*/
<>	149:156823d33999	1754	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<>	149:156823d33999	1755	{
<>	149:156823d33999	1756	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
<>	149:156823d33999	1757	}
<>	149:156823d33999	1758
<>	149:156823d33999	1759	/**
<>	149:156823d33999	1760	* @brief Clear Channel 3 transfer error flag.
<>	149:156823d33999	1761	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<>	149:156823d33999	1762	* @param DMAx DMAx Instance
<>	149:156823d33999	1763	* @retval None
<>	149:156823d33999	1764	*/
<>	149:156823d33999	1765	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<>	149:156823d33999	1766	{
<>	149:156823d33999	1767	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
<>	149:156823d33999	1768	}
<>	149:156823d33999	1769
<>	149:156823d33999	1770	/**
<>	149:156823d33999	1771	* @brief Clear Channel 4 transfer error flag.
<>	149:156823d33999	1772	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<>	149:156823d33999	1773	* @param DMAx DMAx Instance
<>	149:156823d33999	1774	* @retval None
<>	149:156823d33999	1775	*/
<>	149:156823d33999	1776	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<>	149:156823d33999	1777	{
<>	149:156823d33999	1778	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
<>	149:156823d33999	1779	}
<>	149:156823d33999	1780
<>	149:156823d33999	1781	/**
<>	149:156823d33999	1782	* @brief Clear Channel 5 transfer error flag.
<>	149:156823d33999	1783	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<>	149:156823d33999	1784	* @param DMAx DMAx Instance
<>	149:156823d33999	1785	* @retval None
<>	149:156823d33999	1786	*/
<>	149:156823d33999	1787	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<>	149:156823d33999	1788	{
<>	149:156823d33999	1789	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
<>	149:156823d33999	1790	}
<>	149:156823d33999	1791
<>	149:156823d33999	1792	/**
<>	149:156823d33999	1793	* @brief Clear Channel 6 transfer error flag.
<>	149:156823d33999	1794	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<>	149:156823d33999	1795	* @param DMAx DMAx Instance
<>	149:156823d33999	1796	* @retval None
<>	149:156823d33999	1797	*/
<>	149:156823d33999	1798	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<>	149:156823d33999	1799	{
<>	149:156823d33999	1800	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
<>	149:156823d33999	1801	}
<>	149:156823d33999	1802
<>	149:156823d33999	1803	/**
<>	149:156823d33999	1804	* @brief Clear Channel 7 transfer error flag.
<>	149:156823d33999	1805	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<>	149:156823d33999	1806	* @param DMAx DMAx Instance
<>	149:156823d33999	1807	* @retval None
<>	149:156823d33999	1808	*/
<>	149:156823d33999	1809	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<>	149:156823d33999	1810	{
<>	149:156823d33999	1811	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
<>	149:156823d33999	1812	}
<>	149:156823d33999	1813
<>	149:156823d33999	1814	/**
<>	149:156823d33999	1815	* @}
<>	149:156823d33999	1816	*/
<>	149:156823d33999	1817
<>	149:156823d33999	1818	/** @defgroup DMA_LL_EF_IT_Management IT_Management
<>	149:156823d33999	1819	* @{
<>	149:156823d33999	1820	*/
<>	149:156823d33999	1821	/**
<>	149:156823d33999	1822	* @brief Enable Transfer complete interrupt.
<>	149:156823d33999	1823	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<>	149:156823d33999	1824	* @param DMAx DMAx Instance
<>	149:156823d33999	1825	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1826	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1827	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1828	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1829	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1830	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1831	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1832	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1833	* @retval None
<>	149:156823d33999	1834	*/
<>	149:156823d33999	1835	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1836	{
<>	149:156823d33999	1837	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	149:156823d33999	1838	}
<>	149:156823d33999	1839
<>	149:156823d33999	1840	/**
<>	149:156823d33999	1841	* @brief Enable Half transfer interrupt.
<>	149:156823d33999	1842	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<>	149:156823d33999	1843	* @param DMAx DMAx Instance
<>	149:156823d33999	1844	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1845	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1846	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1847	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1848	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1849	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1850	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1851	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1852	* @retval None
<>	149:156823d33999	1853	*/
<>	149:156823d33999	1854	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1855	{
<>	149:156823d33999	1856	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	149:156823d33999	1857	}
<>	149:156823d33999	1858
<>	149:156823d33999	1859	/**
<>	149:156823d33999	1860	* @brief Enable Transfer error interrupt.
<>	149:156823d33999	1861	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<>	149:156823d33999	1862	* @param DMAx DMAx Instance
<>	149:156823d33999	1863	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1864	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1865	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1866	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1867	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1868	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1869	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1870	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1871	* @retval None
<>	149:156823d33999	1872	*/
<>	149:156823d33999	1873	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1874	{
<>	149:156823d33999	1875	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	149:156823d33999	1876	}
<>	149:156823d33999	1877
<>	149:156823d33999	1878	/**
<>	149:156823d33999	1879	* @brief Disable Transfer complete interrupt.
<>	149:156823d33999	1880	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<>	149:156823d33999	1881	* @param DMAx DMAx Instance
<>	149:156823d33999	1882	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1883	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1884	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1885	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1886	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1887	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1888	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1889	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1890	* @retval None
<>	149:156823d33999	1891	*/
<>	149:156823d33999	1892	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1893	{
<>	149:156823d33999	1894	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	149:156823d33999	1895	}
<>	149:156823d33999	1896
<>	149:156823d33999	1897	/**
<>	149:156823d33999	1898	* @brief Disable Half transfer interrupt.
<>	149:156823d33999	1899	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<>	149:156823d33999	1900	* @param DMAx DMAx Instance
<>	149:156823d33999	1901	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1902	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1903	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1904	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1905	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1906	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1907	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1908	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1909	* @retval None
<>	149:156823d33999	1910	*/
<>	149:156823d33999	1911	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1912	{
<>	149:156823d33999	1913	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	149:156823d33999	1914	}
<>	149:156823d33999	1915
<>	149:156823d33999	1916	/**
<>	149:156823d33999	1917	* @brief Disable Transfer error interrupt.
<>	149:156823d33999	1918	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<>	149:156823d33999	1919	* @param DMAx DMAx Instance
<>	149:156823d33999	1920	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1921	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1922	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1923	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1924	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1925	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1926	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1927	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1928	* @retval None
<>	149:156823d33999	1929	*/
<>	149:156823d33999	1930	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1931	{
<>	149:156823d33999	1932	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	149:156823d33999	1933	}
<>	149:156823d33999	1934
<>	149:156823d33999	1935	/**
<>	149:156823d33999	1936	* @brief Check if Transfer complete Interrupt is enabled.
<>	149:156823d33999	1937	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<>	149:156823d33999	1938	* @param DMAx DMAx Instance
<>	149:156823d33999	1939	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1940	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1941	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1942	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1943	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1944	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1945	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1946	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1947	* @retval State of bit (1 or 0).
<>	149:156823d33999	1948	*/
<>	149:156823d33999	1949	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1950	{
<>	149:156823d33999	1951	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	1952	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<>	149:156823d33999	1953	}
<>	149:156823d33999	1954
<>	149:156823d33999	1955	/**
<>	149:156823d33999	1956	* @brief Check if Half transfer Interrupt is enabled.
<>	149:156823d33999	1957	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<>	149:156823d33999	1958	* @param DMAx DMAx Instance
<>	149:156823d33999	1959	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1960	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1961	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1962	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1963	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1964	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1965	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1966	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1967	* @retval State of bit (1 or 0).
<>	149:156823d33999	1968	*/
<>	149:156823d33999	1969	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1970	{
<>	149:156823d33999	1971	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	1972	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<>	149:156823d33999	1973	}
<>	149:156823d33999	1974
<>	149:156823d33999	1975	/**
<>	149:156823d33999	1976	* @brief Check if Transfer error Interrupt is enabled.
<>	149:156823d33999	1977	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<>	149:156823d33999	1978	* @param DMAx DMAx Instance
<>	149:156823d33999	1979	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1980	* @arg @ref LL_DMA_CHANNEL_1
<>	149:156823d33999	1981	* @arg @ref LL_DMA_CHANNEL_2
<>	149:156823d33999	1982	* @arg @ref LL_DMA_CHANNEL_3
<>	149:156823d33999	1983	* @arg @ref LL_DMA_CHANNEL_4
<>	149:156823d33999	1984	* @arg @ref LL_DMA_CHANNEL_5
<>	149:156823d33999	1985	* @arg @ref LL_DMA_CHANNEL_6
<>	149:156823d33999	1986	* @arg @ref LL_DMA_CHANNEL_7
<>	149:156823d33999	1987	* @retval State of bit (1 or 0).
<>	149:156823d33999	1988	*/
<>	149:156823d33999	1989	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	149:156823d33999	1990	{
<>	149:156823d33999	1991	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	149:156823d33999	1992	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<>	149:156823d33999	1993	}
<>	149:156823d33999	1994
<>	149:156823d33999	1995	/**
<>	149:156823d33999	1996	* @}
<>	149:156823d33999	1997	*/
<>	149:156823d33999	1998
<>	149:156823d33999	1999	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	2000	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<>	149:156823d33999	2001	* @{
<>	149:156823d33999	2002	*/
<>	149:156823d33999	2003
<>	149:156823d33999	2004	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
<>	149:156823d33999	2005	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<>	149:156823d33999	2006	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<>	149:156823d33999	2007
<>	149:156823d33999	2008	/**
<>	149:156823d33999	2009	* @}
<>	149:156823d33999	2010	*/
<>	149:156823d33999	2011	#endif /* USE_FULL_LL_DRIVER */
<>	149:156823d33999	2012
<>	149:156823d33999	2013	/**
<>	149:156823d33999	2014	* @}
<>	149:156823d33999	2015	*/
<>	149:156823d33999	2016
<>	149:156823d33999	2017	/**
<>	149:156823d33999	2018	* @}
<>	149:156823d33999	2019	*/
<>	149:156823d33999	2020
<>	149:156823d33999	2021	#endif /* DMA1 \|\| DMA2 */
<>	149:156823d33999	2022
<>	149:156823d33999	2023	/**
<>	149:156823d33999	2024	* @}
<>	149:156823d33999	2025	*/
<>	149:156823d33999	2026
<>	149:156823d33999	2027	#ifdef __cplusplus
<>	149:156823d33999	2028	}
<>	149:156823d33999	2029	#endif
<>	149:156823d33999	2030
<>	149:156823d33999	2031	#endif /* __STM32L1xx_LL_DMA_H */
<>	149:156823d33999	2032
<>	149:156823d33999	2033	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/