mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 184:08ed48f1de7f
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | ****************************************************************************** |
<> | 149:156823d33999 | 3 | * @file stm32l1xx_hal_tim.h |
<> | 149:156823d33999 | 4 | * @author MCD Application Team |
<> | 149:156823d33999 | 5 | * @brief Header file of TIM HAL module. |
<> | 149:156823d33999 | 6 | ****************************************************************************** |
<> | 149:156823d33999 | 7 | * @attention |
<> | 149:156823d33999 | 8 | * |
AnnaBridge | 184:08ed48f1de7f | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 149:156823d33999 | 10 | * |
<> | 149:156823d33999 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 149:156823d33999 | 12 | * are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 149:156823d33999 | 14 | * this list of conditions and the following disclaimer. |
<> | 149:156823d33999 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 149:156823d33999 | 16 | * this list of conditions and the following disclaimer in the documentation |
<> | 149:156823d33999 | 17 | * and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 149:156823d33999 | 19 | * may be used to endorse or promote products derived from this software |
<> | 149:156823d33999 | 20 | * without specific prior written permission. |
<> | 149:156823d33999 | 21 | * |
<> | 149:156823d33999 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 149:156823d33999 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 149:156823d33999 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 149:156823d33999 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 149:156823d33999 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 149:156823d33999 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 149:156823d33999 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 149:156823d33999 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 149:156823d33999 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 149:156823d33999 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 32 | * |
<> | 149:156823d33999 | 33 | ****************************************************************************** |
<> | 149:156823d33999 | 34 | */ |
<> | 149:156823d33999 | 35 | |
<> | 149:156823d33999 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 149:156823d33999 | 37 | #ifndef __STM32L1xx_HAL_TIM_H |
<> | 149:156823d33999 | 38 | #define __STM32L1xx_HAL_TIM_H |
<> | 149:156823d33999 | 39 | |
<> | 149:156823d33999 | 40 | #ifdef __cplusplus |
<> | 149:156823d33999 | 41 | extern "C" { |
<> | 149:156823d33999 | 42 | #endif |
<> | 149:156823d33999 | 43 | |
<> | 149:156823d33999 | 44 | /* Includes ------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 45 | #include "stm32l1xx_hal_def.h" |
<> | 149:156823d33999 | 46 | |
<> | 149:156823d33999 | 47 | /** @addtogroup STM32L1xx_HAL_Driver |
<> | 149:156823d33999 | 48 | * @{ |
<> | 149:156823d33999 | 49 | */ |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | /** @addtogroup TIM |
<> | 149:156823d33999 | 52 | * @{ |
<> | 149:156823d33999 | 53 | */ |
<> | 149:156823d33999 | 54 | |
<> | 149:156823d33999 | 55 | /* Exported types ------------------------------------------------------------*/ |
<> | 149:156823d33999 | 56 | /** @defgroup TIM_Exported_Types TIM Exported Types |
<> | 149:156823d33999 | 57 | * @{ |
<> | 149:156823d33999 | 58 | */ |
<> | 149:156823d33999 | 59 | /** |
<> | 149:156823d33999 | 60 | * @brief TIM Time base Configuration Structure definition |
<> | 149:156823d33999 | 61 | */ |
<> | 149:156823d33999 | 62 | typedef struct |
<> | 149:156823d33999 | 63 | { |
<> | 149:156823d33999 | 64 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
<> | 149:156823d33999 | 65 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
<> | 149:156823d33999 | 66 | |
<> | 149:156823d33999 | 67 | uint32_t CounterMode; /*!< Specifies the counter mode. |
<> | 149:156823d33999 | 68 | This parameter can be a value of @ref TIM_Counter_Mode */ |
<> | 149:156823d33999 | 69 | |
<> | 149:156823d33999 | 70 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
<> | 149:156823d33999 | 71 | Auto-Reload Register at the next update event. |
<> | 149:156823d33999 | 72 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
<> | 149:156823d33999 | 73 | |
<> | 149:156823d33999 | 74 | uint32_t ClockDivision; /*!< Specifies the clock division. |
<> | 149:156823d33999 | 75 | This parameter can be a value of @ref TIM_ClockDivision */ |
<> | 149:156823d33999 | 76 | |
<> | 149:156823d33999 | 77 | } TIM_Base_InitTypeDef; |
<> | 149:156823d33999 | 78 | |
<> | 149:156823d33999 | 79 | /** |
<> | 149:156823d33999 | 80 | * @brief TIM Output Compare Configuration Structure definition |
<> | 149:156823d33999 | 81 | */ |
<> | 149:156823d33999 | 82 | typedef struct |
<> | 149:156823d33999 | 83 | { |
<> | 149:156823d33999 | 84 | uint32_t OCMode; /*!< Specifies the TIM mode. |
<> | 149:156823d33999 | 85 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
<> | 149:156823d33999 | 86 | |
<> | 149:156823d33999 | 87 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
<> | 149:156823d33999 | 88 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
<> | 149:156823d33999 | 89 | |
<> | 149:156823d33999 | 90 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
<> | 149:156823d33999 | 91 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
<> | 149:156823d33999 | 92 | |
<> | 149:156823d33999 | 93 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
<> | 149:156823d33999 | 94 | This parameter can be a value of @ref TIM_Output_Fast_State |
<> | 149:156823d33999 | 95 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
<> | 149:156823d33999 | 96 | |
<> | 149:156823d33999 | 97 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
<> | 149:156823d33999 | 98 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */ |
<> | 149:156823d33999 | 99 | } TIM_OC_InitTypeDef; |
<> | 149:156823d33999 | 100 | |
<> | 149:156823d33999 | 101 | /** |
<> | 149:156823d33999 | 102 | * @brief TIM One Pulse Mode Configuration Structure definition |
<> | 149:156823d33999 | 103 | */ |
<> | 149:156823d33999 | 104 | typedef struct |
<> | 149:156823d33999 | 105 | { |
<> | 149:156823d33999 | 106 | uint32_t OCMode; /*!< Specifies the TIM mode. |
<> | 149:156823d33999 | 107 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
<> | 149:156823d33999 | 108 | |
<> | 149:156823d33999 | 109 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
<> | 149:156823d33999 | 110 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
<> | 149:156823d33999 | 111 | |
<> | 149:156823d33999 | 112 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
<> | 149:156823d33999 | 113 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
<> | 149:156823d33999 | 114 | |
<> | 149:156823d33999 | 115 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
<> | 149:156823d33999 | 116 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */ |
<> | 149:156823d33999 | 117 | |
<> | 149:156823d33999 | 118 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
<> | 149:156823d33999 | 119 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
<> | 149:156823d33999 | 120 | |
<> | 149:156823d33999 | 121 | uint32_t ICSelection; /*!< Specifies the input. |
<> | 149:156823d33999 | 122 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
<> | 149:156823d33999 | 123 | |
<> | 149:156823d33999 | 124 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
<> | 149:156823d33999 | 125 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
<> | 149:156823d33999 | 126 | } TIM_OnePulse_InitTypeDef; |
<> | 149:156823d33999 | 127 | |
<> | 149:156823d33999 | 128 | |
<> | 149:156823d33999 | 129 | /** |
<> | 149:156823d33999 | 130 | * @brief TIM Input Capture Configuration Structure definition |
<> | 149:156823d33999 | 131 | */ |
<> | 149:156823d33999 | 132 | typedef struct |
<> | 149:156823d33999 | 133 | { |
<> | 149:156823d33999 | 134 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
<> | 149:156823d33999 | 135 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
<> | 149:156823d33999 | 136 | |
<> | 149:156823d33999 | 137 | uint32_t ICSelection; /*!< Specifies the input. |
<> | 149:156823d33999 | 138 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
<> | 149:156823d33999 | 139 | |
<> | 149:156823d33999 | 140 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
<> | 149:156823d33999 | 141 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
<> | 149:156823d33999 | 142 | |
<> | 149:156823d33999 | 143 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
<> | 149:156823d33999 | 144 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
<> | 149:156823d33999 | 145 | } TIM_IC_InitTypeDef; |
<> | 149:156823d33999 | 146 | |
<> | 149:156823d33999 | 147 | /** |
<> | 149:156823d33999 | 148 | * @brief TIM Encoder Configuration Structure definition |
<> | 149:156823d33999 | 149 | */ |
<> | 149:156823d33999 | 150 | typedef struct |
<> | 149:156823d33999 | 151 | { |
<> | 149:156823d33999 | 152 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
<> | 149:156823d33999 | 153 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
<> | 149:156823d33999 | 154 | |
<> | 149:156823d33999 | 155 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
<> | 149:156823d33999 | 156 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
<> | 149:156823d33999 | 157 | |
<> | 149:156823d33999 | 158 | uint32_t IC1Selection; /*!< Specifies the input. |
<> | 149:156823d33999 | 159 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
<> | 149:156823d33999 | 160 | |
<> | 149:156823d33999 | 161 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
<> | 149:156823d33999 | 162 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
<> | 149:156823d33999 | 163 | |
<> | 149:156823d33999 | 164 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
<> | 149:156823d33999 | 165 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
<> | 149:156823d33999 | 166 | |
<> | 149:156823d33999 | 167 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
<> | 149:156823d33999 | 168 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
<> | 149:156823d33999 | 169 | |
<> | 149:156823d33999 | 170 | uint32_t IC2Selection; /*!< Specifies the input. |
<> | 149:156823d33999 | 171 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
<> | 149:156823d33999 | 172 | |
<> | 149:156823d33999 | 173 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
<> | 149:156823d33999 | 174 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
<> | 149:156823d33999 | 175 | |
<> | 149:156823d33999 | 176 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
<> | 149:156823d33999 | 177 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
<> | 149:156823d33999 | 178 | } TIM_Encoder_InitTypeDef; |
<> | 149:156823d33999 | 179 | |
<> | 149:156823d33999 | 180 | |
<> | 149:156823d33999 | 181 | /** |
<> | 149:156823d33999 | 182 | * @brief TIM Clock Configuration Handle Structure definition |
<> | 149:156823d33999 | 183 | */ |
<> | 149:156823d33999 | 184 | typedef struct |
<> | 149:156823d33999 | 185 | { |
<> | 149:156823d33999 | 186 | uint32_t ClockSource; /*!< TIM clock sources |
<> | 149:156823d33999 | 187 | This parameter can be a value of @ref TIM_Clock_Source */ |
<> | 149:156823d33999 | 188 | uint32_t ClockPolarity; /*!< TIM clock polarity |
<> | 149:156823d33999 | 189 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
<> | 149:156823d33999 | 190 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
<> | 149:156823d33999 | 191 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
<> | 149:156823d33999 | 192 | uint32_t ClockFilter; /*!< TIM clock filter |
<> | 149:156823d33999 | 193 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
<> | 149:156823d33999 | 194 | }TIM_ClockConfigTypeDef; |
<> | 149:156823d33999 | 195 | |
<> | 149:156823d33999 | 196 | /** |
<> | 149:156823d33999 | 197 | * @brief TIM Clear Input Configuration Handle Structure definition |
<> | 149:156823d33999 | 198 | */ |
<> | 149:156823d33999 | 199 | typedef struct |
<> | 149:156823d33999 | 200 | { |
<> | 149:156823d33999 | 201 | uint32_t ClearInputState; /*!< TIM clear Input state |
<> | 149:156823d33999 | 202 | This parameter can be ENABLE or DISABLE */ |
<> | 149:156823d33999 | 203 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
<> | 149:156823d33999 | 204 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
<> | 149:156823d33999 | 205 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
<> | 149:156823d33999 | 206 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
<> | 149:156823d33999 | 207 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
<> | 149:156823d33999 | 208 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
<> | 149:156823d33999 | 209 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
<> | 149:156823d33999 | 210 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
<> | 149:156823d33999 | 211 | }TIM_ClearInputConfigTypeDef; |
<> | 149:156823d33999 | 212 | |
<> | 149:156823d33999 | 213 | /** |
<> | 149:156823d33999 | 214 | * @brief TIM Slave configuration Structure definition |
<> | 149:156823d33999 | 215 | */ |
<> | 149:156823d33999 | 216 | typedef struct { |
<> | 149:156823d33999 | 217 | uint32_t SlaveMode; /*!< Slave mode selection |
<> | 149:156823d33999 | 218 | This parameter can be a value of @ref TIM_Slave_Mode */ |
<> | 149:156823d33999 | 219 | uint32_t InputTrigger; /*!< Input Trigger source |
<> | 149:156823d33999 | 220 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
<> | 149:156823d33999 | 221 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
<> | 149:156823d33999 | 222 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
<> | 149:156823d33999 | 223 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
<> | 149:156823d33999 | 224 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
<> | 149:156823d33999 | 225 | uint32_t TriggerFilter; /*!< Input trigger filter |
<> | 149:156823d33999 | 226 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
<> | 149:156823d33999 | 227 | |
<> | 149:156823d33999 | 228 | }TIM_SlaveConfigTypeDef; |
<> | 149:156823d33999 | 229 | |
<> | 149:156823d33999 | 230 | /** |
<> | 149:156823d33999 | 231 | * @brief HAL State structures definition |
<> | 149:156823d33999 | 232 | */ |
<> | 149:156823d33999 | 233 | typedef enum |
<> | 149:156823d33999 | 234 | { |
<> | 149:156823d33999 | 235 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ |
<> | 149:156823d33999 | 236 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
<> | 149:156823d33999 | 237 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
<> | 149:156823d33999 | 238 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
<> | 149:156823d33999 | 239 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
<> | 149:156823d33999 | 240 | }HAL_TIM_StateTypeDef; |
<> | 149:156823d33999 | 241 | |
<> | 149:156823d33999 | 242 | /** |
<> | 149:156823d33999 | 243 | * @brief HAL Active channel structures definition |
<> | 149:156823d33999 | 244 | */ |
<> | 149:156823d33999 | 245 | typedef enum |
<> | 149:156823d33999 | 246 | { |
<> | 149:156823d33999 | 247 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ |
<> | 149:156823d33999 | 248 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ |
<> | 149:156823d33999 | 249 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ |
<> | 149:156823d33999 | 250 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ |
<> | 149:156823d33999 | 251 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
<> | 149:156823d33999 | 252 | }HAL_TIM_ActiveChannel; |
<> | 149:156823d33999 | 253 | |
<> | 149:156823d33999 | 254 | /** |
<> | 149:156823d33999 | 255 | * @brief TIM Time Base Handle Structure definition |
<> | 149:156823d33999 | 256 | */ |
<> | 149:156823d33999 | 257 | typedef struct |
<> | 149:156823d33999 | 258 | { |
<> | 149:156823d33999 | 259 | TIM_TypeDef *Instance; /*!< Register base address */ |
<> | 149:156823d33999 | 260 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
<> | 149:156823d33999 | 261 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
<> | 149:156823d33999 | 262 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
<> | 149:156823d33999 | 263 | This array is accessed by a @ref TIM_DMA_Handle_index */ |
<> | 149:156823d33999 | 264 | HAL_LockTypeDef Lock; /*!< Locking object */ |
<> | 149:156823d33999 | 265 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
<> | 149:156823d33999 | 266 | }TIM_HandleTypeDef; |
<> | 149:156823d33999 | 267 | |
<> | 149:156823d33999 | 268 | /** |
<> | 149:156823d33999 | 269 | * @} |
<> | 149:156823d33999 | 270 | */ |
<> | 149:156823d33999 | 271 | |
<> | 149:156823d33999 | 272 | /* Exported constants --------------------------------------------------------*/ |
<> | 149:156823d33999 | 273 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
<> | 149:156823d33999 | 274 | * @{ |
<> | 149:156823d33999 | 275 | */ |
<> | 149:156823d33999 | 276 | |
<> | 149:156823d33999 | 277 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
<> | 149:156823d33999 | 278 | * @{ |
<> | 149:156823d33999 | 279 | */ |
AnnaBridge | 184:08ed48f1de7f | 280 | #define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ |
<> | 149:156823d33999 | 281 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
<> | 149:156823d33999 | 282 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
<> | 149:156823d33999 | 283 | /** |
<> | 149:156823d33999 | 284 | * @} |
<> | 149:156823d33999 | 285 | */ |
<> | 149:156823d33999 | 286 | |
<> | 149:156823d33999 | 287 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
<> | 149:156823d33999 | 288 | * @{ |
<> | 149:156823d33999 | 289 | */ |
<> | 149:156823d33999 | 290 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
AnnaBridge | 184:08ed48f1de7f | 291 | #define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ |
<> | 149:156823d33999 | 292 | /** |
<> | 149:156823d33999 | 293 | * @} |
<> | 149:156823d33999 | 294 | */ |
<> | 149:156823d33999 | 295 | |
<> | 149:156823d33999 | 296 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
<> | 149:156823d33999 | 297 | * @{ |
<> | 149:156823d33999 | 298 | */ |
AnnaBridge | 184:08ed48f1de7f | 299 | #define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ |
<> | 149:156823d33999 | 300 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
<> | 149:156823d33999 | 301 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
<> | 149:156823d33999 | 302 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
<> | 149:156823d33999 | 303 | /** |
<> | 149:156823d33999 | 304 | * @} |
<> | 149:156823d33999 | 305 | */ |
<> | 149:156823d33999 | 306 | |
<> | 149:156823d33999 | 307 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
<> | 149:156823d33999 | 308 | * @{ |
<> | 149:156823d33999 | 309 | */ |
AnnaBridge | 184:08ed48f1de7f | 310 | #define TIM_COUNTERMODE_UP (0x0000U) |
<> | 149:156823d33999 | 311 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
<> | 149:156823d33999 | 312 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
<> | 149:156823d33999 | 313 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
<> | 149:156823d33999 | 314 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
<> | 149:156823d33999 | 315 | /** |
<> | 149:156823d33999 | 316 | * @} |
<> | 149:156823d33999 | 317 | */ |
<> | 149:156823d33999 | 318 | |
<> | 149:156823d33999 | 319 | /** @defgroup TIM_ClockDivision TIM ClockDivision |
<> | 149:156823d33999 | 320 | * @{ |
<> | 149:156823d33999 | 321 | */ |
AnnaBridge | 184:08ed48f1de7f | 322 | #define TIM_CLOCKDIVISION_DIV1 (0x0000U) |
<> | 149:156823d33999 | 323 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
<> | 149:156823d33999 | 324 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
<> | 149:156823d33999 | 325 | /** |
<> | 149:156823d33999 | 326 | * @} |
<> | 149:156823d33999 | 327 | */ |
<> | 149:156823d33999 | 328 | |
<> | 149:156823d33999 | 329 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes |
<> | 149:156823d33999 | 330 | * @{ |
<> | 149:156823d33999 | 331 | */ |
AnnaBridge | 184:08ed48f1de7f | 332 | #define TIM_OCMODE_TIMING (0x0000U) |
<> | 149:156823d33999 | 333 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) |
<> | 149:156823d33999 | 334 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) |
<> | 149:156823d33999 | 335 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
<> | 149:156823d33999 | 336 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
<> | 149:156823d33999 | 337 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) |
<> | 149:156823d33999 | 338 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
<> | 149:156823d33999 | 339 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) |
<> | 149:156823d33999 | 340 | /** |
<> | 149:156823d33999 | 341 | * @} |
<> | 149:156823d33999 | 342 | */ |
<> | 149:156823d33999 | 343 | |
<> | 149:156823d33999 | 344 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
<> | 149:156823d33999 | 345 | * @{ |
<> | 149:156823d33999 | 346 | */ |
AnnaBridge | 184:08ed48f1de7f | 347 | #define TIM_OCFAST_DISABLE (0x0000U) |
<> | 149:156823d33999 | 348 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
<> | 149:156823d33999 | 349 | /** |
<> | 149:156823d33999 | 350 | * @} |
<> | 149:156823d33999 | 351 | */ |
<> | 149:156823d33999 | 352 | |
<> | 149:156823d33999 | 353 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
<> | 149:156823d33999 | 354 | * @{ |
<> | 149:156823d33999 | 355 | */ |
AnnaBridge | 184:08ed48f1de7f | 356 | #define TIM_OCPOLARITY_HIGH (0x0000U) |
<> | 149:156823d33999 | 357 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
<> | 149:156823d33999 | 358 | /** |
<> | 149:156823d33999 | 359 | * @} |
<> | 149:156823d33999 | 360 | */ |
<> | 149:156823d33999 | 361 | |
<> | 149:156823d33999 | 362 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
<> | 149:156823d33999 | 363 | * @{ |
<> | 149:156823d33999 | 364 | */ |
<> | 149:156823d33999 | 365 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
AnnaBridge | 184:08ed48f1de7f | 366 | #define TIM_OCIDLESTATE_RESET (0x0000U) |
<> | 149:156823d33999 | 367 | /** |
<> | 149:156823d33999 | 368 | * @} |
<> | 149:156823d33999 | 369 | */ |
<> | 149:156823d33999 | 370 | |
<> | 149:156823d33999 | 371 | /** @defgroup TIM_Channel TIM Channel |
<> | 149:156823d33999 | 372 | * @{ |
<> | 149:156823d33999 | 373 | */ |
AnnaBridge | 184:08ed48f1de7f | 374 | #define TIM_CHANNEL_1 (0x0000U) |
AnnaBridge | 184:08ed48f1de7f | 375 | #define TIM_CHANNEL_2 (0x0004U) |
AnnaBridge | 184:08ed48f1de7f | 376 | #define TIM_CHANNEL_3 (0x0008U) |
AnnaBridge | 184:08ed48f1de7f | 377 | #define TIM_CHANNEL_4 (0x000CU) |
AnnaBridge | 184:08ed48f1de7f | 378 | #define TIM_CHANNEL_ALL (0x0018U) |
<> | 149:156823d33999 | 379 | /** |
<> | 149:156823d33999 | 380 | * @} |
<> | 149:156823d33999 | 381 | */ |
<> | 149:156823d33999 | 382 | |
<> | 149:156823d33999 | 383 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
<> | 149:156823d33999 | 384 | * @{ |
<> | 149:156823d33999 | 385 | */ |
<> | 149:156823d33999 | 386 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
<> | 149:156823d33999 | 387 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
<> | 149:156823d33999 | 388 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
<> | 149:156823d33999 | 389 | /** |
<> | 149:156823d33999 | 390 | * @} |
<> | 149:156823d33999 | 391 | */ |
<> | 149:156823d33999 | 392 | |
<> | 149:156823d33999 | 393 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
<> | 149:156823d33999 | 394 | * @{ |
<> | 149:156823d33999 | 395 | */ |
<> | 149:156823d33999 | 396 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
<> | 149:156823d33999 | 397 | connected to IC1, IC2, IC3 or IC4, respectively */ |
<> | 149:156823d33999 | 398 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
<> | 149:156823d33999 | 399 | connected to IC2, IC1, IC4 or IC3, respectively */ |
<> | 149:156823d33999 | 400 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
<> | 149:156823d33999 | 401 | /** |
<> | 149:156823d33999 | 402 | * @} |
<> | 149:156823d33999 | 403 | */ |
<> | 149:156823d33999 | 404 | |
<> | 149:156823d33999 | 405 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
<> | 149:156823d33999 | 406 | * @{ |
<> | 149:156823d33999 | 407 | */ |
AnnaBridge | 184:08ed48f1de7f | 408 | #define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ |
<> | 149:156823d33999 | 409 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
<> | 149:156823d33999 | 410 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
<> | 149:156823d33999 | 411 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
<> | 149:156823d33999 | 412 | /** |
<> | 149:156823d33999 | 413 | * @} |
<> | 149:156823d33999 | 414 | */ |
<> | 149:156823d33999 | 415 | |
<> | 149:156823d33999 | 416 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
<> | 149:156823d33999 | 417 | * @{ |
<> | 149:156823d33999 | 418 | */ |
<> | 149:156823d33999 | 419 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
AnnaBridge | 184:08ed48f1de7f | 420 | #define TIM_OPMODE_REPETITIVE (0x0000U) |
<> | 149:156823d33999 | 421 | /** |
<> | 149:156823d33999 | 422 | * @} |
<> | 149:156823d33999 | 423 | */ |
<> | 149:156823d33999 | 424 | |
<> | 149:156823d33999 | 425 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
<> | 149:156823d33999 | 426 | * @{ |
<> | 149:156823d33999 | 427 | */ |
<> | 149:156823d33999 | 428 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
<> | 149:156823d33999 | 429 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
<> | 149:156823d33999 | 430 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
<> | 149:156823d33999 | 431 | /** |
<> | 149:156823d33999 | 432 | * @} |
<> | 149:156823d33999 | 433 | */ |
<> | 149:156823d33999 | 434 | |
<> | 149:156823d33999 | 435 | /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition |
<> | 149:156823d33999 | 436 | * @{ |
<> | 149:156823d33999 | 437 | */ |
<> | 149:156823d33999 | 438 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
<> | 149:156823d33999 | 439 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
<> | 149:156823d33999 | 440 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
<> | 149:156823d33999 | 441 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
<> | 149:156823d33999 | 442 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
<> | 149:156823d33999 | 443 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
<> | 149:156823d33999 | 444 | /** |
<> | 149:156823d33999 | 445 | * @} |
<> | 149:156823d33999 | 446 | */ |
<> | 149:156823d33999 | 447 | |
<> | 149:156823d33999 | 448 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
<> | 149:156823d33999 | 449 | * @{ |
<> | 149:156823d33999 | 450 | */ |
<> | 149:156823d33999 | 451 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
<> | 149:156823d33999 | 452 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
<> | 149:156823d33999 | 453 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
<> | 149:156823d33999 | 454 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
<> | 149:156823d33999 | 455 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
<> | 149:156823d33999 | 456 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
<> | 149:156823d33999 | 457 | /** |
<> | 149:156823d33999 | 458 | * @} |
<> | 149:156823d33999 | 459 | */ |
<> | 149:156823d33999 | 460 | |
<> | 149:156823d33999 | 461 | /** @defgroup TIM_Event_Source TIM Event Source |
<> | 149:156823d33999 | 462 | * @{ |
<> | 149:156823d33999 | 463 | */ |
<> | 149:156823d33999 | 464 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
<> | 149:156823d33999 | 465 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
<> | 149:156823d33999 | 466 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
<> | 149:156823d33999 | 467 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
<> | 149:156823d33999 | 468 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
<> | 149:156823d33999 | 469 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
<> | 149:156823d33999 | 470 | /** |
<> | 149:156823d33999 | 471 | * @} |
<> | 149:156823d33999 | 472 | */ |
<> | 149:156823d33999 | 473 | |
<> | 149:156823d33999 | 474 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
<> | 149:156823d33999 | 475 | * @{ |
<> | 149:156823d33999 | 476 | */ |
<> | 149:156823d33999 | 477 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
<> | 149:156823d33999 | 478 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
<> | 149:156823d33999 | 479 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
<> | 149:156823d33999 | 480 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
<> | 149:156823d33999 | 481 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
<> | 149:156823d33999 | 482 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
<> | 149:156823d33999 | 483 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
<> | 149:156823d33999 | 484 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
<> | 149:156823d33999 | 485 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
<> | 149:156823d33999 | 486 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
<> | 149:156823d33999 | 487 | /** |
<> | 149:156823d33999 | 488 | * @} |
<> | 149:156823d33999 | 489 | */ |
<> | 149:156823d33999 | 490 | |
<> | 149:156823d33999 | 491 | /** @defgroup TIM_Clock_Source TIM Clock Source |
<> | 149:156823d33999 | 492 | * @{ |
<> | 149:156823d33999 | 493 | */ |
<> | 149:156823d33999 | 494 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
<> | 149:156823d33999 | 495 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
AnnaBridge | 184:08ed48f1de7f | 496 | #define TIM_CLOCKSOURCE_ITR0 (0x0000U) |
<> | 149:156823d33999 | 497 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
<> | 149:156823d33999 | 498 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
<> | 149:156823d33999 | 499 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
<> | 149:156823d33999 | 500 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
<> | 149:156823d33999 | 501 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
<> | 149:156823d33999 | 502 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
<> | 149:156823d33999 | 503 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
<> | 149:156823d33999 | 504 | /** |
<> | 149:156823d33999 | 505 | * @} |
<> | 149:156823d33999 | 506 | */ |
<> | 149:156823d33999 | 507 | |
<> | 149:156823d33999 | 508 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
<> | 149:156823d33999 | 509 | * @{ |
<> | 149:156823d33999 | 510 | */ |
<> | 149:156823d33999 | 511 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
<> | 149:156823d33999 | 512 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
<> | 149:156823d33999 | 513 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
<> | 149:156823d33999 | 514 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
<> | 149:156823d33999 | 515 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
<> | 149:156823d33999 | 516 | /** |
<> | 149:156823d33999 | 517 | * @} |
<> | 149:156823d33999 | 518 | */ |
<> | 149:156823d33999 | 519 | |
<> | 149:156823d33999 | 520 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
<> | 149:156823d33999 | 521 | * @{ |
<> | 149:156823d33999 | 522 | */ |
<> | 149:156823d33999 | 523 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
<> | 149:156823d33999 | 524 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
<> | 149:156823d33999 | 525 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
<> | 149:156823d33999 | 526 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
<> | 149:156823d33999 | 527 | /** |
<> | 149:156823d33999 | 528 | * @} |
<> | 149:156823d33999 | 529 | */ |
<> | 149:156823d33999 | 530 | |
<> | 149:156823d33999 | 531 | /** @defgroup TIM_ClearInput_Source TIM ClearInput Source |
<> | 149:156823d33999 | 532 | * @{ |
<> | 149:156823d33999 | 533 | */ |
AnnaBridge | 184:08ed48f1de7f | 534 | #define TIM_CLEARINPUTSOURCE_ETR (0x0001U) |
AnnaBridge | 184:08ed48f1de7f | 535 | #define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U) |
AnnaBridge | 184:08ed48f1de7f | 536 | #define TIM_CLEARINPUTSOURCE_NONE (0x0000U) |
<> | 149:156823d33999 | 537 | /** |
<> | 149:156823d33999 | 538 | * @} |
<> | 149:156823d33999 | 539 | */ |
<> | 149:156823d33999 | 540 | |
<> | 149:156823d33999 | 541 | /** @defgroup TIM_ClearInput_Polarity TIM ClearInput Polarity |
<> | 149:156823d33999 | 542 | * @{ |
<> | 149:156823d33999 | 543 | */ |
<> | 149:156823d33999 | 544 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
<> | 149:156823d33999 | 545 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
<> | 149:156823d33999 | 546 | /** |
<> | 149:156823d33999 | 547 | * @} |
<> | 149:156823d33999 | 548 | */ |
<> | 149:156823d33999 | 549 | |
<> | 149:156823d33999 | 550 | /** @defgroup TIM_ClearInput_Prescaler TIM ClearInput Prescaler |
<> | 149:156823d33999 | 551 | * @{ |
<> | 149:156823d33999 | 552 | */ |
<> | 149:156823d33999 | 553 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
<> | 149:156823d33999 | 554 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
<> | 149:156823d33999 | 555 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
<> | 149:156823d33999 | 556 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
<> | 149:156823d33999 | 557 | /** |
<> | 149:156823d33999 | 558 | * @} |
<> | 149:156823d33999 | 559 | */ |
<> | 149:156823d33999 | 560 | |
<> | 149:156823d33999 | 561 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state |
<> | 149:156823d33999 | 562 | * @{ |
<> | 149:156823d33999 | 563 | */ |
<> | 149:156823d33999 | 564 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
AnnaBridge | 184:08ed48f1de7f | 565 | #define TIM_OSSR_DISABLE (0x0000U) |
<> | 149:156823d33999 | 566 | /** |
<> | 149:156823d33999 | 567 | * @} |
<> | 149:156823d33999 | 568 | */ |
<> | 149:156823d33999 | 569 | |
<> | 149:156823d33999 | 570 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state |
<> | 149:156823d33999 | 571 | * @{ |
<> | 149:156823d33999 | 572 | */ |
<> | 149:156823d33999 | 573 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
AnnaBridge | 184:08ed48f1de7f | 574 | #define TIM_OSSI_DISABLE (0x0000U) |
<> | 149:156823d33999 | 575 | /** |
<> | 149:156823d33999 | 576 | * @} |
<> | 149:156823d33999 | 577 | */ |
<> | 149:156823d33999 | 578 | |
<> | 149:156823d33999 | 579 | /** @defgroup TIM_Lock_level TIM Lock level |
<> | 149:156823d33999 | 580 | * @{ |
<> | 149:156823d33999 | 581 | */ |
AnnaBridge | 184:08ed48f1de7f | 582 | #define TIM_LOCKLEVEL_OFF (0x0000U) |
AnnaBridge | 184:08ed48f1de7f | 583 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
AnnaBridge | 184:08ed48f1de7f | 584 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
AnnaBridge | 184:08ed48f1de7f | 585 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
<> | 149:156823d33999 | 586 | /** |
<> | 149:156823d33999 | 587 | * @} |
<> | 149:156823d33999 | 588 | */ |
<> | 149:156823d33999 | 589 | |
<> | 149:156823d33999 | 590 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
<> | 149:156823d33999 | 591 | * @{ |
<> | 149:156823d33999 | 592 | */ |
<> | 149:156823d33999 | 593 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
AnnaBridge | 184:08ed48f1de7f | 594 | #define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) |
<> | 149:156823d33999 | 595 | /** |
<> | 149:156823d33999 | 596 | * @} |
<> | 149:156823d33999 | 597 | */ |
<> | 149:156823d33999 | 598 | |
<> | 149:156823d33999 | 599 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
<> | 149:156823d33999 | 600 | * @{ |
<> | 149:156823d33999 | 601 | */ |
AnnaBridge | 184:08ed48f1de7f | 602 | #define TIM_TRGO_RESET (0x0000U) |
<> | 149:156823d33999 | 603 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
<> | 149:156823d33999 | 604 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
<> | 149:156823d33999 | 605 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
<> | 149:156823d33999 | 606 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
<> | 149:156823d33999 | 607 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
<> | 149:156823d33999 | 608 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
<> | 149:156823d33999 | 609 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
<> | 149:156823d33999 | 610 | /** |
<> | 149:156823d33999 | 611 | * @} |
<> | 149:156823d33999 | 612 | */ |
<> | 149:156823d33999 | 613 | |
<> | 149:156823d33999 | 614 | /** @defgroup TIM_Slave_Mode TIM Slave Mode |
<> | 149:156823d33999 | 615 | * @{ |
<> | 149:156823d33999 | 616 | */ |
AnnaBridge | 184:08ed48f1de7f | 617 | #define TIM_SLAVEMODE_DISABLE (0x0000U) |
AnnaBridge | 184:08ed48f1de7f | 618 | #define TIM_SLAVEMODE_RESET (0x0004U) |
AnnaBridge | 184:08ed48f1de7f | 619 | #define TIM_SLAVEMODE_GATED (0x0005U) |
AnnaBridge | 184:08ed48f1de7f | 620 | #define TIM_SLAVEMODE_TRIGGER (0x0006U) |
AnnaBridge | 184:08ed48f1de7f | 621 | #define TIM_SLAVEMODE_EXTERNAL1 (0x0007U) |
<> | 149:156823d33999 | 622 | /** |
<> | 149:156823d33999 | 623 | * @} |
<> | 149:156823d33999 | 624 | */ |
<> | 149:156823d33999 | 625 | |
<> | 149:156823d33999 | 626 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
<> | 149:156823d33999 | 627 | * @{ |
<> | 149:156823d33999 | 628 | */ |
AnnaBridge | 184:08ed48f1de7f | 629 | #define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) |
AnnaBridge | 184:08ed48f1de7f | 630 | #define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) |
<> | 149:156823d33999 | 631 | /** |
<> | 149:156823d33999 | 632 | * @} |
<> | 149:156823d33999 | 633 | */ |
<> | 149:156823d33999 | 634 | |
<> | 149:156823d33999 | 635 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
<> | 149:156823d33999 | 636 | * @{ |
<> | 149:156823d33999 | 637 | */ |
AnnaBridge | 184:08ed48f1de7f | 638 | #define TIM_TS_ITR0 (0x0000U) |
AnnaBridge | 184:08ed48f1de7f | 639 | #define TIM_TS_ITR1 (0x0010U) |
AnnaBridge | 184:08ed48f1de7f | 640 | #define TIM_TS_ITR2 (0x0020U) |
AnnaBridge | 184:08ed48f1de7f | 641 | #define TIM_TS_ITR3 (0x0030U) |
AnnaBridge | 184:08ed48f1de7f | 642 | #define TIM_TS_TI1F_ED (0x0040U) |
AnnaBridge | 184:08ed48f1de7f | 643 | #define TIM_TS_TI1FP1 (0x0050U) |
AnnaBridge | 184:08ed48f1de7f | 644 | #define TIM_TS_TI2FP2 (0x0060U) |
AnnaBridge | 184:08ed48f1de7f | 645 | #define TIM_TS_ETRF (0x0070U) |
AnnaBridge | 184:08ed48f1de7f | 646 | #define TIM_TS_NONE (0xFFFFU) |
<> | 149:156823d33999 | 647 | /** |
<> | 149:156823d33999 | 648 | * @} |
<> | 149:156823d33999 | 649 | */ |
<> | 149:156823d33999 | 650 | |
<> | 149:156823d33999 | 651 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
<> | 149:156823d33999 | 652 | * @{ |
<> | 149:156823d33999 | 653 | */ |
<> | 149:156823d33999 | 654 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
<> | 149:156823d33999 | 655 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
<> | 149:156823d33999 | 656 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
<> | 149:156823d33999 | 657 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
<> | 149:156823d33999 | 658 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
<> | 149:156823d33999 | 659 | /** |
<> | 149:156823d33999 | 660 | * @} |
<> | 149:156823d33999 | 661 | */ |
<> | 149:156823d33999 | 662 | |
<> | 149:156823d33999 | 663 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
<> | 149:156823d33999 | 664 | * @{ |
<> | 149:156823d33999 | 665 | */ |
<> | 149:156823d33999 | 666 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
<> | 149:156823d33999 | 667 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
<> | 149:156823d33999 | 668 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
<> | 149:156823d33999 | 669 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
<> | 149:156823d33999 | 670 | /** |
<> | 149:156823d33999 | 671 | * @} |
<> | 149:156823d33999 | 672 | */ |
<> | 149:156823d33999 | 673 | |
<> | 149:156823d33999 | 674 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
<> | 149:156823d33999 | 675 | * @{ |
<> | 149:156823d33999 | 676 | */ |
AnnaBridge | 184:08ed48f1de7f | 677 | #define TIM_TI1SELECTION_CH1 (0x0000U) |
<> | 149:156823d33999 | 678 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
<> | 149:156823d33999 | 679 | /** |
<> | 149:156823d33999 | 680 | * @} |
<> | 149:156823d33999 | 681 | */ |
<> | 149:156823d33999 | 682 | |
<> | 149:156823d33999 | 683 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
<> | 149:156823d33999 | 684 | * @{ |
<> | 149:156823d33999 | 685 | */ |
AnnaBridge | 184:08ed48f1de7f | 686 | #define TIM_DMABASE_CR1 (0x00000000U) |
AnnaBridge | 184:08ed48f1de7f | 687 | #define TIM_DMABASE_CR2 (0x00000001U) |
AnnaBridge | 184:08ed48f1de7f | 688 | #define TIM_DMABASE_SMCR (0x00000002U) |
AnnaBridge | 184:08ed48f1de7f | 689 | #define TIM_DMABASE_DIER (0x00000003U) |
AnnaBridge | 184:08ed48f1de7f | 690 | #define TIM_DMABASE_SR (0x00000004U) |
AnnaBridge | 184:08ed48f1de7f | 691 | #define TIM_DMABASE_EGR (0x00000005U) |
AnnaBridge | 184:08ed48f1de7f | 692 | #define TIM_DMABASE_CCMR1 (0x00000006U) |
AnnaBridge | 184:08ed48f1de7f | 693 | #define TIM_DMABASE_CCMR2 (0x00000007U) |
AnnaBridge | 184:08ed48f1de7f | 694 | #define TIM_DMABASE_CCER (0x00000008U) |
AnnaBridge | 184:08ed48f1de7f | 695 | #define TIM_DMABASE_CNT (0x00000009U) |
AnnaBridge | 184:08ed48f1de7f | 696 | #define TIM_DMABASE_PSC (0x0000000AU) |
AnnaBridge | 184:08ed48f1de7f | 697 | #define TIM_DMABASE_ARR (0x0000000BU) |
AnnaBridge | 184:08ed48f1de7f | 698 | #define TIM_DMABASE_CCR1 (0x0000000DU) |
AnnaBridge | 184:08ed48f1de7f | 699 | #define TIM_DMABASE_CCR2 (0x0000000EU) |
AnnaBridge | 184:08ed48f1de7f | 700 | #define TIM_DMABASE_CCR3 (0x0000000FU) |
AnnaBridge | 184:08ed48f1de7f | 701 | #define TIM_DMABASE_CCR4 (0x00000010U) |
AnnaBridge | 184:08ed48f1de7f | 702 | #define TIM_DMABASE_DCR (0x00000012U) |
AnnaBridge | 184:08ed48f1de7f | 703 | #define TIM_DMABASE_OR (0x00000013U) |
<> | 149:156823d33999 | 704 | /** |
<> | 149:156823d33999 | 705 | * @} |
<> | 149:156823d33999 | 706 | */ |
<> | 149:156823d33999 | 707 | |
<> | 149:156823d33999 | 708 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
<> | 149:156823d33999 | 709 | * @{ |
<> | 149:156823d33999 | 710 | */ |
<> | 149:156823d33999 | 711 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) |
<> | 149:156823d33999 | 712 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) |
<> | 149:156823d33999 | 713 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) |
<> | 149:156823d33999 | 714 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) |
<> | 149:156823d33999 | 715 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) |
<> | 149:156823d33999 | 716 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) |
<> | 149:156823d33999 | 717 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) |
<> | 149:156823d33999 | 718 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) |
<> | 149:156823d33999 | 719 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) |
<> | 149:156823d33999 | 720 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) |
<> | 149:156823d33999 | 721 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) |
<> | 149:156823d33999 | 722 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) |
<> | 149:156823d33999 | 723 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) |
<> | 149:156823d33999 | 724 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) |
<> | 149:156823d33999 | 725 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) |
<> | 149:156823d33999 | 726 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) |
<> | 149:156823d33999 | 727 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) |
<> | 149:156823d33999 | 728 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) |
<> | 149:156823d33999 | 729 | /** |
<> | 149:156823d33999 | 730 | * @} |
<> | 149:156823d33999 | 731 | */ |
<> | 149:156823d33999 | 732 | |
<> | 149:156823d33999 | 733 | /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index |
<> | 149:156823d33999 | 734 | * @{ |
<> | 149:156823d33999 | 735 | */ |
<> | 149:156823d33999 | 736 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
<> | 149:156823d33999 | 737 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
<> | 149:156823d33999 | 738 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
<> | 149:156823d33999 | 739 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
<> | 149:156823d33999 | 740 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
<> | 149:156823d33999 | 741 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
<> | 149:156823d33999 | 742 | /** |
<> | 149:156823d33999 | 743 | * @} |
<> | 149:156823d33999 | 744 | */ |
<> | 149:156823d33999 | 745 | |
<> | 149:156823d33999 | 746 | /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State |
<> | 149:156823d33999 | 747 | * @{ |
<> | 149:156823d33999 | 748 | */ |
AnnaBridge | 184:08ed48f1de7f | 749 | #define TIM_CCx_ENABLE (0x0001U) |
AnnaBridge | 184:08ed48f1de7f | 750 | #define TIM_CCx_DISABLE (0x0000U) |
<> | 149:156823d33999 | 751 | /** |
<> | 149:156823d33999 | 752 | * @} |
<> | 149:156823d33999 | 753 | */ |
<> | 149:156823d33999 | 754 | |
<> | 149:156823d33999 | 755 | /** |
<> | 149:156823d33999 | 756 | * @} |
<> | 149:156823d33999 | 757 | */ |
<> | 149:156823d33999 | 758 | |
<> | 149:156823d33999 | 759 | /* Private Constants -----------------------------------------------------------*/ |
<> | 149:156823d33999 | 760 | /** @defgroup TIM_Private_Constants TIM Private Constants |
<> | 149:156823d33999 | 761 | * @{ |
<> | 149:156823d33999 | 762 | */ |
<> | 149:156823d33999 | 763 | |
<> | 149:156823d33999 | 764 | /* The counter of a timer instance is disabled only if all the CCx |
<> | 149:156823d33999 | 765 | channels have been disabled */ |
<> | 149:156823d33999 | 766 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
<> | 149:156823d33999 | 767 | /** |
<> | 149:156823d33999 | 768 | * @} |
<> | 149:156823d33999 | 769 | */ |
<> | 149:156823d33999 | 770 | |
<> | 149:156823d33999 | 771 | /* Private Macros -----------------------------------------------------------*/ |
<> | 149:156823d33999 | 772 | /** @defgroup TIM_Private_Macros TIM Private Macros |
<> | 149:156823d33999 | 773 | * @{ |
<> | 149:156823d33999 | 774 | */ |
<> | 149:156823d33999 | 775 | |
<> | 149:156823d33999 | 776 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ |
<> | 149:156823d33999 | 777 | ((MODE) == TIM_COUNTERMODE_DOWN) || \ |
<> | 149:156823d33999 | 778 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
<> | 149:156823d33999 | 779 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
<> | 149:156823d33999 | 780 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) |
<> | 149:156823d33999 | 781 | |
<> | 149:156823d33999 | 782 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ |
<> | 149:156823d33999 | 783 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ |
<> | 149:156823d33999 | 784 | ((DIV) == TIM_CLOCKDIVISION_DIV4)) |
<> | 149:156823d33999 | 785 | |
<> | 149:156823d33999 | 786 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
<> | 149:156823d33999 | 787 | ((MODE) == TIM_OCMODE_PWM2)) |
<> | 149:156823d33999 | 788 | |
<> | 149:156823d33999 | 789 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
<> | 149:156823d33999 | 790 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
<> | 149:156823d33999 | 791 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
<> | 149:156823d33999 | 792 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
<> | 149:156823d33999 | 793 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
<> | 149:156823d33999 | 794 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
<> | 149:156823d33999 | 795 | |
<> | 149:156823d33999 | 796 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ |
<> | 149:156823d33999 | 797 | ((STATE) == TIM_OCFAST_ENABLE)) |
<> | 149:156823d33999 | 798 | |
<> | 149:156823d33999 | 799 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ |
<> | 149:156823d33999 | 800 | ((POLARITY) == TIM_OCPOLARITY_LOW)) |
<> | 149:156823d33999 | 801 | |
<> | 149:156823d33999 | 802 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ |
<> | 149:156823d33999 | 803 | ((STATE) == TIM_OCIDLESTATE_RESET)) |
<> | 149:156823d33999 | 804 | |
<> | 149:156823d33999 | 805 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
<> | 149:156823d33999 | 806 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
<> | 149:156823d33999 | 807 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
<> | 149:156823d33999 | 808 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
<> | 149:156823d33999 | 809 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
<> | 149:156823d33999 | 810 | |
<> | 149:156823d33999 | 811 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
<> | 149:156823d33999 | 812 | ((CHANNEL) == TIM_CHANNEL_2)) |
<> | 149:156823d33999 | 813 | |
<> | 149:156823d33999 | 814 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ |
<> | 149:156823d33999 | 815 | ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ |
<> | 149:156823d33999 | 816 | ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) |
<> | 149:156823d33999 | 817 | |
<> | 149:156823d33999 | 818 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ |
<> | 149:156823d33999 | 819 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ |
<> | 149:156823d33999 | 820 | ((SELECTION) == TIM_ICSELECTION_TRC)) |
<> | 149:156823d33999 | 821 | |
<> | 149:156823d33999 | 822 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
<> | 149:156823d33999 | 823 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
<> | 149:156823d33999 | 824 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
<> | 149:156823d33999 | 825 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
<> | 149:156823d33999 | 826 | |
<> | 149:156823d33999 | 827 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ |
<> | 149:156823d33999 | 828 | ((MODE) == TIM_OPMODE_REPETITIVE)) |
<> | 149:156823d33999 | 829 | |
<> | 149:156823d33999 | 830 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ |
<> | 149:156823d33999 | 831 | ((MODE) == TIM_ENCODERMODE_TI2) || \ |
<> | 149:156823d33999 | 832 | ((MODE) == TIM_ENCODERMODE_TI12)) |
<> | 149:156823d33999 | 833 | |
<> | 149:156823d33999 | 834 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
<> | 149:156823d33999 | 835 | |
<> | 149:156823d33999 | 836 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
<> | 149:156823d33999 | 837 | |
<> | 149:156823d33999 | 838 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ |
<> | 149:156823d33999 | 839 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
<> | 149:156823d33999 | 840 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ |
<> | 149:156823d33999 | 841 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ |
<> | 149:156823d33999 | 842 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ |
<> | 149:156823d33999 | 843 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ |
<> | 149:156823d33999 | 844 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ |
<> | 149:156823d33999 | 845 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ |
<> | 149:156823d33999 | 846 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ |
<> | 149:156823d33999 | 847 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) |
<> | 149:156823d33999 | 848 | |
<> | 149:156823d33999 | 849 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ |
<> | 149:156823d33999 | 850 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
<> | 149:156823d33999 | 851 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ |
<> | 149:156823d33999 | 852 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ |
<> | 149:156823d33999 | 853 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
<> | 149:156823d33999 | 854 | |
<> | 149:156823d33999 | 855 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ |
<> | 149:156823d33999 | 856 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ |
<> | 149:156823d33999 | 857 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ |
<> | 149:156823d33999 | 858 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) |
<> | 149:156823d33999 | 859 | |
<> | 149:156823d33999 | 860 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
<> | 149:156823d33999 | 861 | |
<> | 149:156823d33999 | 862 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ |
<> | 149:156823d33999 | 863 | ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ |
<> | 149:156823d33999 | 864 | ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) |
<> | 149:156823d33999 | 865 | |
<> | 149:156823d33999 | 866 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
<> | 149:156823d33999 | 867 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
<> | 149:156823d33999 | 868 | |
<> | 149:156823d33999 | 869 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
<> | 149:156823d33999 | 870 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
<> | 149:156823d33999 | 871 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
<> | 149:156823d33999 | 872 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) |
<> | 149:156823d33999 | 873 | |
<> | 149:156823d33999 | 874 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
<> | 149:156823d33999 | 875 | |
<> | 149:156823d33999 | 876 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ |
<> | 149:156823d33999 | 877 | ((STATE) == TIM_OSSR_DISABLE)) |
<> | 149:156823d33999 | 878 | |
<> | 149:156823d33999 | 879 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ |
<> | 149:156823d33999 | 880 | ((STATE) == TIM_OSSI_DISABLE)) |
<> | 149:156823d33999 | 881 | |
<> | 149:156823d33999 | 882 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ |
<> | 149:156823d33999 | 883 | ((LEVEL) == TIM_LOCKLEVEL_1) || \ |
<> | 149:156823d33999 | 884 | ((LEVEL) == TIM_LOCKLEVEL_2) || \ |
<> | 149:156823d33999 | 885 | ((LEVEL) == TIM_LOCKLEVEL_3)) |
<> | 149:156823d33999 | 886 | |
<> | 149:156823d33999 | 887 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
<> | 149:156823d33999 | 888 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) |
<> | 149:156823d33999 | 889 | |
<> | 149:156823d33999 | 890 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ |
<> | 149:156823d33999 | 891 | ((SOURCE) == TIM_TRGO_ENABLE) || \ |
<> | 149:156823d33999 | 892 | ((SOURCE) == TIM_TRGO_UPDATE) || \ |
<> | 149:156823d33999 | 893 | ((SOURCE) == TIM_TRGO_OC1) || \ |
<> | 149:156823d33999 | 894 | ((SOURCE) == TIM_TRGO_OC1REF) || \ |
<> | 149:156823d33999 | 895 | ((SOURCE) == TIM_TRGO_OC2REF) || \ |
<> | 149:156823d33999 | 896 | ((SOURCE) == TIM_TRGO_OC3REF) || \ |
<> | 149:156823d33999 | 897 | ((SOURCE) == TIM_TRGO_OC4REF)) |
<> | 149:156823d33999 | 898 | |
<> | 149:156823d33999 | 899 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
<> | 149:156823d33999 | 900 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
<> | 149:156823d33999 | 901 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
<> | 149:156823d33999 | 902 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
<> | 149:156823d33999 | 903 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
<> | 149:156823d33999 | 904 | |
<> | 149:156823d33999 | 905 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
<> | 149:156823d33999 | 906 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) |
<> | 149:156823d33999 | 907 | |
<> | 149:156823d33999 | 908 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
<> | 149:156823d33999 | 909 | ((SELECTION) == TIM_TS_ITR1) || \ |
<> | 149:156823d33999 | 910 | ((SELECTION) == TIM_TS_ITR2) || \ |
<> | 149:156823d33999 | 911 | ((SELECTION) == TIM_TS_ITR3) || \ |
<> | 149:156823d33999 | 912 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
<> | 149:156823d33999 | 913 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
<> | 149:156823d33999 | 914 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
<> | 149:156823d33999 | 915 | ((SELECTION) == TIM_TS_ETRF)) |
<> | 149:156823d33999 | 916 | |
<> | 149:156823d33999 | 917 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
<> | 149:156823d33999 | 918 | ((SELECTION) == TIM_TS_ITR1) || \ |
<> | 149:156823d33999 | 919 | ((SELECTION) == TIM_TS_ITR2) || \ |
<> | 149:156823d33999 | 920 | ((SELECTION) == TIM_TS_ITR3) || \ |
<> | 149:156823d33999 | 921 | ((SELECTION) == TIM_TS_NONE)) |
<> | 149:156823d33999 | 922 | |
<> | 149:156823d33999 | 923 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
<> | 149:156823d33999 | 924 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
<> | 149:156823d33999 | 925 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ |
<> | 149:156823d33999 | 926 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
<> | 149:156823d33999 | 927 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
<> | 149:156823d33999 | 928 | |
<> | 149:156823d33999 | 929 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ |
<> | 149:156823d33999 | 930 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ |
<> | 149:156823d33999 | 931 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ |
<> | 149:156823d33999 | 932 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) |
<> | 149:156823d33999 | 933 | |
<> | 149:156823d33999 | 934 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
<> | 149:156823d33999 | 935 | |
<> | 149:156823d33999 | 936 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ |
<> | 149:156823d33999 | 937 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) |
<> | 149:156823d33999 | 938 | |
<> | 149:156823d33999 | 939 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ |
<> | 149:156823d33999 | 940 | ((BASE) == TIM_DMABASE_CR2) || \ |
<> | 149:156823d33999 | 941 | ((BASE) == TIM_DMABASE_SMCR) || \ |
<> | 149:156823d33999 | 942 | ((BASE) == TIM_DMABASE_DIER) || \ |
<> | 149:156823d33999 | 943 | ((BASE) == TIM_DMABASE_SR) || \ |
<> | 149:156823d33999 | 944 | ((BASE) == TIM_DMABASE_EGR) || \ |
<> | 149:156823d33999 | 945 | ((BASE) == TIM_DMABASE_CCMR1) || \ |
<> | 149:156823d33999 | 946 | ((BASE) == TIM_DMABASE_CCMR2) || \ |
<> | 149:156823d33999 | 947 | ((BASE) == TIM_DMABASE_CCER) || \ |
<> | 149:156823d33999 | 948 | ((BASE) == TIM_DMABASE_CNT) || \ |
<> | 149:156823d33999 | 949 | ((BASE) == TIM_DMABASE_PSC) || \ |
<> | 149:156823d33999 | 950 | ((BASE) == TIM_DMABASE_ARR) || \ |
<> | 149:156823d33999 | 951 | ((BASE) == TIM_DMABASE_CCR1) || \ |
<> | 149:156823d33999 | 952 | ((BASE) == TIM_DMABASE_CCR2) || \ |
<> | 149:156823d33999 | 953 | ((BASE) == TIM_DMABASE_CCR3) || \ |
<> | 149:156823d33999 | 954 | ((BASE) == TIM_DMABASE_CCR4) || \ |
<> | 149:156823d33999 | 955 | ((BASE) == TIM_DMABASE_DCR) || \ |
<> | 149:156823d33999 | 956 | ((BASE) == TIM_DMABASE_OR)) |
<> | 149:156823d33999 | 957 | |
<> | 149:156823d33999 | 958 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
<> | 149:156823d33999 | 959 | ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
<> | 149:156823d33999 | 960 | ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
<> | 149:156823d33999 | 961 | ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
<> | 149:156823d33999 | 962 | ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
<> | 149:156823d33999 | 963 | ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
<> | 149:156823d33999 | 964 | ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
<> | 149:156823d33999 | 965 | ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
<> | 149:156823d33999 | 966 | ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
<> | 149:156823d33999 | 967 | ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
<> | 149:156823d33999 | 968 | ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
<> | 149:156823d33999 | 969 | ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
<> | 149:156823d33999 | 970 | ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
<> | 149:156823d33999 | 971 | ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
<> | 149:156823d33999 | 972 | ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
<> | 149:156823d33999 | 973 | ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
<> | 149:156823d33999 | 974 | ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
<> | 149:156823d33999 | 975 | ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
<> | 149:156823d33999 | 976 | |
<> | 149:156823d33999 | 977 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
<> | 149:156823d33999 | 978 | |
<> | 149:156823d33999 | 979 | /** @brief Set TIM IC prescaler |
<> | 149:156823d33999 | 980 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 981 | * @param __CHANNEL__: specifies TIM Channel |
<> | 149:156823d33999 | 982 | * @param __ICPSC__: specifies the prescaler value. |
<> | 149:156823d33999 | 983 | * @retval None |
<> | 149:156823d33999 | 984 | */ |
<> | 149:156823d33999 | 985 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
<> | 149:156823d33999 | 986 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
<> | 149:156823d33999 | 987 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
<> | 149:156823d33999 | 988 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
<> | 149:156823d33999 | 989 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
<> | 149:156823d33999 | 990 | |
<> | 149:156823d33999 | 991 | /** @brief Reset TIM IC prescaler |
<> | 149:156823d33999 | 992 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 993 | * @param __CHANNEL__: specifies TIM Channel |
<> | 149:156823d33999 | 994 | * @retval None |
<> | 149:156823d33999 | 995 | */ |
<> | 149:156823d33999 | 996 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
<> | 149:156823d33999 | 997 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ |
<> | 149:156823d33999 | 998 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ |
<> | 149:156823d33999 | 999 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ |
<> | 149:156823d33999 | 1000 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) |
<> | 149:156823d33999 | 1001 | |
<> | 149:156823d33999 | 1002 | |
<> | 149:156823d33999 | 1003 | /** @brief Set TIM IC polarity |
<> | 149:156823d33999 | 1004 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 1005 | * @param __CHANNEL__: specifies TIM Channel |
<> | 149:156823d33999 | 1006 | * @param __POLARITY__: specifies TIM Channel Polarity |
<> | 149:156823d33999 | 1007 | * @retval None |
<> | 149:156823d33999 | 1008 | */ |
<> | 149:156823d33999 | 1009 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
<> | 149:156823d33999 | 1010 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
<> | 149:156823d33999 | 1011 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ |
<> | 149:156823d33999 | 1012 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ |
<> | 149:156823d33999 | 1013 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) |
<> | 149:156823d33999 | 1014 | |
<> | 149:156823d33999 | 1015 | /** @brief Reset TIM IC polarity |
<> | 149:156823d33999 | 1016 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 1017 | * @param __CHANNEL__: specifies TIM Channel |
<> | 149:156823d33999 | 1018 | * @retval None |
<> | 149:156823d33999 | 1019 | */ |
<> | 149:156823d33999 | 1020 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
<> | 149:156823d33999 | 1021 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
<> | 149:156823d33999 | 1022 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
<> | 149:156823d33999 | 1023 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
<> | 149:156823d33999 | 1024 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) |
<> | 149:156823d33999 | 1025 | |
<> | 149:156823d33999 | 1026 | /** |
<> | 149:156823d33999 | 1027 | * @} |
<> | 149:156823d33999 | 1028 | */ |
<> | 149:156823d33999 | 1029 | |
<> | 149:156823d33999 | 1030 | /* Private Functions --------------------------------------------------------*/ |
<> | 149:156823d33999 | 1031 | |
<> | 149:156823d33999 | 1032 | /* Exported macros -----------------------------------------------------------*/ |
<> | 149:156823d33999 | 1033 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
<> | 149:156823d33999 | 1034 | * @{ |
<> | 149:156823d33999 | 1035 | */ |
<> | 149:156823d33999 | 1036 | |
<> | 149:156823d33999 | 1037 | /** @brief Reset TIM handle state |
<> | 149:156823d33999 | 1038 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1039 | * @retval None |
<> | 149:156823d33999 | 1040 | */ |
<> | 149:156823d33999 | 1041 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
<> | 149:156823d33999 | 1042 | |
<> | 149:156823d33999 | 1043 | /** |
<> | 149:156823d33999 | 1044 | * @brief Enable the TIM peripheral. |
<> | 149:156823d33999 | 1045 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 1046 | * @retval None |
<> | 149:156823d33999 | 1047 | */ |
<> | 149:156823d33999 | 1048 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
<> | 149:156823d33999 | 1049 | |
<> | 149:156823d33999 | 1050 | /** |
<> | 149:156823d33999 | 1051 | * @brief Disable the TIM peripheral. |
<> | 149:156823d33999 | 1052 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 1053 | * @retval None |
<> | 149:156823d33999 | 1054 | */ |
<> | 149:156823d33999 | 1055 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
<> | 149:156823d33999 | 1056 | do { \ |
<> | 149:156823d33999 | 1057 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
<> | 149:156823d33999 | 1058 | { \ |
<> | 149:156823d33999 | 1059 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
<> | 149:156823d33999 | 1060 | } \ |
<> | 149:156823d33999 | 1061 | } while(0) |
<> | 149:156823d33999 | 1062 | |
<> | 149:156823d33999 | 1063 | /** |
<> | 149:156823d33999 | 1064 | * @brief Enables the specified TIM interrupt. |
<> | 149:156823d33999 | 1065 | * @param __HANDLE__: specifies the TIM Handle. |
<> | 149:156823d33999 | 1066 | * @param __INTERRUPT__: specifies the TIM interrupt source to enable. |
<> | 149:156823d33999 | 1067 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1068 | * @arg TIM_IT_UPDATE: Update interrupt |
<> | 149:156823d33999 | 1069 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
<> | 149:156823d33999 | 1070 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
<> | 149:156823d33999 | 1071 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
<> | 149:156823d33999 | 1072 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
<> | 149:156823d33999 | 1073 | * @arg TIM_IT_COM: Commutation interrupt |
<> | 149:156823d33999 | 1074 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
<> | 149:156823d33999 | 1075 | * @retval None |
<> | 149:156823d33999 | 1076 | */ |
<> | 149:156823d33999 | 1077 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
<> | 149:156823d33999 | 1078 | |
<> | 149:156823d33999 | 1079 | /** |
<> | 149:156823d33999 | 1080 | * @brief Disables the specified TIM interrupt. |
<> | 149:156823d33999 | 1081 | * @param __HANDLE__: specifies the TIM Handle. |
<> | 149:156823d33999 | 1082 | * @param __INTERRUPT__: specifies the TIM interrupt source to disable. |
<> | 149:156823d33999 | 1083 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1084 | * @arg TIM_IT_UPDATE: Update interrupt |
<> | 149:156823d33999 | 1085 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
<> | 149:156823d33999 | 1086 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
<> | 149:156823d33999 | 1087 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
<> | 149:156823d33999 | 1088 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
<> | 149:156823d33999 | 1089 | * @arg TIM_IT_COM: Commutation interrupt |
<> | 149:156823d33999 | 1090 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
<> | 149:156823d33999 | 1091 | * @retval None |
<> | 149:156823d33999 | 1092 | */ |
<> | 149:156823d33999 | 1093 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
<> | 149:156823d33999 | 1094 | |
<> | 149:156823d33999 | 1095 | /** |
<> | 149:156823d33999 | 1096 | * @brief Enables the specified DMA request. |
<> | 149:156823d33999 | 1097 | * @param __HANDLE__: specifies the TIM Handle. |
<> | 149:156823d33999 | 1098 | * @param __DMA__: specifies the TIM DMA request to enable. |
<> | 149:156823d33999 | 1099 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1100 | * @arg TIM_DMA_UPDATE: Update DMA request |
<> | 149:156823d33999 | 1101 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
<> | 149:156823d33999 | 1102 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
<> | 149:156823d33999 | 1103 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
<> | 149:156823d33999 | 1104 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
<> | 149:156823d33999 | 1105 | * @arg TIM_DMA_COM: Commutation DMA request |
<> | 149:156823d33999 | 1106 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
<> | 149:156823d33999 | 1107 | * @retval None |
<> | 149:156823d33999 | 1108 | */ |
<> | 149:156823d33999 | 1109 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
<> | 149:156823d33999 | 1110 | |
<> | 149:156823d33999 | 1111 | /** |
<> | 149:156823d33999 | 1112 | * @brief Disables the specified DMA request. |
<> | 149:156823d33999 | 1113 | * @param __HANDLE__: specifies the TIM Handle. |
<> | 149:156823d33999 | 1114 | * @param __DMA__: specifies the TIM DMA request to disable. |
<> | 149:156823d33999 | 1115 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1116 | * @arg TIM_DMA_UPDATE: Update DMA request |
<> | 149:156823d33999 | 1117 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
<> | 149:156823d33999 | 1118 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
<> | 149:156823d33999 | 1119 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
<> | 149:156823d33999 | 1120 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
<> | 149:156823d33999 | 1121 | * @arg TIM_DMA_COM: Commutation DMA request |
<> | 149:156823d33999 | 1122 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
<> | 149:156823d33999 | 1123 | * @retval None |
<> | 149:156823d33999 | 1124 | */ |
<> | 149:156823d33999 | 1125 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
<> | 149:156823d33999 | 1126 | |
<> | 149:156823d33999 | 1127 | /** |
<> | 149:156823d33999 | 1128 | * @brief Checks whether the specified TIM interrupt flag is set or not. |
<> | 149:156823d33999 | 1129 | * @param __HANDLE__: specifies the TIM Handle. |
<> | 149:156823d33999 | 1130 | * @param __FLAG__: specifies the TIM interrupt flag to check. |
<> | 149:156823d33999 | 1131 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1132 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
<> | 149:156823d33999 | 1133 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
<> | 149:156823d33999 | 1134 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
<> | 149:156823d33999 | 1135 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
<> | 149:156823d33999 | 1136 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
<> | 149:156823d33999 | 1137 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
<> | 149:156823d33999 | 1138 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
<> | 149:156823d33999 | 1139 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
<> | 149:156823d33999 | 1140 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
<> | 149:156823d33999 | 1141 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
<> | 149:156823d33999 | 1142 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
<> | 149:156823d33999 | 1143 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
<> | 149:156823d33999 | 1144 | */ |
<> | 149:156823d33999 | 1145 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
<> | 149:156823d33999 | 1146 | |
<> | 149:156823d33999 | 1147 | /** |
<> | 149:156823d33999 | 1148 | * @brief Clears the specified TIM interrupt flag. |
<> | 149:156823d33999 | 1149 | * @param __HANDLE__: specifies the TIM Handle. |
<> | 149:156823d33999 | 1150 | * @param __FLAG__: specifies the TIM interrupt flag to clear. |
<> | 149:156823d33999 | 1151 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1152 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
<> | 149:156823d33999 | 1153 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
<> | 149:156823d33999 | 1154 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
<> | 149:156823d33999 | 1155 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
<> | 149:156823d33999 | 1156 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
<> | 149:156823d33999 | 1157 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
<> | 149:156823d33999 | 1158 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
<> | 149:156823d33999 | 1159 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
<> | 149:156823d33999 | 1160 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
<> | 149:156823d33999 | 1161 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
<> | 149:156823d33999 | 1162 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
<> | 149:156823d33999 | 1163 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
<> | 149:156823d33999 | 1164 | */ |
<> | 149:156823d33999 | 1165 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
<> | 149:156823d33999 | 1166 | |
<> | 149:156823d33999 | 1167 | /** |
<> | 149:156823d33999 | 1168 | * @brief Checks whether the specified TIM interrupt has occurred or not. |
<> | 149:156823d33999 | 1169 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 1170 | * @param __INTERRUPT__: specifies the TIM interrupt source to check. |
<> | 149:156823d33999 | 1171 | * @retval The state of TIM_IT (SET or RESET). |
<> | 149:156823d33999 | 1172 | */ |
<> | 149:156823d33999 | 1173 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
<> | 149:156823d33999 | 1174 | |
<> | 149:156823d33999 | 1175 | /** |
<> | 149:156823d33999 | 1176 | * @brief Clear the TIM interrupt pending bits |
<> | 149:156823d33999 | 1177 | * @param __HANDLE__: TIM handle |
<> | 149:156823d33999 | 1178 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
<> | 149:156823d33999 | 1179 | * @retval None |
<> | 149:156823d33999 | 1180 | */ |
<> | 149:156823d33999 | 1181 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
<> | 149:156823d33999 | 1182 | |
<> | 149:156823d33999 | 1183 | /** |
<> | 149:156823d33999 | 1184 | * @brief Indicates whether or not the TIM Counter is used as downcounter |
<> | 149:156823d33999 | 1185 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1186 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
<> | 149:156823d33999 | 1187 | * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder |
<> | 149:156823d33999 | 1188 | mode. |
<> | 149:156823d33999 | 1189 | */ |
<> | 149:156823d33999 | 1190 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
<> | 149:156823d33999 | 1191 | |
<> | 149:156823d33999 | 1192 | /** |
<> | 149:156823d33999 | 1193 | * @brief Sets the TIM active prescaler register value on update event. |
<> | 149:156823d33999 | 1194 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1195 | * @param __PRESC__: specifies the active prescaler register new value. |
<> | 149:156823d33999 | 1196 | * @retval None |
<> | 149:156823d33999 | 1197 | */ |
<> | 149:156823d33999 | 1198 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
<> | 149:156823d33999 | 1199 | |
<> | 149:156823d33999 | 1200 | /** |
<> | 149:156823d33999 | 1201 | * @brief Sets the TIM Capture Compare Register value on runtime without |
<> | 149:156823d33999 | 1202 | * calling another time ConfigChannel function. |
<> | 149:156823d33999 | 1203 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1204 | * @param __CHANNEL__ : TIM Channels to be configured. |
<> | 149:156823d33999 | 1205 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1206 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
<> | 149:156823d33999 | 1207 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
<> | 149:156823d33999 | 1208 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
<> | 149:156823d33999 | 1209 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
<> | 149:156823d33999 | 1210 | * @param __COMPARE__: specifies the Capture Compare register new value. |
<> | 149:156823d33999 | 1211 | * @retval None |
<> | 149:156823d33999 | 1212 | */ |
<> | 149:156823d33999 | 1213 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
<> | 149:156823d33999 | 1214 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) |
<> | 149:156823d33999 | 1215 | |
<> | 149:156823d33999 | 1216 | /** |
<> | 149:156823d33999 | 1217 | * @brief Gets the TIM Capture Compare Register value on runtime |
<> | 149:156823d33999 | 1218 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1219 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register |
<> | 149:156823d33999 | 1220 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1221 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
<> | 149:156823d33999 | 1222 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
<> | 149:156823d33999 | 1223 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
<> | 149:156823d33999 | 1224 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
<> | 149:156823d33999 | 1225 | * @retval None |
<> | 149:156823d33999 | 1226 | */ |
<> | 149:156823d33999 | 1227 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
<> | 149:156823d33999 | 1228 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) |
<> | 149:156823d33999 | 1229 | |
<> | 149:156823d33999 | 1230 | /** |
<> | 149:156823d33999 | 1231 | * @brief Sets the TIM Counter Register value on runtime. |
<> | 149:156823d33999 | 1232 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1233 | * @param __COUNTER__: specifies the Counter register new value. |
<> | 149:156823d33999 | 1234 | * @retval None |
<> | 149:156823d33999 | 1235 | */ |
<> | 149:156823d33999 | 1236 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
<> | 149:156823d33999 | 1237 | |
<> | 149:156823d33999 | 1238 | /** |
<> | 149:156823d33999 | 1239 | * @brief Gets the TIM Counter Register value on runtime. |
<> | 149:156823d33999 | 1240 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1241 | * @retval None |
<> | 149:156823d33999 | 1242 | */ |
<> | 149:156823d33999 | 1243 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ |
<> | 149:156823d33999 | 1244 | ((__HANDLE__)->Instance->CNT) |
<> | 149:156823d33999 | 1245 | |
<> | 149:156823d33999 | 1246 | /** |
<> | 149:156823d33999 | 1247 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
<> | 149:156823d33999 | 1248 | * another time any Init function. |
<> | 149:156823d33999 | 1249 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1250 | * @param __AUTORELOAD__: specifies the Counter register new value. |
<> | 149:156823d33999 | 1251 | * @retval None |
<> | 149:156823d33999 | 1252 | */ |
<> | 149:156823d33999 | 1253 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
<> | 149:156823d33999 | 1254 | do{ \ |
<> | 149:156823d33999 | 1255 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
<> | 149:156823d33999 | 1256 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
<> | 149:156823d33999 | 1257 | } while(0) |
<> | 149:156823d33999 | 1258 | |
<> | 149:156823d33999 | 1259 | /** |
<> | 149:156823d33999 | 1260 | * @brief Gets the TIM Autoreload Register value on runtime |
<> | 149:156823d33999 | 1261 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1262 | * @retval None |
<> | 149:156823d33999 | 1263 | */ |
<> | 149:156823d33999 | 1264 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ |
<> | 149:156823d33999 | 1265 | ((__HANDLE__)->Instance->ARR) |
<> | 149:156823d33999 | 1266 | |
<> | 149:156823d33999 | 1267 | /** |
<> | 149:156823d33999 | 1268 | * @brief Sets the TIM Clock Division value on runtime without calling |
<> | 149:156823d33999 | 1269 | * another time any Init function. |
<> | 149:156823d33999 | 1270 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1271 | * @param __CKD__: specifies the clock division value. |
<> | 149:156823d33999 | 1272 | * This parameter can be one of the following value: |
<> | 149:156823d33999 | 1273 | * @arg TIM_CLOCKDIVISION_DIV1 |
<> | 149:156823d33999 | 1274 | * @arg TIM_CLOCKDIVISION_DIV2 |
<> | 149:156823d33999 | 1275 | * @arg TIM_CLOCKDIVISION_DIV4 |
<> | 149:156823d33999 | 1276 | * @retval None |
<> | 149:156823d33999 | 1277 | */ |
<> | 149:156823d33999 | 1278 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
<> | 149:156823d33999 | 1279 | do{ \ |
<> | 149:156823d33999 | 1280 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
<> | 149:156823d33999 | 1281 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
<> | 149:156823d33999 | 1282 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
<> | 149:156823d33999 | 1283 | } while(0) |
<> | 149:156823d33999 | 1284 | |
<> | 149:156823d33999 | 1285 | /** |
<> | 149:156823d33999 | 1286 | * @brief Gets the TIM Clock Division value on runtime |
<> | 149:156823d33999 | 1287 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1288 | * @retval None |
<> | 149:156823d33999 | 1289 | */ |
<> | 149:156823d33999 | 1290 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ |
<> | 149:156823d33999 | 1291 | ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
<> | 149:156823d33999 | 1292 | |
<> | 149:156823d33999 | 1293 | /** |
<> | 149:156823d33999 | 1294 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
<> | 149:156823d33999 | 1295 | * another time HAL_TIM_IC_ConfigChannel() function. |
<> | 149:156823d33999 | 1296 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1297 | * @param __CHANNEL__ : TIM Channels to be configured. |
<> | 149:156823d33999 | 1298 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1299 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
<> | 149:156823d33999 | 1300 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
<> | 149:156823d33999 | 1301 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
<> | 149:156823d33999 | 1302 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
<> | 149:156823d33999 | 1303 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
<> | 149:156823d33999 | 1304 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1305 | * @arg TIM_ICPSC_DIV1: no prescaler |
<> | 149:156823d33999 | 1306 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
<> | 149:156823d33999 | 1307 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
<> | 149:156823d33999 | 1308 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
<> | 149:156823d33999 | 1309 | * @retval None |
<> | 149:156823d33999 | 1310 | */ |
<> | 149:156823d33999 | 1311 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
<> | 149:156823d33999 | 1312 | do{ \ |
<> | 149:156823d33999 | 1313 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
<> | 149:156823d33999 | 1314 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
<> | 149:156823d33999 | 1315 | } while(0) |
<> | 149:156823d33999 | 1316 | |
<> | 149:156823d33999 | 1317 | /** |
<> | 149:156823d33999 | 1318 | * @brief Gets the TIM Input Capture prescaler on runtime |
<> | 149:156823d33999 | 1319 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1320 | * @param __CHANNEL__ : TIM Channels to be configured. |
<> | 149:156823d33999 | 1321 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1322 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
<> | 149:156823d33999 | 1323 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
<> | 149:156823d33999 | 1324 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
<> | 149:156823d33999 | 1325 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
<> | 149:156823d33999 | 1326 | * @retval None |
<> | 149:156823d33999 | 1327 | */ |
<> | 149:156823d33999 | 1328 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
<> | 149:156823d33999 | 1329 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
<> | 149:156823d33999 | 1330 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
<> | 149:156823d33999 | 1331 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
<> | 149:156823d33999 | 1332 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) |
<> | 149:156823d33999 | 1333 | |
<> | 149:156823d33999 | 1334 | /** |
<> | 149:156823d33999 | 1335 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register |
<> | 149:156823d33999 | 1336 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1337 | * @note When the USR bit of the TIMx_CR1 register is set, only counter |
<> | 149:156823d33999 | 1338 | * overflow/underflow generates an update interrupt or DMA request (if |
<> | 149:156823d33999 | 1339 | * enabled) |
<> | 149:156823d33999 | 1340 | * @retval None |
<> | 149:156823d33999 | 1341 | */ |
<> | 149:156823d33999 | 1342 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ |
<> | 149:156823d33999 | 1343 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) |
<> | 149:156823d33999 | 1344 | |
<> | 149:156823d33999 | 1345 | /** |
<> | 149:156823d33999 | 1346 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register |
<> | 149:156823d33999 | 1347 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1348 | * @note When the USR bit of the TIMx_CR1 register is reset, any of the |
<> | 149:156823d33999 | 1349 | * following events generate an update interrupt or DMA request (if |
<> | 149:156823d33999 | 1350 | * enabled): |
<> | 149:156823d33999 | 1351 | * (+) Counter overflow/underflow |
<> | 149:156823d33999 | 1352 | * (+) Setting the UG bit |
<> | 149:156823d33999 | 1353 | * (+) Update generation through the slave mode controller |
<> | 149:156823d33999 | 1354 | * @retval None |
<> | 149:156823d33999 | 1355 | */ |
<> | 149:156823d33999 | 1356 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ |
<> | 149:156823d33999 | 1357 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
<> | 149:156823d33999 | 1358 | |
<> | 149:156823d33999 | 1359 | /** |
<> | 149:156823d33999 | 1360 | * @brief Sets the TIM Capture x input polarity on runtime. |
<> | 149:156823d33999 | 1361 | * @param __HANDLE__: TIM handle. |
<> | 149:156823d33999 | 1362 | * @param __CHANNEL__: TIM Channels to be configured. |
<> | 149:156823d33999 | 1363 | * This parameter can be one of the following values: |
<> | 149:156823d33999 | 1364 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
<> | 149:156823d33999 | 1365 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
<> | 149:156823d33999 | 1366 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
<> | 149:156823d33999 | 1367 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
<> | 149:156823d33999 | 1368 | * @param __POLARITY__: Polarity for TIx source |
<> | 149:156823d33999 | 1369 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
<> | 149:156823d33999 | 1370 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
<> | 149:156823d33999 | 1371 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
<> | 149:156823d33999 | 1372 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
<> | 149:156823d33999 | 1373 | * @retval None |
<> | 149:156823d33999 | 1374 | */ |
<> | 149:156823d33999 | 1375 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
<> | 149:156823d33999 | 1376 | do{ \ |
<> | 149:156823d33999 | 1377 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
<> | 149:156823d33999 | 1378 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
<> | 149:156823d33999 | 1379 | }while(0) |
<> | 149:156823d33999 | 1380 | |
<> | 149:156823d33999 | 1381 | /** |
<> | 149:156823d33999 | 1382 | * @} |
<> | 149:156823d33999 | 1383 | */ |
<> | 149:156823d33999 | 1384 | |
<> | 149:156823d33999 | 1385 | /* Include TIM HAL Extension module */ |
<> | 149:156823d33999 | 1386 | #include "stm32l1xx_hal_tim_ex.h" |
<> | 149:156823d33999 | 1387 | |
<> | 149:156823d33999 | 1388 | /* Exported functions --------------------------------------------------------*/ |
<> | 149:156823d33999 | 1389 | /** @addtogroup TIM_Exported_Functions |
<> | 149:156823d33999 | 1390 | * @{ |
<> | 149:156823d33999 | 1391 | */ |
<> | 149:156823d33999 | 1392 | |
<> | 149:156823d33999 | 1393 | /** @addtogroup TIM_Exported_Functions_Group1 |
<> | 149:156823d33999 | 1394 | * @{ |
<> | 149:156823d33999 | 1395 | */ |
<> | 149:156823d33999 | 1396 | /* Time Base functions ********************************************************/ |
<> | 149:156823d33999 | 1397 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1398 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1399 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1400 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1401 | /* Blocking mode: Polling */ |
<> | 149:156823d33999 | 1402 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1403 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1404 | /* Non-Blocking mode: Interrupt */ |
<> | 149:156823d33999 | 1405 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1406 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1407 | /* Non-Blocking mode: DMA */ |
<> | 149:156823d33999 | 1408 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
<> | 149:156823d33999 | 1409 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1410 | /** |
<> | 149:156823d33999 | 1411 | * @} |
<> | 149:156823d33999 | 1412 | */ |
<> | 149:156823d33999 | 1413 | |
<> | 149:156823d33999 | 1414 | /** @addtogroup TIM_Exported_Functions_Group2 |
<> | 149:156823d33999 | 1415 | * @{ |
<> | 149:156823d33999 | 1416 | */ |
<> | 149:156823d33999 | 1417 | /* Timer Output Compare functions **********************************************/ |
<> | 149:156823d33999 | 1418 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1419 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1420 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1421 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1422 | /* Blocking mode: Polling */ |
<> | 149:156823d33999 | 1423 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1424 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1425 | /* Non-Blocking mode: Interrupt */ |
<> | 149:156823d33999 | 1426 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1427 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1428 | /* Non-Blocking mode: DMA */ |
<> | 149:156823d33999 | 1429 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
<> | 149:156823d33999 | 1430 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1431 | |
<> | 149:156823d33999 | 1432 | /** |
<> | 149:156823d33999 | 1433 | * @} |
<> | 149:156823d33999 | 1434 | */ |
<> | 149:156823d33999 | 1435 | |
<> | 149:156823d33999 | 1436 | /** @addtogroup TIM_Exported_Functions_Group3 |
<> | 149:156823d33999 | 1437 | * @{ |
<> | 149:156823d33999 | 1438 | */ |
<> | 149:156823d33999 | 1439 | /* Timer PWM functions *********************************************************/ |
<> | 149:156823d33999 | 1440 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1441 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1442 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1443 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1444 | /* Blocking mode: Polling */ |
<> | 149:156823d33999 | 1445 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1446 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1447 | /* Non-Blocking mode: Interrupt */ |
<> | 149:156823d33999 | 1448 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1449 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1450 | /* Non-Blocking mode: DMA */ |
<> | 149:156823d33999 | 1451 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
<> | 149:156823d33999 | 1452 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1453 | /** |
<> | 149:156823d33999 | 1454 | * @} |
<> | 149:156823d33999 | 1455 | */ |
<> | 149:156823d33999 | 1456 | |
<> | 149:156823d33999 | 1457 | /** @addtogroup TIM_Exported_Functions_Group4 |
<> | 149:156823d33999 | 1458 | * @{ |
<> | 149:156823d33999 | 1459 | */ |
<> | 149:156823d33999 | 1460 | /* Timer Input Capture functions ***********************************************/ |
<> | 149:156823d33999 | 1461 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1462 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1463 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1464 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1465 | /* Blocking mode: Polling */ |
<> | 149:156823d33999 | 1466 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1467 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1468 | /* Non-Blocking mode: Interrupt */ |
<> | 149:156823d33999 | 1469 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1470 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1471 | /* Non-Blocking mode: DMA */ |
<> | 149:156823d33999 | 1472 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
<> | 149:156823d33999 | 1473 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1474 | /** |
<> | 149:156823d33999 | 1475 | * @} |
<> | 149:156823d33999 | 1476 | */ |
<> | 149:156823d33999 | 1477 | |
<> | 149:156823d33999 | 1478 | /** @addtogroup TIM_Exported_Functions_Group5 |
<> | 149:156823d33999 | 1479 | * @{ |
<> | 149:156823d33999 | 1480 | */ |
<> | 149:156823d33999 | 1481 | /* Timer One Pulse functions ***************************************************/ |
<> | 149:156823d33999 | 1482 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
<> | 149:156823d33999 | 1483 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1484 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1485 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1486 | /* Blocking mode: Polling */ |
<> | 149:156823d33999 | 1487 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
<> | 149:156823d33999 | 1488 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
<> | 149:156823d33999 | 1489 | /* Non-Blocking mode: Interrupt */ |
<> | 149:156823d33999 | 1490 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
<> | 149:156823d33999 | 1491 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
<> | 149:156823d33999 | 1492 | /** |
<> | 149:156823d33999 | 1493 | * @} |
<> | 149:156823d33999 | 1494 | */ |
<> | 149:156823d33999 | 1495 | |
<> | 149:156823d33999 | 1496 | /** @addtogroup TIM_Exported_Functions_Group6 |
<> | 149:156823d33999 | 1497 | * @{ |
<> | 149:156823d33999 | 1498 | */ |
<> | 149:156823d33999 | 1499 | /* Timer Encoder functions *****************************************************/ |
<> | 149:156823d33999 | 1500 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
<> | 149:156823d33999 | 1501 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1502 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1503 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1504 | /* Blocking mode: Polling */ |
<> | 149:156823d33999 | 1505 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1506 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1507 | /* Non-Blocking mode: Interrupt */ |
<> | 149:156823d33999 | 1508 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1509 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1510 | /* Non-Blocking mode: DMA */ |
<> | 149:156823d33999 | 1511 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
<> | 149:156823d33999 | 1512 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1513 | |
<> | 149:156823d33999 | 1514 | /** |
<> | 149:156823d33999 | 1515 | * @} |
<> | 149:156823d33999 | 1516 | */ |
<> | 149:156823d33999 | 1517 | |
<> | 149:156823d33999 | 1518 | /** @addtogroup TIM_Exported_Functions_Group7 |
<> | 149:156823d33999 | 1519 | * @{ |
<> | 149:156823d33999 | 1520 | */ |
<> | 149:156823d33999 | 1521 | /* Interrupt Handler functions **********************************************/ |
<> | 149:156823d33999 | 1522 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1523 | /** |
<> | 149:156823d33999 | 1524 | * @} |
<> | 149:156823d33999 | 1525 | */ |
<> | 149:156823d33999 | 1526 | |
<> | 149:156823d33999 | 1527 | /** @addtogroup TIM_Exported_Functions_Group8 |
<> | 149:156823d33999 | 1528 | * @{ |
<> | 149:156823d33999 | 1529 | */ |
<> | 149:156823d33999 | 1530 | /* Control functions *********************************************************/ |
<> | 149:156823d33999 | 1531 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
<> | 149:156823d33999 | 1532 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
<> | 149:156823d33999 | 1533 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
<> | 149:156823d33999 | 1534 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
<> | 149:156823d33999 | 1535 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
<> | 149:156823d33999 | 1536 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
<> | 149:156823d33999 | 1537 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
<> | 149:156823d33999 | 1538 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
<> | 149:156823d33999 | 1539 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
<> | 149:156823d33999 | 1540 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
<> | 149:156823d33999 | 1541 | uint32_t *BurstBuffer, uint32_t BurstLength); |
<> | 149:156823d33999 | 1542 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
<> | 149:156823d33999 | 1543 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
<> | 149:156823d33999 | 1544 | uint32_t *BurstBuffer, uint32_t BurstLength); |
<> | 149:156823d33999 | 1545 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
<> | 149:156823d33999 | 1546 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
<> | 149:156823d33999 | 1547 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
<> | 149:156823d33999 | 1548 | |
<> | 149:156823d33999 | 1549 | /** |
<> | 149:156823d33999 | 1550 | * @} |
<> | 149:156823d33999 | 1551 | */ |
<> | 149:156823d33999 | 1552 | |
<> | 149:156823d33999 | 1553 | /** @addtogroup TIM_Exported_Functions_Group9 |
<> | 149:156823d33999 | 1554 | * @{ |
<> | 149:156823d33999 | 1555 | */ |
<> | 149:156823d33999 | 1556 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
<> | 149:156823d33999 | 1557 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1558 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1559 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1560 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1561 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1562 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1563 | /** |
<> | 149:156823d33999 | 1564 | * @} |
<> | 149:156823d33999 | 1565 | */ |
<> | 149:156823d33999 | 1566 | |
<> | 149:156823d33999 | 1567 | /** @addtogroup TIM_Exported_Functions_Group10 |
<> | 149:156823d33999 | 1568 | * @{ |
<> | 149:156823d33999 | 1569 | */ |
<> | 149:156823d33999 | 1570 | /* Peripheral State functions **************************************************/ |
<> | 149:156823d33999 | 1571 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1572 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1573 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1574 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1575 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1576 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
<> | 149:156823d33999 | 1577 | |
<> | 149:156823d33999 | 1578 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
<> | 149:156823d33999 | 1579 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
<> | 149:156823d33999 | 1580 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
<> | 149:156823d33999 | 1581 | |
<> | 149:156823d33999 | 1582 | /** |
<> | 149:156823d33999 | 1583 | * @} |
<> | 149:156823d33999 | 1584 | */ |
<> | 149:156823d33999 | 1585 | |
<> | 149:156823d33999 | 1586 | /** |
<> | 149:156823d33999 | 1587 | * @} |
<> | 149:156823d33999 | 1588 | */ |
<> | 149:156823d33999 | 1589 | |
<> | 149:156823d33999 | 1590 | /** |
<> | 149:156823d33999 | 1591 | * @} |
<> | 149:156823d33999 | 1592 | */ |
<> | 149:156823d33999 | 1593 | |
<> | 149:156823d33999 | 1594 | /** |
<> | 149:156823d33999 | 1595 | * @} |
<> | 149:156823d33999 | 1596 | */ |
<> | 149:156823d33999 | 1597 | |
<> | 149:156823d33999 | 1598 | #ifdef __cplusplus |
<> | 149:156823d33999 | 1599 | } |
<> | 149:156823d33999 | 1600 | #endif |
<> | 149:156823d33999 | 1601 | |
<> | 149:156823d33999 | 1602 | #endif /* __STM32L1xx_HAL_TIM_H */ |
<> | 149:156823d33999 | 1603 | |
<> | 149:156823d33999 | 1604 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |