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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_cortex.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Header file of CORTEX HAL module.
<> 149:156823d33999 6 ******************************************************************************
<> 149:156823d33999 7 * @attention
<> 149:156823d33999 8 *
AnnaBridge 184:08ed48f1de7f 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 12 * are permitted provided that the following conditions are met:
<> 149:156823d33999 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 14 * this list of conditions and the following disclaimer.
<> 149:156823d33999 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 17 * and/or other materials provided with the distribution.
<> 149:156823d33999 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 19 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 20 * without specific prior written permission.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 32 *
<> 149:156823d33999 33 ******************************************************************************
<> 149:156823d33999 34 */
<> 149:156823d33999 35
<> 149:156823d33999 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 37 #ifndef __STM32L1xx_HAL_CORTEX_H
<> 149:156823d33999 38 #define __STM32L1xx_HAL_CORTEX_H
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifdef __cplusplus
<> 149:156823d33999 41 extern "C" {
<> 149:156823d33999 42 #endif
<> 149:156823d33999 43
<> 149:156823d33999 44 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 45 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 46
<> 149:156823d33999 47 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 48 * @{
<> 149:156823d33999 49 */
<> 149:156823d33999 50
<> 149:156823d33999 51 /** @addtogroup CORTEX
<> 149:156823d33999 52 * @{
<> 149:156823d33999 53 */
<> 149:156823d33999 54
<> 149:156823d33999 55 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 56 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
<> 149:156823d33999 57 * @{
<> 149:156823d33999 58 */
<> 149:156823d33999 59
<> 149:156823d33999 60 #if (__MPU_PRESENT == 1)
<> 149:156823d33999 61 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
<> 149:156823d33999 62 * @brief MPU Region initialization structure
<> 149:156823d33999 63 * @{
<> 149:156823d33999 64 */
<> 149:156823d33999 65 typedef struct
<> 149:156823d33999 66 {
<> 149:156823d33999 67 uint8_t Enable; /*!< Specifies the status of the region.
<> 149:156823d33999 68 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
<> 149:156823d33999 69 uint8_t Number; /*!< Specifies the number of the region to protect.
<> 149:156823d33999 70 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
<> 149:156823d33999 71 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
<> 149:156823d33999 72 uint8_t Size; /*!< Specifies the size of the region to protect.
<> 149:156823d33999 73 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
<> 149:156823d33999 74 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
<> 149:156823d33999 75 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 149:156823d33999 76 uint8_t TypeExtField; /*!< Specifies the TEX field level.
<> 149:156823d33999 77 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
<> 149:156823d33999 78 uint8_t AccessPermission; /*!< Specifies the region access permission type.
<> 149:156823d33999 79 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
<> 149:156823d33999 80 uint8_t DisableExec; /*!< Specifies the instruction access status.
<> 149:156823d33999 81 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
<> 149:156823d33999 82 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
<> 149:156823d33999 83 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
<> 149:156823d33999 84 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
<> 149:156823d33999 85 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
<> 149:156823d33999 86 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
<> 149:156823d33999 87 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
<> 149:156823d33999 88 }MPU_Region_InitTypeDef;
<> 149:156823d33999 89 /**
<> 149:156823d33999 90 * @}
<> 149:156823d33999 91 */
<> 149:156823d33999 92 #endif /* __MPU_PRESENT */
<> 149:156823d33999 93
<> 149:156823d33999 94 /**
<> 149:156823d33999 95 * @}
<> 149:156823d33999 96 */
<> 149:156823d33999 97
<> 149:156823d33999 98 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 99
<> 149:156823d33999 100 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
<> 149:156823d33999 101 * @{
<> 149:156823d33999 102 */
<> 149:156823d33999 103
<> 149:156823d33999 104
<> 149:156823d33999 105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
<> 149:156823d33999 106 * @{
<> 149:156823d33999 107 */
<> 149:156823d33999 108
AnnaBridge 184:08ed48f1de7f 109 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
AnnaBridge 184:08ed48f1de7f 110 4 bits for subpriority */
AnnaBridge 184:08ed48f1de7f 111 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
AnnaBridge 184:08ed48f1de7f 112 3 bits for subpriority */
AnnaBridge 184:08ed48f1de7f 113 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
AnnaBridge 184:08ed48f1de7f 114 2 bits for subpriority */
AnnaBridge 184:08ed48f1de7f 115 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
AnnaBridge 184:08ed48f1de7f 116 1 bits for subpriority */
AnnaBridge 184:08ed48f1de7f 117 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
AnnaBridge 184:08ed48f1de7f 118 0 bits for subpriority */
<> 149:156823d33999 119 /**
<> 149:156823d33999 120 * @}
<> 149:156823d33999 121 */
<> 149:156823d33999 122
<> 149:156823d33999 123 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
<> 149:156823d33999 124 * @{
<> 149:156823d33999 125 */
AnnaBridge 184:08ed48f1de7f 126 #define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
AnnaBridge 184:08ed48f1de7f 127 #define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
<> 149:156823d33999 128
<> 149:156823d33999 129 /**
<> 149:156823d33999 130 * @}
<> 149:156823d33999 131 */
<> 149:156823d33999 132
<> 149:156823d33999 133 #if (__MPU_PRESENT == 1)
<> 149:156823d33999 134 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
<> 149:156823d33999 135 * @{
<> 149:156823d33999 136 */
AnnaBridge 184:08ed48f1de7f 137 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
AnnaBridge 184:08ed48f1de7f 138 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
AnnaBridge 184:08ed48f1de7f 139 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
AnnaBridge 184:08ed48f1de7f 140 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
AnnaBridge 184:08ed48f1de7f 141
<> 149:156823d33999 142 /**
<> 149:156823d33999 143 * @}
<> 149:156823d33999 144 */
<> 149:156823d33999 145
<> 149:156823d33999 146 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
<> 149:156823d33999 147 * @{
<> 149:156823d33999 148 */
<> 149:156823d33999 149 #define MPU_REGION_ENABLE ((uint8_t)0x01)
<> 149:156823d33999 150 #define MPU_REGION_DISABLE ((uint8_t)0x00)
<> 149:156823d33999 151 /**
<> 149:156823d33999 152 * @}
<> 149:156823d33999 153 */
<> 149:156823d33999 154
<> 149:156823d33999 155 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
<> 149:156823d33999 156 * @{
<> 149:156823d33999 157 */
<> 149:156823d33999 158 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
<> 149:156823d33999 159 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
<> 149:156823d33999 160 /**
<> 149:156823d33999 161 * @}
<> 149:156823d33999 162 */
<> 149:156823d33999 163
<> 149:156823d33999 164 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
<> 149:156823d33999 165 * @{
<> 149:156823d33999 166 */
<> 149:156823d33999 167 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
<> 149:156823d33999 168 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
<> 149:156823d33999 169 /**
<> 149:156823d33999 170 * @}
<> 149:156823d33999 171 */
<> 149:156823d33999 172
<> 149:156823d33999 173 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
<> 149:156823d33999 174 * @{
<> 149:156823d33999 175 */
<> 149:156823d33999 176 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
<> 149:156823d33999 177 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
<> 149:156823d33999 178 /**
<> 149:156823d33999 179 * @}
<> 149:156823d33999 180 */
<> 149:156823d33999 181
<> 149:156823d33999 182 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
<> 149:156823d33999 183 * @{
<> 149:156823d33999 184 */
<> 149:156823d33999 185 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
<> 149:156823d33999 186 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
<> 149:156823d33999 187 /**
<> 149:156823d33999 188 * @}
<> 149:156823d33999 189 */
<> 149:156823d33999 190
<> 149:156823d33999 191 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
<> 149:156823d33999 192 * @{
<> 149:156823d33999 193 */
<> 149:156823d33999 194 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
<> 149:156823d33999 195 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
<> 149:156823d33999 196 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
<> 149:156823d33999 197 /**
<> 149:156823d33999 198 * @}
<> 149:156823d33999 199 */
<> 149:156823d33999 200
<> 149:156823d33999 201 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
<> 149:156823d33999 202 * @{
<> 149:156823d33999 203 */
<> 149:156823d33999 204 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
<> 149:156823d33999 205 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
<> 149:156823d33999 206 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
<> 149:156823d33999 207 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
<> 149:156823d33999 208 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
<> 149:156823d33999 209 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
<> 149:156823d33999 210 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
<> 149:156823d33999 211 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
<> 149:156823d33999 212 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
<> 149:156823d33999 213 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
<> 149:156823d33999 214 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
<> 149:156823d33999 215 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
<> 149:156823d33999 216 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
<> 149:156823d33999 217 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
<> 149:156823d33999 218 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
<> 149:156823d33999 219 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
<> 149:156823d33999 220 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
<> 149:156823d33999 221 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
<> 149:156823d33999 222 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
<> 149:156823d33999 223 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
<> 149:156823d33999 224 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
<> 149:156823d33999 225 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
<> 149:156823d33999 226 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
<> 149:156823d33999 227 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
<> 149:156823d33999 228 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
<> 149:156823d33999 229 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
<> 149:156823d33999 230 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
<> 149:156823d33999 231 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
<> 149:156823d33999 232 /**
<> 149:156823d33999 233 * @}
<> 149:156823d33999 234 */
<> 149:156823d33999 235
<> 149:156823d33999 236 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
<> 149:156823d33999 237 * @{
<> 149:156823d33999 238 */
<> 149:156823d33999 239 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
<> 149:156823d33999 240 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
<> 149:156823d33999 241 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
<> 149:156823d33999 242 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
<> 149:156823d33999 243 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
<> 149:156823d33999 244 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
<> 149:156823d33999 245 /**
<> 149:156823d33999 246 * @}
<> 149:156823d33999 247 */
<> 149:156823d33999 248
<> 149:156823d33999 249 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
<> 149:156823d33999 250 * @{
<> 149:156823d33999 251 */
<> 149:156823d33999 252 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
<> 149:156823d33999 253 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
<> 149:156823d33999 254 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
<> 149:156823d33999 255 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
<> 149:156823d33999 256 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
<> 149:156823d33999 257 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
<> 149:156823d33999 258 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
<> 149:156823d33999 259 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
<> 149:156823d33999 260 /**
<> 149:156823d33999 261 * @}
<> 149:156823d33999 262 */
<> 149:156823d33999 263 #endif /* __MPU_PRESENT */
<> 149:156823d33999 264 /**
<> 149:156823d33999 265 * @}
<> 149:156823d33999 266 */
<> 149:156823d33999 267
<> 149:156823d33999 268 /* Exported Macros -----------------------------------------------------------*/
<> 149:156823d33999 269 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
<> 149:156823d33999 270 * @{
<> 149:156823d33999 271 */
<> 149:156823d33999 272
<> 149:156823d33999 273 /** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
<> 149:156823d33999 274 * @{
<> 149:156823d33999 275 */
<> 149:156823d33999 276 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
<> 149:156823d33999 277 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
<> 149:156823d33999 278 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
<> 149:156823d33999 279 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
<> 149:156823d33999 280 ((GROUP) == NVIC_PRIORITYGROUP_4))
<> 149:156823d33999 281
<> 149:156823d33999 282 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<> 149:156823d33999 283
<> 149:156823d33999 284 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<> 149:156823d33999 285
<> 149:156823d33999 286 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
<> 149:156823d33999 287
<> 149:156823d33999 288 /**
<> 149:156823d33999 289 * @}
<> 149:156823d33999 290 */
<> 149:156823d33999 291
<> 149:156823d33999 292 /**
<> 149:156823d33999 293 * @}
<> 149:156823d33999 294 */
<> 149:156823d33999 295
<> 149:156823d33999 296 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 297 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
<> 149:156823d33999 298 * @{
<> 149:156823d33999 299 */
<> 149:156823d33999 300
<> 149:156823d33999 301 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
<> 149:156823d33999 302 * @{
<> 149:156823d33999 303 */
<> 149:156823d33999 304 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
<> 149:156823d33999 305 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
<> 149:156823d33999 306 /**
<> 149:156823d33999 307 * @}
<> 149:156823d33999 308 */
<> 149:156823d33999 309
<> 149:156823d33999 310 #if (__MPU_PRESENT == 1)
<> 149:156823d33999 311 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
<> 149:156823d33999 312 ((STATE) == MPU_REGION_DISABLE))
<> 149:156823d33999 313
<> 149:156823d33999 314 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
<> 149:156823d33999 315 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
<> 149:156823d33999 316
<> 149:156823d33999 317 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
<> 149:156823d33999 318 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
<> 149:156823d33999 319
<> 149:156823d33999 320 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
<> 149:156823d33999 321 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
<> 149:156823d33999 322
<> 149:156823d33999 323 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
<> 149:156823d33999 324 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
<> 149:156823d33999 325
<> 149:156823d33999 326 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
<> 149:156823d33999 327 ((TYPE) == MPU_TEX_LEVEL1) || \
<> 149:156823d33999 328 ((TYPE) == MPU_TEX_LEVEL2))
<> 149:156823d33999 329
<> 149:156823d33999 330 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
<> 149:156823d33999 331 ((TYPE) == MPU_REGION_PRIV_RW) || \
<> 149:156823d33999 332 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
<> 149:156823d33999 333 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
<> 149:156823d33999 334 ((TYPE) == MPU_REGION_PRIV_RO) || \
<> 149:156823d33999 335 ((TYPE) == MPU_REGION_PRIV_RO_URO))
<> 149:156823d33999 336
<> 149:156823d33999 337 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
<> 149:156823d33999 338 ((NUMBER) == MPU_REGION_NUMBER1) || \
<> 149:156823d33999 339 ((NUMBER) == MPU_REGION_NUMBER2) || \
<> 149:156823d33999 340 ((NUMBER) == MPU_REGION_NUMBER3) || \
<> 149:156823d33999 341 ((NUMBER) == MPU_REGION_NUMBER4) || \
<> 149:156823d33999 342 ((NUMBER) == MPU_REGION_NUMBER5) || \
<> 149:156823d33999 343 ((NUMBER) == MPU_REGION_NUMBER6) || \
<> 149:156823d33999 344 ((NUMBER) == MPU_REGION_NUMBER7))
<> 149:156823d33999 345
<> 149:156823d33999 346 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
<> 149:156823d33999 347 ((SIZE) == MPU_REGION_SIZE_64B) || \
<> 149:156823d33999 348 ((SIZE) == MPU_REGION_SIZE_128B) || \
<> 149:156823d33999 349 ((SIZE) == MPU_REGION_SIZE_256B) || \
<> 149:156823d33999 350 ((SIZE) == MPU_REGION_SIZE_512B) || \
<> 149:156823d33999 351 ((SIZE) == MPU_REGION_SIZE_1KB) || \
<> 149:156823d33999 352 ((SIZE) == MPU_REGION_SIZE_2KB) || \
<> 149:156823d33999 353 ((SIZE) == MPU_REGION_SIZE_4KB) || \
<> 149:156823d33999 354 ((SIZE) == MPU_REGION_SIZE_8KB) || \
<> 149:156823d33999 355 ((SIZE) == MPU_REGION_SIZE_16KB) || \
<> 149:156823d33999 356 ((SIZE) == MPU_REGION_SIZE_32KB) || \
<> 149:156823d33999 357 ((SIZE) == MPU_REGION_SIZE_64KB) || \
<> 149:156823d33999 358 ((SIZE) == MPU_REGION_SIZE_128KB) || \
<> 149:156823d33999 359 ((SIZE) == MPU_REGION_SIZE_256KB) || \
<> 149:156823d33999 360 ((SIZE) == MPU_REGION_SIZE_512KB) || \
<> 149:156823d33999 361 ((SIZE) == MPU_REGION_SIZE_1MB) || \
<> 149:156823d33999 362 ((SIZE) == MPU_REGION_SIZE_2MB) || \
<> 149:156823d33999 363 ((SIZE) == MPU_REGION_SIZE_4MB) || \
<> 149:156823d33999 364 ((SIZE) == MPU_REGION_SIZE_8MB) || \
<> 149:156823d33999 365 ((SIZE) == MPU_REGION_SIZE_16MB) || \
<> 149:156823d33999 366 ((SIZE) == MPU_REGION_SIZE_32MB) || \
<> 149:156823d33999 367 ((SIZE) == MPU_REGION_SIZE_64MB) || \
<> 149:156823d33999 368 ((SIZE) == MPU_REGION_SIZE_128MB) || \
<> 149:156823d33999 369 ((SIZE) == MPU_REGION_SIZE_256MB) || \
<> 149:156823d33999 370 ((SIZE) == MPU_REGION_SIZE_512MB) || \
<> 149:156823d33999 371 ((SIZE) == MPU_REGION_SIZE_1GB) || \
<> 149:156823d33999 372 ((SIZE) == MPU_REGION_SIZE_2GB) || \
<> 149:156823d33999 373 ((SIZE) == MPU_REGION_SIZE_4GB))
<> 149:156823d33999 374
<> 149:156823d33999 375 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
<> 149:156823d33999 376 #endif /* __MPU_PRESENT */
<> 149:156823d33999 377
<> 149:156823d33999 378 /**
<> 149:156823d33999 379 * @}
<> 149:156823d33999 380 */
<> 149:156823d33999 381
<> 149:156823d33999 382 /* Private functions ---------------------------------------------------------*/
<> 149:156823d33999 383 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
<> 149:156823d33999 384 * @brief CORTEX private functions
<> 149:156823d33999 385 * @{
<> 149:156823d33999 386 */
<> 149:156823d33999 387
<> 149:156823d33999 388
<> 149:156823d33999 389 /**
<> 149:156823d33999 390 * @}
<> 149:156823d33999 391 */
<> 149:156823d33999 392
<> 149:156823d33999 393 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 394 /** @addtogroup CORTEX_Exported_Functions
<> 149:156823d33999 395 * @{
<> 149:156823d33999 396 */
<> 149:156823d33999 397
<> 149:156823d33999 398 /** @addtogroup CORTEX_Exported_Functions_Group1
<> 149:156823d33999 399 * @{
<> 149:156823d33999 400 */
<> 149:156823d33999 401 /* Initialization and de-initialization functions *****************************/
<> 149:156823d33999 402 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
<> 149:156823d33999 403 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
<> 149:156823d33999 404 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
<> 149:156823d33999 405 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
<> 149:156823d33999 406 void HAL_NVIC_SystemReset(void);
<> 149:156823d33999 407 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
<> 149:156823d33999 408 /**
<> 149:156823d33999 409 * @}
<> 149:156823d33999 410 */
<> 149:156823d33999 411
<> 149:156823d33999 412 /** @addtogroup CORTEX_Exported_Functions_Group2
<> 149:156823d33999 413 * @{
<> 149:156823d33999 414 */
<> 149:156823d33999 415 /* Peripheral Control functions ***********************************************/
<> 149:156823d33999 416 #if (__MPU_PRESENT == 1)
AnnaBridge 184:08ed48f1de7f 417 void HAL_MPU_Enable(uint32_t MPU_Control);
AnnaBridge 184:08ed48f1de7f 418 void HAL_MPU_Disable(void);
<> 149:156823d33999 419 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
<> 149:156823d33999 420 #endif /* __MPU_PRESENT */
<> 149:156823d33999 421 uint32_t HAL_NVIC_GetPriorityGrouping(void);
<> 149:156823d33999 422 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
<> 149:156823d33999 423 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
<> 149:156823d33999 424 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
<> 149:156823d33999 425 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
<> 149:156823d33999 426 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
<> 149:156823d33999 427 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
<> 149:156823d33999 428 void HAL_SYSTICK_IRQHandler(void);
<> 149:156823d33999 429 void HAL_SYSTICK_Callback(void);
<> 149:156823d33999 430 /**
<> 149:156823d33999 431 * @}
<> 149:156823d33999 432 */
<> 149:156823d33999 433
<> 149:156823d33999 434 /**
<> 149:156823d33999 435 * @}
<> 149:156823d33999 436 */
<> 149:156823d33999 437
<> 149:156823d33999 438 /**
<> 149:156823d33999 439 * @}
<> 149:156823d33999 440 */
<> 149:156823d33999 441
<> 149:156823d33999 442 /**
<> 149:156823d33999 443 * @}
<> 149:156823d33999 444 */
<> 149:156823d33999 445
<> 149:156823d33999 446 #ifdef __cplusplus
<> 149:156823d33999 447 }
<> 149:156823d33999 448 #endif
<> 149:156823d33999 449
<> 149:156823d33999 450 #endif /* __STM32L1xx_HAL_CORTEX_H */
<> 149:156823d33999 451
<> 149:156823d33999 452
<> 149:156823d33999 453 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/