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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Child:: 184:08ed48f1de7f

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_hal_cortex.h
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @version V1.2.0
<>	149:156823d33999	6	* @date 01-July-2016
<>	149:156823d33999	7	* @brief Header file of CORTEX HAL module.
<>	149:156823d33999	8	******************************************************************************
<>	149:156823d33999	9	* @attention
<>	149:156823d33999	10	*
<>	149:156823d33999	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	149:156823d33999	12	*
<>	149:156823d33999	13	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	14	* are permitted provided that the following conditions are met:
<>	149:156823d33999	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	16	* this list of conditions and the following disclaimer.
<>	149:156823d33999	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	18	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	19	* and/or other materials provided with the distribution.
<>	149:156823d33999	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	21	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	22	* without specific prior written permission.
<>	149:156823d33999	23	*
<>	149:156823d33999	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	34	*
<>	149:156823d33999	35	******************************************************************************
<>	149:156823d33999	36	*/
<>	149:156823d33999	37
<>	149:156823d33999	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	149:156823d33999	39	#ifndef __STM32L1xx_HAL_CORTEX_H
<>	149:156823d33999	40	#define __STM32L1xx_HAL_CORTEX_H
<>	149:156823d33999	41
<>	149:156823d33999	42	#ifdef __cplusplus
<>	149:156823d33999	43	extern "C" {
<>	149:156823d33999	44	#endif
<>	149:156823d33999	45
<>	149:156823d33999	46	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	47	#include "stm32l1xx_hal_def.h"
<>	149:156823d33999	48
<>	149:156823d33999	49	/** @addtogroup STM32L1xx_HAL_Driver
<>	149:156823d33999	50	* @{
<>	149:156823d33999	51	*/
<>	149:156823d33999	52
<>	149:156823d33999	53	/** @addtogroup CORTEX
<>	149:156823d33999	54	* @{
<>	149:156823d33999	55	*/
<>	149:156823d33999	56
<>	149:156823d33999	57	/* Exported types ------------------------------------------------------------*/
<>	149:156823d33999	58	/** @defgroup CORTEX_Exported_Types Cortex Exported Types
<>	149:156823d33999	59	* @{
<>	149:156823d33999	60	*/
<>	149:156823d33999	61
<>	149:156823d33999	62	#if (__MPU_PRESENT == 1)
<>	149:156823d33999	63	/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
<>	149:156823d33999	64	* @brief MPU Region initialization structure
<>	149:156823d33999	65	* @{
<>	149:156823d33999	66	*/
<>	149:156823d33999	67	typedef struct
<>	149:156823d33999	68	{
<>	149:156823d33999	69	uint8_t Enable; /*!< Specifies the status of the region.
<>	149:156823d33999	70	This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
<>	149:156823d33999	71	uint8_t Number; /*!< Specifies the number of the region to protect.
<>	149:156823d33999	72	This parameter can be a value of @ref CORTEX_MPU_Region_Number */
<>	149:156823d33999	73	uint32_t BaseAddress; /!< Specifies the base address of the region to protect. /
<>	149:156823d33999	74	uint8_t Size; /*!< Specifies the size of the region to protect.
<>	149:156823d33999	75	This parameter can be a value of @ref CORTEX_MPU_Region_Size */
<>	149:156823d33999	76	uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
<>	149:156823d33999	77	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<>	149:156823d33999	78	uint8_t TypeExtField; /*!< Specifies the TEX field level.
<>	149:156823d33999	79	This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
<>	149:156823d33999	80	uint8_t AccessPermission; /*!< Specifies the region access permission type.
<>	149:156823d33999	81	This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
<>	149:156823d33999	82	uint8_t DisableExec; /*!< Specifies the instruction access status.
<>	149:156823d33999	83	This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
<>	149:156823d33999	84	uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
<>	149:156823d33999	85	This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
<>	149:156823d33999	86	uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
<>	149:156823d33999	87	This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
<>	149:156823d33999	88	uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
<>	149:156823d33999	89	This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
<>	149:156823d33999	90	}MPU_Region_InitTypeDef;
<>	149:156823d33999	91	/**
<>	149:156823d33999	92	* @}
<>	149:156823d33999	93	*/
<>	149:156823d33999	94	#endif /* __MPU_PRESENT */
<>	149:156823d33999	95
<>	149:156823d33999	96	/**
<>	149:156823d33999	97	* @}
<>	149:156823d33999	98	*/
<>	149:156823d33999	99
<>	149:156823d33999	100	/* Exported constants --------------------------------------------------------*/
<>	149:156823d33999	101
<>	149:156823d33999	102	/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
<>	149:156823d33999	103	* @{
<>	149:156823d33999	104	*/
<>	149:156823d33999	105
<>	149:156823d33999	106
<>	149:156823d33999	107	/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
<>	149:156823d33999	108	* @{
<>	149:156823d33999	109	*/
<>	149:156823d33999	110
<>	149:156823d33999	111	#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
<>	149:156823d33999	112	4 bits for subpriority */
<>	149:156823d33999	113	#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
<>	149:156823d33999	114	3 bits for subpriority */
<>	149:156823d33999	115	#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
<>	149:156823d33999	116	2 bits for subpriority */
<>	149:156823d33999	117	#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
<>	149:156823d33999	118	1 bits for subpriority */
<>	149:156823d33999	119	#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
<>	149:156823d33999	120	0 bits for subpriority */
<>	149:156823d33999	121	/**
<>	149:156823d33999	122	* @}
<>	149:156823d33999	123	*/
<>	149:156823d33999	124
<>	149:156823d33999	125	/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
<>	149:156823d33999	126	* @{
<>	149:156823d33999	127	*/
<>	149:156823d33999	128	#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
<>	149:156823d33999	129	#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
<>	149:156823d33999	130
<>	149:156823d33999	131	/**
<>	149:156823d33999	132	* @}
<>	149:156823d33999	133	*/
<>	149:156823d33999	134
<>	149:156823d33999	135	#if (__MPU_PRESENT == 1)
<>	149:156823d33999	136	/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
<>	149:156823d33999	137	* @{
<>	149:156823d33999	138	*/
<>	149:156823d33999	139	#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
<>	149:156823d33999	140	#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
<>	149:156823d33999	141	#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
<>	149:156823d33999	142	#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
<>	149:156823d33999	143	/**
<>	149:156823d33999	144	* @}
<>	149:156823d33999	145	*/
<>	149:156823d33999	146
<>	149:156823d33999	147	/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
<>	149:156823d33999	148	* @{
<>	149:156823d33999	149	*/
<>	149:156823d33999	150	#define MPU_REGION_ENABLE ((uint8_t)0x01)
<>	149:156823d33999	151	#define MPU_REGION_DISABLE ((uint8_t)0x00)
<>	149:156823d33999	152	/**
<>	149:156823d33999	153	* @}
<>	149:156823d33999	154	*/
<>	149:156823d33999	155
<>	149:156823d33999	156	/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
<>	149:156823d33999	157	* @{
<>	149:156823d33999	158	*/
<>	149:156823d33999	159	#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
<>	149:156823d33999	160	#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
<>	149:156823d33999	161	/**
<>	149:156823d33999	162	* @}
<>	149:156823d33999	163	*/
<>	149:156823d33999	164
<>	149:156823d33999	165	/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
<>	149:156823d33999	166	* @{
<>	149:156823d33999	167	*/
<>	149:156823d33999	168	#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
<>	149:156823d33999	169	#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
<>	149:156823d33999	170	/**
<>	149:156823d33999	171	* @}
<>	149:156823d33999	172	*/
<>	149:156823d33999	173
<>	149:156823d33999	174	/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
<>	149:156823d33999	175	* @{
<>	149:156823d33999	176	*/
<>	149:156823d33999	177	#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
<>	149:156823d33999	178	#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
<>	149:156823d33999	179	/**
<>	149:156823d33999	180	* @}
<>	149:156823d33999	181	*/
<>	149:156823d33999	182
<>	149:156823d33999	183	/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
<>	149:156823d33999	184	* @{
<>	149:156823d33999	185	*/
<>	149:156823d33999	186	#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
<>	149:156823d33999	187	#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
<>	149:156823d33999	188	/**
<>	149:156823d33999	189	* @}
<>	149:156823d33999	190	*/
<>	149:156823d33999	191
<>	149:156823d33999	192	/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
<>	149:156823d33999	193	* @{
<>	149:156823d33999	194	*/
<>	149:156823d33999	195	#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
<>	149:156823d33999	196	#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
<>	149:156823d33999	197	#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
<>	149:156823d33999	198	/**
<>	149:156823d33999	199	* @}
<>	149:156823d33999	200	*/
<>	149:156823d33999	201
<>	149:156823d33999	202	/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
<>	149:156823d33999	203	* @{
<>	149:156823d33999	204	*/
<>	149:156823d33999	205	#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
<>	149:156823d33999	206	#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
<>	149:156823d33999	207	#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
<>	149:156823d33999	208	#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
<>	149:156823d33999	209	#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
<>	149:156823d33999	210	#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
<>	149:156823d33999	211	#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
<>	149:156823d33999	212	#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
<>	149:156823d33999	213	#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
<>	149:156823d33999	214	#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
<>	149:156823d33999	215	#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
<>	149:156823d33999	216	#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
<>	149:156823d33999	217	#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
<>	149:156823d33999	218	#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
<>	149:156823d33999	219	#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
<>	149:156823d33999	220	#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
<>	149:156823d33999	221	#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
<>	149:156823d33999	222	#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
<>	149:156823d33999	223	#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
<>	149:156823d33999	224	#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
<>	149:156823d33999	225	#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
<>	149:156823d33999	226	#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
<>	149:156823d33999	227	#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
<>	149:156823d33999	228	#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
<>	149:156823d33999	229	#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
<>	149:156823d33999	230	#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
<>	149:156823d33999	231	#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
<>	149:156823d33999	232	#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
<>	149:156823d33999	233	/**
<>	149:156823d33999	234	* @}
<>	149:156823d33999	235	*/
<>	149:156823d33999	236
<>	149:156823d33999	237	/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
<>	149:156823d33999	238	* @{
<>	149:156823d33999	239	*/
<>	149:156823d33999	240	#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
<>	149:156823d33999	241	#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
<>	149:156823d33999	242	#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
<>	149:156823d33999	243	#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
<>	149:156823d33999	244	#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
<>	149:156823d33999	245	#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
<>	149:156823d33999	246	/**
<>	149:156823d33999	247	* @}
<>	149:156823d33999	248	*/
<>	149:156823d33999	249
<>	149:156823d33999	250	/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
<>	149:156823d33999	251	* @{
<>	149:156823d33999	252	*/
<>	149:156823d33999	253	#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
<>	149:156823d33999	254	#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
<>	149:156823d33999	255	#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
<>	149:156823d33999	256	#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
<>	149:156823d33999	257	#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
<>	149:156823d33999	258	#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
<>	149:156823d33999	259	#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
<>	149:156823d33999	260	#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
<>	149:156823d33999	261	/**
<>	149:156823d33999	262	* @}
<>	149:156823d33999	263	*/
<>	149:156823d33999	264	#endif /* __MPU_PRESENT */
<>	149:156823d33999	265	/**
<>	149:156823d33999	266	* @}
<>	149:156823d33999	267	*/
<>	149:156823d33999	268
<>	149:156823d33999	269	/* Exported Macros -----------------------------------------------------------*/
<>	149:156823d33999	270	/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
<>	149:156823d33999	271	* @{
<>	149:156823d33999	272	*/
<>	149:156823d33999	273
<>	149:156823d33999	274	/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
<>	149:156823d33999	275	* @{
<>	149:156823d33999	276	*/
<>	149:156823d33999	277	#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) \|\| \
<>	149:156823d33999	278	((GROUP) == NVIC_PRIORITYGROUP_1) \|\| \
<>	149:156823d33999	279	((GROUP) == NVIC_PRIORITYGROUP_2) \|\| \
<>	149:156823d33999	280	((GROUP) == NVIC_PRIORITYGROUP_3) \|\| \
<>	149:156823d33999	281	((GROUP) == NVIC_PRIORITYGROUP_4))
<>	149:156823d33999	282
<>	149:156823d33999	283	#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<>	149:156823d33999	284
<>	149:156823d33999	285	#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<>	149:156823d33999	286
<>	149:156823d33999	287	#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
<>	149:156823d33999	288
<>	149:156823d33999	289	/**
<>	149:156823d33999	290	* @}
<>	149:156823d33999	291	*/
<>	149:156823d33999	292
<>	149:156823d33999	293	/**
<>	149:156823d33999	294	* @}
<>	149:156823d33999	295	*/
<>	149:156823d33999	296
<>	149:156823d33999	297	/* Private macro -------------------------------------------------------------*/
<>	149:156823d33999	298	/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
<>	149:156823d33999	299	* @{
<>	149:156823d33999	300	*/
<>	149:156823d33999	301
<>	149:156823d33999	302	/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
<>	149:156823d33999	303	* @{
<>	149:156823d33999	304	*/
<>	149:156823d33999	305	#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) \|\| \
<>	149:156823d33999	306	((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
<>	149:156823d33999	307	/**
<>	149:156823d33999	308	* @}
<>	149:156823d33999	309	*/
<>	149:156823d33999	310
<>	149:156823d33999	311	#if (__MPU_PRESENT == 1)
<>	149:156823d33999	312	#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) \|\| \
<>	149:156823d33999	313	((STATE) == MPU_REGION_DISABLE))
<>	149:156823d33999	314
<>	149:156823d33999	315	#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) \|\| \
<>	149:156823d33999	316	((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
<>	149:156823d33999	317
<>	149:156823d33999	318	#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) \|\| \
<>	149:156823d33999	319	((STATE) == MPU_ACCESS_NOT_SHAREABLE))
<>	149:156823d33999	320
<>	149:156823d33999	321	#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) \|\| \
<>	149:156823d33999	322	((STATE) == MPU_ACCESS_NOT_CACHEABLE))
<>	149:156823d33999	323
<>	149:156823d33999	324	#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) \|\| \
<>	149:156823d33999	325	((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
<>	149:156823d33999	326
<>	149:156823d33999	327	#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) \|\| \
<>	149:156823d33999	328	((TYPE) == MPU_TEX_LEVEL1) \|\| \
<>	149:156823d33999	329	((TYPE) == MPU_TEX_LEVEL2))
<>	149:156823d33999	330
<>	149:156823d33999	331	#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) \|\| \
<>	149:156823d33999	332	((TYPE) == MPU_REGION_PRIV_RW) \|\| \
<>	149:156823d33999	333	((TYPE) == MPU_REGION_PRIV_RW_URO) \|\| \
<>	149:156823d33999	334	((TYPE) == MPU_REGION_FULL_ACCESS) \|\| \
<>	149:156823d33999	335	((TYPE) == MPU_REGION_PRIV_RO) \|\| \
<>	149:156823d33999	336	((TYPE) == MPU_REGION_PRIV_RO_URO))
<>	149:156823d33999	337
<>	149:156823d33999	338	#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) \|\| \
<>	149:156823d33999	339	((NUMBER) == MPU_REGION_NUMBER1) \|\| \
<>	149:156823d33999	340	((NUMBER) == MPU_REGION_NUMBER2) \|\| \
<>	149:156823d33999	341	((NUMBER) == MPU_REGION_NUMBER3) \|\| \
<>	149:156823d33999	342	((NUMBER) == MPU_REGION_NUMBER4) \|\| \
<>	149:156823d33999	343	((NUMBER) == MPU_REGION_NUMBER5) \|\| \
<>	149:156823d33999	344	((NUMBER) == MPU_REGION_NUMBER6) \|\| \
<>	149:156823d33999	345	((NUMBER) == MPU_REGION_NUMBER7))
<>	149:156823d33999	346
<>	149:156823d33999	347	#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) \|\| \
<>	149:156823d33999	348	((SIZE) == MPU_REGION_SIZE_64B) \|\| \
<>	149:156823d33999	349	((SIZE) == MPU_REGION_SIZE_128B) \|\| \
<>	149:156823d33999	350	((SIZE) == MPU_REGION_SIZE_256B) \|\| \
<>	149:156823d33999	351	((SIZE) == MPU_REGION_SIZE_512B) \|\| \
<>	149:156823d33999	352	((SIZE) == MPU_REGION_SIZE_1KB) \|\| \
<>	149:156823d33999	353	((SIZE) == MPU_REGION_SIZE_2KB) \|\| \
<>	149:156823d33999	354	((SIZE) == MPU_REGION_SIZE_4KB) \|\| \
<>	149:156823d33999	355	((SIZE) == MPU_REGION_SIZE_8KB) \|\| \
<>	149:156823d33999	356	((SIZE) == MPU_REGION_SIZE_16KB) \|\| \
<>	149:156823d33999	357	((SIZE) == MPU_REGION_SIZE_32KB) \|\| \
<>	149:156823d33999	358	((SIZE) == MPU_REGION_SIZE_64KB) \|\| \
<>	149:156823d33999	359	((SIZE) == MPU_REGION_SIZE_128KB) \|\| \
<>	149:156823d33999	360	((SIZE) == MPU_REGION_SIZE_256KB) \|\| \
<>	149:156823d33999	361	((SIZE) == MPU_REGION_SIZE_512KB) \|\| \
<>	149:156823d33999	362	((SIZE) == MPU_REGION_SIZE_1MB) \|\| \
<>	149:156823d33999	363	((SIZE) == MPU_REGION_SIZE_2MB) \|\| \
<>	149:156823d33999	364	((SIZE) == MPU_REGION_SIZE_4MB) \|\| \
<>	149:156823d33999	365	((SIZE) == MPU_REGION_SIZE_8MB) \|\| \
<>	149:156823d33999	366	((SIZE) == MPU_REGION_SIZE_16MB) \|\| \
<>	149:156823d33999	367	((SIZE) == MPU_REGION_SIZE_32MB) \|\| \
<>	149:156823d33999	368	((SIZE) == MPU_REGION_SIZE_64MB) \|\| \
<>	149:156823d33999	369	((SIZE) == MPU_REGION_SIZE_128MB) \|\| \
<>	149:156823d33999	370	((SIZE) == MPU_REGION_SIZE_256MB) \|\| \
<>	149:156823d33999	371	((SIZE) == MPU_REGION_SIZE_512MB) \|\| \
<>	149:156823d33999	372	((SIZE) == MPU_REGION_SIZE_1GB) \|\| \
<>	149:156823d33999	373	((SIZE) == MPU_REGION_SIZE_2GB) \|\| \
<>	149:156823d33999	374	((SIZE) == MPU_REGION_SIZE_4GB))
<>	149:156823d33999	375
<>	149:156823d33999	376	#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
<>	149:156823d33999	377	#endif /* __MPU_PRESENT */
<>	149:156823d33999	378
<>	149:156823d33999	379	/**
<>	149:156823d33999	380	* @}
<>	149:156823d33999	381	*/
<>	149:156823d33999	382
<>	149:156823d33999	383	/* Private functions ---------------------------------------------------------*/
<>	149:156823d33999	384	/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
<>	149:156823d33999	385	* @brief CORTEX private functions
<>	149:156823d33999	386	* @{
<>	149:156823d33999	387	*/
<>	149:156823d33999	388
<>	149:156823d33999	389	#if (__MPU_PRESENT == 1)
<>	149:156823d33999	390	/**
<>	149:156823d33999	391	* @brief Disables the MPU
<>	149:156823d33999	392	* @retval None
<>	149:156823d33999	393	*/
<>	149:156823d33999	394	__STATIC_INLINE void HAL_MPU_Disable(void)
<>	149:156823d33999	395	{
<>	149:156823d33999	396	/* Disable fault exceptions */
<>	149:156823d33999	397	SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
<>	149:156823d33999	398
<>	149:156823d33999	399	/* Disable the MPU */
<>	149:156823d33999	400	MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
<>	149:156823d33999	401	}
<>	149:156823d33999	402
<>	149:156823d33999	403	/**
<>	149:156823d33999	404	* @brief Enables the MPU
<>	149:156823d33999	405	* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
<>	149:156823d33999	406	* NMI, FAULTMASK and privileged accessto the default memory
<>	149:156823d33999	407	* This parameter can be one of the following values:
<>	149:156823d33999	408	* @arg MPU_HFNMI_PRIVDEF_NONE
<>	149:156823d33999	409	* @arg MPU_HARDFAULT_NMI
<>	149:156823d33999	410	* @arg MPU_PRIVILEGED_DEFAULT
<>	149:156823d33999	411	* @arg MPU_HFNMI_PRIVDEF
<>	149:156823d33999	412	* @retval None
<>	149:156823d33999	413	*/
<>	149:156823d33999	414	__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
<>	149:156823d33999	415	{
<>	149:156823d33999	416	/* Enable the MPU */
<>	149:156823d33999	417	MPU->CTRL = MPU_Control \| MPU_CTRL_ENABLE_Msk;
<>	149:156823d33999	418
<>	149:156823d33999	419	/* Enable fault exceptions */
<>	149:156823d33999	420	SCB->SHCSR \|= SCB_SHCSR_MEMFAULTENA_Msk;
<>	149:156823d33999	421	}
<>	149:156823d33999	422	#endif /* __MPU_PRESENT */
<>	149:156823d33999	423
<>	149:156823d33999	424	/**
<>	149:156823d33999	425	* @}
<>	149:156823d33999	426	*/
<>	149:156823d33999	427
<>	149:156823d33999	428	/* Exported functions --------------------------------------------------------*/
<>	149:156823d33999	429	/** @addtogroup CORTEX_Exported_Functions
<>	149:156823d33999	430	* @{
<>	149:156823d33999	431	*/
<>	149:156823d33999	432
<>	149:156823d33999	433	/** @addtogroup CORTEX_Exported_Functions_Group1
<>	149:156823d33999	434	* @{
<>	149:156823d33999	435	*/
<>	149:156823d33999	436	/* Initialization and de-initialization functions *****************************/
<>	149:156823d33999	437	void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
<>	149:156823d33999	438	void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
<>	149:156823d33999	439	void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
<>	149:156823d33999	440	void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
<>	149:156823d33999	441	void HAL_NVIC_SystemReset(void);
<>	149:156823d33999	442	uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
<>	149:156823d33999	443	/**
<>	149:156823d33999	444	* @}
<>	149:156823d33999	445	*/
<>	149:156823d33999	446
<>	149:156823d33999	447	/** @addtogroup CORTEX_Exported_Functions_Group2
<>	149:156823d33999	448	* @{
<>	149:156823d33999	449	*/
<>	149:156823d33999	450	/* Peripheral Control functions ***********************************************/
<>	149:156823d33999	451	#if (__MPU_PRESENT == 1)
<>	149:156823d33999	452	void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
<>	149:156823d33999	453	#endif /* __MPU_PRESENT */
<>	149:156823d33999	454	uint32_t HAL_NVIC_GetPriorityGrouping(void);
<>	149:156823d33999	455	void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
<>	149:156823d33999	456	uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
<>	149:156823d33999	457	void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
<>	149:156823d33999	458	void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
<>	149:156823d33999	459	uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
<>	149:156823d33999	460	void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
<>	149:156823d33999	461	void HAL_SYSTICK_IRQHandler(void);
<>	149:156823d33999	462	void HAL_SYSTICK_Callback(void);
<>	149:156823d33999	463	/**
<>	149:156823d33999	464	* @}
<>	149:156823d33999	465	*/
<>	149:156823d33999	466
<>	149:156823d33999	467	/**
<>	149:156823d33999	468	* @}
<>	149:156823d33999	469	*/
<>	149:156823d33999	470
<>	149:156823d33999	471	/**
<>	149:156823d33999	472	* @}
<>	149:156823d33999	473	*/
<>	149:156823d33999	474
<>	149:156823d33999	475	/**
<>	149:156823d33999	476	* @}
<>	149:156823d33999	477	*/
<>	149:156823d33999	478
<>	149:156823d33999	479	#ifdef __cplusplus
<>	149:156823d33999	480	}
<>	149:156823d33999	481	#endif
<>	149:156823d33999	482
<>	149:156823d33999	483	#endif /* __STM32L1xx_HAL_CORTEX_H */
<>	149:156823d33999	484
<>	149:156823d33999	485
<>	149:156823d33999	486	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/