mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 181:57724642e740 1 /* mbed Microcontroller Library
AnnaBridge 181:57724642e740 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 181:57724642e740 3 *
AnnaBridge 181:57724642e740 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 181:57724642e740 5 * you may not use this file except in compliance with the License.
AnnaBridge 181:57724642e740 6 * You may obtain a copy of the License at
AnnaBridge 181:57724642e740 7 *
AnnaBridge 181:57724642e740 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 181:57724642e740 9 *
AnnaBridge 181:57724642e740 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 181:57724642e740 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 181:57724642e740 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 181:57724642e740 13 * See the License for the specific language governing permissions and
AnnaBridge 181:57724642e740 14 * limitations under the License.
AnnaBridge 181:57724642e740 15 */
AnnaBridge 181:57724642e740 16
AnnaBridge 181:57724642e740 17 /**
AnnaBridge 181:57724642e740 18 * This file configures the system clock as follows:
AnnaBridge 181:57724642e740 19 *-----------------------------------------------------------------------------
AnnaBridge 181:57724642e740 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
AnnaBridge 181:57724642e740 21 * | (external 24 MHz clock) | (internal 16 MHz)
AnnaBridge 181:57724642e740 22 * | 2- PLL_HSE_XTAL |
AnnaBridge 181:57724642e740 23 * | (external 24 MHz xtal) |
AnnaBridge 181:57724642e740 24 *-----------------------------------------------------------------------------
AnnaBridge 181:57724642e740 25 * SYSCLK(MHz) | 32 | 32
AnnaBridge 181:57724642e740 26 *-----------------------------------------------------------------------------
AnnaBridge 181:57724642e740 27 * AHBCLK (MHz) | 32 | 32
AnnaBridge 181:57724642e740 28 *-----------------------------------------------------------------------------
AnnaBridge 181:57724642e740 29 * APB1CLK (MHz) | 32 | 32
AnnaBridge 181:57724642e740 30 *-----------------------------------------------------------------------------
AnnaBridge 181:57724642e740 31 * APB2CLK (MHz) | 32 | 32
AnnaBridge 181:57724642e740 32 *-----------------------------------------------------------------------------
AnnaBridge 181:57724642e740 33 * USB capable (48 MHz precise clock) | YES | NO
AnnaBridge 181:57724642e740 34 *-----------------------------------------------------------------------------
AnnaBridge 181:57724642e740 35 ******************************************************************************
AnnaBridge 181:57724642e740 36 */
AnnaBridge 181:57724642e740 37
AnnaBridge 181:57724642e740 38 #include "stm32l1xx.h"
AnnaBridge 181:57724642e740 39 #include "stdio.h"
AnnaBridge 181:57724642e740 40 #include "mbed_debug.h"
AnnaBridge 181:57724642e740 41
AnnaBridge 181:57724642e740 42 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 181:57724642e740 43 Internal SRAM. */
AnnaBridge 181:57724642e740 44 /* #define VECT_TAB_SRAM */
AnnaBridge 181:57724642e740 45 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
AnnaBridge 181:57724642e740 46 This value must be a multiple of 0x200. */
AnnaBridge 181:57724642e740 47
AnnaBridge 181:57724642e740 48 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
AnnaBridge 181:57724642e740 49 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
AnnaBridge 181:57724642e740 50 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
AnnaBridge 181:57724642e740 51
AnnaBridge 181:57724642e740 52
AnnaBridge 181:57724642e740 53 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
AnnaBridge 181:57724642e740 54 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 181:57724642e740 55 #endif
AnnaBridge 181:57724642e740 56
AnnaBridge 181:57724642e740 57 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 181:57724642e740 58
AnnaBridge 181:57724642e740 59
AnnaBridge 181:57724642e740 60 /**
AnnaBridge 181:57724642e740 61 * @brief Setup the microcontroller system.
AnnaBridge 181:57724642e740 62 * Initialize the Embedded Flash Interface, the PLL and update the
AnnaBridge 181:57724642e740 63 * SystemCoreClock variable.
AnnaBridge 181:57724642e740 64 * @param None
AnnaBridge 181:57724642e740 65 * @retval None
AnnaBridge 181:57724642e740 66 */
AnnaBridge 181:57724642e740 67 void SystemInit (void)
AnnaBridge 181:57724642e740 68 {
AnnaBridge 181:57724642e740 69 /*!< Set MSION bit */
AnnaBridge 181:57724642e740 70 RCC->CR |= (uint32_t)0x00000100;
AnnaBridge 181:57724642e740 71
AnnaBridge 181:57724642e740 72 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
AnnaBridge 181:57724642e740 73 RCC->CFGR &= (uint32_t)0x88FFC00C;
AnnaBridge 181:57724642e740 74
AnnaBridge 181:57724642e740 75 /*!< Reset HSION, HSEON, CSSON and PLLON bits */
AnnaBridge 181:57724642e740 76 RCC->CR &= (uint32_t)0xEEFEFFFE;
AnnaBridge 181:57724642e740 77
AnnaBridge 181:57724642e740 78 /*!< Reset HSEBYP bit */
AnnaBridge 181:57724642e740 79 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 181:57724642e740 80
AnnaBridge 181:57724642e740 81 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
AnnaBridge 181:57724642e740 82 RCC->CFGR &= (uint32_t)0xFF02FFFF;
AnnaBridge 181:57724642e740 83
AnnaBridge 181:57724642e740 84 /*!< Disable all interrupts */
AnnaBridge 181:57724642e740 85 RCC->CIR = 0x00000000;
AnnaBridge 181:57724642e740 86
AnnaBridge 181:57724642e740 87 #ifdef DATA_IN_ExtSRAM
AnnaBridge 181:57724642e740 88 SystemInit_ExtMemCtl();
AnnaBridge 181:57724642e740 89 #endif /* DATA_IN_ExtSRAM */
AnnaBridge 181:57724642e740 90
AnnaBridge 181:57724642e740 91
AnnaBridge 181:57724642e740 92 #if defined(__ICCARM__)
AnnaBridge 181:57724642e740 93 #pragma section=".intvec"
AnnaBridge 181:57724642e740 94 #define FLASH_VTOR_BASE ((uint32_t)__section_begin(".intvec"))
AnnaBridge 181:57724642e740 95 #elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
AnnaBridge 181:57724642e740 96 extern uint32_t Load$$LR$$LR_IROM1$$Base[];
AnnaBridge 181:57724642e740 97 #define FLASH_VTOR_BASE ((uint32_t)Load$$LR$$LR_IROM1$$Base)
AnnaBridge 181:57724642e740 98 #elif defined(__GNUC__)
AnnaBridge 181:57724642e740 99 extern uint32_t g_pfnVectors[];
AnnaBridge 181:57724642e740 100 #define FLASH_VTOR_BASE ((uint32_t)g_pfnVectors)
AnnaBridge 181:57724642e740 101 #else
AnnaBridge 181:57724642e740 102 #error "Flash vector address not set for this toolchain"
AnnaBridge 181:57724642e740 103 #endif
AnnaBridge 181:57724642e740 104
AnnaBridge 181:57724642e740 105 #ifdef VECT_TAB_SRAM
AnnaBridge 181:57724642e740 106 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
AnnaBridge 181:57724642e740 107 #else
AnnaBridge 181:57724642e740 108 SCB->VTOR = FLASH_VTOR_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
AnnaBridge 181:57724642e740 109 #endif
AnnaBridge 181:57724642e740 110
AnnaBridge 181:57724642e740 111 }
AnnaBridge 181:57724642e740 112
AnnaBridge 181:57724642e740 113 /**
AnnaBridge 181:57724642e740 114 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 181:57724642e740 115 * AHB/APBx prescalers and Flash settings
AnnaBridge 181:57724642e740 116 * @note This function should be called only once the RCC clock configuration
AnnaBridge 181:57724642e740 117 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 181:57724642e740 118 * @param None
AnnaBridge 181:57724642e740 119 * @retval None
AnnaBridge 181:57724642e740 120 */
AnnaBridge 181:57724642e740 121 void SetSysClock(void)
AnnaBridge 181:57724642e740 122 {
AnnaBridge 181:57724642e740 123 /* 1- Try to start with HSE and external clock */
AnnaBridge 181:57724642e740 124 #if USE_PLL_HSE_EXTC != 0
AnnaBridge 181:57724642e740 125 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 181:57724642e740 126 #endif
AnnaBridge 181:57724642e740 127 {
AnnaBridge 181:57724642e740 128 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 181:57724642e740 129 #if USE_PLL_HSE_XTAL != 0
AnnaBridge 181:57724642e740 130 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 181:57724642e740 131 #endif
AnnaBridge 181:57724642e740 132 {
AnnaBridge 181:57724642e740 133 /* 3- If fail start with HSI clock */
AnnaBridge 181:57724642e740 134 if (SetSysClock_PLL_HSI() == 0) {
AnnaBridge 181:57724642e740 135 while(1) {
AnnaBridge 181:57724642e740 136 // [TODO] Put something here to tell the user that a problem occured...
AnnaBridge 181:57724642e740 137 }
AnnaBridge 181:57724642e740 138 }
AnnaBridge 181:57724642e740 139 }
AnnaBridge 181:57724642e740 140 }
AnnaBridge 181:57724642e740 141
AnnaBridge 181:57724642e740 142 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 181:57724642e740 143 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
AnnaBridge 181:57724642e740 144 }
AnnaBridge 181:57724642e740 145
AnnaBridge 181:57724642e740 146 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
AnnaBridge 181:57724642e740 147 /******************************************************************************/
AnnaBridge 181:57724642e740 148 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 181:57724642e740 149 /******************************************************************************/
AnnaBridge 181:57724642e740 150 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 181:57724642e740 151 {
AnnaBridge 181:57724642e740 152 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 181:57724642e740 153 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 181:57724642e740 154
AnnaBridge 181:57724642e740 155 /* Used to gain time after DeepSleep in case HSI is used */
AnnaBridge 181:57724642e740 156 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
AnnaBridge 181:57724642e740 157 return 0;
AnnaBridge 181:57724642e740 158 }
AnnaBridge 181:57724642e740 159
AnnaBridge 181:57724642e740 160 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 181:57724642e740 161 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 181:57724642e740 162 regarding system frequency refer to product datasheet. */
AnnaBridge 181:57724642e740 163 __PWR_CLK_ENABLE();
AnnaBridge 181:57724642e740 164 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 181:57724642e740 165
AnnaBridge 181:57724642e740 166 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
AnnaBridge 181:57724642e740 167 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 181:57724642e740 168 if (bypass == 0) {
AnnaBridge 181:57724642e740 169 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
AnnaBridge 181:57724642e740 170 } else {
AnnaBridge 181:57724642e740 171 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 24 MHz clock on OSC_IN */
AnnaBridge 181:57724642e740 172 }
AnnaBridge 181:57724642e740 173 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
AnnaBridge 181:57724642e740 174 // SYSCLK = 32 MHz ((24 MHz * 4) / 3)
AnnaBridge 181:57724642e740 175 // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
AnnaBridge 181:57724642e740 176 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 181:57724642e740 177 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 181:57724642e740 178 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
AnnaBridge 181:57724642e740 179 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
AnnaBridge 181:57724642e740 180
AnnaBridge 181:57724642e740 181 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 181:57724642e740 182 return 0; // FAIL
AnnaBridge 181:57724642e740 183 }
AnnaBridge 181:57724642e740 184
AnnaBridge 181:57724642e740 185 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 181:57724642e740 186 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 181:57724642e740 187 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
AnnaBridge 181:57724642e740 188 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
AnnaBridge 181:57724642e740 189 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 181:57724642e740 190 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 181:57724642e740 191 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
AnnaBridge 181:57724642e740 192 return 0; // FAIL
AnnaBridge 181:57724642e740 193 }
AnnaBridge 181:57724642e740 194
AnnaBridge 181:57724642e740 195 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 181:57724642e740 196 //if (bypass == 0)
AnnaBridge 181:57724642e740 197 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
AnnaBridge 181:57724642e740 198 //else
AnnaBridge 181:57724642e740 199 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
AnnaBridge 181:57724642e740 200
AnnaBridge 181:57724642e740 201 return 1; // OK
AnnaBridge 181:57724642e740 202 }
AnnaBridge 181:57724642e740 203 #endif
AnnaBridge 181:57724642e740 204
AnnaBridge 181:57724642e740 205 /******************************************************************************/
AnnaBridge 181:57724642e740 206 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 181:57724642e740 207 /******************************************************************************/
AnnaBridge 181:57724642e740 208 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 181:57724642e740 209 {
AnnaBridge 181:57724642e740 210 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 181:57724642e740 211 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 181:57724642e740 212
AnnaBridge 181:57724642e740 213 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 181:57724642e740 214 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 181:57724642e740 215 regarding system frequency refer to product datasheet. */
AnnaBridge 181:57724642e740 216 __PWR_CLK_ENABLE();
AnnaBridge 181:57724642e740 217 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 181:57724642e740 218
AnnaBridge 181:57724642e740 219 /* Enable HSI oscillator and activate PLL with HSI as source */
AnnaBridge 181:57724642e740 220 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
AnnaBridge 181:57724642e740 221 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 181:57724642e740 222 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 181:57724642e740 223 // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
AnnaBridge 181:57724642e740 224 // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
AnnaBridge 181:57724642e740 225 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 181:57724642e740 226 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 181:57724642e740 227 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
AnnaBridge 181:57724642e740 228 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
AnnaBridge 181:57724642e740 229 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 181:57724642e740 230 return 0; // FAIL
AnnaBridge 181:57724642e740 231 }
AnnaBridge 181:57724642e740 232
AnnaBridge 181:57724642e740 233 /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
AnnaBridge 181:57724642e740 234 while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
AnnaBridge 181:57724642e740 235
AnnaBridge 181:57724642e740 236 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 181:57724642e740 237 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 181:57724642e740 238 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
AnnaBridge 181:57724642e740 239 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
AnnaBridge 181:57724642e740 240 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 181:57724642e740 241 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 181:57724642e740 242 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
AnnaBridge 181:57724642e740 243 return 0; // FAIL
AnnaBridge 181:57724642e740 244 }
AnnaBridge 181:57724642e740 245
AnnaBridge 181:57724642e740 246 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 181:57724642e740 247 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 181:57724642e740 248
AnnaBridge 181:57724642e740 249 return 1; // OK
AnnaBridge 181:57724642e740 250 }
AnnaBridge 181:57724642e740 251
AnnaBridge 181:57724642e740 252