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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 186:707f6e361f3e

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_tim.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief TIM HAL module driver.
<>	144:ef7eb2e8f9f7	6	* @brief This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	7	* functionalities of the Timer (TIM) peripheral:
<>	144:ef7eb2e8f9f7	8	* + Timer Base Initialization
<>	144:ef7eb2e8f9f7	9	* + Timer Base Start
<>	144:ef7eb2e8f9f7	10	* + Timer Base Start Interruption
<>	144:ef7eb2e8f9f7	11	* + Timer Base Start DMA
<>	144:ef7eb2e8f9f7	12	* + Timer Output Compare/PWM Initialization
<>	144:ef7eb2e8f9f7	13	* + Timer Output Compare/PWM Channel Configuration
<>	144:ef7eb2e8f9f7	14	* + Timer Output Compare/PWM Start
<>	144:ef7eb2e8f9f7	15	* + Timer Output Compare/PWM Start Interruption
<>	144:ef7eb2e8f9f7	16	* + Timer Output Compare/PWM Start DMA
<>	144:ef7eb2e8f9f7	17	* + Timer Input Capture Initialization
<>	144:ef7eb2e8f9f7	18	* + Timer Input Capture Channel Configuration
<>	144:ef7eb2e8f9f7	19	* + Timer Input Capture Start
<>	144:ef7eb2e8f9f7	20	* + Timer Input Capture Start Interruption
<>	144:ef7eb2e8f9f7	21	* + Timer Input Capture Start DMA
<>	144:ef7eb2e8f9f7	22	* + Timer One Pulse Initialization
<>	144:ef7eb2e8f9f7	23	* + Timer One Pulse Channel Configuration
<>	144:ef7eb2e8f9f7	24	* + Timer One Pulse Start
<>	144:ef7eb2e8f9f7	25	* + Timer Encoder Interface Initialization
<>	144:ef7eb2e8f9f7	26	* + Timer Encoder Interface Start
<>	144:ef7eb2e8f9f7	27	* + Timer Encoder Interface Start Interruption
<>	144:ef7eb2e8f9f7	28	* + Timer Encoder Interface Start DMA
<>	144:ef7eb2e8f9f7	29	* + Timer OCRef clear configuration
<>	144:ef7eb2e8f9f7	30	* + Timer External Clock configuration
<>	144:ef7eb2e8f9f7	31	* + Timer Complementary signal bread and dead time configuration
<>	144:ef7eb2e8f9f7	32	* + Timer Master and Slave synchronization configuration
<>	144:ef7eb2e8f9f7	33	@verbatim
<>	144:ef7eb2e8f9f7	34	==============================================================================
<>	144:ef7eb2e8f9f7	35	##### TIMER Generic features #####
<>	144:ef7eb2e8f9f7	36	==============================================================================
<>	144:ef7eb2e8f9f7	37	[..] The Timer features include:
<>	144:ef7eb2e8f9f7	38	(#) 16-bit up, down, up/down auto-reload counter.
<>	144:ef7eb2e8f9f7	39	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
<>	144:ef7eb2e8f9f7	40	frequency either by any factor between 1 and 65536.
<>	144:ef7eb2e8f9f7	41	(#) Up to 4 independent channels for:
<>	144:ef7eb2e8f9f7	42	(++) Input Capture
<>	144:ef7eb2e8f9f7	43	(++) Output Compare
<>	144:ef7eb2e8f9f7	44	(++) PWM generation (Edge and Center-aligned Mode)
<>	144:ef7eb2e8f9f7	45	(++) One-pulse mode output
<>	144:ef7eb2e8f9f7	46	(#) Synchronization circuit to control the timer with external signals and to interconnect
<>	144:ef7eb2e8f9f7	47	several timers together.
<>	144:ef7eb2e8f9f7	48	(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
<>	144:ef7eb2e8f9f7	49	purposes
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	52	================================================================================
<>	144:ef7eb2e8f9f7	53	[..]
<>	144:ef7eb2e8f9f7	54	(#) Initialize the TIM low level resources by implementing the following functions
<>	144:ef7eb2e8f9f7	55	depending from feature used :
<>	144:ef7eb2e8f9f7	56	(++) Time Base : HAL_TIM_Base_MspInit()
<>	144:ef7eb2e8f9f7	57	(++) Input Capture : HAL_TIM_IC_MspInit()
<>	144:ef7eb2e8f9f7	58	(++) Output Compare : HAL_TIM_OC_MspInit()
<>	144:ef7eb2e8f9f7	59	(++) PWM generation : HAL_TIM_PWM_MspInit()
<>	144:ef7eb2e8f9f7	60	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<>	144:ef7eb2e8f9f7	61	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	(#) Initialize the TIM low level resources :
<>	144:ef7eb2e8f9f7	64	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	65	(##) TIM pins configuration
<>	144:ef7eb2e8f9f7	66	(+++) Enable the clock for the TIM GPIOs using the following function:
<>	144:ef7eb2e8f9f7	67	__HAL_RCC_GPIOx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	68	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	(#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
<>	144:ef7eb2e8f9f7	71	using the following function:
<>	144:ef7eb2e8f9f7	72	HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
<>	144:ef7eb2e8f9f7	73
<>	144:ef7eb2e8f9f7	74	(#) Configure the TIM in the desired functioning mode using one of the
<>	144:ef7eb2e8f9f7	75	initialization function of this driver:
<>	144:ef7eb2e8f9f7	76	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<>	144:ef7eb2e8f9f7	77	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<>	144:ef7eb2e8f9f7	78	Output Compare signal.
<>	144:ef7eb2e8f9f7	79	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<>	144:ef7eb2e8f9f7	80	PWM signal.
<>	144:ef7eb2e8f9f7	81	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<>	144:ef7eb2e8f9f7	82	external signal.
<>	144:ef7eb2e8f9f7	83	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode.
<>	144:ef7eb2e8f9f7	84	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<>	144:ef7eb2e8f9f7	85
<>	144:ef7eb2e8f9f7	86	(#) Activate the TIM peripheral using one of the start functions:
<>	144:ef7eb2e8f9f7	87	HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(),
<>	144:ef7eb2e8f9f7	88	HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(),
<>	144:ef7eb2e8f9f7	89	HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(),
<>	144:ef7eb2e8f9f7	90	HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(),
<>	144:ef7eb2e8f9f7	91	HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(),
<>	144:ef7eb2e8f9f7	92	HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT()
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	(#) The DMA Burst is managed with the two following functions:
<>	144:ef7eb2e8f9f7	95	HAL_TIM_DMABurst_WriteStart
<>	144:ef7eb2e8f9f7	96	HAL_TIM_DMABurst_ReadStart
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	@endverbatim
<>	144:ef7eb2e8f9f7	99	******************************************************************************
<>	144:ef7eb2e8f9f7	100	* @attention
<>	144:ef7eb2e8f9f7	101	*
<>	144:ef7eb2e8f9f7	102	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	103	*
<>	144:ef7eb2e8f9f7	104	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	105	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	106	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	107	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	108	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	109	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	110	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	111	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	112	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	113	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	114	*
<>	144:ef7eb2e8f9f7	115	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	116	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	117	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	118	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	119	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	120	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	121	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	122	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	123	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	124	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	125	*
<>	144:ef7eb2e8f9f7	126	******************************************************************************
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	130	#include "stm32l0xx_hal.h"
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	133	* @{
<>	144:ef7eb2e8f9f7	134	*/
<>	144:ef7eb2e8f9f7	135
<>	144:ef7eb2e8f9f7	136	#ifdef HAL_TIM_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	/** @addtogroup TIM
<>	144:ef7eb2e8f9f7	139	* @brief TIM HAL module driver
<>	144:ef7eb2e8f9f7	140	* @{
<>	144:ef7eb2e8f9f7	141	*/
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	/** @addtogroup TIM_Private
<>	144:ef7eb2e8f9f7	144	* @{
<>	144:ef7eb2e8f9f7	145	*/
<>	144:ef7eb2e8f9f7	146	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	147	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	148	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	149	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	150	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	151	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
<>	144:ef7eb2e8f9f7	152	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	153	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	154	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	155	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	156	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	157	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	158	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	159	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	160	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	161	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	162	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
<>	144:ef7eb2e8f9f7	163	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<>	144:ef7eb2e8f9f7	164	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<>	144:ef7eb2e8f9f7	165	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	166	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	167	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef htim,TIM_SlaveConfigTypeDef sSlaveConfig);
<>	144:ef7eb2e8f9f7	168	/**
<>	144:ef7eb2e8f9f7	169	* @}
<>	144:ef7eb2e8f9f7	170	*/
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	/*******************************************************************************/
<>	144:ef7eb2e8f9f7	173	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	174	/*******************************************************************************/
<>	144:ef7eb2e8f9f7	175
<>	144:ef7eb2e8f9f7	176	/** @addtogroup TIM_Exported_Functions
<>	144:ef7eb2e8f9f7	177	* @{
<>	144:ef7eb2e8f9f7	178	*/
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	/** @addtogroup TIM_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	181	* @brief Time Base functions
<>	144:ef7eb2e8f9f7	182	*
<>	144:ef7eb2e8f9f7	183	@verbatim
<>	144:ef7eb2e8f9f7	184	==============================================================================
<>	144:ef7eb2e8f9f7	185	##### Timer Base functions #####
<>	144:ef7eb2e8f9f7	186	==============================================================================
<>	144:ef7eb2e8f9f7	187	[..]
<>	144:ef7eb2e8f9f7	188	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	189	(+) Initialize and configure the TIM base.
<>	144:ef7eb2e8f9f7	190	(+) De-initialize the TIM base.
<>	144:ef7eb2e8f9f7	191	(+) Start the Timer Base.
<>	144:ef7eb2e8f9f7	192	(+) Stop the Timer Base.
<>	144:ef7eb2e8f9f7	193	(+) Start the Timer Base and enable interrupt.
<>	144:ef7eb2e8f9f7	194	(+) Stop the Timer Base and disable interrupt.
<>	144:ef7eb2e8f9f7	195	(+) Start the Timer Base and enable DMA transfer.
<>	144:ef7eb2e8f9f7	196	(+) Stop the Timer Base and disable DMA transfer.
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198	@endverbatim
<>	144:ef7eb2e8f9f7	199	* @{
<>	144:ef7eb2e8f9f7	200	*/
<>	144:ef7eb2e8f9f7	201	/**
<>	144:ef7eb2e8f9f7	202	* @brief Initializes the TIM Time base Unit according to the specified
<>	144:ef7eb2e8f9f7	203	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	204	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	205	* @retval HAL status
<>	144:ef7eb2e8f9f7	206	*/
<>	144:ef7eb2e8f9f7	207	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	208	{
<>	144:ef7eb2e8f9f7	209	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	210	if(htim == NULL)
<>	144:ef7eb2e8f9f7	211	{
<>	144:ef7eb2e8f9f7	212	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	213	}
<>	144:ef7eb2e8f9f7	214
<>	144:ef7eb2e8f9f7	215	/* Check the parameters */
<>	144:ef7eb2e8f9f7	216	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	217	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	218	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	219	assert_param(IS_TIM_PERIOD(htim->Init.Period));
<>	144:ef7eb2e8f9f7	220	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<>	144:ef7eb2e8f9f7	221
<>	144:ef7eb2e8f9f7	222	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	223	{
<>	144:ef7eb2e8f9f7	224	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	225	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	228	HAL_TIM_Base_MspInit(htim);
<>	144:ef7eb2e8f9f7	229	}
<>	144:ef7eb2e8f9f7	230
<>	144:ef7eb2e8f9f7	231	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	232	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	233
<>	144:ef7eb2e8f9f7	234	/* Set the Time Base configuration */
<>	144:ef7eb2e8f9f7	235	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	238	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	239
<>	144:ef7eb2e8f9f7	240	return HAL_OK;
<>	144:ef7eb2e8f9f7	241	}
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	/**
<>	144:ef7eb2e8f9f7	244	* @brief DeInitializes the TIM Base peripheral
<>	144:ef7eb2e8f9f7	245	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	246	* @retval HAL status
<>	144:ef7eb2e8f9f7	247	*/
<>	144:ef7eb2e8f9f7	248	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	249	{
<>	144:ef7eb2e8f9f7	250	/* Check the parameters */
<>	144:ef7eb2e8f9f7	251	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	252
<>	144:ef7eb2e8f9f7	253	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	256	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	259	HAL_TIM_Base_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	/* Change TIM state */
<>	144:ef7eb2e8f9f7	262	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/* Release Lock */
<>	144:ef7eb2e8f9f7	265	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	return HAL_OK;
<>	144:ef7eb2e8f9f7	268	}
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	/**
<>	144:ef7eb2e8f9f7	271	* @brief Initializes the TIM Base MSP.
<>	144:ef7eb2e8f9f7	272	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	273	* @retval None
<>	144:ef7eb2e8f9f7	274	*/
<>	144:ef7eb2e8f9f7	275	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	276	{
<>	144:ef7eb2e8f9f7	277	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	278	UNUSED(htim);
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	281	the HAL_TIM_Base_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283	}
<>	144:ef7eb2e8f9f7	284
<>	144:ef7eb2e8f9f7	285	/**
<>	144:ef7eb2e8f9f7	286	* @brief DeInitializes TIM Base MSP.
<>	144:ef7eb2e8f9f7	287	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	288	* @retval None
<>	144:ef7eb2e8f9f7	289	*/
<>	144:ef7eb2e8f9f7	290	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	291	{
<>	144:ef7eb2e8f9f7	292	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	293	UNUSED(htim);
<>	144:ef7eb2e8f9f7	294
<>	144:ef7eb2e8f9f7	295	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	296	the HAL_TIM_Base_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	297	*/
<>	144:ef7eb2e8f9f7	298	}
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/**
<>	144:ef7eb2e8f9f7	301	* @brief Starts the TIM Base generation.
<>	144:ef7eb2e8f9f7	302	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	303	* @retval HAL status
<>	144:ef7eb2e8f9f7	304	*/
<>	144:ef7eb2e8f9f7	305	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	306	{
<>	144:ef7eb2e8f9f7	307	/* Check the parameters */
<>	144:ef7eb2e8f9f7	308	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	311	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	314	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	317	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/* Return function status */
<>	144:ef7eb2e8f9f7	320	return HAL_OK;
<>	144:ef7eb2e8f9f7	321	}
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323	/**
<>	144:ef7eb2e8f9f7	324	* @brief Stops the TIM Base generation.
<>	144:ef7eb2e8f9f7	325	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	326	* @retval HAL status
<>	144:ef7eb2e8f9f7	327	*/
<>	144:ef7eb2e8f9f7	328	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	329	{
<>	144:ef7eb2e8f9f7	330	/* Check the parameters */
<>	144:ef7eb2e8f9f7	331	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	334	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	337	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	340	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/* Return function status */
<>	144:ef7eb2e8f9f7	343	return HAL_OK;
<>	144:ef7eb2e8f9f7	344	}
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/**
<>	144:ef7eb2e8f9f7	347	* @brief Starts the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	348	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	349	* @retval HAL status
<>	144:ef7eb2e8f9f7	350	*/
<>	144:ef7eb2e8f9f7	351	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	352	{
<>	144:ef7eb2e8f9f7	353	/* Check the parameters */
<>	144:ef7eb2e8f9f7	354	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/* Enable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	357	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	360	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	/* Return function status */
<>	144:ef7eb2e8f9f7	363	return HAL_OK;
<>	144:ef7eb2e8f9f7	364	}
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/**
<>	144:ef7eb2e8f9f7	367	* @brief Stops the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	368	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	369	* @retval HAL status
<>	144:ef7eb2e8f9f7	370	*/
<>	144:ef7eb2e8f9f7	371	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	372	{
<>	144:ef7eb2e8f9f7	373	/* Check the parameters */
<>	144:ef7eb2e8f9f7	374	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	375	/* Disable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	376	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	377
<>	144:ef7eb2e8f9f7	378	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	379	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	380
<>	144:ef7eb2e8f9f7	381	/* Return function status */
<>	144:ef7eb2e8f9f7	382	return HAL_OK;
<>	144:ef7eb2e8f9f7	383	}
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @brief Starts the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	387	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	388	* @param pData: The source Buffer address.
<>	144:ef7eb2e8f9f7	389	* @param Length: The length of data to be transferred from memory to peripheral.
<>	144:ef7eb2e8f9f7	390	* @retval HAL status
<>	144:ef7eb2e8f9f7	391	*/
<>	144:ef7eb2e8f9f7	392	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	393	{
<>	144:ef7eb2e8f9f7	394	/* Check the parameters */
<>	144:ef7eb2e8f9f7	395	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	396
<>	144:ef7eb2e8f9f7	397	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	398	{
<>	144:ef7eb2e8f9f7	399	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	400	}
<>	144:ef7eb2e8f9f7	401	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	402	{
<>	151:5eaa88a5bcc7	403	if((pData == 0U ) && (Length > 0U))
<>	144:ef7eb2e8f9f7	404	{
<>	144:ef7eb2e8f9f7	405	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	406	}
<>	144:ef7eb2e8f9f7	407	else
<>	144:ef7eb2e8f9f7	408	{
<>	144:ef7eb2e8f9f7	409	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	410	}
<>	144:ef7eb2e8f9f7	411	}
<>	144:ef7eb2e8f9f7	412	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	413	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	416	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	419	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/* Enable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	422	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	425	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	/* Return function status */
<>	144:ef7eb2e8f9f7	428	return HAL_OK;
<>	144:ef7eb2e8f9f7	429	}
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/**
<>	144:ef7eb2e8f9f7	432	* @brief Stops the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	433	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	434	* @retval HAL status
<>	144:ef7eb2e8f9f7	435	*/
<>	144:ef7eb2e8f9f7	436	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	437	{
<>	144:ef7eb2e8f9f7	438	/* Check the parameters */
<>	144:ef7eb2e8f9f7	439	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	442	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	445	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/* Change the htim state */
<>	144:ef7eb2e8f9f7	448	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/* Return function status */
<>	144:ef7eb2e8f9f7	451	return HAL_OK;
<>	144:ef7eb2e8f9f7	452	}
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/**
<>	144:ef7eb2e8f9f7	455	* @}
<>	144:ef7eb2e8f9f7	456	*/
<>	144:ef7eb2e8f9f7	457
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/** @addtogroup TIM_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	460	* @brief Time Output Compare functions
<>	144:ef7eb2e8f9f7	461	*
<>	144:ef7eb2e8f9f7	462	@verbatim
<>	144:ef7eb2e8f9f7	463	==============================================================================
<>	144:ef7eb2e8f9f7	464	##### Timer Output Compare functions #####
<>	144:ef7eb2e8f9f7	465	==============================================================================
<>	144:ef7eb2e8f9f7	466	[..]
<>	144:ef7eb2e8f9f7	467	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	468	(+) Initialize and configure the TIM Output Compare.
<>	144:ef7eb2e8f9f7	469	(+) De-initialize the TIM Output Compare.
<>	144:ef7eb2e8f9f7	470	(+) Start the Timer Output Compare.
<>	144:ef7eb2e8f9f7	471	(+) Stop the Timer Output Compare.
<>	144:ef7eb2e8f9f7	472	(+) Start the Timer Output Compare and enable interrupt.
<>	144:ef7eb2e8f9f7	473	(+) Stop the Timer Output Compare and disable interrupt.
<>	144:ef7eb2e8f9f7	474	(+) Start the Timer Output Compare and enable DMA transfer.
<>	144:ef7eb2e8f9f7	475	(+) Stop the Timer Output Compare and disable DMA transfer.
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	@endverbatim
<>	144:ef7eb2e8f9f7	478	* @{
<>	144:ef7eb2e8f9f7	479	*/
<>	144:ef7eb2e8f9f7	480	/**
<>	144:ef7eb2e8f9f7	481	* @brief Initializes the TIM Output Compare according to the specified
<>	144:ef7eb2e8f9f7	482	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	483	* @param htim: TIM Output Compare handle
<>	144:ef7eb2e8f9f7	484	* @retval HAL status
<>	144:ef7eb2e8f9f7	485	*/
<>	144:ef7eb2e8f9f7	486	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<>	144:ef7eb2e8f9f7	487	{
<>	144:ef7eb2e8f9f7	488	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	489	if(htim == NULL)
<>	144:ef7eb2e8f9f7	490	{
<>	144:ef7eb2e8f9f7	491	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	492	}
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	/* Check the parameters */
<>	144:ef7eb2e8f9f7	495	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	496	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	497	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	498	assert_param(IS_TIM_PERIOD(htim->Init.Period));
<>	144:ef7eb2e8f9f7	499	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<>	144:ef7eb2e8f9f7	500
<>	144:ef7eb2e8f9f7	501	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	502	{
<>	144:ef7eb2e8f9f7	503	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	504	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	505
<>	144:ef7eb2e8f9f7	506	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/
<>	144:ef7eb2e8f9f7	507	HAL_TIM_OC_MspInit(htim);
<>	144:ef7eb2e8f9f7	508	}
<>	144:ef7eb2e8f9f7	509	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	510	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	/* Init the base time for the Output Compare */
<>	144:ef7eb2e8f9f7	513	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	514
<>	144:ef7eb2e8f9f7	515	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	516	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	517
<>	144:ef7eb2e8f9f7	518	return HAL_OK;
<>	144:ef7eb2e8f9f7	519	}
<>	144:ef7eb2e8f9f7	520
<>	144:ef7eb2e8f9f7	521	/**
<>	144:ef7eb2e8f9f7	522	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	523	* @param htim: TIM Output Compare handle
<>	144:ef7eb2e8f9f7	524	* @retval HAL status
<>	144:ef7eb2e8f9f7	525	*/
<>	144:ef7eb2e8f9f7	526	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	527	{
<>	144:ef7eb2e8f9f7	528	/* Check the parameters */
<>	144:ef7eb2e8f9f7	529	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	534	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	537	HAL_TIM_OC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	538
<>	144:ef7eb2e8f9f7	539	/* Change TIM state */
<>	144:ef7eb2e8f9f7	540	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	/* Release Lock */
<>	144:ef7eb2e8f9f7	543	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	544
<>	144:ef7eb2e8f9f7	545	return HAL_OK;
<>	144:ef7eb2e8f9f7	546	}
<>	144:ef7eb2e8f9f7	547
<>	144:ef7eb2e8f9f7	548	/**
<>	144:ef7eb2e8f9f7	549	* @brief Initializes the TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	550	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	551	* @retval None
<>	144:ef7eb2e8f9f7	552	*/
<>	144:ef7eb2e8f9f7	553	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	554	{
<>	144:ef7eb2e8f9f7	555	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	556	UNUSED(htim);
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	559	the HAL_TIM_OC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	560	*/
<>	144:ef7eb2e8f9f7	561	}
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	/**
<>	144:ef7eb2e8f9f7	564	* @brief DeInitializes TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	565	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	566	* @retval None
<>	144:ef7eb2e8f9f7	567	*/
<>	144:ef7eb2e8f9f7	568	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	569	{
<>	144:ef7eb2e8f9f7	570	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	571	UNUSED(htim);
<>	144:ef7eb2e8f9f7	572
<>	144:ef7eb2e8f9f7	573	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	574	the HAL_TIM_OC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	575	*/
<>	144:ef7eb2e8f9f7	576	}
<>	144:ef7eb2e8f9f7	577
<>	144:ef7eb2e8f9f7	578	/**
<>	144:ef7eb2e8f9f7	579	* @brief Starts the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	580	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	581	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	582	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	583	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	584	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	585	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	586	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	587	* @retval HAL status
<>	144:ef7eb2e8f9f7	588	*/
<>	144:ef7eb2e8f9f7	589	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	590	{
<>	144:ef7eb2e8f9f7	591	/* Check the parameters */
<>	144:ef7eb2e8f9f7	592	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	593
<>	144:ef7eb2e8f9f7	594	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	595	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	598	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	/* Return function status */
<>	144:ef7eb2e8f9f7	601	return HAL_OK;
<>	144:ef7eb2e8f9f7	602	}
<>	144:ef7eb2e8f9f7	603
<>	144:ef7eb2e8f9f7	604	/**
<>	144:ef7eb2e8f9f7	605	* @brief Stops the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	606	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	607	* @param Channel: TIM Channel to be disabled.
<>	144:ef7eb2e8f9f7	608	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	609	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	610	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	611	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	612	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	613	* @retval HAL status
<>	144:ef7eb2e8f9f7	614	*/
<>	144:ef7eb2e8f9f7	615	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	616	{
<>	144:ef7eb2e8f9f7	617	/* Check the parameters */
<>	144:ef7eb2e8f9f7	618	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	621	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	622
<>	144:ef7eb2e8f9f7	623	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	624	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/* Return function status */
<>	144:ef7eb2e8f9f7	627	return HAL_OK;
<>	144:ef7eb2e8f9f7	628	}
<>	144:ef7eb2e8f9f7	629
<>	144:ef7eb2e8f9f7	630	/**
<>	144:ef7eb2e8f9f7	631	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	632	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	633	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	634	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	635	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	636	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	637	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	638	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	639	* @retval HAL status
<>	144:ef7eb2e8f9f7	640	*/
<>	144:ef7eb2e8f9f7	641	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	642	{
<>	144:ef7eb2e8f9f7	643	/* Check the parameters */
<>	144:ef7eb2e8f9f7	644	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	645
<>	144:ef7eb2e8f9f7	646	switch (Channel)
<>	144:ef7eb2e8f9f7	647	{
<>	144:ef7eb2e8f9f7	648	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	649	{
<>	144:ef7eb2e8f9f7	650	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	651	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	652	}
<>	144:ef7eb2e8f9f7	653	break;
<>	144:ef7eb2e8f9f7	654
<>	144:ef7eb2e8f9f7	655	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	656	{
<>	144:ef7eb2e8f9f7	657	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	658	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	659	}
<>	144:ef7eb2e8f9f7	660	break;
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	663	{
<>	144:ef7eb2e8f9f7	664	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	665	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	666	}
<>	144:ef7eb2e8f9f7	667	break;
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	670	{
<>	144:ef7eb2e8f9f7	671	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	672	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	673	}
<>	144:ef7eb2e8f9f7	674	break;
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	default:
<>	144:ef7eb2e8f9f7	677	break;
<>	144:ef7eb2e8f9f7	678	}
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	681	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	684	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	/* Return function status */
<>	144:ef7eb2e8f9f7	687	return HAL_OK;
<>	144:ef7eb2e8f9f7	688	}
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/**
<>	144:ef7eb2e8f9f7	691	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	692	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	693	* @param Channel: TIM Channel to be disabled.
<>	144:ef7eb2e8f9f7	694	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	695	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	696	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	697	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	698	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	699	* @retval HAL status
<>	144:ef7eb2e8f9f7	700	*/
<>	144:ef7eb2e8f9f7	701	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	702	{
<>	144:ef7eb2e8f9f7	703	/* Check the parameters */
<>	144:ef7eb2e8f9f7	704	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	705
<>	144:ef7eb2e8f9f7	706	switch (Channel)
<>	144:ef7eb2e8f9f7	707	{
<>	144:ef7eb2e8f9f7	708	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	709	{
<>	144:ef7eb2e8f9f7	710	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	711	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	712	}
<>	144:ef7eb2e8f9f7	713	break;
<>	144:ef7eb2e8f9f7	714
<>	144:ef7eb2e8f9f7	715	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	716	{
<>	144:ef7eb2e8f9f7	717	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	718	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	719	}
<>	144:ef7eb2e8f9f7	720	break;
<>	144:ef7eb2e8f9f7	721
<>	144:ef7eb2e8f9f7	722	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	723	{
<>	144:ef7eb2e8f9f7	724	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	725	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	726	}
<>	144:ef7eb2e8f9f7	727	break;
<>	144:ef7eb2e8f9f7	728
<>	144:ef7eb2e8f9f7	729	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	730	{
<>	144:ef7eb2e8f9f7	731	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	732	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	733	}
<>	144:ef7eb2e8f9f7	734	break;
<>	144:ef7eb2e8f9f7	735
<>	144:ef7eb2e8f9f7	736	default:
<>	144:ef7eb2e8f9f7	737	break;
<>	144:ef7eb2e8f9f7	738	}
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	741	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	744	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	745
<>	144:ef7eb2e8f9f7	746	/* Return function status */
<>	144:ef7eb2e8f9f7	747	return HAL_OK;
<>	144:ef7eb2e8f9f7	748	}
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/**
<>	144:ef7eb2e8f9f7	751	* @brief Starts the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	752	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	753	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	754	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	755	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	756	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	757	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	758	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	759	* @param pData: The source Buffer address.
<>	144:ef7eb2e8f9f7	760	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	761	* @retval HAL status
<>	144:ef7eb2e8f9f7	762	*/
<>	144:ef7eb2e8f9f7	763	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	764	{
<>	144:ef7eb2e8f9f7	765	/* Check the parameters */
<>	144:ef7eb2e8f9f7	766	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	767
<>	144:ef7eb2e8f9f7	768	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	769	{
<>	144:ef7eb2e8f9f7	770	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	771	}
<>	144:ef7eb2e8f9f7	772	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	773	{
<>	151:5eaa88a5bcc7	774	if(((uint32_t)pData == 0U ) && (Length > 0U))
<>	144:ef7eb2e8f9f7	775	{
<>	144:ef7eb2e8f9f7	776	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	777	}
<>	144:ef7eb2e8f9f7	778	else
<>	144:ef7eb2e8f9f7	779	{
<>	144:ef7eb2e8f9f7	780	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	781	}
<>	144:ef7eb2e8f9f7	782	}
<>	144:ef7eb2e8f9f7	783	switch (Channel)
<>	144:ef7eb2e8f9f7	784	{
<>	144:ef7eb2e8f9f7	785	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	786	{
<>	144:ef7eb2e8f9f7	787	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	788	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	789
<>	144:ef7eb2e8f9f7	790	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	791	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	792
<>	144:ef7eb2e8f9f7	793	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	794	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	797	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	798	}
<>	144:ef7eb2e8f9f7	799	break;
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	802	{
<>	144:ef7eb2e8f9f7	803	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	804	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	805
<>	144:ef7eb2e8f9f7	806	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	807	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	810	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	813	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	break;
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	818	{
<>	144:ef7eb2e8f9f7	819	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	820	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	823	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	826	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	829	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	830	}
<>	144:ef7eb2e8f9f7	831	break;
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	834	{
<>	144:ef7eb2e8f9f7	835	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	836	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	839	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	842	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	845	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	846	}
<>	144:ef7eb2e8f9f7	847	break;
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	default:
<>	144:ef7eb2e8f9f7	850	break;
<>	144:ef7eb2e8f9f7	851	}
<>	144:ef7eb2e8f9f7	852
<>	144:ef7eb2e8f9f7	853	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	854	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	855
<>	144:ef7eb2e8f9f7	856	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	857	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	/* Return function status */
<>	144:ef7eb2e8f9f7	860	return HAL_OK;
<>	144:ef7eb2e8f9f7	861	}
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	/**
<>	144:ef7eb2e8f9f7	864	* @brief Stops the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	865	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	866	* @param Channel: TIM Channel to be disabled.
<>	144:ef7eb2e8f9f7	867	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	868	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	869	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	870	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	871	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	872	* @retval HAL status
<>	144:ef7eb2e8f9f7	873	*/
<>	144:ef7eb2e8f9f7	874	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	875	{
<>	144:ef7eb2e8f9f7	876	/* Check the parameters */
<>	144:ef7eb2e8f9f7	877	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	878
<>	144:ef7eb2e8f9f7	879	switch (Channel)
<>	144:ef7eb2e8f9f7	880	{
<>	144:ef7eb2e8f9f7	881	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	882	{
<>	144:ef7eb2e8f9f7	883	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	884	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	885	}
<>	144:ef7eb2e8f9f7	886	break;
<>	144:ef7eb2e8f9f7	887
<>	144:ef7eb2e8f9f7	888	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	889	{
<>	144:ef7eb2e8f9f7	890	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	891	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	892	}
<>	144:ef7eb2e8f9f7	893	break;
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	896	{
<>	144:ef7eb2e8f9f7	897	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	898	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	899	}
<>	144:ef7eb2e8f9f7	900	break;
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	903	{
<>	144:ef7eb2e8f9f7	904	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	905	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	906	}
<>	144:ef7eb2e8f9f7	907	break;
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	default:
<>	144:ef7eb2e8f9f7	910	break;
<>	144:ef7eb2e8f9f7	911	}
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	914	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	917	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	/* Change the htim state */
<>	144:ef7eb2e8f9f7	920	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/* Return function status */
<>	144:ef7eb2e8f9f7	923	return HAL_OK;
<>	144:ef7eb2e8f9f7	924	}
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/**
<>	144:ef7eb2e8f9f7	927	* @}
<>	144:ef7eb2e8f9f7	928	*/
<>	144:ef7eb2e8f9f7	929
<>	144:ef7eb2e8f9f7	930	/** @addtogroup TIM_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	931	* @brief Time PWM functions
<>	144:ef7eb2e8f9f7	932	*
<>	144:ef7eb2e8f9f7	933	@verbatim
<>	144:ef7eb2e8f9f7	934	==============================================================================
<>	144:ef7eb2e8f9f7	935	##### Timer PWM functions #####
<>	144:ef7eb2e8f9f7	936	==============================================================================
<>	144:ef7eb2e8f9f7	937	[..]
<>	144:ef7eb2e8f9f7	938	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	939	(+) Initialize and configure the TIM OPWM.
<>	144:ef7eb2e8f9f7	940	(+) De-initialize the TIM PWM.
<>	144:ef7eb2e8f9f7	941	(+) Start the Timer PWM.
<>	144:ef7eb2e8f9f7	942	(+) Stop the Timer PWM.
<>	144:ef7eb2e8f9f7	943	(+) Start the Timer PWM and enable interrupt.
<>	144:ef7eb2e8f9f7	944	(+) Stop the Timer PWM and disable interrupt.
<>	144:ef7eb2e8f9f7	945	(+) Start the Timer PWM and enable DMA transfer.
<>	144:ef7eb2e8f9f7	946	(+) Stop the Timer PWM and disable DMA transfer.
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	@endverbatim
<>	144:ef7eb2e8f9f7	949	* @{
<>	144:ef7eb2e8f9f7	950	*/
<>	144:ef7eb2e8f9f7	951	/**
<>	144:ef7eb2e8f9f7	952	* @brief Initializes the TIM PWM Time Base according to the specified
<>	144:ef7eb2e8f9f7	953	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	954	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	955	* @retval HAL status
<>	144:ef7eb2e8f9f7	956	*/
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958
<>	144:ef7eb2e8f9f7	959	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	960	{
<>	144:ef7eb2e8f9f7	961	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	962	if(htim == NULL)
<>	144:ef7eb2e8f9f7	963	{
<>	144:ef7eb2e8f9f7	964	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	965	}
<>	144:ef7eb2e8f9f7	966
<>	144:ef7eb2e8f9f7	967	/* Check the parameters */
<>	144:ef7eb2e8f9f7	968	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	969	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	970	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	971	assert_param(IS_TIM_PERIOD(htim->Init.Period));
<>	144:ef7eb2e8f9f7	972	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	975	{
<>	144:ef7eb2e8f9f7	976	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	977	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	980	HAL_TIM_PWM_MspInit(htim);
<>	144:ef7eb2e8f9f7	981	}
<>	144:ef7eb2e8f9f7	982
<>	144:ef7eb2e8f9f7	983	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	984	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/* Init the base time for the PWM */
<>	144:ef7eb2e8f9f7	987	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	990	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	991
<>	144:ef7eb2e8f9f7	992	return HAL_OK;
<>	144:ef7eb2e8f9f7	993	}
<>	144:ef7eb2e8f9f7	994
<>	144:ef7eb2e8f9f7	995	/**
<>	144:ef7eb2e8f9f7	996	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	997	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	998	* @retval HAL status
<>	144:ef7eb2e8f9f7	999	*/
<>	144:ef7eb2e8f9f7	1000	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1001	{
<>	144:ef7eb2e8f9f7	1002	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1003	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1006
<>	144:ef7eb2e8f9f7	1007	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1008	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1011	HAL_TIM_PWM_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1014	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	/* Release Lock */
<>	144:ef7eb2e8f9f7	1017	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019	return HAL_OK;
<>	144:ef7eb2e8f9f7	1020	}
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	/**
<>	144:ef7eb2e8f9f7	1023	* @brief Initializes the TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1024	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1025	* @retval None
<>	144:ef7eb2e8f9f7	1026	*/
<>	144:ef7eb2e8f9f7	1027	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1028	{
<>	144:ef7eb2e8f9f7	1029	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1030	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1033	the HAL_TIM_PWM_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1034	*/
<>	144:ef7eb2e8f9f7	1035	}
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/**
<>	144:ef7eb2e8f9f7	1038	* @brief DeInitializes TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1039	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1040	* @retval None
<>	144:ef7eb2e8f9f7	1041	*/
<>	144:ef7eb2e8f9f7	1042	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1043	{
<>	144:ef7eb2e8f9f7	1044	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1045	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1048	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1049	*/
<>	144:ef7eb2e8f9f7	1050	}
<>	144:ef7eb2e8f9f7	1051
<>	144:ef7eb2e8f9f7	1052	/**
<>	144:ef7eb2e8f9f7	1053	* @brief Starts the PWM signal generation.
<>	144:ef7eb2e8f9f7	1054	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1055	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1056	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1057	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1058	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1059	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1060	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1061	* @retval HAL status
<>	144:ef7eb2e8f9f7	1062	*/
<>	144:ef7eb2e8f9f7	1063	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1064	{
<>	144:ef7eb2e8f9f7	1065	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1066	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1069	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1072	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1073
<>	144:ef7eb2e8f9f7	1074	/* Return function status */
<>	144:ef7eb2e8f9f7	1075	return HAL_OK;
<>	144:ef7eb2e8f9f7	1076	}
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	/**
<>	144:ef7eb2e8f9f7	1079	* @brief Stops the PWM signal generation.
<>	144:ef7eb2e8f9f7	1080	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1081	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1082	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1083	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1084	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1085	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1086	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1087	* @retval HAL status
<>	144:ef7eb2e8f9f7	1088	*/
<>	144:ef7eb2e8f9f7	1089	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1090	{
<>	144:ef7eb2e8f9f7	1091	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1092	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1095	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1098	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1101	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/* Return function status */
<>	144:ef7eb2e8f9f7	1104	return HAL_OK;
<>	144:ef7eb2e8f9f7	1105	}
<>	144:ef7eb2e8f9f7	1106
<>	144:ef7eb2e8f9f7	1107	/**
<>	144:ef7eb2e8f9f7	1108	* @brief Starts the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1109	* @param htim : TIM handle
Anna Bridge	186:707f6e361f3e	1110	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	1111	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1112	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1113	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1114	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1115	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1116	* @retval HAL status
<>	144:ef7eb2e8f9f7	1117	*/
<>	144:ef7eb2e8f9f7	1118	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1119	{
<>	144:ef7eb2e8f9f7	1120	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1121	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	switch (Channel)
<>	144:ef7eb2e8f9f7	1124	{
<>	144:ef7eb2e8f9f7	1125	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1126	{
<>	144:ef7eb2e8f9f7	1127	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1128	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1129	}
<>	144:ef7eb2e8f9f7	1130	break;
<>	144:ef7eb2e8f9f7	1131
<>	144:ef7eb2e8f9f7	1132	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1133	{
<>	144:ef7eb2e8f9f7	1134	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1135	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1136	}
<>	144:ef7eb2e8f9f7	1137	break;
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1140	{
<>	144:ef7eb2e8f9f7	1141	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1142	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1143	}
<>	144:ef7eb2e8f9f7	1144	break;
<>	144:ef7eb2e8f9f7	1145
<>	144:ef7eb2e8f9f7	1146	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1147	{
<>	144:ef7eb2e8f9f7	1148	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1149	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1150	}
<>	144:ef7eb2e8f9f7	1151	break;
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	default:
<>	144:ef7eb2e8f9f7	1154	break;
<>	144:ef7eb2e8f9f7	1155	}
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1158	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1159
<>	144:ef7eb2e8f9f7	1160	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1161	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	/* Return function status */
<>	144:ef7eb2e8f9f7	1164	return HAL_OK;
<>	144:ef7eb2e8f9f7	1165	}
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	/**
<>	144:ef7eb2e8f9f7	1168	* @brief Stops the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1169	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1170	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1171	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1172	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1173	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1174	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1175	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1176	* @retval HAL status
<>	144:ef7eb2e8f9f7	1177	*/
<>	144:ef7eb2e8f9f7	1178	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1179	{
<>	144:ef7eb2e8f9f7	1180	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1181	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	switch (Channel)
<>	144:ef7eb2e8f9f7	1184	{
<>	144:ef7eb2e8f9f7	1185	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1186	{
<>	144:ef7eb2e8f9f7	1187	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1188	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1189	}
<>	144:ef7eb2e8f9f7	1190	break;
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1193	{
<>	144:ef7eb2e8f9f7	1194	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1195	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1196	}
<>	144:ef7eb2e8f9f7	1197	break;
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1200	{
<>	144:ef7eb2e8f9f7	1201	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1202	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1203	}
<>	144:ef7eb2e8f9f7	1204	break;
<>	144:ef7eb2e8f9f7	1205
<>	144:ef7eb2e8f9f7	1206	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1207	{
<>	144:ef7eb2e8f9f7	1208	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1209	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1210	}
<>	144:ef7eb2e8f9f7	1211	break;
<>	144:ef7eb2e8f9f7	1212
<>	144:ef7eb2e8f9f7	1213	default:
<>	144:ef7eb2e8f9f7	1214	break;
<>	144:ef7eb2e8f9f7	1215	}
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1218	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1221	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	/* Return function status */
<>	144:ef7eb2e8f9f7	1224	return HAL_OK;
<>	144:ef7eb2e8f9f7	1225	}
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	/**
<>	144:ef7eb2e8f9f7	1228	* @brief Starts the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1229	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1230	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1231	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1232	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1233	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1234	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1235	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1236	* @param pData: The source Buffer address. This buffer contains the values
<>	144:ef7eb2e8f9f7	1237	* which will be loaded inside the capture/compare registers.
<>	144:ef7eb2e8f9f7	1238	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	1239	* @retval HAL status
<>	144:ef7eb2e8f9f7	1240	*/
<>	144:ef7eb2e8f9f7	1241	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1242	{
<>	144:ef7eb2e8f9f7	1243	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1244	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1245
<>	144:ef7eb2e8f9f7	1246	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1247	{
<>	144:ef7eb2e8f9f7	1248	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1249	}
<>	144:ef7eb2e8f9f7	1250	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1251	{
<>	151:5eaa88a5bcc7	1252	if(((uint32_t)pData == 0U ) && (Length > 0U))
<>	144:ef7eb2e8f9f7	1253	{
<>	144:ef7eb2e8f9f7	1254	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1255	}
<>	144:ef7eb2e8f9f7	1256	else
<>	144:ef7eb2e8f9f7	1257	{
<>	144:ef7eb2e8f9f7	1258	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1259	}
<>	144:ef7eb2e8f9f7	1260	}
<>	144:ef7eb2e8f9f7	1261	switch (Channel)
<>	144:ef7eb2e8f9f7	1262	{
<>	144:ef7eb2e8f9f7	1263	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1264	{
<>	144:ef7eb2e8f9f7	1265	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1266	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1267
<>	144:ef7eb2e8f9f7	1268	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1269	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1272	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1275	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1276	}
<>	144:ef7eb2e8f9f7	1277	break;
<>	144:ef7eb2e8f9f7	1278
<>	144:ef7eb2e8f9f7	1279	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1280	{
<>	144:ef7eb2e8f9f7	1281	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1282	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1285	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1288	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	1289
<>	144:ef7eb2e8f9f7	1290	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1291	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1292	}
<>	144:ef7eb2e8f9f7	1293	break;
<>	144:ef7eb2e8f9f7	1294
<>	144:ef7eb2e8f9f7	1295	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1296	{
<>	144:ef7eb2e8f9f7	1297	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1298	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1301	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1302
<>	144:ef7eb2e8f9f7	1303	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1304	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	1305
<>	144:ef7eb2e8f9f7	1306	/* Enable the TIM Output Capture/Compare 3 request */
<>	144:ef7eb2e8f9f7	1307	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1308	}
<>	144:ef7eb2e8f9f7	1309	break;
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1312	{
<>	144:ef7eb2e8f9f7	1313	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1314	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1315
<>	144:ef7eb2e8f9f7	1316	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1317	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1318
<>	144:ef7eb2e8f9f7	1319	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1320	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	1321
<>	144:ef7eb2e8f9f7	1322	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1323	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1324	}
<>	144:ef7eb2e8f9f7	1325	break;
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	default:
<>	144:ef7eb2e8f9f7	1328	break;
<>	144:ef7eb2e8f9f7	1329	}
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1332	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1333
<>	144:ef7eb2e8f9f7	1334	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1335	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	/* Return function status */
<>	144:ef7eb2e8f9f7	1338	return HAL_OK;
<>	144:ef7eb2e8f9f7	1339	}
<>	144:ef7eb2e8f9f7	1340
<>	144:ef7eb2e8f9f7	1341	/**
<>	144:ef7eb2e8f9f7	1342	* @brief Stops the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1343	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1344	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1345	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1346	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1347	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1348	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1349	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1350	* @retval HAL status
<>	144:ef7eb2e8f9f7	1351	*/
<>	144:ef7eb2e8f9f7	1352	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1353	{
<>	144:ef7eb2e8f9f7	1354	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1355	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1356
<>	144:ef7eb2e8f9f7	1357	switch (Channel)
<>	144:ef7eb2e8f9f7	1358	{
<>	144:ef7eb2e8f9f7	1359	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1360	{
<>	144:ef7eb2e8f9f7	1361	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1362	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1363	}
<>	144:ef7eb2e8f9f7	1364	break;
<>	144:ef7eb2e8f9f7	1365
<>	144:ef7eb2e8f9f7	1366	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1367	{
<>	144:ef7eb2e8f9f7	1368	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1369	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1370	}
<>	144:ef7eb2e8f9f7	1371	break;
<>	144:ef7eb2e8f9f7	1372
<>	144:ef7eb2e8f9f7	1373	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1374	{
<>	144:ef7eb2e8f9f7	1375	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1376	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1377	}
<>	144:ef7eb2e8f9f7	1378	break;
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1381	{
<>	144:ef7eb2e8f9f7	1382	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1383	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1384	}
<>	144:ef7eb2e8f9f7	1385	break;
<>	144:ef7eb2e8f9f7	1386
<>	144:ef7eb2e8f9f7	1387	default:
<>	144:ef7eb2e8f9f7	1388	break;
<>	144:ef7eb2e8f9f7	1389	}
<>	144:ef7eb2e8f9f7	1390
<>	144:ef7eb2e8f9f7	1391	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1392	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1395	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1396
<>	144:ef7eb2e8f9f7	1397	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1398	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1399
<>	144:ef7eb2e8f9f7	1400	/* Return function status */
<>	144:ef7eb2e8f9f7	1401	return HAL_OK;
<>	144:ef7eb2e8f9f7	1402	}
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/**
<>	144:ef7eb2e8f9f7	1405	* @}
<>	144:ef7eb2e8f9f7	1406	*/
<>	144:ef7eb2e8f9f7	1407
<>	144:ef7eb2e8f9f7	1408	/** @addtogroup TIM_Exported_Functions_Group4
<>	144:ef7eb2e8f9f7	1409	* @brief Time Input Capture functions
<>	144:ef7eb2e8f9f7	1410	*
<>	144:ef7eb2e8f9f7	1411	@verbatim
<>	144:ef7eb2e8f9f7	1412	==============================================================================
<>	144:ef7eb2e8f9f7	1413	##### Timer Input Capture functions #####
<>	144:ef7eb2e8f9f7	1414	==============================================================================
<>	144:ef7eb2e8f9f7	1415	[..]
<>	144:ef7eb2e8f9f7	1416	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1417	(+) Initialize and configure the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1418	(+) De-initialize the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1419	(+) Start the Timer Input Capture.
<>	144:ef7eb2e8f9f7	1420	(+) Stop the Timer Input Capture.
<>	144:ef7eb2e8f9f7	1421	(+) Start the Timer Input Capture and enable interrupt.
<>	144:ef7eb2e8f9f7	1422	(+) Stop the Timer Input Capture and disable interrupt.
<>	144:ef7eb2e8f9f7	1423	(+) Start the Timer Input Capture and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1424	(+) Stop the Timer Input Capture and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1425
<>	144:ef7eb2e8f9f7	1426	@endverbatim
<>	144:ef7eb2e8f9f7	1427	* @{
<>	144:ef7eb2e8f9f7	1428	*/
<>	144:ef7eb2e8f9f7	1429	/**
<>	144:ef7eb2e8f9f7	1430	* @brief Initializes the TIM Input Capture Time base according to the specified
<>	144:ef7eb2e8f9f7	1431	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1432	* @param htim: TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1433	* @retval HAL status
<>	144:ef7eb2e8f9f7	1434	*/
<>	144:ef7eb2e8f9f7	1435	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1436	{
<>	144:ef7eb2e8f9f7	1437	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1438	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1439	{
<>	144:ef7eb2e8f9f7	1440	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1441	}
<>	144:ef7eb2e8f9f7	1442
<>	144:ef7eb2e8f9f7	1443	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1444	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1445	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1446	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	1447	assert_param(IS_TIM_PERIOD(htim->Init.Period));
<>	144:ef7eb2e8f9f7	1448	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1451	{
<>	144:ef7eb2e8f9f7	1452	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1453	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1456	HAL_TIM_IC_MspInit(htim);
<>	144:ef7eb2e8f9f7	1457	}
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1460	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	/* Init the base time for the input capture */
<>	144:ef7eb2e8f9f7	1463	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1464
<>	144:ef7eb2e8f9f7	1465	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1466	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1467
<>	144:ef7eb2e8f9f7	1468	return HAL_OK;
<>	144:ef7eb2e8f9f7	1469	}
<>	144:ef7eb2e8f9f7	1470
<>	144:ef7eb2e8f9f7	1471	/**
<>	144:ef7eb2e8f9f7	1472	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	1473	* @param htim: TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1474	* @retval HAL status
<>	144:ef7eb2e8f9f7	1475	*/
<>	144:ef7eb2e8f9f7	1476	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1477	{
<>	144:ef7eb2e8f9f7	1478	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1479	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1482
<>	144:ef7eb2e8f9f7	1483	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1484	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1485
<>	144:ef7eb2e8f9f7	1486	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1487	HAL_TIM_IC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1488
<>	144:ef7eb2e8f9f7	1489	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1490	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1491
<>	144:ef7eb2e8f9f7	1492	/* Release Lock */
<>	144:ef7eb2e8f9f7	1493	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1494
<>	144:ef7eb2e8f9f7	1495	return HAL_OK;
<>	144:ef7eb2e8f9f7	1496	}
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/**
<>	144:ef7eb2e8f9f7	1499	* @brief Initializes the TIM INput Capture MSP.
<>	144:ef7eb2e8f9f7	1500	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1501	* @retval None
<>	144:ef7eb2e8f9f7	1502	*/
<>	144:ef7eb2e8f9f7	1503	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1504	{
<>	144:ef7eb2e8f9f7	1505	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1506	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1507
<>	144:ef7eb2e8f9f7	1508	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1509	the HAL_TIM_IC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1510	*/
<>	144:ef7eb2e8f9f7	1511	}
<>	144:ef7eb2e8f9f7	1512
<>	144:ef7eb2e8f9f7	1513	/**
<>	144:ef7eb2e8f9f7	1514	* @brief DeInitializes TIM Input Capture MSP.
<>	144:ef7eb2e8f9f7	1515	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1516	* @retval None
<>	144:ef7eb2e8f9f7	1517	*/
<>	144:ef7eb2e8f9f7	1518	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1519	{
<>	144:ef7eb2e8f9f7	1520	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1521	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1524	the HAL_TIM_IC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1525	*/
<>	144:ef7eb2e8f9f7	1526	}
<>	144:ef7eb2e8f9f7	1527	/**
<>	144:ef7eb2e8f9f7	1528	* @brief Starts the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1529	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1530	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1531	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1532	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1533	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1534	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1535	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1536	* @retval HAL status
<>	144:ef7eb2e8f9f7	1537	*/
<>	144:ef7eb2e8f9f7	1538	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1539	{
<>	144:ef7eb2e8f9f7	1540	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1541	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1544	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1547	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	/* Return function status */
<>	144:ef7eb2e8f9f7	1550	return HAL_OK;
<>	144:ef7eb2e8f9f7	1551	}
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	/**
<>	144:ef7eb2e8f9f7	1554	* @brief Stops the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1555	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1556	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1557	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1558	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1559	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1560	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1561	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1562	* @retval HAL status
<>	144:ef7eb2e8f9f7	1563	*/
<>	144:ef7eb2e8f9f7	1564	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1565	{
<>	144:ef7eb2e8f9f7	1566	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1567	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1568
<>	144:ef7eb2e8f9f7	1569	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1570	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1573	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1574
<>	144:ef7eb2e8f9f7	1575	/* Return function status */
<>	144:ef7eb2e8f9f7	1576	return HAL_OK;
<>	144:ef7eb2e8f9f7	1577	}
<>	144:ef7eb2e8f9f7	1578
<>	144:ef7eb2e8f9f7	1579	/**
<>	144:ef7eb2e8f9f7	1580	* @brief Starts the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1581	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1582	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1583	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1584	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1585	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1586	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1587	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1588	* @retval HAL status
<>	144:ef7eb2e8f9f7	1589	*/
<>	144:ef7eb2e8f9f7	1590	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1591	{
<>	144:ef7eb2e8f9f7	1592	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1593	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1594
<>	144:ef7eb2e8f9f7	1595	switch (Channel)
<>	144:ef7eb2e8f9f7	1596	{
<>	144:ef7eb2e8f9f7	1597	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1598	{
<>	144:ef7eb2e8f9f7	1599	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1600	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1601	}
<>	144:ef7eb2e8f9f7	1602	break;
<>	144:ef7eb2e8f9f7	1603
<>	144:ef7eb2e8f9f7	1604	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1605	{
<>	144:ef7eb2e8f9f7	1606	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1607	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1608	}
<>	144:ef7eb2e8f9f7	1609	break;
<>	144:ef7eb2e8f9f7	1610
<>	144:ef7eb2e8f9f7	1611	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1612	{
<>	144:ef7eb2e8f9f7	1613	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1614	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1615	}
<>	144:ef7eb2e8f9f7	1616	break;
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1619	{
<>	144:ef7eb2e8f9f7	1620	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1621	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1622	}
<>	144:ef7eb2e8f9f7	1623	break;
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	default:
<>	144:ef7eb2e8f9f7	1626	break;
<>	144:ef7eb2e8f9f7	1627	}
<>	144:ef7eb2e8f9f7	1628	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1629	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1630
<>	144:ef7eb2e8f9f7	1631	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1632	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1633
<>	144:ef7eb2e8f9f7	1634	/* Return function status */
<>	144:ef7eb2e8f9f7	1635	return HAL_OK;
<>	144:ef7eb2e8f9f7	1636	}
<>	144:ef7eb2e8f9f7	1637
<>	144:ef7eb2e8f9f7	1638	/**
<>	144:ef7eb2e8f9f7	1639	* @brief Stops the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1640	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1641	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1642	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1643	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1644	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1645	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1646	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1647	* @retval HAL status
<>	144:ef7eb2e8f9f7	1648	*/
<>	144:ef7eb2e8f9f7	1649	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1650	{
<>	144:ef7eb2e8f9f7	1651	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1652	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1653
<>	144:ef7eb2e8f9f7	1654	switch (Channel)
<>	144:ef7eb2e8f9f7	1655	{
<>	144:ef7eb2e8f9f7	1656	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1657	{
<>	144:ef7eb2e8f9f7	1658	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1659	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1660	}
<>	144:ef7eb2e8f9f7	1661	break;
<>	144:ef7eb2e8f9f7	1662
<>	144:ef7eb2e8f9f7	1663	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1664	{
<>	144:ef7eb2e8f9f7	1665	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1666	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1667	}
<>	144:ef7eb2e8f9f7	1668	break;
<>	144:ef7eb2e8f9f7	1669
<>	144:ef7eb2e8f9f7	1670	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1671	{
<>	144:ef7eb2e8f9f7	1672	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1673	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1674	}
<>	144:ef7eb2e8f9f7	1675	break;
<>	144:ef7eb2e8f9f7	1676
<>	144:ef7eb2e8f9f7	1677	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1678	{
<>	144:ef7eb2e8f9f7	1679	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1680	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1681	}
<>	144:ef7eb2e8f9f7	1682	break;
<>	144:ef7eb2e8f9f7	1683
<>	144:ef7eb2e8f9f7	1684	default:
<>	144:ef7eb2e8f9f7	1685	break;
<>	144:ef7eb2e8f9f7	1686	}
<>	144:ef7eb2e8f9f7	1687
<>	144:ef7eb2e8f9f7	1688	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1689	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1690
<>	144:ef7eb2e8f9f7	1691	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1692	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694	/* Return function status */
<>	144:ef7eb2e8f9f7	1695	return HAL_OK;
<>	144:ef7eb2e8f9f7	1696	}
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/**
<>	144:ef7eb2e8f9f7	1699	* @brief Starts the TIM Input Capture measurement on in DMA mode.
<>	144:ef7eb2e8f9f7	1700	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1701	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1702	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1703	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1704	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1705	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1706	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1707	* @param pData: The destination Buffer address.
<>	144:ef7eb2e8f9f7	1708	* @param Length: The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	1709	* @retval HAL status
<>	144:ef7eb2e8f9f7	1710	*/
<>	144:ef7eb2e8f9f7	1711	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1712	{
<>	144:ef7eb2e8f9f7	1713	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1714	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1715	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1718	{
<>	144:ef7eb2e8f9f7	1719	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1720	}
<>	144:ef7eb2e8f9f7	1721	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1722	{
<>	151:5eaa88a5bcc7	1723	if((pData == 0U ) && (Length > 0U))
<>	144:ef7eb2e8f9f7	1724	{
<>	144:ef7eb2e8f9f7	1725	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1726	}
<>	144:ef7eb2e8f9f7	1727	else
<>	144:ef7eb2e8f9f7	1728	{
<>	144:ef7eb2e8f9f7	1729	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1730	}
<>	144:ef7eb2e8f9f7	1731	}
<>	144:ef7eb2e8f9f7	1732
<>	144:ef7eb2e8f9f7	1733	switch (Channel)
<>	144:ef7eb2e8f9f7	1734	{
<>	144:ef7eb2e8f9f7	1735	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1736	{
<>	144:ef7eb2e8f9f7	1737	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1738	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1739
<>	144:ef7eb2e8f9f7	1740	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1741	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1742
<>	144:ef7eb2e8f9f7	1743	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1744	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1745
<>	144:ef7eb2e8f9f7	1746	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1747	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1748	}
<>	144:ef7eb2e8f9f7	1749	break;
<>	144:ef7eb2e8f9f7	1750
<>	144:ef7eb2e8f9f7	1751	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1752	{
<>	144:ef7eb2e8f9f7	1753	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1754	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1755
<>	144:ef7eb2e8f9f7	1756	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1757	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1760	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1761
<>	144:ef7eb2e8f9f7	1762	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1763	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1764	}
<>	144:ef7eb2e8f9f7	1765	break;
<>	144:ef7eb2e8f9f7	1766
<>	144:ef7eb2e8f9f7	1767	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1768	{
<>	144:ef7eb2e8f9f7	1769	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1770	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1771
<>	144:ef7eb2e8f9f7	1772	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1773	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1774
<>	144:ef7eb2e8f9f7	1775	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1776	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1777
<>	144:ef7eb2e8f9f7	1778	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1779	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1780	}
<>	144:ef7eb2e8f9f7	1781	break;
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1784	{
<>	144:ef7eb2e8f9f7	1785	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1786	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1787
<>	144:ef7eb2e8f9f7	1788	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1789	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1790
<>	144:ef7eb2e8f9f7	1791	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1792	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1795	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1796	}
<>	144:ef7eb2e8f9f7	1797	break;
<>	144:ef7eb2e8f9f7	1798
<>	144:ef7eb2e8f9f7	1799	default:
<>	144:ef7eb2e8f9f7	1800	break;
<>	144:ef7eb2e8f9f7	1801	}
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1804	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1805
<>	144:ef7eb2e8f9f7	1806	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1807	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	/* Return function status */
<>	144:ef7eb2e8f9f7	1810	return HAL_OK;
<>	144:ef7eb2e8f9f7	1811	}
<>	144:ef7eb2e8f9f7	1812
<>	144:ef7eb2e8f9f7	1813	/**
<>	144:ef7eb2e8f9f7	1814	* @brief Stops the TIM Input Capture measurement on in DMA mode.
<>	144:ef7eb2e8f9f7	1815	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1816	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1817	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1818	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1819	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1820	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1821	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1822	* @retval HAL status
<>	144:ef7eb2e8f9f7	1823	*/
<>	144:ef7eb2e8f9f7	1824	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1825	{
<>	144:ef7eb2e8f9f7	1826	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1827	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1828	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1829
<>	144:ef7eb2e8f9f7	1830	switch (Channel)
<>	144:ef7eb2e8f9f7	1831	{
<>	144:ef7eb2e8f9f7	1832	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1833	{
<>	144:ef7eb2e8f9f7	1834	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1835	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1836	}
<>	144:ef7eb2e8f9f7	1837	break;
<>	144:ef7eb2e8f9f7	1838
<>	144:ef7eb2e8f9f7	1839	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1840	{
<>	144:ef7eb2e8f9f7	1841	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1842	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1843	}
<>	144:ef7eb2e8f9f7	1844	break;
<>	144:ef7eb2e8f9f7	1845
<>	144:ef7eb2e8f9f7	1846	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1847	{
<>	144:ef7eb2e8f9f7	1848	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1849	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1850	}
<>	144:ef7eb2e8f9f7	1851	break;
<>	144:ef7eb2e8f9f7	1852
<>	144:ef7eb2e8f9f7	1853	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1854	{
<>	144:ef7eb2e8f9f7	1855	/* Disable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1856	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1857	}
<>	144:ef7eb2e8f9f7	1858	break;
<>	144:ef7eb2e8f9f7	1859
<>	144:ef7eb2e8f9f7	1860	default:
<>	144:ef7eb2e8f9f7	1861	break;
<>	144:ef7eb2e8f9f7	1862	}
<>	144:ef7eb2e8f9f7	1863
<>	144:ef7eb2e8f9f7	1864	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1865	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1866
<>	144:ef7eb2e8f9f7	1867	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1868	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1869
<>	144:ef7eb2e8f9f7	1870	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1871	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1872
<>	144:ef7eb2e8f9f7	1873	/* Return function status */
<>	144:ef7eb2e8f9f7	1874	return HAL_OK;
<>	144:ef7eb2e8f9f7	1875	}
<>	144:ef7eb2e8f9f7	1876
<>	144:ef7eb2e8f9f7	1877	/**
<>	144:ef7eb2e8f9f7	1878	* @}
<>	144:ef7eb2e8f9f7	1879	*/
<>	144:ef7eb2e8f9f7	1880
<>	144:ef7eb2e8f9f7	1881	/** @addtogroup TIM_Exported_Functions_Group5
<>	144:ef7eb2e8f9f7	1882	* @brief Time One Pulse functions
<>	144:ef7eb2e8f9f7	1883	*
<>	144:ef7eb2e8f9f7	1884	@verbatim
<>	144:ef7eb2e8f9f7	1885	==============================================================================
<>	144:ef7eb2e8f9f7	1886	##### Timer One Pulse functions #####
<>	144:ef7eb2e8f9f7	1887	==============================================================================
<>	144:ef7eb2e8f9f7	1888	[..]
<>	144:ef7eb2e8f9f7	1889	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1890	(+) Initialize and configure the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1891	(+) De-initialize the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1892	(+) Start the Timer One Pulse.
<>	144:ef7eb2e8f9f7	1893	(+) Stop the Timer One Pulse.
<>	144:ef7eb2e8f9f7	1894	(+) Start the Timer One Pulse and enable interrupt.
<>	144:ef7eb2e8f9f7	1895	(+) Stop the Timer One Pulse and disable interrupt.
<>	144:ef7eb2e8f9f7	1896	(+) Start the Timer One Pulse and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1897	(+) Stop the Timer One Pulse and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	@endverbatim
<>	144:ef7eb2e8f9f7	1900	* @{
<>	144:ef7eb2e8f9f7	1901	*/
<>	144:ef7eb2e8f9f7	1902	/**
<>	144:ef7eb2e8f9f7	1903	* @brief Initializes the TIM One Pulse Time Base according to the specified
<>	144:ef7eb2e8f9f7	1904	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1905	* @param htim: TIM OnePulse handle
<>	144:ef7eb2e8f9f7	1906	* @param OnePulseMode: Select the One pulse mode.
<>	144:ef7eb2e8f9f7	1907	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1908	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<>	144:ef7eb2e8f9f7	1909	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
<>	144:ef7eb2e8f9f7	1910	* @retval HAL status
<>	144:ef7eb2e8f9f7	1911	*/
<>	144:ef7eb2e8f9f7	1912	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<>	144:ef7eb2e8f9f7	1913	{
<>	144:ef7eb2e8f9f7	1914	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1915	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1916	{
<>	144:ef7eb2e8f9f7	1917	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1918	}
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1921	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1922	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1923	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	1924	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<>	144:ef7eb2e8f9f7	1925	assert_param(IS_TIM_PERIOD(htim->Init.Period));
<>	144:ef7eb2e8f9f7	1926	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<>	144:ef7eb2e8f9f7	1927
<>	144:ef7eb2e8f9f7	1928	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1929	{
<>	144:ef7eb2e8f9f7	1930	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1931	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1932
<>	144:ef7eb2e8f9f7	1933	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1934	HAL_TIM_OnePulse_MspInit(htim);
<>	144:ef7eb2e8f9f7	1935	}
<>	144:ef7eb2e8f9f7	1936
<>	144:ef7eb2e8f9f7	1937	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1938	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1939
<>	144:ef7eb2e8f9f7	1940	/* Configure the Time base in the One Pulse Mode */
<>	144:ef7eb2e8f9f7	1941	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1942
<>	144:ef7eb2e8f9f7	1943	/* Reset the OPM Bit */
<>	144:ef7eb2e8f9f7	1944	htim->Instance->CR1 &= ~TIM_CR1_OPM;
<>	144:ef7eb2e8f9f7	1945
<>	144:ef7eb2e8f9f7	1946	/* Configure the OPM Mode */
<>	144:ef7eb2e8f9f7	1947	htim->Instance->CR1 \|= OnePulseMode;
<>	144:ef7eb2e8f9f7	1948
<>	144:ef7eb2e8f9f7	1949	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1950	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1951
<>	144:ef7eb2e8f9f7	1952	return HAL_OK;
<>	144:ef7eb2e8f9f7	1953	}
<>	144:ef7eb2e8f9f7	1954
<>	144:ef7eb2e8f9f7	1955	/**
<>	144:ef7eb2e8f9f7	1956	* @brief DeInitializes the TIM One Pulse
<>	144:ef7eb2e8f9f7	1957	* @param htim: TIM One Pulse handle
<>	144:ef7eb2e8f9f7	1958	* @retval HAL status
<>	144:ef7eb2e8f9f7	1959	*/
<>	144:ef7eb2e8f9f7	1960	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1961	{
<>	144:ef7eb2e8f9f7	1962	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1963	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1964
<>	144:ef7eb2e8f9f7	1965	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1966
<>	144:ef7eb2e8f9f7	1967	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1968	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1969
<>	144:ef7eb2e8f9f7	1970	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	1971	HAL_TIM_OnePulse_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1972
<>	144:ef7eb2e8f9f7	1973	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1974	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1975
<>	144:ef7eb2e8f9f7	1976	/* Release Lock */
<>	144:ef7eb2e8f9f7	1977	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1978
<>	144:ef7eb2e8f9f7	1979	return HAL_OK;
<>	144:ef7eb2e8f9f7	1980	}
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	/**
<>	144:ef7eb2e8f9f7	1983	* @brief Initializes the TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	1984	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1985	* @retval None
<>	144:ef7eb2e8f9f7	1986	*/
<>	144:ef7eb2e8f9f7	1987	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1988	{
<>	144:ef7eb2e8f9f7	1989	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1990	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1991
<>	144:ef7eb2e8f9f7	1992	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1993	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1994	*/
<>	144:ef7eb2e8f9f7	1995	}
<>	144:ef7eb2e8f9f7	1996
<>	144:ef7eb2e8f9f7	1997	/**
<>	144:ef7eb2e8f9f7	1998	* @brief DeInitializes TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	1999	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2000	* @retval None
<>	144:ef7eb2e8f9f7	2001	*/
<>	144:ef7eb2e8f9f7	2002	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2003	{
<>	144:ef7eb2e8f9f7	2004	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2005	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2008	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2009	*/
<>	144:ef7eb2e8f9f7	2010	}
<>	144:ef7eb2e8f9f7	2011
<>	144:ef7eb2e8f9f7	2012	/**
<>	144:ef7eb2e8f9f7	2013	* @brief Starts the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2014	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2015	* @param OutputChannel : TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2016	* This parameter is not used since both channels TIM_CHANNEL_1 and
<>	144:ef7eb2e8f9f7	2017	* TIM_CHANNEL_2 are automatically selected.
<>	144:ef7eb2e8f9f7	2018	* @retval HAL status
<>	144:ef7eb2e8f9f7	2019	*/
<>	144:ef7eb2e8f9f7	2020	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2021	{
<>	144:ef7eb2e8f9f7	2022	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2023	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2024	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2025	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2026	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2027
<>	144:ef7eb2e8f9f7	2028	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2029	(the counter starts in response to a stimulus and generate a pulse */
<>	144:ef7eb2e8f9f7	2030
<>	144:ef7eb2e8f9f7	2031	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2032	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2033
<>	144:ef7eb2e8f9f7	2034	/* Return function status */
<>	144:ef7eb2e8f9f7	2035	return HAL_OK;
<>	144:ef7eb2e8f9f7	2036	}
<>	144:ef7eb2e8f9f7	2037
<>	144:ef7eb2e8f9f7	2038	/**
<>	144:ef7eb2e8f9f7	2039	* @brief Stops the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2040	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2041	* @param OutputChannel : TIM Channels to be disable.
<>	144:ef7eb2e8f9f7	2042	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2043	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2044	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2045	* @retval HAL status
<>	144:ef7eb2e8f9f7	2046	*/
<>	144:ef7eb2e8f9f7	2047	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2048	{
<>	144:ef7eb2e8f9f7	2049	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2050	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2051	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2052	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2053	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	144:ef7eb2e8f9f7	2054
<>	144:ef7eb2e8f9f7	2055	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2056	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2057
<>	144:ef7eb2e8f9f7	2058	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2059	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2060
<>	144:ef7eb2e8f9f7	2061	/* Return function status */
<>	144:ef7eb2e8f9f7	2062	return HAL_OK;
<>	144:ef7eb2e8f9f7	2063	}
<>	144:ef7eb2e8f9f7	2064
<>	144:ef7eb2e8f9f7	2065	/**
<>	144:ef7eb2e8f9f7	2066	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2067	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2068	* @param OutputChannel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2069	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2070	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2071	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2072	* @retval HAL status
<>	144:ef7eb2e8f9f7	2073	*/
<>	144:ef7eb2e8f9f7	2074	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2075	{
<>	144:ef7eb2e8f9f7	2076	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2077	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2078	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2079	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2080	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2081
<>	144:ef7eb2e8f9f7	2082	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2083	(the counter starts in response to a stimulus and generate a pulse */
<>	144:ef7eb2e8f9f7	2084
<>	144:ef7eb2e8f9f7	2085	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2086	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2087
<>	144:ef7eb2e8f9f7	2088	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2089	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2090
<>	144:ef7eb2e8f9f7	2091	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2092	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2093
<>	144:ef7eb2e8f9f7	2094	/* Return function status */
<>	144:ef7eb2e8f9f7	2095	return HAL_OK;
<>	144:ef7eb2e8f9f7	2096	}
<>	144:ef7eb2e8f9f7	2097
<>	144:ef7eb2e8f9f7	2098	/**
<>	144:ef7eb2e8f9f7	2099	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2100	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2101	* @param OutputChannel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2102	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2103	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2104	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2105	* @retval HAL status
<>	144:ef7eb2e8f9f7	2106	*/
<>	144:ef7eb2e8f9f7	2107	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2108	{
<>	144:ef7eb2e8f9f7	2109	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2110	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2111
<>	144:ef7eb2e8f9f7	2112	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2113	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2114
<>	144:ef7eb2e8f9f7	2115	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2116	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2117	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2118	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2119	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	144:ef7eb2e8f9f7	2120	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2121	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2124	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126	/* Return function status */
<>	144:ef7eb2e8f9f7	2127	return HAL_OK;
<>	144:ef7eb2e8f9f7	2128	}
<>	144:ef7eb2e8f9f7	2129
<>	144:ef7eb2e8f9f7	2130	/**
<>	144:ef7eb2e8f9f7	2131	* @}
<>	144:ef7eb2e8f9f7	2132	*/
<>	144:ef7eb2e8f9f7	2133
<>	144:ef7eb2e8f9f7	2134	/** @addtogroup TIM_Exported_Functions_Group6
<>	144:ef7eb2e8f9f7	2135	* @brief Time Encoder functions
<>	144:ef7eb2e8f9f7	2136	*
<>	144:ef7eb2e8f9f7	2137	@verbatim
<>	144:ef7eb2e8f9f7	2138	==============================================================================
<>	144:ef7eb2e8f9f7	2139	##### Timer Encoder functions #####
<>	144:ef7eb2e8f9f7	2140	==============================================================================
<>	144:ef7eb2e8f9f7	2141	[..]
<>	144:ef7eb2e8f9f7	2142	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2143	(+) Initialize and configure the TIM Encoder.
<>	144:ef7eb2e8f9f7	2144	(+) De-initialize the TIM Encoder.
<>	144:ef7eb2e8f9f7	2145	(+) Start the Timer Encoder.
<>	144:ef7eb2e8f9f7	2146	(+) Stop the Timer Encoder.
<>	144:ef7eb2e8f9f7	2147	(+) Start the Timer Encoder and enable interrupt.
<>	144:ef7eb2e8f9f7	2148	(+) Stop the Timer Encoder and disable interrupt.
<>	144:ef7eb2e8f9f7	2149	(+) Start the Timer Encoder and enable DMA transfer.
<>	144:ef7eb2e8f9f7	2150	(+) Stop the Timer Encoder and disable DMA transfer.
<>	144:ef7eb2e8f9f7	2151
<>	144:ef7eb2e8f9f7	2152	@endverbatim
<>	144:ef7eb2e8f9f7	2153	* @{
<>	144:ef7eb2e8f9f7	2154	*/
<>	144:ef7eb2e8f9f7	2155	/**
<>	144:ef7eb2e8f9f7	2156	* @brief Initializes the TIM Encoder Interface and create the associated handle.
<>	144:ef7eb2e8f9f7	2157	* @param htim: TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2158	* @param sConfig: TIM Encoder Interface configuration structure
<>	144:ef7eb2e8f9f7	2159	* @retval HAL status
<>	144:ef7eb2e8f9f7	2160	*/
<>	144:ef7eb2e8f9f7	2161	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
<>	144:ef7eb2e8f9f7	2162	{
<>	151:5eaa88a5bcc7	2163	uint32_t tmpsmcr = 0U;
<>	151:5eaa88a5bcc7	2164	uint32_t tmpccmr1 = 0U;
<>	151:5eaa88a5bcc7	2165	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	2168	if(htim == NULL)
<>	144:ef7eb2e8f9f7	2169	{
<>	144:ef7eb2e8f9f7	2170	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2171	}
<>	144:ef7eb2e8f9f7	2172
<>	144:ef7eb2e8f9f7	2173	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2174	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2175	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<>	144:ef7eb2e8f9f7	2176	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<>	144:ef7eb2e8f9f7	2177	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<>	144:ef7eb2e8f9f7	2178	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<>	144:ef7eb2e8f9f7	2179	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<>	144:ef7eb2e8f9f7	2180	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<>	144:ef7eb2e8f9f7	2181	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<>	144:ef7eb2e8f9f7	2182	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<>	144:ef7eb2e8f9f7	2183	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<>	144:ef7eb2e8f9f7	2184	assert_param(IS_TIM_PERIOD(htim->Init.Period));
<>	144:ef7eb2e8f9f7	2185	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<>	144:ef7eb2e8f9f7	2186
<>	144:ef7eb2e8f9f7	2187	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	2188	{
<>	144:ef7eb2e8f9f7	2189	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	2190	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	2191
<>	144:ef7eb2e8f9f7	2192	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	2193	HAL_TIM_Encoder_MspInit(htim);
<>	144:ef7eb2e8f9f7	2194	}
<>	144:ef7eb2e8f9f7	2195
<>	144:ef7eb2e8f9f7	2196	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	2197	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2198
<>	144:ef7eb2e8f9f7	2199	/* Reset the SMS bits */
<>	144:ef7eb2e8f9f7	2200	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	2201
<>	144:ef7eb2e8f9f7	2202	/* Configure the Time base in the Encoder Mode */
<>	144:ef7eb2e8f9f7	2203	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	2204
<>	144:ef7eb2e8f9f7	2205	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	2206	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	2207
<>	144:ef7eb2e8f9f7	2208	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	2209	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	2210
<>	144:ef7eb2e8f9f7	2211	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	2212	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	2213
<>	144:ef7eb2e8f9f7	2214	/* Set the encoder Mode */
<>	144:ef7eb2e8f9f7	2215	tmpsmcr \|= sConfig->EncoderMode;
<>	144:ef7eb2e8f9f7	2216
<>	144:ef7eb2e8f9f7	2217	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
<>	144:ef7eb2e8f9f7	2218	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
<>	151:5eaa88a5bcc7	2219	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8U));
<>	144:ef7eb2e8f9f7	2220
<>	144:ef7eb2e8f9f7	2221	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<>	144:ef7eb2e8f9f7	2222	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
<>	144:ef7eb2e8f9f7	2223	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
<>	151:5eaa88a5bcc7	2224	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8U);
<>	151:5eaa88a5bcc7	2225	tmpccmr1 \|= (sConfig->IC1Filter << 4U) \| (sConfig->IC2Filter << 12U);
<>	144:ef7eb2e8f9f7	2226
<>	144:ef7eb2e8f9f7	2227	/* Set the TI1 and the TI2 Polarities */
<>	144:ef7eb2e8f9f7	2228	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
<>	144:ef7eb2e8f9f7	2229	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
<>	151:5eaa88a5bcc7	2230	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4U);
<>	144:ef7eb2e8f9f7	2231
<>	144:ef7eb2e8f9f7	2232	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	2233	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	2234
<>	144:ef7eb2e8f9f7	2235	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	2236	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	2237
<>	144:ef7eb2e8f9f7	2238	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	2239	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	2240
<>	144:ef7eb2e8f9f7	2241	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	2242	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	return HAL_OK;
<>	144:ef7eb2e8f9f7	2245	}
<>	144:ef7eb2e8f9f7	2246
<>	144:ef7eb2e8f9f7	2247	/**
<>	144:ef7eb2e8f9f7	2248	* @brief DeInitializes the TIM Encoder interface
<>	144:ef7eb2e8f9f7	2249	* @param htim: TIM Encoder handle
<>	144:ef7eb2e8f9f7	2250	* @retval HAL status
<>	144:ef7eb2e8f9f7	2251	*/
<>	144:ef7eb2e8f9f7	2252	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2253	{
<>	144:ef7eb2e8f9f7	2254	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2255	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2256
<>	144:ef7eb2e8f9f7	2257	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2258
<>	144:ef7eb2e8f9f7	2259	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	2260	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2261
<>	144:ef7eb2e8f9f7	2262	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	2263	HAL_TIM_Encoder_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	2264
<>	144:ef7eb2e8f9f7	2265	/* Change TIM state */
<>	144:ef7eb2e8f9f7	2266	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	2267
<>	144:ef7eb2e8f9f7	2268	/* Release Lock */
<>	144:ef7eb2e8f9f7	2269	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2270
<>	144:ef7eb2e8f9f7	2271	return HAL_OK;
<>	144:ef7eb2e8f9f7	2272	}
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274
<>	144:ef7eb2e8f9f7	2275	/**
<>	144:ef7eb2e8f9f7	2276	* @brief Initializes the TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2277	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2278	* @retval None
<>	144:ef7eb2e8f9f7	2279	*/
<>	144:ef7eb2e8f9f7	2280	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2281	{
<>	144:ef7eb2e8f9f7	2282	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2283	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2284
<>	144:ef7eb2e8f9f7	2285	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2286	the HAL_TIM_Encoder_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2287	*/
<>	144:ef7eb2e8f9f7	2288	}
<>	144:ef7eb2e8f9f7	2289
<>	144:ef7eb2e8f9f7	2290
<>	144:ef7eb2e8f9f7	2291	/**
<>	144:ef7eb2e8f9f7	2292	* @brief DeInitializes TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2293	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2294	* @retval None
<>	144:ef7eb2e8f9f7	2295	*/
<>	144:ef7eb2e8f9f7	2296	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2297	{
<>	144:ef7eb2e8f9f7	2298	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2299	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2300
<>	144:ef7eb2e8f9f7	2301	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2302	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2303	*/
<>	144:ef7eb2e8f9f7	2304	}
<>	144:ef7eb2e8f9f7	2305
<>	144:ef7eb2e8f9f7	2306	/**
<>	144:ef7eb2e8f9f7	2307	* @brief Starts the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2308	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2309	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2310	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2311	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2312	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2313	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2314	* @retval HAL status
<>	144:ef7eb2e8f9f7	2315	*/
<>	144:ef7eb2e8f9f7	2316	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2317	{
<>	144:ef7eb2e8f9f7	2318	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2319	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2320
<>	144:ef7eb2e8f9f7	2321	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2322	switch (Channel)
<>	144:ef7eb2e8f9f7	2323	{
<>	144:ef7eb2e8f9f7	2324	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2325	{
<>	144:ef7eb2e8f9f7	2326	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2327	break;
<>	144:ef7eb2e8f9f7	2328	}
<>	144:ef7eb2e8f9f7	2329	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2330	{
<>	144:ef7eb2e8f9f7	2331	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2332	break;
<>	144:ef7eb2e8f9f7	2333	}
<>	144:ef7eb2e8f9f7	2334	default :
<>	144:ef7eb2e8f9f7	2335	{
<>	144:ef7eb2e8f9f7	2336	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2337	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2338	break;
<>	144:ef7eb2e8f9f7	2339	}
<>	144:ef7eb2e8f9f7	2340	}
<>	144:ef7eb2e8f9f7	2341	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2342	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2343
<>	144:ef7eb2e8f9f7	2344	/* Return function status */
<>	144:ef7eb2e8f9f7	2345	return HAL_OK;
<>	144:ef7eb2e8f9f7	2346	}
<>	144:ef7eb2e8f9f7	2347
<>	144:ef7eb2e8f9f7	2348	/**
<>	144:ef7eb2e8f9f7	2349	* @brief Stops the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2350	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2351	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	2352	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2353	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2354	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2355	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2356	* @retval HAL status
<>	144:ef7eb2e8f9f7	2357	*/
<>	144:ef7eb2e8f9f7	2358	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2359	{
<>	144:ef7eb2e8f9f7	2360	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2361	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2362
<>	144:ef7eb2e8f9f7	2363	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2364	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2365	switch (Channel)
<>	144:ef7eb2e8f9f7	2366	{
<>	144:ef7eb2e8f9f7	2367	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2368	{
<>	144:ef7eb2e8f9f7	2369	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2370	break;
<>	144:ef7eb2e8f9f7	2371	}
<>	144:ef7eb2e8f9f7	2372	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2373	{
<>	144:ef7eb2e8f9f7	2374	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2375	break;
<>	144:ef7eb2e8f9f7	2376	}
<>	144:ef7eb2e8f9f7	2377	default :
<>	144:ef7eb2e8f9f7	2378	{
<>	144:ef7eb2e8f9f7	2379	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2380	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2381	break;
<>	144:ef7eb2e8f9f7	2382	}
<>	144:ef7eb2e8f9f7	2383	}
<>	144:ef7eb2e8f9f7	2384	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2385	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2386
<>	144:ef7eb2e8f9f7	2387	/* Return function status */
<>	144:ef7eb2e8f9f7	2388	return HAL_OK;
<>	144:ef7eb2e8f9f7	2389	}
<>	144:ef7eb2e8f9f7	2390
<>	144:ef7eb2e8f9f7	2391	/**
<>	144:ef7eb2e8f9f7	2392	* @brief Starts the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2393	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2394	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2395	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2396	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2397	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2398	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2399	* @retval HAL status
<>	144:ef7eb2e8f9f7	2400	*/
<>	144:ef7eb2e8f9f7	2401	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2402	{
<>	144:ef7eb2e8f9f7	2403	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2404	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2405
<>	144:ef7eb2e8f9f7	2406	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2407	/* Enable the capture compare Interrupts 1 and/or 2 */
<>	144:ef7eb2e8f9f7	2408	switch (Channel)
<>	144:ef7eb2e8f9f7	2409	{
<>	144:ef7eb2e8f9f7	2410	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2411	{
<>	144:ef7eb2e8f9f7	2412	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2413	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2414	break;
<>	144:ef7eb2e8f9f7	2415	}
<>	144:ef7eb2e8f9f7	2416	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2417	{
<>	144:ef7eb2e8f9f7	2418	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2419	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2420	break;
<>	144:ef7eb2e8f9f7	2421	}
<>	144:ef7eb2e8f9f7	2422	default :
<>	144:ef7eb2e8f9f7	2423	{
<>	144:ef7eb2e8f9f7	2424	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2425	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2426	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2427	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2428	break;
<>	144:ef7eb2e8f9f7	2429	}
<>	144:ef7eb2e8f9f7	2430	}
<>	144:ef7eb2e8f9f7	2431
<>	144:ef7eb2e8f9f7	2432	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2433	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2434
<>	144:ef7eb2e8f9f7	2435	/* Return function status */
<>	144:ef7eb2e8f9f7	2436	return HAL_OK;
<>	144:ef7eb2e8f9f7	2437	}
<>	144:ef7eb2e8f9f7	2438
<>	144:ef7eb2e8f9f7	2439	/**
<>	144:ef7eb2e8f9f7	2440	* @brief Stops the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2441	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2442	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	2443	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2444	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2445	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2446	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2447	* @retval HAL status
<>	144:ef7eb2e8f9f7	2448	*/
<>	144:ef7eb2e8f9f7	2449	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2450	{
<>	144:ef7eb2e8f9f7	2451	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2452	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2453
<>	144:ef7eb2e8f9f7	2454	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2455	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2456	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2457	{
<>	144:ef7eb2e8f9f7	2458	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2459
<>	144:ef7eb2e8f9f7	2460	/* Disable the capture compare Interrupts 1 */
<>	144:ef7eb2e8f9f7	2461	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2462	}
<>	144:ef7eb2e8f9f7	2463	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2464	{
<>	144:ef7eb2e8f9f7	2465	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2466
<>	144:ef7eb2e8f9f7	2467	/* Disable the capture compare Interrupts 2 */
<>	144:ef7eb2e8f9f7	2468	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2469	}
<>	144:ef7eb2e8f9f7	2470	else
<>	144:ef7eb2e8f9f7	2471	{
<>	144:ef7eb2e8f9f7	2472	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2473	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2474
<>	144:ef7eb2e8f9f7	2475	/* Disable the capture compare Interrupts 1 and 2 */
<>	144:ef7eb2e8f9f7	2476	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2477	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2478	}
<>	144:ef7eb2e8f9f7	2479
<>	144:ef7eb2e8f9f7	2480	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2481	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2482
<>	144:ef7eb2e8f9f7	2483	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2484	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2485
<>	144:ef7eb2e8f9f7	2486	/* Return function status */
<>	144:ef7eb2e8f9f7	2487	return HAL_OK;
<>	144:ef7eb2e8f9f7	2488	}
<>	144:ef7eb2e8f9f7	2489
<>	144:ef7eb2e8f9f7	2490	/**
<>	144:ef7eb2e8f9f7	2491	* @brief Starts the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2492	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2493	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2494	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2495	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2496	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2497	* @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected
<>	144:ef7eb2e8f9f7	2498	* @param pData1: The destination Buffer address for IC1.
<>	144:ef7eb2e8f9f7	2499	* @param pData2: The destination Buffer address for IC2.
<>	144:ef7eb2e8f9f7	2500	* @param Length: The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	2501	* @retval HAL status
<>	144:ef7eb2e8f9f7	2502	*/
<>	144:ef7eb2e8f9f7	2503	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
<>	144:ef7eb2e8f9f7	2504	{
<>	144:ef7eb2e8f9f7	2505	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2506	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2507
<>	144:ef7eb2e8f9f7	2508	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	2509	{
<>	144:ef7eb2e8f9f7	2510	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2511	}
<>	144:ef7eb2e8f9f7	2512	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	2513	{
<>	151:5eaa88a5bcc7	2514	if((((pData1 == 0U) \|\| (pData2 == 0U) )) && (Length > 0U))
<>	144:ef7eb2e8f9f7	2515	{
<>	144:ef7eb2e8f9f7	2516	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2517	}
<>	144:ef7eb2e8f9f7	2518	else
<>	144:ef7eb2e8f9f7	2519	{
<>	144:ef7eb2e8f9f7	2520	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2521	}
<>	144:ef7eb2e8f9f7	2522	}
<>	144:ef7eb2e8f9f7	2523
<>	144:ef7eb2e8f9f7	2524	switch (Channel)
<>	144:ef7eb2e8f9f7	2525	{
<>	144:ef7eb2e8f9f7	2526	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2527	{
<>	144:ef7eb2e8f9f7	2528	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2529	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2530
<>	144:ef7eb2e8f9f7	2531	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2532	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2533
<>	144:ef7eb2e8f9f7	2534	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2535	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<>	144:ef7eb2e8f9f7	2536
<>	144:ef7eb2e8f9f7	2537	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2538	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2539
<>	144:ef7eb2e8f9f7	2540	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2541	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2542
<>	144:ef7eb2e8f9f7	2543	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2544	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2545	}
<>	144:ef7eb2e8f9f7	2546	break;
<>	144:ef7eb2e8f9f7	2547
<>	144:ef7eb2e8f9f7	2548	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2549	{
<>	144:ef7eb2e8f9f7	2550	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2551	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2552
<>	144:ef7eb2e8f9f7	2553	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2554	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<>	144:ef7eb2e8f9f7	2555	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2556	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2557
<>	144:ef7eb2e8f9f7	2558	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2559	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2560
<>	144:ef7eb2e8f9f7	2561	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2562	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2563
<>	144:ef7eb2e8f9f7	2564	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2565	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2566	}
<>	144:ef7eb2e8f9f7	2567	break;
<>	144:ef7eb2e8f9f7	2568
<>	144:ef7eb2e8f9f7	2569	case TIM_CHANNEL_ALL:
<>	144:ef7eb2e8f9f7	2570	{
<>	144:ef7eb2e8f9f7	2571	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2572	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2573
<>	144:ef7eb2e8f9f7	2574	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2575	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2576
<>	144:ef7eb2e8f9f7	2577	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2578	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<>	144:ef7eb2e8f9f7	2579
<>	144:ef7eb2e8f9f7	2580	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2581	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2582
<>	144:ef7eb2e8f9f7	2583	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2584	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2585
<>	144:ef7eb2e8f9f7	2586	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2587	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2588
<>	144:ef7eb2e8f9f7	2589	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2590	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2591
<>	144:ef7eb2e8f9f7	2592	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2593	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2594	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2595
<>	144:ef7eb2e8f9f7	2596	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2597	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2598	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2599	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2600	}
<>	144:ef7eb2e8f9f7	2601	break;
<>	144:ef7eb2e8f9f7	2602
<>	144:ef7eb2e8f9f7	2603	default:
<>	144:ef7eb2e8f9f7	2604	break;
<>	144:ef7eb2e8f9f7	2605	}
<>	144:ef7eb2e8f9f7	2606	/* Return function status */
<>	144:ef7eb2e8f9f7	2607	return HAL_OK;
<>	144:ef7eb2e8f9f7	2608	}
<>	144:ef7eb2e8f9f7	2609
<>	144:ef7eb2e8f9f7	2610	/**
<>	144:ef7eb2e8f9f7	2611	* @brief Stops the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2612	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2613	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2614	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2615	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2616	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2617	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2618	* @retval HAL status
<>	144:ef7eb2e8f9f7	2619	*/
<>	144:ef7eb2e8f9f7	2620	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2621	{
<>	144:ef7eb2e8f9f7	2622	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2623	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2624
<>	144:ef7eb2e8f9f7	2625	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2626	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2627	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2628	{
<>	144:ef7eb2e8f9f7	2629	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2630
<>	144:ef7eb2e8f9f7	2631	/* Disable the capture compare DMA Request 1 */
<>	144:ef7eb2e8f9f7	2632	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2633	}
<>	144:ef7eb2e8f9f7	2634	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2635	{
<>	144:ef7eb2e8f9f7	2636	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2637
<>	144:ef7eb2e8f9f7	2638	/* Disable the capture compare DMA Request 2 */
<>	144:ef7eb2e8f9f7	2639	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2640	}
<>	144:ef7eb2e8f9f7	2641	else
<>	144:ef7eb2e8f9f7	2642	{
<>	144:ef7eb2e8f9f7	2643	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2644	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2645
<>	144:ef7eb2e8f9f7	2646	/* Disable the capture compare DMA Request 1 and 2 */
<>	144:ef7eb2e8f9f7	2647	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2648	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2649	}
<>	144:ef7eb2e8f9f7	2650
<>	144:ef7eb2e8f9f7	2651	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2652	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2653
<>	144:ef7eb2e8f9f7	2654	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2655	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2656
<>	144:ef7eb2e8f9f7	2657	/* Return function status */
<>	144:ef7eb2e8f9f7	2658	return HAL_OK;
<>	144:ef7eb2e8f9f7	2659	}
<>	144:ef7eb2e8f9f7	2660
<>	144:ef7eb2e8f9f7	2661	/**
<>	144:ef7eb2e8f9f7	2662	* @}
<>	144:ef7eb2e8f9f7	2663	*/
<>	144:ef7eb2e8f9f7	2664
<>	144:ef7eb2e8f9f7	2665	/** @addtogroup TIM_Exported_Functions_Group7
<>	144:ef7eb2e8f9f7	2666	* @brief IRQ handler management
<>	144:ef7eb2e8f9f7	2667	*
<>	144:ef7eb2e8f9f7	2668	@verbatim
<>	144:ef7eb2e8f9f7	2669	==============================================================================
<>	144:ef7eb2e8f9f7	2670	##### IRQ handler management #####
<>	144:ef7eb2e8f9f7	2671	==============================================================================
<>	144:ef7eb2e8f9f7	2672	[..]
<>	144:ef7eb2e8f9f7	2673	This section provides Timer IRQ handler function.
<>	144:ef7eb2e8f9f7	2674
<>	144:ef7eb2e8f9f7	2675	@endverbatim
<>	144:ef7eb2e8f9f7	2676	* @{
<>	144:ef7eb2e8f9f7	2677	*/
<>	144:ef7eb2e8f9f7	2678	/**
<>	144:ef7eb2e8f9f7	2679	* @brief This function handles TIM interrupts requests.
<>	144:ef7eb2e8f9f7	2680	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	2681	* @retval None
<>	144:ef7eb2e8f9f7	2682	*/
<>	144:ef7eb2e8f9f7	2683	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2684	{
<>	144:ef7eb2e8f9f7	2685	/* Capture compare 1 event */
<>	144:ef7eb2e8f9f7	2686	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<>	144:ef7eb2e8f9f7	2687	{
<>	144:ef7eb2e8f9f7	2688	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<>	144:ef7eb2e8f9f7	2689	{
<>	144:ef7eb2e8f9f7	2690	{
<>	144:ef7eb2e8f9f7	2691	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2692	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	2693
<>	144:ef7eb2e8f9f7	2694	/* Input capture event */
<>	151:5eaa88a5bcc7	2695	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
<>	144:ef7eb2e8f9f7	2696	{
<>	144:ef7eb2e8f9f7	2697	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2698	}
<>	144:ef7eb2e8f9f7	2699	/* Output compare event */
<>	144:ef7eb2e8f9f7	2700	else
<>	144:ef7eb2e8f9f7	2701	{
<>	144:ef7eb2e8f9f7	2702	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2703	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2704	}
<>	144:ef7eb2e8f9f7	2705	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2706	}
<>	144:ef7eb2e8f9f7	2707	}
<>	144:ef7eb2e8f9f7	2708	}
<>	144:ef7eb2e8f9f7	2709	/* Capture compare 2 event */
<>	144:ef7eb2e8f9f7	2710	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<>	144:ef7eb2e8f9f7	2711	{
<>	144:ef7eb2e8f9f7	2712	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<>	144:ef7eb2e8f9f7	2713	{
<>	144:ef7eb2e8f9f7	2714	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2715	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	2716	/* Input capture event */
<>	151:5eaa88a5bcc7	2717	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
<>	144:ef7eb2e8f9f7	2718	{
<>	144:ef7eb2e8f9f7	2719	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2720	}
<>	144:ef7eb2e8f9f7	2721	/* Output compare event */
<>	144:ef7eb2e8f9f7	2722	else
<>	144:ef7eb2e8f9f7	2723	{
<>	144:ef7eb2e8f9f7	2724	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2725	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2726	}
<>	144:ef7eb2e8f9f7	2727	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2728	}
<>	144:ef7eb2e8f9f7	2729	}
<>	144:ef7eb2e8f9f7	2730	/* Capture compare 3 event */
<>	144:ef7eb2e8f9f7	2731	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<>	144:ef7eb2e8f9f7	2732	{
<>	144:ef7eb2e8f9f7	2733	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<>	144:ef7eb2e8f9f7	2734	{
<>	144:ef7eb2e8f9f7	2735	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	2736	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	2737	/* Input capture event */
<>	151:5eaa88a5bcc7	2738	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
<>	144:ef7eb2e8f9f7	2739	{
<>	144:ef7eb2e8f9f7	2740	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2741	}
<>	144:ef7eb2e8f9f7	2742	/* Output compare event */
<>	144:ef7eb2e8f9f7	2743	else
<>	144:ef7eb2e8f9f7	2744	{
<>	144:ef7eb2e8f9f7	2745	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2746	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2747	}
<>	144:ef7eb2e8f9f7	2748	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2749	}
<>	144:ef7eb2e8f9f7	2750	}
<>	144:ef7eb2e8f9f7	2751	/* Capture compare 4 event */
<>	144:ef7eb2e8f9f7	2752	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<>	144:ef7eb2e8f9f7	2753	{
<>	144:ef7eb2e8f9f7	2754	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<>	144:ef7eb2e8f9f7	2755	{
<>	144:ef7eb2e8f9f7	2756	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	2757	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	2758	/* Input capture event */
<>	151:5eaa88a5bcc7	2759	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
<>	144:ef7eb2e8f9f7	2760	{
<>	144:ef7eb2e8f9f7	2761	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2762	}
<>	144:ef7eb2e8f9f7	2763	/* Output compare event */
<>	144:ef7eb2e8f9f7	2764	else
<>	144:ef7eb2e8f9f7	2765	{
<>	144:ef7eb2e8f9f7	2766	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2767	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2768	}
<>	144:ef7eb2e8f9f7	2769	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2770	}
<>	144:ef7eb2e8f9f7	2771	}
<>	144:ef7eb2e8f9f7	2772	/* TIM Update event */
<>	144:ef7eb2e8f9f7	2773	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<>	144:ef7eb2e8f9f7	2774	{
<>	144:ef7eb2e8f9f7	2775	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<>	144:ef7eb2e8f9f7	2776	{
<>	144:ef7eb2e8f9f7	2777	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	2778	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2779	}
<>	144:ef7eb2e8f9f7	2780	}
<>	144:ef7eb2e8f9f7	2781	/* TIM Trigger detection event */
<>	144:ef7eb2e8f9f7	2782	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<>	144:ef7eb2e8f9f7	2783	{
<>	144:ef7eb2e8f9f7	2784	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<>	144:ef7eb2e8f9f7	2785	{
<>	144:ef7eb2e8f9f7	2786	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	2787	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	2788	}
<>	144:ef7eb2e8f9f7	2789	}
<>	144:ef7eb2e8f9f7	2790	}
<>	144:ef7eb2e8f9f7	2791
<>	144:ef7eb2e8f9f7	2792	/**
<>	144:ef7eb2e8f9f7	2793	* @}
<>	144:ef7eb2e8f9f7	2794	*/
<>	144:ef7eb2e8f9f7	2795
<>	144:ef7eb2e8f9f7	2796	/** @addtogroup TIM_Exported_Functions_Group8
<>	144:ef7eb2e8f9f7	2797	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	2798	*
<>	144:ef7eb2e8f9f7	2799	@verbatim
<>	144:ef7eb2e8f9f7	2800	==============================================================================
<>	144:ef7eb2e8f9f7	2801	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	2802	==============================================================================
<>	144:ef7eb2e8f9f7	2803	[..]
<>	144:ef7eb2e8f9f7	2804	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2805	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<>	144:ef7eb2e8f9f7	2806	(+) Configure External Clock source.
<>	144:ef7eb2e8f9f7	2807	(+) Configure Master and the Slave synchronization.
<>	144:ef7eb2e8f9f7	2808	(+) Configure the DMA Burst Mode.
<>	144:ef7eb2e8f9f7	2809
<>	144:ef7eb2e8f9f7	2810	@endverbatim
<>	144:ef7eb2e8f9f7	2811	* @{
<>	144:ef7eb2e8f9f7	2812	*/
<>	144:ef7eb2e8f9f7	2813	/**
<>	144:ef7eb2e8f9f7	2814	* @brief Initializes the TIM Output Compare Channels according to the specified
<>	144:ef7eb2e8f9f7	2815	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2816	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2817	* @param sConfig: TIM Output Compare configuration structure
<>	151:5eaa88a5bcc7	2818	* @param Channel: TIM Channel to be configure.
<>	144:ef7eb2e8f9f7	2819	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2820	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2821	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2822	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2823	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	2824	* @retval HAL status
<>	144:ef7eb2e8f9f7	2825	*/
<>	144:ef7eb2e8f9f7	2826	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2827	{
<>	144:ef7eb2e8f9f7	2828	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2829	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	2830	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	2831	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	2832
<>	151:5eaa88a5bcc7	2833	/* Process lock */
<>	144:ef7eb2e8f9f7	2834	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2835
<>	144:ef7eb2e8f9f7	2836	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2837
<>	144:ef7eb2e8f9f7	2838	switch (Channel)
<>	144:ef7eb2e8f9f7	2839	{
<>	144:ef7eb2e8f9f7	2840	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2841	{
<>	144:ef7eb2e8f9f7	2842	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2843	/* Configure the TIM Channel 1 in Output Compare */
<>	144:ef7eb2e8f9f7	2844	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2845	}
<>	144:ef7eb2e8f9f7	2846	break;
<>	144:ef7eb2e8f9f7	2847
<>	144:ef7eb2e8f9f7	2848	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2849	{
<>	144:ef7eb2e8f9f7	2850	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2851	/* Configure the TIM Channel 2 in Output Compare */
<>	144:ef7eb2e8f9f7	2852	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2853	}
<>	144:ef7eb2e8f9f7	2854	break;
<>	144:ef7eb2e8f9f7	2855
<>	144:ef7eb2e8f9f7	2856	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	2857	{
<>	144:ef7eb2e8f9f7	2858	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2859	/* Configure the TIM Channel 3 in Output Compare */
<>	144:ef7eb2e8f9f7	2860	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2861	}
<>	144:ef7eb2e8f9f7	2862	break;
<>	144:ef7eb2e8f9f7	2863
<>	144:ef7eb2e8f9f7	2864	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	2865	{
<>	144:ef7eb2e8f9f7	2866	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2867	/* Configure the TIM Channel 4 in Output Compare */
<>	144:ef7eb2e8f9f7	2868	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2869	}
<>	144:ef7eb2e8f9f7	2870	break;
<>	144:ef7eb2e8f9f7	2871
<>	144:ef7eb2e8f9f7	2872	default:
<>	144:ef7eb2e8f9f7	2873	break;
<>	144:ef7eb2e8f9f7	2874	}
<>	144:ef7eb2e8f9f7	2875	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2876
<>	144:ef7eb2e8f9f7	2877	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2878
<>	144:ef7eb2e8f9f7	2879	return HAL_OK;
<>	144:ef7eb2e8f9f7	2880	}
<>	144:ef7eb2e8f9f7	2881
<>	144:ef7eb2e8f9f7	2882	/**
<>	144:ef7eb2e8f9f7	2883	* @brief Initializes the TIM Input Capture Channels according to the specified
<>	144:ef7eb2e8f9f7	2884	* parameters in the TIM_IC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2885	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2886	* @param sConfig: TIM Input Capture configuration structure
<>	144:ef7eb2e8f9f7	2887	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2888	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2889	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2890	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2891	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2892	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	2893	* @retval HAL status
<>	144:ef7eb2e8f9f7	2894	*/
<>	144:ef7eb2e8f9f7	2895	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2896	{
<>	144:ef7eb2e8f9f7	2897	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2898	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2899	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<>	144:ef7eb2e8f9f7	2900	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<>	144:ef7eb2e8f9f7	2901	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<>	144:ef7eb2e8f9f7	2902	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<>	144:ef7eb2e8f9f7	2903
<>	144:ef7eb2e8f9f7	2904	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2905
<>	144:ef7eb2e8f9f7	2906	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2907
<>	144:ef7eb2e8f9f7	2908	if (Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2909	{
<>	144:ef7eb2e8f9f7	2910	/* TI1 Configuration */
<>	144:ef7eb2e8f9f7	2911	TIM_TI1_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	2912	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	2913	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	2914	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	2915
<>	144:ef7eb2e8f9f7	2916	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	2917	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	2918
<>	144:ef7eb2e8f9f7	2919	/* Set the IC1PSC value */
<>	144:ef7eb2e8f9f7	2920	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	2921	}
<>	144:ef7eb2e8f9f7	2922	else if (Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2923	{
<>	144:ef7eb2e8f9f7	2924	/* TI2 Configuration */
<>	144:ef7eb2e8f9f7	2925	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2926
<>	144:ef7eb2e8f9f7	2927	TIM_TI2_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	2928	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	2929	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	2930	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	2931
<>	144:ef7eb2e8f9f7	2932	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	2933	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	2934
<>	144:ef7eb2e8f9f7	2935	/* Set the IC2PSC value */
<>	151:5eaa88a5bcc7	2936	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8U);
<>	144:ef7eb2e8f9f7	2937	}
<>	144:ef7eb2e8f9f7	2938	else if (Channel == TIM_CHANNEL_3)
<>	144:ef7eb2e8f9f7	2939	{
<>	144:ef7eb2e8f9f7	2940	/* TI3 Configuration */
<>	144:ef7eb2e8f9f7	2941	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2942
<>	144:ef7eb2e8f9f7	2943	TIM_TI3_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	2944	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	2945	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	2946	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	2947
<>	144:ef7eb2e8f9f7	2948	/* Reset the IC3PSC Bits */
<>	144:ef7eb2e8f9f7	2949	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<>	144:ef7eb2e8f9f7	2950
<>	144:ef7eb2e8f9f7	2951	/* Set the IC3PSC value */
<>	144:ef7eb2e8f9f7	2952	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	2953	}
<>	144:ef7eb2e8f9f7	2954	else
<>	144:ef7eb2e8f9f7	2955	{
<>	144:ef7eb2e8f9f7	2956	/* TI4 Configuration */
<>	144:ef7eb2e8f9f7	2957	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2958
<>	144:ef7eb2e8f9f7	2959	TIM_TI4_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	2960	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	2961	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	2962	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	2963
<>	144:ef7eb2e8f9f7	2964	/* Reset the IC4PSC Bits */
<>	144:ef7eb2e8f9f7	2965	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<>	144:ef7eb2e8f9f7	2966
<>	144:ef7eb2e8f9f7	2967	/* Set the IC4PSC value */
<>	151:5eaa88a5bcc7	2968	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8U);
<>	144:ef7eb2e8f9f7	2969	}
<>	144:ef7eb2e8f9f7	2970
<>	144:ef7eb2e8f9f7	2971	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2972
<>	144:ef7eb2e8f9f7	2973	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2974
<>	144:ef7eb2e8f9f7	2975	return HAL_OK;
<>	144:ef7eb2e8f9f7	2976	}
<>	144:ef7eb2e8f9f7	2977
<>	144:ef7eb2e8f9f7	2978	/**
<>	144:ef7eb2e8f9f7	2979	* @brief Initializes the TIM PWM channels according to the specified
<>	144:ef7eb2e8f9f7	2980	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2981	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2982	* @param sConfig: TIM PWM configuration structure
<>	151:5eaa88a5bcc7	2983	* @param Channel: TIM Channel to be configured.
<>	144:ef7eb2e8f9f7	2984	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2985	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2986	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2987	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2988	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	2989	* @retval HAL status
<>	144:ef7eb2e8f9f7	2990	*/
<>	144:ef7eb2e8f9f7	2991	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2992	{
<>	144:ef7eb2e8f9f7	2993	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2994
<>	144:ef7eb2e8f9f7	2995	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2996	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	2997	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	2998	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	2999	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<>	144:ef7eb2e8f9f7	3000
<>	144:ef7eb2e8f9f7	3001	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3002
<>	144:ef7eb2e8f9f7	3003	switch (Channel)
<>	144:ef7eb2e8f9f7	3004	{
<>	144:ef7eb2e8f9f7	3005	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3006	{
<>	144:ef7eb2e8f9f7	3007	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3008	/* Configure the Channel 1 in PWM mode */
<>	144:ef7eb2e8f9f7	3009	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3010
<>	144:ef7eb2e8f9f7	3011	/* Set the Preload enable bit for channel1 */
<>	144:ef7eb2e8f9f7	3012	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
<>	144:ef7eb2e8f9f7	3013
<>	144:ef7eb2e8f9f7	3014	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3015	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<>	144:ef7eb2e8f9f7	3016	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3017	}
<>	144:ef7eb2e8f9f7	3018	break;
<>	144:ef7eb2e8f9f7	3019
<>	144:ef7eb2e8f9f7	3020	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3021	{
<>	144:ef7eb2e8f9f7	3022	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3023	/* Configure the Channel 2 in PWM mode */
<>	144:ef7eb2e8f9f7	3024	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3025
<>	144:ef7eb2e8f9f7	3026	/* Set the Preload enable bit for channel2 */
<>	144:ef7eb2e8f9f7	3027	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
<>	144:ef7eb2e8f9f7	3028
<>	144:ef7eb2e8f9f7	3029	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3030	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<>	151:5eaa88a5bcc7	3031	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8U;
<>	144:ef7eb2e8f9f7	3032	}
<>	144:ef7eb2e8f9f7	3033	break;
<>	144:ef7eb2e8f9f7	3034
<>	144:ef7eb2e8f9f7	3035	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3036	{
<>	144:ef7eb2e8f9f7	3037	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3038	/* Configure the Channel 3 in PWM mode */
<>	144:ef7eb2e8f9f7	3039	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3040
<>	144:ef7eb2e8f9f7	3041	/* Set the Preload enable bit for channel3 */
<>	144:ef7eb2e8f9f7	3042	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
<>	144:ef7eb2e8f9f7	3043
<>	144:ef7eb2e8f9f7	3044	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3045	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<>	144:ef7eb2e8f9f7	3046	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3047	}
<>	144:ef7eb2e8f9f7	3048	break;
<>	144:ef7eb2e8f9f7	3049
<>	144:ef7eb2e8f9f7	3050	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3051	{
<>	144:ef7eb2e8f9f7	3052	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3053	/* Configure the Channel 4 in PWM mode */
<>	144:ef7eb2e8f9f7	3054	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3055
<>	144:ef7eb2e8f9f7	3056	/* Set the Preload enable bit for channel4 */
<>	144:ef7eb2e8f9f7	3057	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
<>	144:ef7eb2e8f9f7	3058
<>	144:ef7eb2e8f9f7	3059	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3060	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<>	151:5eaa88a5bcc7	3061	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8U;
<>	144:ef7eb2e8f9f7	3062	}
<>	144:ef7eb2e8f9f7	3063	break;
<>	144:ef7eb2e8f9f7	3064
<>	144:ef7eb2e8f9f7	3065	default:
<>	144:ef7eb2e8f9f7	3066	break;
<>	144:ef7eb2e8f9f7	3067	}
<>	144:ef7eb2e8f9f7	3068
<>	144:ef7eb2e8f9f7	3069	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3070
<>	144:ef7eb2e8f9f7	3071	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3072
<>	144:ef7eb2e8f9f7	3073	return HAL_OK;
<>	144:ef7eb2e8f9f7	3074	}
<>	144:ef7eb2e8f9f7	3075
<>	144:ef7eb2e8f9f7	3076	/**
<>	144:ef7eb2e8f9f7	3077	* @brief Initializes the TIM One Pulse Channels according to the specified
<>	144:ef7eb2e8f9f7	3078	* parameters in the TIM_OnePulse_InitTypeDef.
<>	144:ef7eb2e8f9f7	3079	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3080	* @param sConfig: TIM One Pulse configuration structure
<>	144:ef7eb2e8f9f7	3081	* @param OutputChannel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	3082	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3083	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3084	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3085	* @param InputChannel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	3086	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3087	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3088	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3089	* @retval HAL status
<>	144:ef7eb2e8f9f7	3090	*/
<>	144:ef7eb2e8f9f7	3091	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<>	144:ef7eb2e8f9f7	3092	{
<>	144:ef7eb2e8f9f7	3093	TIM_OC_InitTypeDef temp1;
<>	144:ef7eb2e8f9f7	3094
<>	144:ef7eb2e8f9f7	3095	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3096	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<>	144:ef7eb2e8f9f7	3097	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<>	144:ef7eb2e8f9f7	3098
<>	144:ef7eb2e8f9f7	3099	if(OutputChannel != InputChannel)
<>	144:ef7eb2e8f9f7	3100	{
<>	144:ef7eb2e8f9f7	3101	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3102
<>	144:ef7eb2e8f9f7	3103	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3104
<>	144:ef7eb2e8f9f7	3105	/* Extract the Ouput compare configuration from sConfig structure */
<>	144:ef7eb2e8f9f7	3106	temp1.OCMode = sConfig->OCMode;
<>	144:ef7eb2e8f9f7	3107	temp1.Pulse = sConfig->Pulse;
<>	144:ef7eb2e8f9f7	3108	temp1.OCPolarity = sConfig->OCPolarity;
<>	144:ef7eb2e8f9f7	3109
<>	144:ef7eb2e8f9f7	3110	switch (OutputChannel)
<>	144:ef7eb2e8f9f7	3111	{
<>	144:ef7eb2e8f9f7	3112	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3113	{
<>	144:ef7eb2e8f9f7	3114	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3115
<>	144:ef7eb2e8f9f7	3116	TIM_OC1_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3117	}
<>	144:ef7eb2e8f9f7	3118	break;
<>	144:ef7eb2e8f9f7	3119	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3120	{
<>	144:ef7eb2e8f9f7	3121	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3122
<>	144:ef7eb2e8f9f7	3123	TIM_OC2_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3124	}
<>	144:ef7eb2e8f9f7	3125	break;
<>	144:ef7eb2e8f9f7	3126	default:
<>	144:ef7eb2e8f9f7	3127	break;
<>	144:ef7eb2e8f9f7	3128	}
<>	144:ef7eb2e8f9f7	3129	switch (InputChannel)
<>	144:ef7eb2e8f9f7	3130	{
<>	144:ef7eb2e8f9f7	3131	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3132	{
<>	144:ef7eb2e8f9f7	3133	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3134
<>	144:ef7eb2e8f9f7	3135	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3136	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3137
<>	144:ef7eb2e8f9f7	3138	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	3139	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	3140
<>	144:ef7eb2e8f9f7	3141	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3142	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3143	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
<>	144:ef7eb2e8f9f7	3144
<>	144:ef7eb2e8f9f7	3145	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3146	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3147	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3148	}
<>	144:ef7eb2e8f9f7	3149	break;
<>	144:ef7eb2e8f9f7	3150	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3151	{
<>	144:ef7eb2e8f9f7	3152	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3153
<>	144:ef7eb2e8f9f7	3154	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3155	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3156
<>	144:ef7eb2e8f9f7	3157	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	3158	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	3159
<>	144:ef7eb2e8f9f7	3160	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3161	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3162	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
<>	144:ef7eb2e8f9f7	3163
<>	144:ef7eb2e8f9f7	3164	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3165	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3166	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3167	}
<>	144:ef7eb2e8f9f7	3168	break;
<>	144:ef7eb2e8f9f7	3169
<>	144:ef7eb2e8f9f7	3170	default:
<>	144:ef7eb2e8f9f7	3171	break;
<>	144:ef7eb2e8f9f7	3172	}
<>	144:ef7eb2e8f9f7	3173
<>	144:ef7eb2e8f9f7	3174	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3175
<>	144:ef7eb2e8f9f7	3176	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3177
<>	144:ef7eb2e8f9f7	3178	return HAL_OK;
<>	144:ef7eb2e8f9f7	3179	}
<>	144:ef7eb2e8f9f7	3180	else
<>	144:ef7eb2e8f9f7	3181	{
<>	144:ef7eb2e8f9f7	3182	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3183	}
<>	144:ef7eb2e8f9f7	3184	}
<>	144:ef7eb2e8f9f7	3185
<>	144:ef7eb2e8f9f7	3186	/**
<>	144:ef7eb2e8f9f7	3187	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<>	144:ef7eb2e8f9f7	3188	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3189	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
<>	144:ef7eb2e8f9f7	3190	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3191	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3192	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3193	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3194	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3195	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3196	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3197	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3198	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3199	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3200	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3201	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3202	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3203	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3204	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3205	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3206	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3207	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3208	* @param BurstRequestSrc: TIM DMA Request sources.
<>	144:ef7eb2e8f9f7	3209	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3210	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3211	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3212	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3213	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3214	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3215	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3216	* @param BurstBuffer: The Buffer address.
<>	144:ef7eb2e8f9f7	3217	* @param BurstLength: DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3218	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
<>	144:ef7eb2e8f9f7	3219	* @retval HAL status
<>	144:ef7eb2e8f9f7	3220	*/
<>	144:ef7eb2e8f9f7	3221	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3222	uint32_t* BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3223	{
<>	144:ef7eb2e8f9f7	3224	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3225	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3226	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3227	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3228	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3229
<>	144:ef7eb2e8f9f7	3230	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3231	{
<>	144:ef7eb2e8f9f7	3232	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3233	}
<>	144:ef7eb2e8f9f7	3234	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3235	{
<>	151:5eaa88a5bcc7	3236	if((BurstBuffer == 0U ) && (BurstLength > 0U))
<>	144:ef7eb2e8f9f7	3237	{
<>	144:ef7eb2e8f9f7	3238	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3239	}
<>	144:ef7eb2e8f9f7	3240	else
<>	144:ef7eb2e8f9f7	3241	{
<>	144:ef7eb2e8f9f7	3242	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3243	}
<>	144:ef7eb2e8f9f7	3244	}
<>	144:ef7eb2e8f9f7	3245	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3246	{
<>	144:ef7eb2e8f9f7	3247	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3248	{
<>	144:ef7eb2e8f9f7	3249	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3250	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3251
<>	144:ef7eb2e8f9f7	3252	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3253	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3254
<>	144:ef7eb2e8f9f7	3255	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3256	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3257	}
<>	144:ef7eb2e8f9f7	3258	break;
<>	144:ef7eb2e8f9f7	3259	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3260	{
<>	144:ef7eb2e8f9f7	3261	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3262	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3263
<>	144:ef7eb2e8f9f7	3264	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3265	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3266
<>	144:ef7eb2e8f9f7	3267	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3268	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3269	}
<>	144:ef7eb2e8f9f7	3270	break;
<>	144:ef7eb2e8f9f7	3271	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3272	{
<>	144:ef7eb2e8f9f7	3273	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3274	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3275
<>	144:ef7eb2e8f9f7	3276	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3277	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3278
<>	144:ef7eb2e8f9f7	3279	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3280	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3281	}
<>	144:ef7eb2e8f9f7	3282	break;
<>	144:ef7eb2e8f9f7	3283	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3284	{
<>	144:ef7eb2e8f9f7	3285	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3286	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3287
<>	144:ef7eb2e8f9f7	3288	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3289	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3290
<>	144:ef7eb2e8f9f7	3291	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3292	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3293	}
<>	144:ef7eb2e8f9f7	3294	break;
<>	144:ef7eb2e8f9f7	3295	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3296	{
<>	144:ef7eb2e8f9f7	3297	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3298	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3299
<>	144:ef7eb2e8f9f7	3300	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3301	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3302
<>	144:ef7eb2e8f9f7	3303	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3304	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3305	}
<>	144:ef7eb2e8f9f7	3306	break;
<>	144:ef7eb2e8f9f7	3307	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3308	{
<>	144:ef7eb2e8f9f7	3309	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3310	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3311
<>	144:ef7eb2e8f9f7	3312	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3313	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3314
<>	144:ef7eb2e8f9f7	3315	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3316	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3317	}
<>	144:ef7eb2e8f9f7	3318	break;
<>	144:ef7eb2e8f9f7	3319	default:
<>	144:ef7eb2e8f9f7	3320	break;
<>	144:ef7eb2e8f9f7	3321	}
<>	144:ef7eb2e8f9f7	3322	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3323	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3324
<>	144:ef7eb2e8f9f7	3325	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3326	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3327
<>	144:ef7eb2e8f9f7	3328	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3329
<>	144:ef7eb2e8f9f7	3330	/* Return function status */
<>	144:ef7eb2e8f9f7	3331	return HAL_OK;
<>	144:ef7eb2e8f9f7	3332	}
<>	144:ef7eb2e8f9f7	3333
<>	144:ef7eb2e8f9f7	3334	/**
<>	144:ef7eb2e8f9f7	3335	* @brief Stops the TIM DMA Burst mode
<>	144:ef7eb2e8f9f7	3336	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3337	* @param BurstRequestSrc: TIM DMA Request sources to disable
<>	144:ef7eb2e8f9f7	3338	* @retval HAL status
<>	144:ef7eb2e8f9f7	3339	*/
<>	144:ef7eb2e8f9f7	3340	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3341	{
<>	144:ef7eb2e8f9f7	3342	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3343	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3344
<>	144:ef7eb2e8f9f7	3345	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3346	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3347	{
<>	144:ef7eb2e8f9f7	3348	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3349	{
<>	144:ef7eb2e8f9f7	3350	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3351	}
<>	144:ef7eb2e8f9f7	3352	break;
<>	144:ef7eb2e8f9f7	3353	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3354	{
<>	144:ef7eb2e8f9f7	3355	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3356	}
<>	144:ef7eb2e8f9f7	3357	break;
<>	144:ef7eb2e8f9f7	3358	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3359	{
<>	144:ef7eb2e8f9f7	3360	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3361	}
<>	144:ef7eb2e8f9f7	3362	break;
<>	144:ef7eb2e8f9f7	3363	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3364	{
<>	144:ef7eb2e8f9f7	3365	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3366	}
<>	144:ef7eb2e8f9f7	3367	break;
<>	144:ef7eb2e8f9f7	3368	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3369	{
<>	144:ef7eb2e8f9f7	3370	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3371	}
<>	144:ef7eb2e8f9f7	3372	break;
<>	144:ef7eb2e8f9f7	3373	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3374	{
<>	144:ef7eb2e8f9f7	3375	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3376	}
<>	144:ef7eb2e8f9f7	3377	break;
<>	144:ef7eb2e8f9f7	3378	default:
<>	144:ef7eb2e8f9f7	3379	break;
<>	144:ef7eb2e8f9f7	3380	}
<>	144:ef7eb2e8f9f7	3381	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3382	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3383
<>	144:ef7eb2e8f9f7	3384	/* Return function status */
<>	144:ef7eb2e8f9f7	3385	return HAL_OK;
<>	144:ef7eb2e8f9f7	3386	}
<>	144:ef7eb2e8f9f7	3387
<>	144:ef7eb2e8f9f7	3388	/**
<>	144:ef7eb2e8f9f7	3389	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<>	144:ef7eb2e8f9f7	3390	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3391	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
<>	144:ef7eb2e8f9f7	3392	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3393	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3394	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3395	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3396	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3397	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3398	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3399	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3400	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3401	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3402	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3403	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3404	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3405	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3406	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3407	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3408	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3409	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3410	* @param BurstRequestSrc: TIM DMA Request sources.
<>	144:ef7eb2e8f9f7	3411	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3412	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3413	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3414	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3415	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3416	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3417	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3418	* @param BurstBuffer: The Buffer address.
<>	144:ef7eb2e8f9f7	3419	* @param BurstLength: DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3420	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
<>	144:ef7eb2e8f9f7	3421	* @retval HAL status
<>	144:ef7eb2e8f9f7	3422	*/
<>	144:ef7eb2e8f9f7	3423	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3424	uint32_t *BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3425	{
<>	144:ef7eb2e8f9f7	3426	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3427	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3428	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3429	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3430	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3431
<>	144:ef7eb2e8f9f7	3432	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3433	{
<>	144:ef7eb2e8f9f7	3434	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3435	}
<>	144:ef7eb2e8f9f7	3436	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3437	{
<>	151:5eaa88a5bcc7	3438	if((BurstBuffer == 0U ) && (BurstLength > 0U))
<>	144:ef7eb2e8f9f7	3439	{
<>	144:ef7eb2e8f9f7	3440	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3441	}
<>	144:ef7eb2e8f9f7	3442	else
<>	144:ef7eb2e8f9f7	3443	{
<>	144:ef7eb2e8f9f7	3444	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3445	}
<>	144:ef7eb2e8f9f7	3446	}
<>	144:ef7eb2e8f9f7	3447	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3448	{
<>	144:ef7eb2e8f9f7	3449	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3450	{
<>	144:ef7eb2e8f9f7	3451	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3452	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3453
<>	144:ef7eb2e8f9f7	3454	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3455	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3456
<>	144:ef7eb2e8f9f7	3457	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3458	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3459	}
<>	144:ef7eb2e8f9f7	3460	break;
<>	144:ef7eb2e8f9f7	3461	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3462	{
<>	144:ef7eb2e8f9f7	3463	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3464	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3465
<>	144:ef7eb2e8f9f7	3466	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3467	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3468
<>	144:ef7eb2e8f9f7	3469	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3470	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3471	}
<>	144:ef7eb2e8f9f7	3472	break;
<>	144:ef7eb2e8f9f7	3473	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3474	{
<>	144:ef7eb2e8f9f7	3475	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3476	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3477
<>	144:ef7eb2e8f9f7	3478	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3479	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3480
<>	144:ef7eb2e8f9f7	3481	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3482	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3483	}
<>	144:ef7eb2e8f9f7	3484	break;
<>	144:ef7eb2e8f9f7	3485	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3486	{
<>	144:ef7eb2e8f9f7	3487	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3488	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3489
<>	144:ef7eb2e8f9f7	3490	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3491	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3492
<>	144:ef7eb2e8f9f7	3493	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3494	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3495	}
<>	144:ef7eb2e8f9f7	3496	break;
<>	144:ef7eb2e8f9f7	3497	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3498	{
<>	144:ef7eb2e8f9f7	3499	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3500	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3501
<>	144:ef7eb2e8f9f7	3502	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3503	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3504
<>	144:ef7eb2e8f9f7	3505	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3506	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3507	}
<>	144:ef7eb2e8f9f7	3508	break;
<>	144:ef7eb2e8f9f7	3509	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3510	{
<>	144:ef7eb2e8f9f7	3511	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3512	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3513
<>	144:ef7eb2e8f9f7	3514	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3515	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3516
<>	144:ef7eb2e8f9f7	3517	/* Enable the DMA Stream */
<>	151:5eaa88a5bcc7	3518	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3519	}
<>	144:ef7eb2e8f9f7	3520	break;
<>	144:ef7eb2e8f9f7	3521	default:
<>	144:ef7eb2e8f9f7	3522	break;
<>	144:ef7eb2e8f9f7	3523	}
<>	144:ef7eb2e8f9f7	3524
<>	144:ef7eb2e8f9f7	3525	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3526	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3527
<>	144:ef7eb2e8f9f7	3528	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3529	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3530
<>	144:ef7eb2e8f9f7	3531	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3532
<>	144:ef7eb2e8f9f7	3533	/* Return function status */
<>	144:ef7eb2e8f9f7	3534	return HAL_OK;
<>	144:ef7eb2e8f9f7	3535	}
<>	144:ef7eb2e8f9f7	3536
<>	144:ef7eb2e8f9f7	3537	/**
<>	144:ef7eb2e8f9f7	3538	* @brief Stop the DMA burst reading
<>	144:ef7eb2e8f9f7	3539	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3540	* @param BurstRequestSrc: TIM DMA Request sources to disable.
<>	144:ef7eb2e8f9f7	3541	* @retval HAL status
<>	144:ef7eb2e8f9f7	3542	*/
<>	144:ef7eb2e8f9f7	3543	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3544	{
<>	144:ef7eb2e8f9f7	3545	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3546	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3547
<>	144:ef7eb2e8f9f7	3548	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3549	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3550	{
<>	144:ef7eb2e8f9f7	3551	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3552	{
<>	144:ef7eb2e8f9f7	3553	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3554	}
<>	144:ef7eb2e8f9f7	3555	break;
<>	144:ef7eb2e8f9f7	3556	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3557	{
<>	144:ef7eb2e8f9f7	3558	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3559	}
<>	144:ef7eb2e8f9f7	3560	break;
<>	144:ef7eb2e8f9f7	3561	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3562	{
<>	144:ef7eb2e8f9f7	3563	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3564	}
<>	144:ef7eb2e8f9f7	3565	break;
<>	144:ef7eb2e8f9f7	3566	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3567	{
<>	144:ef7eb2e8f9f7	3568	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3569	}
<>	144:ef7eb2e8f9f7	3570	break;
<>	144:ef7eb2e8f9f7	3571	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3572	{
<>	144:ef7eb2e8f9f7	3573	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3574	}
<>	144:ef7eb2e8f9f7	3575	break;
<>	144:ef7eb2e8f9f7	3576	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3577	{
<>	144:ef7eb2e8f9f7	3578	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3579	}
<>	144:ef7eb2e8f9f7	3580	break;
<>	144:ef7eb2e8f9f7	3581	default:
<>	144:ef7eb2e8f9f7	3582	break;
<>	144:ef7eb2e8f9f7	3583	}
<>	144:ef7eb2e8f9f7	3584
<>	144:ef7eb2e8f9f7	3585	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3586	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3587
<>	144:ef7eb2e8f9f7	3588	/* Return function status */
<>	144:ef7eb2e8f9f7	3589	return HAL_OK;
<>	144:ef7eb2e8f9f7	3590	}
<>	144:ef7eb2e8f9f7	3591
<>	144:ef7eb2e8f9f7	3592	/**
<>	144:ef7eb2e8f9f7	3593	* @brief Generate a software event
<>	144:ef7eb2e8f9f7	3594	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3595	* @param EventSource: specifies the event source.
<>	144:ef7eb2e8f9f7	3596	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3597	* @arg TIM_EventSource_Update: Timer update Event source
<>	144:ef7eb2e8f9f7	3598	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<>	144:ef7eb2e8f9f7	3599	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
<>	144:ef7eb2e8f9f7	3600	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
<>	144:ef7eb2e8f9f7	3601	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
<>	144:ef7eb2e8f9f7	3602	* @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source
<>	144:ef7eb2e8f9f7	3603	* @note TIM6 can only generate an update event.
<>	144:ef7eb2e8f9f7	3604	* @retval HAL status
<>	144:ef7eb2e8f9f7	3605	*/
<>	144:ef7eb2e8f9f7	3606
<>	144:ef7eb2e8f9f7	3607	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<>	144:ef7eb2e8f9f7	3608	{
<>	144:ef7eb2e8f9f7	3609	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3610	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3611	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<>	144:ef7eb2e8f9f7	3612
<>	144:ef7eb2e8f9f7	3613	/* Process Locked */
<>	144:ef7eb2e8f9f7	3614	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3615
<>	144:ef7eb2e8f9f7	3616	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3617	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3618
<>	144:ef7eb2e8f9f7	3619	/* Set the event sources */
<>	144:ef7eb2e8f9f7	3620	htim->Instance->EGR = EventSource;
<>	144:ef7eb2e8f9f7	3621
<>	144:ef7eb2e8f9f7	3622	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3623	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3624
<>	144:ef7eb2e8f9f7	3625	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3626
<>	144:ef7eb2e8f9f7	3627	/* Return function status */
<>	144:ef7eb2e8f9f7	3628	return HAL_OK;
<>	144:ef7eb2e8f9f7	3629	}
<>	144:ef7eb2e8f9f7	3630
<>	144:ef7eb2e8f9f7	3631	/**
<>	144:ef7eb2e8f9f7	3632	* @brief Configures the OCRef clear feature
<>	144:ef7eb2e8f9f7	3633	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3634	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3635	* contains the OCREF clear feature and parameters for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3636	* @param Channel: specifies the TIM Channel.
<>	144:ef7eb2e8f9f7	3637	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3638	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3639	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3640	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	3641	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	3642	* @retval HAL status
<>	144:ef7eb2e8f9f7	3643	*/
<>	144:ef7eb2e8f9f7	3644	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3645	{
<>	144:ef7eb2e8f9f7	3646	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3647	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3648	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	3649	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<>	144:ef7eb2e8f9f7	3650	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<>	144:ef7eb2e8f9f7	3651	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<>	144:ef7eb2e8f9f7	3652	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<>	144:ef7eb2e8f9f7	3653
<>	144:ef7eb2e8f9f7	3654	/* Process Locked */
<>	144:ef7eb2e8f9f7	3655	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3656
<>	144:ef7eb2e8f9f7	3657	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3658
<>	144:ef7eb2e8f9f7	3659	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
<>	144:ef7eb2e8f9f7	3660	{
<>	144:ef7eb2e8f9f7	3661	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3662	sClearInputConfig->ClearInputPrescaler,
<>	144:ef7eb2e8f9f7	3663	sClearInputConfig->ClearInputPolarity,
<>	144:ef7eb2e8f9f7	3664	sClearInputConfig->ClearInputFilter);
<>	144:ef7eb2e8f9f7	3665
<>	144:ef7eb2e8f9f7	3666	/* Set the OCREF clear selection bit */
<>	144:ef7eb2e8f9f7	3667	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
<>	144:ef7eb2e8f9f7	3668	}
<>	144:ef7eb2e8f9f7	3669
<>	144:ef7eb2e8f9f7	3670	switch (Channel)
<>	144:ef7eb2e8f9f7	3671	{
<>	144:ef7eb2e8f9f7	3672	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3673	{
<>	144:ef7eb2e8f9f7	3674	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3675	{
<>	144:ef7eb2e8f9f7	3676	/* Enable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3677	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3678	}
<>	144:ef7eb2e8f9f7	3679	else
<>	144:ef7eb2e8f9f7	3680	{
<>	144:ef7eb2e8f9f7	3681	/* Disable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3682	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3683	}
<>	144:ef7eb2e8f9f7	3684	}
<>	144:ef7eb2e8f9f7	3685	break;
<>	144:ef7eb2e8f9f7	3686	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3687	{
<>	144:ef7eb2e8f9f7	3688	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3689	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3690	{
<>	144:ef7eb2e8f9f7	3691	/* Enable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3692	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3693	}
<>	144:ef7eb2e8f9f7	3694	else
<>	144:ef7eb2e8f9f7	3695	{
<>	144:ef7eb2e8f9f7	3696	/* Disable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3697	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3698	}
<>	144:ef7eb2e8f9f7	3699	}
<>	144:ef7eb2e8f9f7	3700	break;
<>	144:ef7eb2e8f9f7	3701	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3702	{
<>	144:ef7eb2e8f9f7	3703	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3704	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3705	{
<>	144:ef7eb2e8f9f7	3706	/* Enable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3707	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3708	}
<>	144:ef7eb2e8f9f7	3709	else
<>	144:ef7eb2e8f9f7	3710	{
<>	144:ef7eb2e8f9f7	3711	/* Disable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3712	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3713	}
<>	144:ef7eb2e8f9f7	3714	}
<>	144:ef7eb2e8f9f7	3715	break;
<>	144:ef7eb2e8f9f7	3716	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3717	{
<>	144:ef7eb2e8f9f7	3718	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3719	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3720	{
<>	144:ef7eb2e8f9f7	3721	/* Enable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3722	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3723	}
<>	144:ef7eb2e8f9f7	3724	else
<>	144:ef7eb2e8f9f7	3725	{
<>	144:ef7eb2e8f9f7	3726	/* Disable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3727	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3728	}
<>	144:ef7eb2e8f9f7	3729	}
<>	144:ef7eb2e8f9f7	3730	break;
<>	144:ef7eb2e8f9f7	3731	default:
<>	144:ef7eb2e8f9f7	3732	break;
<>	144:ef7eb2e8f9f7	3733	}
<>	144:ef7eb2e8f9f7	3734
<>	144:ef7eb2e8f9f7	3735	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3736
<>	144:ef7eb2e8f9f7	3737	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3738
<>	144:ef7eb2e8f9f7	3739	return HAL_OK;
<>	144:ef7eb2e8f9f7	3740	}
<>	144:ef7eb2e8f9f7	3741
<>	144:ef7eb2e8f9f7	3742	/**
<>	144:ef7eb2e8f9f7	3743	* @brief Configures the clock source to be used
<>	144:ef7eb2e8f9f7	3744	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3745	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3746	* contains the clock source information for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3747	* @retval HAL status
<>	144:ef7eb2e8f9f7	3748	*/
<>	144:ef7eb2e8f9f7	3749	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
<>	144:ef7eb2e8f9f7	3750	{
<>	151:5eaa88a5bcc7	3751	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	3752
<>	144:ef7eb2e8f9f7	3753	/* Process Locked */
<>	144:ef7eb2e8f9f7	3754	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3755
<>	144:ef7eb2e8f9f7	3756	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3757
<>	144:ef7eb2e8f9f7	3758	/* Check the clock source */
<>	144:ef7eb2e8f9f7	3759	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<>	144:ef7eb2e8f9f7	3760
<>	144:ef7eb2e8f9f7	3761	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<>	144:ef7eb2e8f9f7	3762	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3763	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	3764	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	3765	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3766
<>	144:ef7eb2e8f9f7	3767	switch (sClockSourceConfig->ClockSource)
<>	144:ef7eb2e8f9f7	3768	{
<>	144:ef7eb2e8f9f7	3769	case TIM_CLOCKSOURCE_INTERNAL:
<>	144:ef7eb2e8f9f7	3770	{
<>	144:ef7eb2e8f9f7	3771	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3772	/* Disable slave mode to clock the prescaler directly with the internal clock */
<>	144:ef7eb2e8f9f7	3773	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3774	}
<>	144:ef7eb2e8f9f7	3775	break;
<>	144:ef7eb2e8f9f7	3776
<>	144:ef7eb2e8f9f7	3777	case TIM_CLOCKSOURCE_ETRMODE1:
<>	144:ef7eb2e8f9f7	3778	{
<>	144:ef7eb2e8f9f7	3779	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3780	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	3781	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3782	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3783	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	3784	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3785	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	3786	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3787	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3788	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	3789	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3790	/* Reset the SMS and TS Bits */
<>	144:ef7eb2e8f9f7	3791	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	3792	/* Select the External clock mode1 and the ETRF trigger */
<>	144:ef7eb2e8f9f7	3793	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
<>	144:ef7eb2e8f9f7	3794	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	3795	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3796	}
<>	144:ef7eb2e8f9f7	3797	break;
<>	144:ef7eb2e8f9f7	3798
<>	144:ef7eb2e8f9f7	3799	case TIM_CLOCKSOURCE_ETRMODE2:
<>	144:ef7eb2e8f9f7	3800	{
<>	144:ef7eb2e8f9f7	3801	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3802	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	3803	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3804	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3805	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	3806	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3807	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	3808	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3809	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3810	/* Enable the External clock mode2 */
<>	144:ef7eb2e8f9f7	3811	htim->Instance->SMCR \|= TIM_SMCR_ECE;
<>	144:ef7eb2e8f9f7	3812	}
<>	144:ef7eb2e8f9f7	3813	break;
<>	144:ef7eb2e8f9f7	3814
<>	144:ef7eb2e8f9f7	3815	case TIM_CLOCKSOURCE_TI1:
<>	144:ef7eb2e8f9f7	3816	{
<>	144:ef7eb2e8f9f7	3817	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3818	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3819	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3820	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	3821	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3822	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3823	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<>	144:ef7eb2e8f9f7	3824	}
<>	144:ef7eb2e8f9f7	3825	break;
<>	144:ef7eb2e8f9f7	3826	case TIM_CLOCKSOURCE_TI2:
<>	144:ef7eb2e8f9f7	3827	{
<>	144:ef7eb2e8f9f7	3828	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3829	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3830	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3831	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	3832	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3833	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3834	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<>	144:ef7eb2e8f9f7	3835	}
<>	144:ef7eb2e8f9f7	3836	break;
<>	144:ef7eb2e8f9f7	3837	case TIM_CLOCKSOURCE_TI1ED:
<>	144:ef7eb2e8f9f7	3838	{
<>	144:ef7eb2e8f9f7	3839	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3840	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3841	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3842	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	3843	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3844	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3845	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<>	144:ef7eb2e8f9f7	3846	}
<>	144:ef7eb2e8f9f7	3847	break;
<>	144:ef7eb2e8f9f7	3848	case TIM_CLOCKSOURCE_ITR0:
<>	144:ef7eb2e8f9f7	3849	{
<>	144:ef7eb2e8f9f7	3850	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3851	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<>	144:ef7eb2e8f9f7	3852	}
<>	144:ef7eb2e8f9f7	3853	break;
<>	144:ef7eb2e8f9f7	3854	case TIM_CLOCKSOURCE_ITR1:
<>	144:ef7eb2e8f9f7	3855	{
<>	144:ef7eb2e8f9f7	3856	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3857	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<>	144:ef7eb2e8f9f7	3858	}
<>	144:ef7eb2e8f9f7	3859	break;
<>	144:ef7eb2e8f9f7	3860	case TIM_CLOCKSOURCE_ITR2:
<>	144:ef7eb2e8f9f7	3861	{
<>	144:ef7eb2e8f9f7	3862	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3863	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<>	144:ef7eb2e8f9f7	3864	}
<>	144:ef7eb2e8f9f7	3865	break;
<>	144:ef7eb2e8f9f7	3866	case TIM_CLOCKSOURCE_ITR3:
<>	144:ef7eb2e8f9f7	3867	{
<>	144:ef7eb2e8f9f7	3868	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3869	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<>	144:ef7eb2e8f9f7	3870	}
<>	144:ef7eb2e8f9f7	3871	break;
<>	144:ef7eb2e8f9f7	3872
<>	144:ef7eb2e8f9f7	3873	default:
<>	144:ef7eb2e8f9f7	3874	break;
<>	144:ef7eb2e8f9f7	3875	}
<>	144:ef7eb2e8f9f7	3876	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3877
<>	144:ef7eb2e8f9f7	3878	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3879
<>	144:ef7eb2e8f9f7	3880	return HAL_OK;
<>	144:ef7eb2e8f9f7	3881	}
<>	144:ef7eb2e8f9f7	3882
<>	144:ef7eb2e8f9f7	3883	/**
<>	144:ef7eb2e8f9f7	3884	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
<>	144:ef7eb2e8f9f7	3885	* or a XOR combination between CH1_input, CH2_input & CH3_input
<>	144:ef7eb2e8f9f7	3886	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3887	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
<>	144:ef7eb2e8f9f7	3888	* output of a XOR gate.
<>	144:ef7eb2e8f9f7	3889	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3890	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<>	144:ef7eb2e8f9f7	3891	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<>	144:ef7eb2e8f9f7	3892	* pins are connected to the TI1 input (XOR combination)
<>	144:ef7eb2e8f9f7	3893	* @retval HAL status
<>	144:ef7eb2e8f9f7	3894	*/
<>	144:ef7eb2e8f9f7	3895	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<>	144:ef7eb2e8f9f7	3896	{
<>	151:5eaa88a5bcc7	3897	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	3898
<>	144:ef7eb2e8f9f7	3899	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3900	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3901	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<>	144:ef7eb2e8f9f7	3902
<>	144:ef7eb2e8f9f7	3903	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	3904	tmpcr2 = htim->Instance->CR2;
<>	144:ef7eb2e8f9f7	3905
<>	144:ef7eb2e8f9f7	3906	/* Reset the TI1 selection */
<>	144:ef7eb2e8f9f7	3907	tmpcr2 &= ~TIM_CR2_TI1S;
<>	144:ef7eb2e8f9f7	3908
<>	144:ef7eb2e8f9f7	3909	/* Set the the TI1 selection */
<>	144:ef7eb2e8f9f7	3910	tmpcr2 \|= TI1_Selection;
<>	144:ef7eb2e8f9f7	3911
<>	144:ef7eb2e8f9f7	3912	/* Write to TIMxCR2 */
<>	144:ef7eb2e8f9f7	3913	htim->Instance->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	3914
<>	144:ef7eb2e8f9f7	3915	return HAL_OK;
<>	144:ef7eb2e8f9f7	3916	}
<>	144:ef7eb2e8f9f7	3917
<>	144:ef7eb2e8f9f7	3918	/**
<>	144:ef7eb2e8f9f7	3919	* @brief Configures the TIM in Slave mode
<>	144:ef7eb2e8f9f7	3920	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3921	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3922	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	3923	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	3924	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	3925	* @retval HAL status
<>	144:ef7eb2e8f9f7	3926	*/
<>	144:ef7eb2e8f9f7	3927	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
<>	144:ef7eb2e8f9f7	3928	{
<>	144:ef7eb2e8f9f7	3929	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3930	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3931	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	3932	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	3933
<>	144:ef7eb2e8f9f7	3934	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3935
<>	144:ef7eb2e8f9f7	3936	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3937
<>	144:ef7eb2e8f9f7	3938	/* Configuration in slave mode */
<>	144:ef7eb2e8f9f7	3939	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	3940
<>	144:ef7eb2e8f9f7	3941	/* Disable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	3942	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	3943
<>	144:ef7eb2e8f9f7	3944	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	3945	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	3946
<>	144:ef7eb2e8f9f7	3947	/* Set the new state */
<>	144:ef7eb2e8f9f7	3948	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3949
<>	144:ef7eb2e8f9f7	3950	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3951
<>	144:ef7eb2e8f9f7	3952	return HAL_OK;
<>	144:ef7eb2e8f9f7	3953	}
<>	144:ef7eb2e8f9f7	3954
<>	144:ef7eb2e8f9f7	3955	/**
<>	144:ef7eb2e8f9f7	3956	* @brief Configures the TIM in Slave mode in interrupt mode
<>	144:ef7eb2e8f9f7	3957	* @param htim : TIM handle.
<>	144:ef7eb2e8f9f7	3958	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3959	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	3960	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	3961	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	3962	* @retval HAL status
<>	144:ef7eb2e8f9f7	3963	*/
<>	144:ef7eb2e8f9f7	3964	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	3965	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	3966	{
<>	144:ef7eb2e8f9f7	3967	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3968	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3969	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	3970	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	3971
<>	144:ef7eb2e8f9f7	3972	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3973
<>	144:ef7eb2e8f9f7	3974	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3975
<>	144:ef7eb2e8f9f7	3976	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	3977
<>	144:ef7eb2e8f9f7	3978	/* Enable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	3979	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	3980
<>	144:ef7eb2e8f9f7	3981	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	3982	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	3983
<>	144:ef7eb2e8f9f7	3984	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3985
<>	144:ef7eb2e8f9f7	3986	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3987
<>	144:ef7eb2e8f9f7	3988	return HAL_OK;
<>	144:ef7eb2e8f9f7	3989	}
<>	144:ef7eb2e8f9f7	3990
<>	144:ef7eb2e8f9f7	3991	/**
<>	144:ef7eb2e8f9f7	3992	* @brief Read the captured value from Capture Compare unit
<>	144:ef7eb2e8f9f7	3993	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3994	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	3995	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3996	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3997	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3998	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	3999	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	4000	* @retval Captured value
<>	144:ef7eb2e8f9f7	4001	*/
<>	144:ef7eb2e8f9f7	4002	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	4003	{
<>	151:5eaa88a5bcc7	4004	uint32_t tmpreg = 0U;
<>	144:ef7eb2e8f9f7	4005
<>	144:ef7eb2e8f9f7	4006	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4007
<>	144:ef7eb2e8f9f7	4008	switch (Channel)
<>	144:ef7eb2e8f9f7	4009	{
<>	144:ef7eb2e8f9f7	4010	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	4011	{
<>	144:ef7eb2e8f9f7	4012	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4013	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4014
<>	144:ef7eb2e8f9f7	4015	/* Return the capture 1 value */
<>	144:ef7eb2e8f9f7	4016	tmpreg = htim->Instance->CCR1;
<>	144:ef7eb2e8f9f7	4017
<>	144:ef7eb2e8f9f7	4018	break;
<>	144:ef7eb2e8f9f7	4019	}
<>	144:ef7eb2e8f9f7	4020	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	4021	{
<>	144:ef7eb2e8f9f7	4022	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4023	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4024
<>	144:ef7eb2e8f9f7	4025	/* Return the capture 2 value */
<>	144:ef7eb2e8f9f7	4026	tmpreg = htim->Instance->CCR2;
<>	144:ef7eb2e8f9f7	4027
<>	144:ef7eb2e8f9f7	4028	break;
<>	144:ef7eb2e8f9f7	4029	}
<>	144:ef7eb2e8f9f7	4030
<>	144:ef7eb2e8f9f7	4031	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	4032	{
<>	144:ef7eb2e8f9f7	4033	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4034	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4035
<>	144:ef7eb2e8f9f7	4036	/* Return the capture 3 value */
<>	144:ef7eb2e8f9f7	4037	tmpreg = htim->Instance->CCR3;
<>	144:ef7eb2e8f9f7	4038
<>	144:ef7eb2e8f9f7	4039	break;
<>	144:ef7eb2e8f9f7	4040	}
<>	144:ef7eb2e8f9f7	4041
<>	144:ef7eb2e8f9f7	4042	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	4043	{
<>	144:ef7eb2e8f9f7	4044	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4045	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4046
<>	144:ef7eb2e8f9f7	4047	/* Return the capture 4 value */
<>	144:ef7eb2e8f9f7	4048	tmpreg = htim->Instance->CCR4;
<>	144:ef7eb2e8f9f7	4049
<>	144:ef7eb2e8f9f7	4050	break;
<>	144:ef7eb2e8f9f7	4051	}
<>	144:ef7eb2e8f9f7	4052
<>	144:ef7eb2e8f9f7	4053	default:
<>	144:ef7eb2e8f9f7	4054	break;
<>	144:ef7eb2e8f9f7	4055	}
<>	144:ef7eb2e8f9f7	4056
<>	144:ef7eb2e8f9f7	4057	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4058	return tmpreg;
<>	144:ef7eb2e8f9f7	4059	}
<>	144:ef7eb2e8f9f7	4060
<>	144:ef7eb2e8f9f7	4061	/**
<>	144:ef7eb2e8f9f7	4062	* @}
<>	144:ef7eb2e8f9f7	4063	*/
<>	144:ef7eb2e8f9f7	4064
<>	144:ef7eb2e8f9f7	4065	/** @addtogroup TIM_Exported_Functions_Group9
<>	144:ef7eb2e8f9f7	4066	* @brief TIM Callbacks functions
<>	144:ef7eb2e8f9f7	4067	*
<>	144:ef7eb2e8f9f7	4068	@verbatim
<>	144:ef7eb2e8f9f7	4069	==============================================================================
<>	144:ef7eb2e8f9f7	4070	##### TIM Callbacks functions #####
<>	144:ef7eb2e8f9f7	4071	==============================================================================
<>	144:ef7eb2e8f9f7	4072	[..]
<>	144:ef7eb2e8f9f7	4073	This section provides TIM callback functions:
<>	144:ef7eb2e8f9f7	4074	(+) Timer Period elapsed callback
<>	144:ef7eb2e8f9f7	4075	(+) Timer Output Compare callback
<>	144:ef7eb2e8f9f7	4076	(+) Timer Input capture callback
<>	144:ef7eb2e8f9f7	4077	(+) Timer Trigger callback
<>	144:ef7eb2e8f9f7	4078	(+) Timer Error callback
<>	144:ef7eb2e8f9f7	4079
<>	144:ef7eb2e8f9f7	4080	@endverbatim
<>	144:ef7eb2e8f9f7	4081	* @{
<>	144:ef7eb2e8f9f7	4082	*/
<>	144:ef7eb2e8f9f7	4083
<>	144:ef7eb2e8f9f7	4084	/**
<>	144:ef7eb2e8f9f7	4085	* @brief Period elapsed callback in non blocking mode
<>	144:ef7eb2e8f9f7	4086	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4087	* @retval None
<>	144:ef7eb2e8f9f7	4088	*/
<>	144:ef7eb2e8f9f7	4089	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4090	{
<>	144:ef7eb2e8f9f7	4091	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4092	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4093
<>	144:ef7eb2e8f9f7	4094	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4095	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4096	*/
<>	144:ef7eb2e8f9f7	4097
<>	144:ef7eb2e8f9f7	4098	}
<>	144:ef7eb2e8f9f7	4099	/**
<>	144:ef7eb2e8f9f7	4100	* @brief Output Compare callback in non blocking mode
<>	144:ef7eb2e8f9f7	4101	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4102	* @retval None
<>	144:ef7eb2e8f9f7	4103	*/
<>	144:ef7eb2e8f9f7	4104	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4105	{
<>	144:ef7eb2e8f9f7	4106	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4107	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4108
<>	144:ef7eb2e8f9f7	4109	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4110	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4111	*/
<>	144:ef7eb2e8f9f7	4112	}
<>	144:ef7eb2e8f9f7	4113	/**
<>	144:ef7eb2e8f9f7	4114	* @brief Input Capture callback in non blocking mode
<>	144:ef7eb2e8f9f7	4115	* @param htim: TIM IC handle
<>	144:ef7eb2e8f9f7	4116	* @retval None
<>	144:ef7eb2e8f9f7	4117	*/
<>	144:ef7eb2e8f9f7	4118	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4119	{
<>	144:ef7eb2e8f9f7	4120	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4121	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4122
<>	144:ef7eb2e8f9f7	4123	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4124	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4125	*/
<>	144:ef7eb2e8f9f7	4126	}
<>	144:ef7eb2e8f9f7	4127
<>	144:ef7eb2e8f9f7	4128	/**
<>	144:ef7eb2e8f9f7	4129	* @brief PWM Pulse finished callback in non blocking mode
<>	144:ef7eb2e8f9f7	4130	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4131	* @retval None
<>	144:ef7eb2e8f9f7	4132	*/
<>	144:ef7eb2e8f9f7	4133	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4134	{
<>	144:ef7eb2e8f9f7	4135	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4136	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4137
<>	144:ef7eb2e8f9f7	4138	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4139	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4140	*/
<>	144:ef7eb2e8f9f7	4141	}
<>	144:ef7eb2e8f9f7	4142
<>	144:ef7eb2e8f9f7	4143	/**
<>	144:ef7eb2e8f9f7	4144	* @brief Hall Trigger detection callback in non blocking mode
<>	144:ef7eb2e8f9f7	4145	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4146	* @retval None
<>	144:ef7eb2e8f9f7	4147	*/
<>	144:ef7eb2e8f9f7	4148	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4149	{
<>	144:ef7eb2e8f9f7	4150	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4151	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4152
<>	144:ef7eb2e8f9f7	4153	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4154	the HAL_TIM_TriggerCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4155	*/
<>	144:ef7eb2e8f9f7	4156	}
<>	144:ef7eb2e8f9f7	4157
<>	144:ef7eb2e8f9f7	4158	/**
<>	144:ef7eb2e8f9f7	4159	* @brief Timer error callback in non blocking mode
<>	144:ef7eb2e8f9f7	4160	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4161	* @retval None
<>	144:ef7eb2e8f9f7	4162	*/
<>	144:ef7eb2e8f9f7	4163	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4164	{
<>	144:ef7eb2e8f9f7	4165	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4166	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4167
<>	144:ef7eb2e8f9f7	4168	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4169	the HAL_TIM_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4170	*/
<>	144:ef7eb2e8f9f7	4171	}
<>	144:ef7eb2e8f9f7	4172
<>	144:ef7eb2e8f9f7	4173	/**
<>	144:ef7eb2e8f9f7	4174	* @}
<>	144:ef7eb2e8f9f7	4175	*/
<>	144:ef7eb2e8f9f7	4176
<>	144:ef7eb2e8f9f7	4177	/** @addtogroup TIM_Exported_Functions_Group10
<>	144:ef7eb2e8f9f7	4178	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	4179	*
<>	144:ef7eb2e8f9f7	4180	@verbatim
<>	144:ef7eb2e8f9f7	4181	==============================================================================
<>	144:ef7eb2e8f9f7	4182	##### Peripheral State functions #####
<>	144:ef7eb2e8f9f7	4183	==============================================================================
<>	144:ef7eb2e8f9f7	4184	[..]
<>	144:ef7eb2e8f9f7	4185	This subsection permits to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	4186	and the data flow.
<>	144:ef7eb2e8f9f7	4187
<>	144:ef7eb2e8f9f7	4188	@endverbatim
<>	144:ef7eb2e8f9f7	4189	* @{
<>	144:ef7eb2e8f9f7	4190	*/
<>	144:ef7eb2e8f9f7	4191
<>	144:ef7eb2e8f9f7	4192	/**
<>	144:ef7eb2e8f9f7	4193	* @brief Return the TIM Base state
<>	144:ef7eb2e8f9f7	4194	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4195	* @retval HAL state
<>	144:ef7eb2e8f9f7	4196	*/
<>	144:ef7eb2e8f9f7	4197	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4198	{
<>	144:ef7eb2e8f9f7	4199	return htim->State;
<>	144:ef7eb2e8f9f7	4200	}
<>	144:ef7eb2e8f9f7	4201
<>	144:ef7eb2e8f9f7	4202	/**
<>	144:ef7eb2e8f9f7	4203	* @brief Return the TIM OC state
<>	144:ef7eb2e8f9f7	4204	* @param htim: TIM Ouput Compare handle
<>	144:ef7eb2e8f9f7	4205	* @retval HAL state
<>	144:ef7eb2e8f9f7	4206	*/
<>	144:ef7eb2e8f9f7	4207	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4208	{
<>	144:ef7eb2e8f9f7	4209	return htim->State;
<>	144:ef7eb2e8f9f7	4210	}
<>	144:ef7eb2e8f9f7	4211
<>	144:ef7eb2e8f9f7	4212	/**
<>	144:ef7eb2e8f9f7	4213	* @brief Return the TIM PWM state
<>	144:ef7eb2e8f9f7	4214	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4215	* @retval HAL state
<>	144:ef7eb2e8f9f7	4216	*/
<>	144:ef7eb2e8f9f7	4217	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4218	{
<>	144:ef7eb2e8f9f7	4219	return htim->State;
<>	144:ef7eb2e8f9f7	4220	}
<>	144:ef7eb2e8f9f7	4221
<>	144:ef7eb2e8f9f7	4222	/**
<>	144:ef7eb2e8f9f7	4223	* @brief Return the TIM Input Capture state
<>	144:ef7eb2e8f9f7	4224	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4225	* @retval HAL state
<>	144:ef7eb2e8f9f7	4226	*/
<>	144:ef7eb2e8f9f7	4227	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4228	{
<>	144:ef7eb2e8f9f7	4229	return htim->State;
<>	144:ef7eb2e8f9f7	4230	}
<>	144:ef7eb2e8f9f7	4231
<>	144:ef7eb2e8f9f7	4232	/**
<>	144:ef7eb2e8f9f7	4233	* @brief Return the TIM One Pulse Mode state
<>	144:ef7eb2e8f9f7	4234	* @param htim: TIM OPM handle
<>	144:ef7eb2e8f9f7	4235	* @retval HAL state
<>	144:ef7eb2e8f9f7	4236	*/
<>	144:ef7eb2e8f9f7	4237	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4238	{
<>	144:ef7eb2e8f9f7	4239	return htim->State;
<>	144:ef7eb2e8f9f7	4240	}
<>	144:ef7eb2e8f9f7	4241
<>	144:ef7eb2e8f9f7	4242	/**
<>	144:ef7eb2e8f9f7	4243	* @brief Return the TIM Encoder Mode state
<>	144:ef7eb2e8f9f7	4244	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4245	* @retval HAL state
<>	144:ef7eb2e8f9f7	4246	*/
<>	144:ef7eb2e8f9f7	4247	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4248	{
<>	144:ef7eb2e8f9f7	4249	return htim->State;
<>	144:ef7eb2e8f9f7	4250	}
<>	144:ef7eb2e8f9f7	4251
<>	144:ef7eb2e8f9f7	4252
<>	144:ef7eb2e8f9f7	4253
<>	144:ef7eb2e8f9f7	4254	/**
<>	144:ef7eb2e8f9f7	4255	* @brief TIM DMA error callback
<>	144:ef7eb2e8f9f7	4256	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4257	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4258	* @retval None
<>	144:ef7eb2e8f9f7	4259	*/
<>	144:ef7eb2e8f9f7	4260	void TIM_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4261	{
<>	144:ef7eb2e8f9f7	4262	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4263
<>	144:ef7eb2e8f9f7	4264	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4265
<>	144:ef7eb2e8f9f7	4266	HAL_TIM_ErrorCallback(htim);
<>	144:ef7eb2e8f9f7	4267	}
<>	144:ef7eb2e8f9f7	4268
<>	144:ef7eb2e8f9f7	4269	/**
<>	144:ef7eb2e8f9f7	4270	* @brief TIM DMA Delay Pulse complete callback.
<>	144:ef7eb2e8f9f7	4271	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4272	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4273	* @retval None
<>	144:ef7eb2e8f9f7	4274	*/
<>	144:ef7eb2e8f9f7	4275	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4276	{
<>	144:ef7eb2e8f9f7	4277	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4278
<>	144:ef7eb2e8f9f7	4279	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4280
<>	144:ef7eb2e8f9f7	4281	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4282	{
<>	144:ef7eb2e8f9f7	4283	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4284	}
<>	144:ef7eb2e8f9f7	4285	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4286	{
<>	144:ef7eb2e8f9f7	4287	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4288	}
<>	144:ef7eb2e8f9f7	4289	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4290	{
<>	144:ef7eb2e8f9f7	4291	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4292	}
<>	144:ef7eb2e8f9f7	4293	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4294	{
<>	144:ef7eb2e8f9f7	4295	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4296	}
<>	144:ef7eb2e8f9f7	4297	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	4298
<>	144:ef7eb2e8f9f7	4299	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4300	}
<>	144:ef7eb2e8f9f7	4301	/**
<>	144:ef7eb2e8f9f7	4302	* @brief TIM DMA Capture complete callback.
<>	144:ef7eb2e8f9f7	4303	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4304	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4305	* @retval None
<>	144:ef7eb2e8f9f7	4306	*/
<>	144:ef7eb2e8f9f7	4307	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4308	{
<>	144:ef7eb2e8f9f7	4309	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4310
<>	144:ef7eb2e8f9f7	4311	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4312
<>	144:ef7eb2e8f9f7	4313	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4314	{
<>	144:ef7eb2e8f9f7	4315	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4316	}
<>	144:ef7eb2e8f9f7	4317	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4318	{
<>	144:ef7eb2e8f9f7	4319	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4320	}
<>	144:ef7eb2e8f9f7	4321	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4322	{
<>	144:ef7eb2e8f9f7	4323	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4324	}
<>	144:ef7eb2e8f9f7	4325	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4326	{
<>	144:ef7eb2e8f9f7	4327	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4328	}
<>	144:ef7eb2e8f9f7	4329
<>	144:ef7eb2e8f9f7	4330	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	4331
<>	144:ef7eb2e8f9f7	4332	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4333	}
<>	144:ef7eb2e8f9f7	4334
<>	144:ef7eb2e8f9f7	4335
<>	144:ef7eb2e8f9f7	4336	/**
<>	144:ef7eb2e8f9f7	4337	* @}
<>	144:ef7eb2e8f9f7	4338	*/
<>	144:ef7eb2e8f9f7	4339
<>	144:ef7eb2e8f9f7	4340	/**
<>	144:ef7eb2e8f9f7	4341	* @}
<>	144:ef7eb2e8f9f7	4342	*/
<>	144:ef7eb2e8f9f7	4343	/*************************************************************/
<>	144:ef7eb2e8f9f7	4344	/* Private functions */
<>	144:ef7eb2e8f9f7	4345	/*************************************************************/
<>	144:ef7eb2e8f9f7	4346
<>	144:ef7eb2e8f9f7	4347	/** @addtogroup TIM_Private TIM Private
<>	144:ef7eb2e8f9f7	4348	* @{
<>	144:ef7eb2e8f9f7	4349	*/
<>	144:ef7eb2e8f9f7	4350	/**
<>	144:ef7eb2e8f9f7	4351	* @brief TIM DMA Period Elapse complete callback.
<>	144:ef7eb2e8f9f7	4352	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4353	* @retval None
<>	144:ef7eb2e8f9f7	4354	*/
<>	144:ef7eb2e8f9f7	4355	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4356	{
<>	144:ef7eb2e8f9f7	4357	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4358
<>	144:ef7eb2e8f9f7	4359	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4360
<>	144:ef7eb2e8f9f7	4361	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	4362	}
<>	144:ef7eb2e8f9f7	4363
<>	144:ef7eb2e8f9f7	4364
<>	144:ef7eb2e8f9f7	4365	/**
<>	144:ef7eb2e8f9f7	4366	* @brief TIM DMA Trigger callback.
<>	144:ef7eb2e8f9f7	4367	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4368	* @retval None
<>	144:ef7eb2e8f9f7	4369	*/
<>	144:ef7eb2e8f9f7	4370	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4371	{
<>	144:ef7eb2e8f9f7	4372	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4373
<>	144:ef7eb2e8f9f7	4374	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4375
<>	144:ef7eb2e8f9f7	4376	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	4377	}
<>	144:ef7eb2e8f9f7	4378
<>	144:ef7eb2e8f9f7	4379	/**
<>	144:ef7eb2e8f9f7	4380	* @brief Time Base configuration
<>	144:ef7eb2e8f9f7	4381	* @param TIMx : TIM peripheral
<>	144:ef7eb2e8f9f7	4382	* @param Structure : TIM Base configuration structure
<>	144:ef7eb2e8f9f7	4383	* @retval None
<>	144:ef7eb2e8f9f7	4384	*/
<>	144:ef7eb2e8f9f7	4385	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
<>	144:ef7eb2e8f9f7	4386	{
<>	151:5eaa88a5bcc7	4387	uint32_t tmpcr1 = 0U;
<>	144:ef7eb2e8f9f7	4388	tmpcr1 = TIMx->CR1;
<>	144:ef7eb2e8f9f7	4389
<>	144:ef7eb2e8f9f7	4390	/* Set TIM Time Base Unit parameters ---------------------------------------*/
<>	144:ef7eb2e8f9f7	4391	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4392	{
<>	144:ef7eb2e8f9f7	4393	/* Select the Counter Mode */
<>	144:ef7eb2e8f9f7	4394	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
<>	144:ef7eb2e8f9f7	4395	tmpcr1 \|= Structure->CounterMode;
<>	144:ef7eb2e8f9f7	4396	}
<>	144:ef7eb2e8f9f7	4397
<>	144:ef7eb2e8f9f7	4398	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4399	{
<>	144:ef7eb2e8f9f7	4400	/* Set the clock division */
<>	144:ef7eb2e8f9f7	4401	tmpcr1 &= ~TIM_CR1_CKD;
<>	144:ef7eb2e8f9f7	4402	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
<>	144:ef7eb2e8f9f7	4403	}
<>	144:ef7eb2e8f9f7	4404
<>	144:ef7eb2e8f9f7	4405	TIMx->CR1 = tmpcr1;
<>	144:ef7eb2e8f9f7	4406
<>	144:ef7eb2e8f9f7	4407	/* Set the Autoreload value */
<>	144:ef7eb2e8f9f7	4408	TIMx->ARR = (uint32_t)Structure->Period ;
<>	144:ef7eb2e8f9f7	4409
<>	144:ef7eb2e8f9f7	4410	/* Set the Prescaler value */
<>	144:ef7eb2e8f9f7	4411	TIMx->PSC = (uint32_t)Structure->Prescaler;
<>	144:ef7eb2e8f9f7	4412
<>	144:ef7eb2e8f9f7	4413	/* Generate an update event to reload the Prescaler value immediatly */
<>	144:ef7eb2e8f9f7	4414	TIMx->EGR = TIM_EGR_UG;
<>	144:ef7eb2e8f9f7	4415	}
<>	144:ef7eb2e8f9f7	4416
<>	144:ef7eb2e8f9f7	4417	/**
<>	144:ef7eb2e8f9f7	4418	* @brief Time Ouput Compare 1 configuration
<>	144:ef7eb2e8f9f7	4419	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4420	* @param OC_Config: The ouput configuration structure
<>	144:ef7eb2e8f9f7	4421	* @retval None
<>	144:ef7eb2e8f9f7	4422	*/
<>	144:ef7eb2e8f9f7	4423	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4424	{
<>	151:5eaa88a5bcc7	4425	uint32_t tmpccmrx = 0U;
<>	151:5eaa88a5bcc7	4426	uint32_t tmpccer = 0U;
<>	151:5eaa88a5bcc7	4427	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4428
<>	144:ef7eb2e8f9f7	4429	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4430	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4431
<>	144:ef7eb2e8f9f7	4432	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4433	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4434	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4435	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4436
<>	144:ef7eb2e8f9f7	4437	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4438	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4439
<>	144:ef7eb2e8f9f7	4440	/* Reset the Output Compare Mode Bits */
<>	144:ef7eb2e8f9f7	4441	tmpccmrx &= ~TIM_CCMR1_OC1M;
<>	144:ef7eb2e8f9f7	4442	tmpccmrx &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4443	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4444	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4445
<>	144:ef7eb2e8f9f7	4446	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4447	tmpccer &= ~TIM_CCER_CC1P;
<>	144:ef7eb2e8f9f7	4448	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4449	tmpccer \|= OC_Config->OCPolarity;
<>	144:ef7eb2e8f9f7	4450
<>	144:ef7eb2e8f9f7	4451	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4452	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4453
<>	144:ef7eb2e8f9f7	4454	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4455	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4456
<>	144:ef7eb2e8f9f7	4457	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4458	TIMx->CCR1 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4459
<>	144:ef7eb2e8f9f7	4460	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4461	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4462	}
<>	144:ef7eb2e8f9f7	4463
<>	144:ef7eb2e8f9f7	4464	/**
<>	144:ef7eb2e8f9f7	4465	* @brief Time Ouput Compare 2 configuration
<>	144:ef7eb2e8f9f7	4466	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4467	* @param OC_Config: The ouput configuration structure
<>	144:ef7eb2e8f9f7	4468	* @retval None
<>	144:ef7eb2e8f9f7	4469	*/
<>	144:ef7eb2e8f9f7	4470	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4471	{
<>	151:5eaa88a5bcc7	4472	uint32_t tmpccmrx = 0U;
<>	151:5eaa88a5bcc7	4473	uint32_t tmpccer = 0U;
<>	151:5eaa88a5bcc7	4474	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4475
<>	144:ef7eb2e8f9f7	4476	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4477	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	4478
<>	144:ef7eb2e8f9f7	4479	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4480	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4481	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4482	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4483
<>	144:ef7eb2e8f9f7	4484	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4485	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4486
<>	144:ef7eb2e8f9f7	4487	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4488	tmpccmrx &= ~TIM_CCMR1_OC2M;
<>	144:ef7eb2e8f9f7	4489	tmpccmrx &= ~TIM_CCMR1_CC2S;
<>	144:ef7eb2e8f9f7	4490
<>	144:ef7eb2e8f9f7	4491	/* Select the Output Compare Mode */
<>	151:5eaa88a5bcc7	4492	tmpccmrx \|= (OC_Config->OCMode << 8U);
<>	144:ef7eb2e8f9f7	4493
<>	144:ef7eb2e8f9f7	4494	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4495	tmpccer &= ~TIM_CCER_CC2P;
<>	144:ef7eb2e8f9f7	4496	/* Set the Output Compare Polarity */
<>	151:5eaa88a5bcc7	4497	tmpccer \|= (OC_Config->OCPolarity << 4U);
<>	144:ef7eb2e8f9f7	4498
<>	144:ef7eb2e8f9f7	4499	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4500	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4501
<>	144:ef7eb2e8f9f7	4502	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4503	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4504
<>	144:ef7eb2e8f9f7	4505	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4506	TIMx->CCR2 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4507
<>	144:ef7eb2e8f9f7	4508	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4509	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4510	}
<>	144:ef7eb2e8f9f7	4511
<>	144:ef7eb2e8f9f7	4512	/**
<>	144:ef7eb2e8f9f7	4513	* @brief Time Ouput Compare 3 configuration
<>	144:ef7eb2e8f9f7	4514	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4515	* @param OC_Config: The ouput configuration structure
<>	144:ef7eb2e8f9f7	4516	* @retval None
<>	144:ef7eb2e8f9f7	4517	*/
<>	144:ef7eb2e8f9f7	4518	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4519	{
<>	151:5eaa88a5bcc7	4520	uint32_t tmpccmrx = 0U;
<>	151:5eaa88a5bcc7	4521	uint32_t tmpccer = 0U;
<>	151:5eaa88a5bcc7	4522	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4523
<>	144:ef7eb2e8f9f7	4524	/* Disable the Channel 3: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4525	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	4526
<>	144:ef7eb2e8f9f7	4527	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4528	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4529	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4530	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4531
<>	144:ef7eb2e8f9f7	4532	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4533	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4534
<>	144:ef7eb2e8f9f7	4535	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4536	tmpccmrx &= ~TIM_CCMR2_OC3M;
<>	144:ef7eb2e8f9f7	4537	tmpccmrx &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	4538	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4539	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4540
<>	144:ef7eb2e8f9f7	4541	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4542	tmpccer &= ~TIM_CCER_CC3P;
<>	144:ef7eb2e8f9f7	4543	/* Set the Output Compare Polarity */
<>	151:5eaa88a5bcc7	4544	tmpccer \|= (OC_Config->OCPolarity << 8U);
<>	144:ef7eb2e8f9f7	4545
<>	144:ef7eb2e8f9f7	4546	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4547	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4548
<>	144:ef7eb2e8f9f7	4549	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4550	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4551
<>	144:ef7eb2e8f9f7	4552	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4553	TIMx->CCR3 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4554
<>	144:ef7eb2e8f9f7	4555	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4556	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4557	}
<>	144:ef7eb2e8f9f7	4558
<>	144:ef7eb2e8f9f7	4559	/**
<>	144:ef7eb2e8f9f7	4560	* @brief Time Ouput Compare 4 configuration
<>	144:ef7eb2e8f9f7	4561	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4562	* @param OC_Config: The ouput configuration structure
<>	144:ef7eb2e8f9f7	4563	* @retval None
<>	144:ef7eb2e8f9f7	4564	*/
<>	144:ef7eb2e8f9f7	4565	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4566	{
<>	151:5eaa88a5bcc7	4567	uint32_t tmpccmrx = 0U;
<>	151:5eaa88a5bcc7	4568	uint32_t tmpccer = 0U;
<>	151:5eaa88a5bcc7	4569	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4570
<>	144:ef7eb2e8f9f7	4571	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	4572	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	4573
<>	144:ef7eb2e8f9f7	4574	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4575	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4576	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4577	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4578
<>	144:ef7eb2e8f9f7	4579	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4580	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4581
<>	144:ef7eb2e8f9f7	4582	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4583	tmpccmrx &= ~TIM_CCMR2_OC4M;
<>	144:ef7eb2e8f9f7	4584	tmpccmrx &= ~TIM_CCMR2_CC4S;
<>	144:ef7eb2e8f9f7	4585
<>	144:ef7eb2e8f9f7	4586	/* Select the Output Compare Mode */
<>	151:5eaa88a5bcc7	4587	tmpccmrx \|= (OC_Config->OCMode << 8U);
<>	144:ef7eb2e8f9f7	4588
<>	144:ef7eb2e8f9f7	4589	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4590	tmpccer &= ~TIM_CCER_CC4P;
<>	144:ef7eb2e8f9f7	4591	/* Set the Output Compare Polarity */
<>	151:5eaa88a5bcc7	4592	tmpccer \|= (OC_Config->OCPolarity << 12U);
<>	144:ef7eb2e8f9f7	4593
<>	144:ef7eb2e8f9f7	4594	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4595	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4596
<>	144:ef7eb2e8f9f7	4597	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4598	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4599
<>	144:ef7eb2e8f9f7	4600	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4601	TIMx->CCR4 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4602
<>	144:ef7eb2e8f9f7	4603	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4604	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4605	}
<>	144:ef7eb2e8f9f7	4606
<>	144:ef7eb2e8f9f7	4607	/**
<>	144:ef7eb2e8f9f7	4608	* @brief Configure the TI1 as Input.
<>	144:ef7eb2e8f9f7	4609	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	4610	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	4611	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4612	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	4613	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	4614	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	4615	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	4616	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4617	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	4618	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	4619	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	4620	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	4621	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	4622	* @retval None
<>	144:ef7eb2e8f9f7	4623	*/
<>	144:ef7eb2e8f9f7	4624	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	4625	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	4626	{
<>	151:5eaa88a5bcc7	4627	uint32_t tmpccmr1 = 0U;
<>	151:5eaa88a5bcc7	4628	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4629
<>	144:ef7eb2e8f9f7	4630	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4631	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4632	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4633	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4634
<>	144:ef7eb2e8f9f7	4635	/* Select the Input */
<>	144:ef7eb2e8f9f7	4636	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4637	{
<>	144:ef7eb2e8f9f7	4638	tmpccmr1 &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4639	tmpccmr1 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	4640	}
<>	144:ef7eb2e8f9f7	4641	else
<>	144:ef7eb2e8f9f7	4642	{
<>	144:ef7eb2e8f9f7	4643	tmpccmr1 &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4644	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
<>	144:ef7eb2e8f9f7	4645	}
<>	144:ef7eb2e8f9f7	4646
<>	144:ef7eb2e8f9f7	4647	/* Set the filter */
<>	144:ef7eb2e8f9f7	4648	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	151:5eaa88a5bcc7	4649	tmpccmr1 \|= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
<>	144:ef7eb2e8f9f7	4650
<>	144:ef7eb2e8f9f7	4651	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	4652	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	4653	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
<>	144:ef7eb2e8f9f7	4654
<>	144:ef7eb2e8f9f7	4655	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	4656	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	4657	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4658	}
<>	144:ef7eb2e8f9f7	4659
<>	144:ef7eb2e8f9f7	4660	/**
<>	144:ef7eb2e8f9f7	4661	* @brief Configure the Polarity and Filter for TI1.
<>	144:ef7eb2e8f9f7	4662	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	4663	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	4664	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4665	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	4666	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	4667	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	4668	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	4669	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	4670	* @retval None
<>	144:ef7eb2e8f9f7	4671	*/
<>	144:ef7eb2e8f9f7	4672	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	4673	{
<>	151:5eaa88a5bcc7	4674	uint32_t tmpccmr1 = 0U;
<>	151:5eaa88a5bcc7	4675	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4676
<>	144:ef7eb2e8f9f7	4677	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4678	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4679	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4680	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4681
<>	144:ef7eb2e8f9f7	4682	/* Set the filter */
<>	144:ef7eb2e8f9f7	4683	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	151:5eaa88a5bcc7	4684	tmpccmr1 \|= (TIM_ICFilter << 4U);
<>	144:ef7eb2e8f9f7	4685
<>	144:ef7eb2e8f9f7	4686	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	4687	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	4688	tmpccer \|= TIM_ICPolarity;
<>	144:ef7eb2e8f9f7	4689
<>	144:ef7eb2e8f9f7	4690	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	4691	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	4692	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4693	}
<>	144:ef7eb2e8f9f7	4694
<>	144:ef7eb2e8f9f7	4695	/**
<>	144:ef7eb2e8f9f7	4696	* @brief Configure the TI2 as Input.
<>	144:ef7eb2e8f9f7	4697	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4698	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	4699	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4700	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	4701	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	4702	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	4703	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	4704	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4705	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	4706	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	4707	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	4708	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	4709	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	4710	* @retval None
<>	144:ef7eb2e8f9f7	4711	*/
<>	144:ef7eb2e8f9f7	4712	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	4713	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	4714	{
<>	151:5eaa88a5bcc7	4715	uint32_t tmpccmr1 = 0U;
<>	151:5eaa88a5bcc7	4716	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4717
<>	144:ef7eb2e8f9f7	4718	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4719	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	4720	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4721	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4722
<>	144:ef7eb2e8f9f7	4723	/* Select the Input */
<>	144:ef7eb2e8f9f7	4724	tmpccmr1 &= ~TIM_CCMR1_CC2S;
<>	151:5eaa88a5bcc7	4725	tmpccmr1 \|= (TIM_ICSelection << 8U);
<>	144:ef7eb2e8f9f7	4726
<>	144:ef7eb2e8f9f7	4727	/* Set the filter */
<>	144:ef7eb2e8f9f7	4728	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	151:5eaa88a5bcc7	4729	tmpccmr1 \|= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
<>	144:ef7eb2e8f9f7	4730
<>	144:ef7eb2e8f9f7	4731	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	4732	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	151:5eaa88a5bcc7	4733	tmpccer \|= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
<>	144:ef7eb2e8f9f7	4734
<>	144:ef7eb2e8f9f7	4735	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	4736	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	4737	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4738	}
<>	144:ef7eb2e8f9f7	4739
<>	144:ef7eb2e8f9f7	4740	/**
<>	144:ef7eb2e8f9f7	4741	* @brief Configure the Polarity and Filter for TI2.
<>	144:ef7eb2e8f9f7	4742	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	4743	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	4744	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4745	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	4746	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	4747	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	4748	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	4749	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	4750	* @retval None
<>	144:ef7eb2e8f9f7	4751	*/
<>	144:ef7eb2e8f9f7	4752	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	4753	{
<>	151:5eaa88a5bcc7	4754	uint32_t tmpccmr1 = 0U;
<>	151:5eaa88a5bcc7	4755	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4756
<>	144:ef7eb2e8f9f7	4757	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4758	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	4759	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4760	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4761
<>	144:ef7eb2e8f9f7	4762	/* Set the filter */
<>	144:ef7eb2e8f9f7	4763	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	151:5eaa88a5bcc7	4764	tmpccmr1 \|= (TIM_ICFilter << 12U);
<>	144:ef7eb2e8f9f7	4765
<>	144:ef7eb2e8f9f7	4766	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	4767	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	151:5eaa88a5bcc7	4768	tmpccer \|= (TIM_ICPolarity << 4U);
<>	144:ef7eb2e8f9f7	4769
<>	144:ef7eb2e8f9f7	4770	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	4771	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	4772	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4773	}
<>	144:ef7eb2e8f9f7	4774
<>	144:ef7eb2e8f9f7	4775	/**
<>	144:ef7eb2e8f9f7	4776	* @brief Configure the TI3 as Input.
<>	144:ef7eb2e8f9f7	4777	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4778	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	4779	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4780	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	4781	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	4782	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	4783	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	4784	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4785	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	4786	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	4787	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	4788	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	4789	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	4790	* @retval None
<>	144:ef7eb2e8f9f7	4791	*/
<>	144:ef7eb2e8f9f7	4792	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	4793	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	4794	{
<>	151:5eaa88a5bcc7	4795	uint32_t tmpccmr2 = 0U;
<>	151:5eaa88a5bcc7	4796	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4797
<>	144:ef7eb2e8f9f7	4798	/* Disable the Channel 3: Reset the CC3E Bit */
<>	144:ef7eb2e8f9f7	4799	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	4800	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4801	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4802
<>	144:ef7eb2e8f9f7	4803	/* Select the Input */
<>	144:ef7eb2e8f9f7	4804	tmpccmr2 &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	4805	tmpccmr2 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	4806
<>	144:ef7eb2e8f9f7	4807	/* Set the filter */
<>	144:ef7eb2e8f9f7	4808	tmpccmr2 &= ~TIM_CCMR2_IC3F;
<>	151:5eaa88a5bcc7	4809	tmpccmr2 \|= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
<>	144:ef7eb2e8f9f7	4810
<>	144:ef7eb2e8f9f7	4811	/* Select the Polarity and set the CC3E Bit */
<>	144:ef7eb2e8f9f7	4812	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
<>	151:5eaa88a5bcc7	4813	tmpccer \|= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
<>	144:ef7eb2e8f9f7	4814
<>	144:ef7eb2e8f9f7	4815	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	4816	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	4817	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4818	}
<>	144:ef7eb2e8f9f7	4819
<>	144:ef7eb2e8f9f7	4820	/**
<>	144:ef7eb2e8f9f7	4821	* @brief Configure the TI4 as Input.
<>	144:ef7eb2e8f9f7	4822	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4823	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	4824	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4825	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	4826	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	4827	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	4828	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	4829	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4830	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	4831	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	4832	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	4833	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	4834	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	4835	* @retval None
<>	144:ef7eb2e8f9f7	4836	*/
<>	144:ef7eb2e8f9f7	4837	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	4838	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	4839	{
<>	151:5eaa88a5bcc7	4840	uint32_t tmpccmr2 = 0U;
<>	151:5eaa88a5bcc7	4841	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4842
<>	144:ef7eb2e8f9f7	4843	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	4844	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	4845	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4846	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4847
<>	144:ef7eb2e8f9f7	4848	/* Select the Input */
<>	144:ef7eb2e8f9f7	4849	tmpccmr2 &= ~TIM_CCMR2_CC4S;
<>	151:5eaa88a5bcc7	4850	tmpccmr2 \|= (TIM_ICSelection << 8U);
<>	144:ef7eb2e8f9f7	4851
<>	144:ef7eb2e8f9f7	4852	/* Set the filter */
<>	144:ef7eb2e8f9f7	4853	tmpccmr2 &= ~TIM_CCMR2_IC4F;
<>	151:5eaa88a5bcc7	4854	tmpccmr2 \|= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
<>	144:ef7eb2e8f9f7	4855
<>	144:ef7eb2e8f9f7	4856	/* Select the Polarity and set the CC4E Bit */
<>	144:ef7eb2e8f9f7	4857	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
<>	151:5eaa88a5bcc7	4858	tmpccer \|= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
<>	144:ef7eb2e8f9f7	4859
<>	144:ef7eb2e8f9f7	4860	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	4861	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	4862	TIMx->CCER = tmpccer ;
<>	144:ef7eb2e8f9f7	4863	}
<>	144:ef7eb2e8f9f7	4864
<>	144:ef7eb2e8f9f7	4865	/**
<>	144:ef7eb2e8f9f7	4866	* @brief Selects the Input Trigger source
<>	144:ef7eb2e8f9f7	4867	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4868	* @param InputTriggerSource: The Input Trigger source.
<>	144:ef7eb2e8f9f7	4869	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4870	* @arg TIM_TS_ITR0: Internal Trigger 0
<>	144:ef7eb2e8f9f7	4871	* @arg TIM_TS_ITR1: Internal Trigger 1
<>	144:ef7eb2e8f9f7	4872	* @arg TIM_TS_ITR2: Internal Trigger 2
<>	144:ef7eb2e8f9f7	4873	* @arg TIM_TS_ITR3: Internal Trigger 3
<>	144:ef7eb2e8f9f7	4874	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
<>	144:ef7eb2e8f9f7	4875	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
<>	144:ef7eb2e8f9f7	4876	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
<>	144:ef7eb2e8f9f7	4877	* @arg TIM_TS_ETRF: External Trigger input
<>	144:ef7eb2e8f9f7	4878	* @retval None
<>	144:ef7eb2e8f9f7	4879	*/
<>	144:ef7eb2e8f9f7	4880	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<>	144:ef7eb2e8f9f7	4881	{
<>	151:5eaa88a5bcc7	4882	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	4883
<>	144:ef7eb2e8f9f7	4884	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	4885	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	4886	/* Reset the TS Bits */
<>	144:ef7eb2e8f9f7	4887	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	4888	/* Set the Input Trigger source and the slave mode*/
<>	144:ef7eb2e8f9f7	4889	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
<>	144:ef7eb2e8f9f7	4890	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	4891	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	4892	}
<>	144:ef7eb2e8f9f7	4893	/**
<>	144:ef7eb2e8f9f7	4894	* @brief Configures the TIMx External Trigger (ETR).
<>	144:ef7eb2e8f9f7	4895	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4896	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
<>	144:ef7eb2e8f9f7	4897	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4898	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
<>	144:ef7eb2e8f9f7	4899	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
<>	144:ef7eb2e8f9f7	4900	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
<>	144:ef7eb2e8f9f7	4901	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
<>	144:ef7eb2e8f9f7	4902	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
<>	144:ef7eb2e8f9f7	4903	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4904	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
<>	144:ef7eb2e8f9f7	4905	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
<>	144:ef7eb2e8f9f7	4906	* @param ExtTRGFilter: External Trigger Filter.
<>	144:ef7eb2e8f9f7	4907	* This parameter must be a value between 0x00 and 0x0F
<>	144:ef7eb2e8f9f7	4908	* @retval None
<>	144:ef7eb2e8f9f7	4909	*/
<>	144:ef7eb2e8f9f7	4910	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<>	144:ef7eb2e8f9f7	4911	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<>	144:ef7eb2e8f9f7	4912	{
<>	151:5eaa88a5bcc7	4913	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	4914
<>	144:ef7eb2e8f9f7	4915	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	4916
<>	144:ef7eb2e8f9f7	4917	/* Reset the ETR Bits */
<>	144:ef7eb2e8f9f7	4918	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	4919
<>	144:ef7eb2e8f9f7	4920	/* Set the Prescaler, the Filter value and the Polarity */
<>	144:ef7eb2e8f9f7	4921	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
<>	144:ef7eb2e8f9f7	4922
<>	144:ef7eb2e8f9f7	4923	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	4924	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	4925	}
<>	144:ef7eb2e8f9f7	4926
<>	144:ef7eb2e8f9f7	4927	/**
<>	144:ef7eb2e8f9f7	4928	* @brief Enables or disables the TIM Capture Compare Channel x.
<>	144:ef7eb2e8f9f7	4929	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4930	* @param Channel: specifies the TIM Channel
<>	144:ef7eb2e8f9f7	4931	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4932	* @arg TIM_Channel_1: TIM Channel 1
<>	144:ef7eb2e8f9f7	4933	* @arg TIM_Channel_2: TIM Channel 2
<>	144:ef7eb2e8f9f7	4934	* @arg TIM_Channel_3: TIM Channel 3
<>	144:ef7eb2e8f9f7	4935	* @arg TIM_Channel_4: TIM Channel 4
<>	144:ef7eb2e8f9f7	4936	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
<>	144:ef7eb2e8f9f7	4937	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<>	144:ef7eb2e8f9f7	4938	* @retval None
<>	144:ef7eb2e8f9f7	4939	*/
<>	144:ef7eb2e8f9f7	4940	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<>	144:ef7eb2e8f9f7	4941	{
<>	151:5eaa88a5bcc7	4942	uint32_t tmp = 0U;
<>	144:ef7eb2e8f9f7	4943
<>	144:ef7eb2e8f9f7	4944	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4945	assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel));
<>	144:ef7eb2e8f9f7	4946
<>	144:ef7eb2e8f9f7	4947	tmp = TIM_CCER_CC1E << Channel;
<>	144:ef7eb2e8f9f7	4948
<>	144:ef7eb2e8f9f7	4949	/* Reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	4950	TIMx->CCER &= ~tmp;
<>	144:ef7eb2e8f9f7	4951
<>	144:ef7eb2e8f9f7	4952	/* Set or reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	4953	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
<>	144:ef7eb2e8f9f7	4954	}
<>	144:ef7eb2e8f9f7	4955	/**
<>	144:ef7eb2e8f9f7	4956	* @brief Set the slave timer configuration.
<>	144:ef7eb2e8f9f7	4957	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4958	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	4959	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	4960	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	4961	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	4962	* @retval None
<>	144:ef7eb2e8f9f7	4963	*/
<>	144:ef7eb2e8f9f7	4964	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	4965	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	4966	{
<>	151:5eaa88a5bcc7	4967	uint32_t tmpsmcr = 0U;
<>	151:5eaa88a5bcc7	4968	uint32_t tmpccmr1 = 0U;
<>	151:5eaa88a5bcc7	4969	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4970
<>	144:ef7eb2e8f9f7	4971	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	4972	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	4973
<>	144:ef7eb2e8f9f7	4974	/* Reset the Trigger Selection Bits */
<>	144:ef7eb2e8f9f7	4975	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	4976	/* Set the Input Trigger source */
<>	144:ef7eb2e8f9f7	4977	tmpsmcr \|= sSlaveConfig->InputTrigger;
<>	144:ef7eb2e8f9f7	4978
<>	144:ef7eb2e8f9f7	4979	/* Reset the slave mode Bits */
<>	144:ef7eb2e8f9f7	4980	tmpsmcr &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	4981	/* Set the slave mode */
<>	144:ef7eb2e8f9f7	4982	tmpsmcr \|= sSlaveConfig->SlaveMode;
<>	144:ef7eb2e8f9f7	4983
<>	144:ef7eb2e8f9f7	4984	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	4985	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	4986
<>	144:ef7eb2e8f9f7	4987	/* Configure the trigger prescaler, filter, and polarity */
<>	144:ef7eb2e8f9f7	4988	switch (sSlaveConfig->InputTrigger)
<>	144:ef7eb2e8f9f7	4989	{
<>	144:ef7eb2e8f9f7	4990	case TIM_TS_ETRF:
<>	144:ef7eb2e8f9f7	4991	{
<>	144:ef7eb2e8f9f7	4992	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4993	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4994	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<>	144:ef7eb2e8f9f7	4995	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	4996	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4997	/* Configure the ETR Trigger source */
<>	144:ef7eb2e8f9f7	4998	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	4999	sSlaveConfig->TriggerPrescaler,
<>	144:ef7eb2e8f9f7	5000	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	5001	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	5002	}
<>	144:ef7eb2e8f9f7	5003	break;
<>	144:ef7eb2e8f9f7	5004
<>	144:ef7eb2e8f9f7	5005	case TIM_TS_TI1F_ED:
<>	144:ef7eb2e8f9f7	5006	{
<>	144:ef7eb2e8f9f7	5007	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5008	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5009	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	5010
<>	144:ef7eb2e8f9f7	5011	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	5012	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	5013	htim->Instance->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	5014	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	5015
<>	144:ef7eb2e8f9f7	5016	/* Set the filter */
<>	144:ef7eb2e8f9f7	5017	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	151:5eaa88a5bcc7	5018	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4U);
<>	144:ef7eb2e8f9f7	5019
<>	144:ef7eb2e8f9f7	5020	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5021	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	5022	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5023
<>	144:ef7eb2e8f9f7	5024	}
<>	144:ef7eb2e8f9f7	5025	break;
<>	144:ef7eb2e8f9f7	5026
<>	144:ef7eb2e8f9f7	5027	case TIM_TS_TI1FP1:
<>	144:ef7eb2e8f9f7	5028	{
<>	144:ef7eb2e8f9f7	5029	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5030	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5031	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	5032	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	5033
<>	144:ef7eb2e8f9f7	5034	/* Configure TI1 Filter and Polarity */
<>	144:ef7eb2e8f9f7	5035	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	5036	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	5037	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	5038	}
<>	144:ef7eb2e8f9f7	5039	break;
<>	144:ef7eb2e8f9f7	5040
<>	144:ef7eb2e8f9f7	5041	case TIM_TS_TI2FP2:
<>	144:ef7eb2e8f9f7	5042	{
<>	144:ef7eb2e8f9f7	5043	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5044	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5045	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	5046	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	5047
<>	144:ef7eb2e8f9f7	5048	/* Configure TI2 Filter and Polarity */
<>	144:ef7eb2e8f9f7	5049	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	5050	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	5051	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	5052	}
<>	144:ef7eb2e8f9f7	5053	break;
<>	144:ef7eb2e8f9f7	5054
<>	144:ef7eb2e8f9f7	5055	case TIM_TS_ITR0:
<>	144:ef7eb2e8f9f7	5056	{
<>	144:ef7eb2e8f9f7	5057	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5058	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5059	}
<>	144:ef7eb2e8f9f7	5060	break;
<>	144:ef7eb2e8f9f7	5061
<>	144:ef7eb2e8f9f7	5062	case TIM_TS_ITR1:
<>	144:ef7eb2e8f9f7	5063	{
<>	144:ef7eb2e8f9f7	5064	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5065	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5066	}
<>	144:ef7eb2e8f9f7	5067	break;
<>	144:ef7eb2e8f9f7	5068
<>	144:ef7eb2e8f9f7	5069	case TIM_TS_ITR2:
<>	144:ef7eb2e8f9f7	5070	{
<>	144:ef7eb2e8f9f7	5071	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5072	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5073	}
<>	144:ef7eb2e8f9f7	5074	break;
<>	144:ef7eb2e8f9f7	5075
<>	144:ef7eb2e8f9f7	5076	case TIM_TS_ITR3:
<>	144:ef7eb2e8f9f7	5077	{
<>	144:ef7eb2e8f9f7	5078	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5079	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5080	}
<>	144:ef7eb2e8f9f7	5081	break;
<>	144:ef7eb2e8f9f7	5082
<>	144:ef7eb2e8f9f7	5083	default:
<>	144:ef7eb2e8f9f7	5084	break;
<>	144:ef7eb2e8f9f7	5085	}
<>	144:ef7eb2e8f9f7	5086	}
<>	144:ef7eb2e8f9f7	5087
<>	144:ef7eb2e8f9f7	5088	/**
<>	144:ef7eb2e8f9f7	5089	* @}
<>	144:ef7eb2e8f9f7	5090	*/
<>	144:ef7eb2e8f9f7	5091
<>	144:ef7eb2e8f9f7	5092	/**
<>	144:ef7eb2e8f9f7	5093	* @}
<>	144:ef7eb2e8f9f7	5094	*/
<>	144:ef7eb2e8f9f7	5095
<>	144:ef7eb2e8f9f7	5096	/**
<>	144:ef7eb2e8f9f7	5097	* @}
<>	144:ef7eb2e8f9f7	5098	*/
<>	144:ef7eb2e8f9f7	5099
<>	144:ef7eb2e8f9f7	5100	/**
<>	144:ef7eb2e8f9f7	5101	* @}
<>	144:ef7eb2e8f9f7	5102	*/
<>	144:ef7eb2e8f9f7	5103
<>	144:ef7eb2e8f9f7	5104	#endif /* HAL_TIM_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5105
<>	144:ef7eb2e8f9f7	5106	/**
<>	144:ef7eb2e8f9f7	5107	* @}
<>	144:ef7eb2e8f9f7	5108	*/
<>	144:ef7eb2e8f9f7	5109	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	5110