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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.c@151:5eaa88a5bcc7, 2016-11-24 (annotated)

Committer:
<>
Date:
Thu Nov 24 17:03:03 2016 +0000
Revision:
151:5eaa88a5bcc7
Parent:
149:156823d33999
Child:
186:707f6e361f3e
This updates the lib to the mbed lib v130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_tim.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer (TIM) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Timer Base Initialization
<> 144:ef7eb2e8f9f7 11 * + Timer Base Start
<> 144:ef7eb2e8f9f7 12 * + Timer Base Start Interruption
<> 144:ef7eb2e8f9f7 13 * + Timer Base Start DMA
<> 144:ef7eb2e8f9f7 14 * + Timer Output Compare/PWM Initialization
<> 144:ef7eb2e8f9f7 15 * + Timer Output Compare/PWM Channel Configuration
<> 144:ef7eb2e8f9f7 16 * + Timer Output Compare/PWM Start
<> 144:ef7eb2e8f9f7 17 * + Timer Output Compare/PWM Start Interruption
<> 144:ef7eb2e8f9f7 18 * + Timer Output Compare/PWM Start DMA
<> 144:ef7eb2e8f9f7 19 * + Timer Input Capture Initialization
<> 144:ef7eb2e8f9f7 20 * + Timer Input Capture Channel Configuration
<> 144:ef7eb2e8f9f7 21 * + Timer Input Capture Start
<> 144:ef7eb2e8f9f7 22 * + Timer Input Capture Start Interruption
<> 144:ef7eb2e8f9f7 23 * + Timer Input Capture Start DMA
<> 144:ef7eb2e8f9f7 24 * + Timer One Pulse Initialization
<> 144:ef7eb2e8f9f7 25 * + Timer One Pulse Channel Configuration
<> 144:ef7eb2e8f9f7 26 * + Timer One Pulse Start
<> 144:ef7eb2e8f9f7 27 * + Timer Encoder Interface Initialization
<> 144:ef7eb2e8f9f7 28 * + Timer Encoder Interface Start
<> 144:ef7eb2e8f9f7 29 * + Timer Encoder Interface Start Interruption
<> 144:ef7eb2e8f9f7 30 * + Timer Encoder Interface Start DMA
<> 144:ef7eb2e8f9f7 31 * + Timer OCRef clear configuration
<> 144:ef7eb2e8f9f7 32 * + Timer External Clock configuration
<> 144:ef7eb2e8f9f7 33 * + Timer Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 34 * + Timer Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 35 @verbatim
<> 144:ef7eb2e8f9f7 36 ==============================================================================
<> 144:ef7eb2e8f9f7 37 ##### TIMER Generic features #####
<> 144:ef7eb2e8f9f7 38 ==============================================================================
<> 144:ef7eb2e8f9f7 39 [..] The Timer features include:
<> 144:ef7eb2e8f9f7 40 (#) 16-bit up, down, up/down auto-reload counter.
<> 144:ef7eb2e8f9f7 41 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
<> 144:ef7eb2e8f9f7 42 frequency either by any factor between 1 and 65536.
<> 144:ef7eb2e8f9f7 43 (#) Up to 4 independent channels for:
<> 144:ef7eb2e8f9f7 44 (++) Input Capture
<> 144:ef7eb2e8f9f7 45 (++) Output Compare
<> 144:ef7eb2e8f9f7 46 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 47 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 48 (#) Synchronization circuit to control the timer with external signals and to interconnect
<> 144:ef7eb2e8f9f7 49 several timers together.
<> 144:ef7eb2e8f9f7 50 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
<> 144:ef7eb2e8f9f7 51 purposes
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 54 ================================================================================
<> 144:ef7eb2e8f9f7 55 [..]
<> 144:ef7eb2e8f9f7 56 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 57 depending from feature used :
<> 144:ef7eb2e8f9f7 58 (++) Time Base : HAL_TIM_Base_MspInit()
<> 144:ef7eb2e8f9f7 59 (++) Input Capture : HAL_TIM_IC_MspInit()
<> 144:ef7eb2e8f9f7 60 (++) Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 61 (++) PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 62 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 63 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 66 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 67 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 68 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 69 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 70 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
<> 144:ef7eb2e8f9f7 73 using the following function:
<> 144:ef7eb2e8f9f7 74 HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 77 initialization function of this driver:
<> 144:ef7eb2e8f9f7 78 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<> 144:ef7eb2e8f9f7 79 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<> 144:ef7eb2e8f9f7 80 Output Compare signal.
<> 144:ef7eb2e8f9f7 81 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<> 144:ef7eb2e8f9f7 82 PWM signal.
<> 144:ef7eb2e8f9f7 83 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<> 144:ef7eb2e8f9f7 84 external signal.
<> 144:ef7eb2e8f9f7 85 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode.
<> 144:ef7eb2e8f9f7 86 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 89 HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(),
<> 144:ef7eb2e8f9f7 90 HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(),
<> 144:ef7eb2e8f9f7 91 HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(),
<> 144:ef7eb2e8f9f7 92 HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(),
<> 144:ef7eb2e8f9f7 93 HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(),
<> 144:ef7eb2e8f9f7 94 HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT()
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 (#) The DMA Burst is managed with the two following functions:
<> 144:ef7eb2e8f9f7 97 HAL_TIM_DMABurst_WriteStart
<> 144:ef7eb2e8f9f7 98 HAL_TIM_DMABurst_ReadStart
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 @endverbatim
<> 144:ef7eb2e8f9f7 101 ******************************************************************************
<> 144:ef7eb2e8f9f7 102 * @attention
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 107 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 108 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 109 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 110 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 111 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 112 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 113 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 114 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 115 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 118 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 119 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 120 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 121 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 122 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 123 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 124 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 125 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 126 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 127 *
<> 144:ef7eb2e8f9f7 128 ******************************************************************************
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @addtogroup TIM
<> 144:ef7eb2e8f9f7 141 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 142 * @{
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @addtogroup TIM_Private
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 150 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 151 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 152 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 153 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
<> 144:ef7eb2e8f9f7 154 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 155 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 156 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 157 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 158 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 159 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 160 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 161 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 162 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 163 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 164 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
<> 144:ef7eb2e8f9f7 165 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<> 144:ef7eb2e8f9f7 166 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<> 144:ef7eb2e8f9f7 167 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 168 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 169 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 175 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 176 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @addtogroup TIM_Exported_Functions
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** @addtogroup TIM_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 183 * @brief Time Base functions
<> 144:ef7eb2e8f9f7 184 *
<> 144:ef7eb2e8f9f7 185 @verbatim
<> 144:ef7eb2e8f9f7 186 ==============================================================================
<> 144:ef7eb2e8f9f7 187 ##### Timer Base functions #####
<> 144:ef7eb2e8f9f7 188 ==============================================================================
<> 144:ef7eb2e8f9f7 189 [..]
<> 144:ef7eb2e8f9f7 190 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 191 (+) Initialize and configure the TIM base.
<> 144:ef7eb2e8f9f7 192 (+) De-initialize the TIM base.
<> 144:ef7eb2e8f9f7 193 (+) Start the Timer Base.
<> 144:ef7eb2e8f9f7 194 (+) Stop the Timer Base.
<> 144:ef7eb2e8f9f7 195 (+) Start the Timer Base and enable interrupt.
<> 144:ef7eb2e8f9f7 196 (+) Stop the Timer Base and disable interrupt.
<> 144:ef7eb2e8f9f7 197 (+) Start the Timer Base and enable DMA transfer.
<> 144:ef7eb2e8f9f7 198 (+) Stop the Timer Base and disable DMA transfer.
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 @endverbatim
<> 144:ef7eb2e8f9f7 201 * @{
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @brief Initializes the TIM Time base Unit according to the specified
<> 144:ef7eb2e8f9f7 205 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 206 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 207 * @retval HAL status
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 212 if(htim == NULL)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Check the parameters */
<> 144:ef7eb2e8f9f7 218 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 220 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 221 assert_param(IS_TIM_PERIOD(htim->Init.Period));
<> 144:ef7eb2e8f9f7 222 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 227 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 230 HAL_TIM_Base_MspInit(htim);
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 234 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Set the Time Base configuration */
<> 144:ef7eb2e8f9f7 237 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 240 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 return HAL_OK;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @brief DeInitializes the TIM Base peripheral
<> 144:ef7eb2e8f9f7 247 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 248 * @retval HAL status
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 /* Check the parameters */
<> 144:ef7eb2e8f9f7 253 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 258 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 261 HAL_TIM_Base_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Change TIM state */
<> 144:ef7eb2e8f9f7 264 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Release Lock */
<> 144:ef7eb2e8f9f7 267 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 return HAL_OK;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief Initializes the TIM Base MSP.
<> 144:ef7eb2e8f9f7 274 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 275 * @retval None
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 280 UNUSED(htim);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 283 the HAL_TIM_Base_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @brief DeInitializes TIM Base MSP.
<> 144:ef7eb2e8f9f7 289 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 290 * @retval None
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 295 UNUSED(htim);
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 298 the HAL_TIM_Base_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @brief Starts the TIM Base generation.
<> 144:ef7eb2e8f9f7 304 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 305 * @retval HAL status
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 /* Check the parameters */
<> 144:ef7eb2e8f9f7 310 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 313 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 316 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 319 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Return function status */
<> 144:ef7eb2e8f9f7 322 return HAL_OK;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Stops the TIM Base generation.
<> 144:ef7eb2e8f9f7 327 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 328 * @retval HAL status
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 /* Check the parameters */
<> 144:ef7eb2e8f9f7 333 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 336 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 339 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 342 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Return function status */
<> 144:ef7eb2e8f9f7 345 return HAL_OK;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @brief Starts the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 350 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 351 * @retval HAL status
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 /* Check the parameters */
<> 144:ef7eb2e8f9f7 356 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Enable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 359 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 362 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Return function status */
<> 144:ef7eb2e8f9f7 365 return HAL_OK;
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @brief Stops the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 370 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 371 * @retval HAL status
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 /* Check the parameters */
<> 144:ef7eb2e8f9f7 376 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 377 /* Disable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 378 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 381 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Return function status */
<> 144:ef7eb2e8f9f7 384 return HAL_OK;
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @brief Starts the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 389 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 390 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 391 * @param Length: The length of data to be transferred from memory to peripheral.
<> 144:ef7eb2e8f9f7 392 * @retval HAL status
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 /* Check the parameters */
<> 144:ef7eb2e8f9f7 397 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 404 {
<> 151:5eaa88a5bcc7 405 if((pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409 else
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 415 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 418 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 421 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Enable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 424 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 427 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Return function status */
<> 144:ef7eb2e8f9f7 430 return HAL_OK;
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @brief Stops the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 435 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 436 * @retval HAL status
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 /* Check the parameters */
<> 144:ef7eb2e8f9f7 441 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 444 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 447 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Change the htim state */
<> 144:ef7eb2e8f9f7 450 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Return function status */
<> 144:ef7eb2e8f9f7 453 return HAL_OK;
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @}
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /** @addtogroup TIM_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 462 * @brief Time Output Compare functions
<> 144:ef7eb2e8f9f7 463 *
<> 144:ef7eb2e8f9f7 464 @verbatim
<> 144:ef7eb2e8f9f7 465 ==============================================================================
<> 144:ef7eb2e8f9f7 466 ##### Timer Output Compare functions #####
<> 144:ef7eb2e8f9f7 467 ==============================================================================
<> 144:ef7eb2e8f9f7 468 [..]
<> 144:ef7eb2e8f9f7 469 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 470 (+) Initialize and configure the TIM Output Compare.
<> 144:ef7eb2e8f9f7 471 (+) De-initialize the TIM Output Compare.
<> 144:ef7eb2e8f9f7 472 (+) Start the Timer Output Compare.
<> 144:ef7eb2e8f9f7 473 (+) Stop the Timer Output Compare.
<> 144:ef7eb2e8f9f7 474 (+) Start the Timer Output Compare and enable interrupt.
<> 144:ef7eb2e8f9f7 475 (+) Stop the Timer Output Compare and disable interrupt.
<> 144:ef7eb2e8f9f7 476 (+) Start the Timer Output Compare and enable DMA transfer.
<> 144:ef7eb2e8f9f7 477 (+) Stop the Timer Output Compare and disable DMA transfer.
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 @endverbatim
<> 144:ef7eb2e8f9f7 480 * @{
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @brief Initializes the TIM Output Compare according to the specified
<> 144:ef7eb2e8f9f7 484 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 485 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 486 * @retval HAL status
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 491 if(htim == NULL)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Check the parameters */
<> 144:ef7eb2e8f9f7 497 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 498 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 499 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 500 assert_param(IS_TIM_PERIOD(htim->Init.Period));
<> 144:ef7eb2e8f9f7 501 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 506 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/
<> 144:ef7eb2e8f9f7 509 HAL_TIM_OC_MspInit(htim);
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 512 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Init the base time for the Output Compare */
<> 144:ef7eb2e8f9f7 515 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 518 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 return HAL_OK;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /**
<> 144:ef7eb2e8f9f7 524 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 525 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 526 * @retval HAL status
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 /* Check the parameters */
<> 144:ef7eb2e8f9f7 531 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 536 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 539 HAL_TIM_OC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Change TIM state */
<> 144:ef7eb2e8f9f7 542 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Release Lock */
<> 144:ef7eb2e8f9f7 545 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 return HAL_OK;
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Initializes the TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 552 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 553 * @retval None
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 558 UNUSED(htim);
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 561 the HAL_TIM_OC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /**
<> 144:ef7eb2e8f9f7 566 * @brief DeInitializes TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 567 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 568 * @retval None
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 573 UNUSED(htim);
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 576 the HAL_TIM_OC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @brief Starts the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 582 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 583 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 584 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 585 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 586 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 587 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 588 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 589 * @retval HAL status
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 /* Check the parameters */
<> 144:ef7eb2e8f9f7 594 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 597 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 600 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Return function status */
<> 144:ef7eb2e8f9f7 603 return HAL_OK;
<> 144:ef7eb2e8f9f7 604 }
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @brief Stops the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 608 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 609 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 610 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 611 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 612 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 613 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 614 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 615 * @retval HAL status
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 /* Check the parameters */
<> 144:ef7eb2e8f9f7 620 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 623 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 626 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Return function status */
<> 144:ef7eb2e8f9f7 629 return HAL_OK;
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /**
<> 144:ef7eb2e8f9f7 633 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 634 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 635 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 636 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 637 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 638 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 639 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 640 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 641 * @retval HAL status
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 /* Check the parameters */
<> 144:ef7eb2e8f9f7 646 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 switch (Channel)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 653 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655 break;
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 660 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662 break;
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 667 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669 break;
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 674 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 break;
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 default:
<> 144:ef7eb2e8f9f7 679 break;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 683 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 686 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Return function status */
<> 144:ef7eb2e8f9f7 689 return HAL_OK;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /**
<> 144:ef7eb2e8f9f7 693 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 694 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 695 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 696 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 697 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 698 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 699 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 700 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 701 * @retval HAL status
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 /* Check the parameters */
<> 144:ef7eb2e8f9f7 706 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 switch (Channel)
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 713 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715 break;
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 720 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722 break;
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 727 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 break;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 734 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736 break;
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 default:
<> 144:ef7eb2e8f9f7 739 break;
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 743 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 746 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Return function status */
<> 144:ef7eb2e8f9f7 749 return HAL_OK;
<> 144:ef7eb2e8f9f7 750 }
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /**
<> 144:ef7eb2e8f9f7 753 * @brief Starts the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 754 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 755 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 756 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 757 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 758 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 759 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 760 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 761 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 762 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 763 * @retval HAL status
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 /* Check the parameters */
<> 144:ef7eb2e8f9f7 768 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 775 {
<> 151:5eaa88a5bcc7 776 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 777 {
<> 144:ef7eb2e8f9f7 778 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780 else
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784 }
<> 144:ef7eb2e8f9f7 785 switch (Channel)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 790 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 793 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 796 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 799 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801 break;
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 804 {
<> 144:ef7eb2e8f9f7 805 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 806 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 809 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 812 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 815 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 break;
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 822 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 825 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 828 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 831 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833 break;
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 838 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 841 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 844 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 847 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 break;
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 default:
<> 144:ef7eb2e8f9f7 852 break;
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 856 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 859 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Return function status */
<> 144:ef7eb2e8f9f7 862 return HAL_OK;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /**
<> 144:ef7eb2e8f9f7 866 * @brief Stops the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 867 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 868 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 869 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 870 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 871 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 872 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 873 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 874 * @retval HAL status
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 877 {
<> 144:ef7eb2e8f9f7 878 /* Check the parameters */
<> 144:ef7eb2e8f9f7 879 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 switch (Channel)
<> 144:ef7eb2e8f9f7 882 {
<> 144:ef7eb2e8f9f7 883 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 886 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888 break;
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 891 {
<> 144:ef7eb2e8f9f7 892 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 893 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895 break;
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 900 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902 break;
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 908 }
<> 144:ef7eb2e8f9f7 909 break;
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 default:
<> 144:ef7eb2e8f9f7 912 break;
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 916 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 919 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Change the htim state */
<> 144:ef7eb2e8f9f7 922 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Return function status */
<> 144:ef7eb2e8f9f7 925 return HAL_OK;
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /**
<> 144:ef7eb2e8f9f7 929 * @}
<> 144:ef7eb2e8f9f7 930 */
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /** @addtogroup TIM_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 933 * @brief Time PWM functions
<> 144:ef7eb2e8f9f7 934 *
<> 144:ef7eb2e8f9f7 935 @verbatim
<> 144:ef7eb2e8f9f7 936 ==============================================================================
<> 144:ef7eb2e8f9f7 937 ##### Timer PWM functions #####
<> 144:ef7eb2e8f9f7 938 ==============================================================================
<> 144:ef7eb2e8f9f7 939 [..]
<> 144:ef7eb2e8f9f7 940 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 941 (+) Initialize and configure the TIM OPWM.
<> 144:ef7eb2e8f9f7 942 (+) De-initialize the TIM PWM.
<> 144:ef7eb2e8f9f7 943 (+) Start the Timer PWM.
<> 144:ef7eb2e8f9f7 944 (+) Stop the Timer PWM.
<> 144:ef7eb2e8f9f7 945 (+) Start the Timer PWM and enable interrupt.
<> 144:ef7eb2e8f9f7 946 (+) Stop the Timer PWM and disable interrupt.
<> 144:ef7eb2e8f9f7 947 (+) Start the Timer PWM and enable DMA transfer.
<> 144:ef7eb2e8f9f7 948 (+) Stop the Timer PWM and disable DMA transfer.
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 @endverbatim
<> 144:ef7eb2e8f9f7 951 * @{
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953 /**
<> 144:ef7eb2e8f9f7 954 * @brief Initializes the TIM PWM Time Base according to the specified
<> 144:ef7eb2e8f9f7 955 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 956 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 957 * @retval HAL status
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 962 {
<> 144:ef7eb2e8f9f7 963 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 964 if(htim == NULL)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /* Check the parameters */
<> 144:ef7eb2e8f9f7 970 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 971 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 972 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 973 assert_param(IS_TIM_PERIOD(htim->Init.Period));
<> 144:ef7eb2e8f9f7 974 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 979 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 982 HAL_TIM_PWM_MspInit(htim);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 986 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Init the base time for the PWM */
<> 144:ef7eb2e8f9f7 989 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 992 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 return HAL_OK;
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /**
<> 144:ef7eb2e8f9f7 998 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 999 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1000 * @retval HAL status
<> 144:ef7eb2e8f9f7 1001 */
<> 144:ef7eb2e8f9f7 1002 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1005 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1010 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1013 HAL_TIM_PWM_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1016 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Release Lock */
<> 144:ef7eb2e8f9f7 1019 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 return HAL_OK;
<> 144:ef7eb2e8f9f7 1022 }
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /**
<> 144:ef7eb2e8f9f7 1025 * @brief Initializes the TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1026 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1027 * @retval None
<> 144:ef7eb2e8f9f7 1028 */
<> 144:ef7eb2e8f9f7 1029 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1030 {
<> 144:ef7eb2e8f9f7 1031 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1032 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1035 the HAL_TIM_PWM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1036 */
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /**
<> 144:ef7eb2e8f9f7 1040 * @brief DeInitializes TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1041 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1042 * @retval None
<> 144:ef7eb2e8f9f7 1043 */
<> 144:ef7eb2e8f9f7 1044 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1047 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1050 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1051 */
<> 144:ef7eb2e8f9f7 1052 }
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /**
<> 144:ef7eb2e8f9f7 1055 * @brief Starts the PWM signal generation.
<> 144:ef7eb2e8f9f7 1056 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1057 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1058 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1059 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1060 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1061 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1062 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1063 * @retval HAL status
<> 144:ef7eb2e8f9f7 1064 */
<> 144:ef7eb2e8f9f7 1065 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1068 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1071 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1074 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /* Return function status */
<> 144:ef7eb2e8f9f7 1077 return HAL_OK;
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /**
<> 144:ef7eb2e8f9f7 1081 * @brief Stops the PWM signal generation.
<> 144:ef7eb2e8f9f7 1082 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1083 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1084 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1085 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1086 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1087 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1088 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1089 * @retval HAL status
<> 144:ef7eb2e8f9f7 1090 */
<> 144:ef7eb2e8f9f7 1091 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1092 {
<> 144:ef7eb2e8f9f7 1093 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1094 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1097 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1100 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1103 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /* Return function status */
<> 144:ef7eb2e8f9f7 1106 return HAL_OK;
<> 144:ef7eb2e8f9f7 1107 }
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /**
<> 144:ef7eb2e8f9f7 1110 * @brief Starts the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1111 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1112 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1113 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1114 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1115 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1116 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1117 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1118 * @retval HAL status
<> 144:ef7eb2e8f9f7 1119 */
<> 144:ef7eb2e8f9f7 1120 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1121 {
<> 144:ef7eb2e8f9f7 1122 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1123 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 switch (Channel)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1130 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132 break;
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1135 {
<> 144:ef7eb2e8f9f7 1136 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1137 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1138 }
<> 144:ef7eb2e8f9f7 1139 break;
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1142 {
<> 144:ef7eb2e8f9f7 1143 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1144 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1145 }
<> 144:ef7eb2e8f9f7 1146 break;
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1151 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1152 }
<> 144:ef7eb2e8f9f7 1153 break;
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 default:
<> 144:ef7eb2e8f9f7 1156 break;
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1160 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1163 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* Return function status */
<> 144:ef7eb2e8f9f7 1166 return HAL_OK;
<> 144:ef7eb2e8f9f7 1167 }
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169 /**
<> 144:ef7eb2e8f9f7 1170 * @brief Stops the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1171 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1172 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1173 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1174 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1175 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1176 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1177 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1178 * @retval HAL status
<> 144:ef7eb2e8f9f7 1179 */
<> 144:ef7eb2e8f9f7 1180 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1181 {
<> 144:ef7eb2e8f9f7 1182 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1183 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 switch (Channel)
<> 144:ef7eb2e8f9f7 1186 {
<> 144:ef7eb2e8f9f7 1187 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1188 {
<> 144:ef7eb2e8f9f7 1189 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1190 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 break;
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1197 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199 break;
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1202 {
<> 144:ef7eb2e8f9f7 1203 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1204 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1205 }
<> 144:ef7eb2e8f9f7 1206 break;
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1209 {
<> 144:ef7eb2e8f9f7 1210 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1211 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1212 }
<> 144:ef7eb2e8f9f7 1213 break;
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 default:
<> 144:ef7eb2e8f9f7 1216 break;
<> 144:ef7eb2e8f9f7 1217 }
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1220 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1223 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* Return function status */
<> 144:ef7eb2e8f9f7 1226 return HAL_OK;
<> 144:ef7eb2e8f9f7 1227 }
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 /**
<> 144:ef7eb2e8f9f7 1230 * @brief Starts the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1231 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1232 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1233 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1234 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1235 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1236 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1237 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1238 * @param pData: The source Buffer address. This buffer contains the values
<> 144:ef7eb2e8f9f7 1239 * which will be loaded inside the capture/compare registers.
<> 144:ef7eb2e8f9f7 1240 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1241 * @retval HAL status
<> 144:ef7eb2e8f9f7 1242 */
<> 144:ef7eb2e8f9f7 1243 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1244 {
<> 144:ef7eb2e8f9f7 1245 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1246 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1249 {
<> 144:ef7eb2e8f9f7 1250 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1253 {
<> 151:5eaa88a5bcc7 1254 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1255 {
<> 144:ef7eb2e8f9f7 1256 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1257 }
<> 144:ef7eb2e8f9f7 1258 else
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1261 }
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263 switch (Channel)
<> 144:ef7eb2e8f9f7 1264 {
<> 144:ef7eb2e8f9f7 1265 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1266 {
<> 144:ef7eb2e8f9f7 1267 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1268 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1271 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1274 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1277 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1278 }
<> 144:ef7eb2e8f9f7 1279 break;
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1282 {
<> 144:ef7eb2e8f9f7 1283 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1284 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1287 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1290 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1293 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295 break;
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1298 {
<> 144:ef7eb2e8f9f7 1299 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1300 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1303 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1306 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /* Enable the TIM Output Capture/Compare 3 request */
<> 144:ef7eb2e8f9f7 1309 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1310 }
<> 144:ef7eb2e8f9f7 1311 break;
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1314 {
<> 144:ef7eb2e8f9f7 1315 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1316 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1319 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1322 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1325 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1326 }
<> 144:ef7eb2e8f9f7 1327 break;
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 default:
<> 144:ef7eb2e8f9f7 1330 break;
<> 144:ef7eb2e8f9f7 1331 }
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1334 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1337 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Return function status */
<> 144:ef7eb2e8f9f7 1340 return HAL_OK;
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /**
<> 144:ef7eb2e8f9f7 1344 * @brief Stops the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1345 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1346 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1347 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1348 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1349 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1350 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1351 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1352 * @retval HAL status
<> 144:ef7eb2e8f9f7 1353 */
<> 144:ef7eb2e8f9f7 1354 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1355 {
<> 144:ef7eb2e8f9f7 1356 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1357 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 switch (Channel)
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1362 {
<> 144:ef7eb2e8f9f7 1363 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1364 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1365 }
<> 144:ef7eb2e8f9f7 1366 break;
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1369 {
<> 144:ef7eb2e8f9f7 1370 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1371 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1372 }
<> 144:ef7eb2e8f9f7 1373 break;
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1376 {
<> 144:ef7eb2e8f9f7 1377 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1378 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1379 }
<> 144:ef7eb2e8f9f7 1380 break;
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1383 {
<> 144:ef7eb2e8f9f7 1384 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1385 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387 break;
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 default:
<> 144:ef7eb2e8f9f7 1390 break;
<> 144:ef7eb2e8f9f7 1391 }
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1394 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1397 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1400 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /* Return function status */
<> 144:ef7eb2e8f9f7 1403 return HAL_OK;
<> 144:ef7eb2e8f9f7 1404 }
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /**
<> 144:ef7eb2e8f9f7 1407 * @}
<> 144:ef7eb2e8f9f7 1408 */
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /** @addtogroup TIM_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 1411 * @brief Time Input Capture functions
<> 144:ef7eb2e8f9f7 1412 *
<> 144:ef7eb2e8f9f7 1413 @verbatim
<> 144:ef7eb2e8f9f7 1414 ==============================================================================
<> 144:ef7eb2e8f9f7 1415 ##### Timer Input Capture functions #####
<> 144:ef7eb2e8f9f7 1416 ==============================================================================
<> 144:ef7eb2e8f9f7 1417 [..]
<> 144:ef7eb2e8f9f7 1418 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1419 (+) Initialize and configure the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1420 (+) De-initialize the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1421 (+) Start the Timer Input Capture.
<> 144:ef7eb2e8f9f7 1422 (+) Stop the Timer Input Capture.
<> 144:ef7eb2e8f9f7 1423 (+) Start the Timer Input Capture and enable interrupt.
<> 144:ef7eb2e8f9f7 1424 (+) Stop the Timer Input Capture and disable interrupt.
<> 144:ef7eb2e8f9f7 1425 (+) Start the Timer Input Capture and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1426 (+) Stop the Timer Input Capture and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 @endverbatim
<> 144:ef7eb2e8f9f7 1429 * @{
<> 144:ef7eb2e8f9f7 1430 */
<> 144:ef7eb2e8f9f7 1431 /**
<> 144:ef7eb2e8f9f7 1432 * @brief Initializes the TIM Input Capture Time base according to the specified
<> 144:ef7eb2e8f9f7 1433 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1434 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1435 * @retval HAL status
<> 144:ef7eb2e8f9f7 1436 */
<> 144:ef7eb2e8f9f7 1437 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1438 {
<> 144:ef7eb2e8f9f7 1439 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1440 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1441 {
<> 144:ef7eb2e8f9f7 1442 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1443 }
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1446 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1447 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1448 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1449 assert_param(IS_TIM_PERIOD(htim->Init.Period));
<> 144:ef7eb2e8f9f7 1450 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1453 {
<> 144:ef7eb2e8f9f7 1454 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1455 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1458 HAL_TIM_IC_MspInit(htim);
<> 144:ef7eb2e8f9f7 1459 }
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1462 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 /* Init the base time for the input capture */
<> 144:ef7eb2e8f9f7 1465 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1468 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 return HAL_OK;
<> 144:ef7eb2e8f9f7 1471 }
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /**
<> 144:ef7eb2e8f9f7 1474 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1475 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1476 * @retval HAL status
<> 144:ef7eb2e8f9f7 1477 */
<> 144:ef7eb2e8f9f7 1478 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1479 {
<> 144:ef7eb2e8f9f7 1480 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1481 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1486 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1489 HAL_TIM_IC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1492 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 /* Release Lock */
<> 144:ef7eb2e8f9f7 1495 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 return HAL_OK;
<> 144:ef7eb2e8f9f7 1498 }
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /**
<> 144:ef7eb2e8f9f7 1501 * @brief Initializes the TIM INput Capture MSP.
<> 144:ef7eb2e8f9f7 1502 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1503 * @retval None
<> 144:ef7eb2e8f9f7 1504 */
<> 144:ef7eb2e8f9f7 1505 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1506 {
<> 144:ef7eb2e8f9f7 1507 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1508 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1511 the HAL_TIM_IC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1512 */
<> 144:ef7eb2e8f9f7 1513 }
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 /**
<> 144:ef7eb2e8f9f7 1516 * @brief DeInitializes TIM Input Capture MSP.
<> 144:ef7eb2e8f9f7 1517 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1518 * @retval None
<> 144:ef7eb2e8f9f7 1519 */
<> 144:ef7eb2e8f9f7 1520 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1523 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1526 the HAL_TIM_IC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1527 */
<> 144:ef7eb2e8f9f7 1528 }
<> 144:ef7eb2e8f9f7 1529 /**
<> 144:ef7eb2e8f9f7 1530 * @brief Starts the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1531 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1532 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1533 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1534 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1535 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1536 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1537 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1538 * @retval HAL status
<> 144:ef7eb2e8f9f7 1539 */
<> 144:ef7eb2e8f9f7 1540 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1541 {
<> 144:ef7eb2e8f9f7 1542 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1543 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1546 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1549 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 /* Return function status */
<> 144:ef7eb2e8f9f7 1552 return HAL_OK;
<> 144:ef7eb2e8f9f7 1553 }
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 /**
<> 144:ef7eb2e8f9f7 1556 * @brief Stops the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1557 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1558 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1559 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1560 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1561 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1562 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1563 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1564 * @retval HAL status
<> 144:ef7eb2e8f9f7 1565 */
<> 144:ef7eb2e8f9f7 1566 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1567 {
<> 144:ef7eb2e8f9f7 1568 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1569 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1572 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1575 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 /* Return function status */
<> 144:ef7eb2e8f9f7 1578 return HAL_OK;
<> 144:ef7eb2e8f9f7 1579 }
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 /**
<> 144:ef7eb2e8f9f7 1582 * @brief Starts the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1583 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1584 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1585 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1586 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1587 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1588 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1589 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1590 * @retval HAL status
<> 144:ef7eb2e8f9f7 1591 */
<> 144:ef7eb2e8f9f7 1592 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1593 {
<> 144:ef7eb2e8f9f7 1594 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1595 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 switch (Channel)
<> 144:ef7eb2e8f9f7 1598 {
<> 144:ef7eb2e8f9f7 1599 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1600 {
<> 144:ef7eb2e8f9f7 1601 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1602 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1603 }
<> 144:ef7eb2e8f9f7 1604 break;
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1607 {
<> 144:ef7eb2e8f9f7 1608 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1609 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1610 }
<> 144:ef7eb2e8f9f7 1611 break;
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1614 {
<> 144:ef7eb2e8f9f7 1615 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1616 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1617 }
<> 144:ef7eb2e8f9f7 1618 break;
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1621 {
<> 144:ef7eb2e8f9f7 1622 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1623 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1624 }
<> 144:ef7eb2e8f9f7 1625 break;
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 default:
<> 144:ef7eb2e8f9f7 1628 break;
<> 144:ef7eb2e8f9f7 1629 }
<> 144:ef7eb2e8f9f7 1630 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1631 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1634 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /* Return function status */
<> 144:ef7eb2e8f9f7 1637 return HAL_OK;
<> 144:ef7eb2e8f9f7 1638 }
<> 144:ef7eb2e8f9f7 1639
<> 144:ef7eb2e8f9f7 1640 /**
<> 144:ef7eb2e8f9f7 1641 * @brief Stops the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1642 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1643 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1644 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1645 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1646 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1647 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1648 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1649 * @retval HAL status
<> 144:ef7eb2e8f9f7 1650 */
<> 144:ef7eb2e8f9f7 1651 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1652 {
<> 144:ef7eb2e8f9f7 1653 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1654 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656 switch (Channel)
<> 144:ef7eb2e8f9f7 1657 {
<> 144:ef7eb2e8f9f7 1658 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1659 {
<> 144:ef7eb2e8f9f7 1660 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1661 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1662 }
<> 144:ef7eb2e8f9f7 1663 break;
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1666 {
<> 144:ef7eb2e8f9f7 1667 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1668 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1669 }
<> 144:ef7eb2e8f9f7 1670 break;
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1673 {
<> 144:ef7eb2e8f9f7 1674 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1675 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1676 }
<> 144:ef7eb2e8f9f7 1677 break;
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1682 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1683 }
<> 144:ef7eb2e8f9f7 1684 break;
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 default:
<> 144:ef7eb2e8f9f7 1687 break;
<> 144:ef7eb2e8f9f7 1688 }
<> 144:ef7eb2e8f9f7 1689
<> 144:ef7eb2e8f9f7 1690 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1691 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1694 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /* Return function status */
<> 144:ef7eb2e8f9f7 1697 return HAL_OK;
<> 144:ef7eb2e8f9f7 1698 }
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /**
<> 144:ef7eb2e8f9f7 1701 * @brief Starts the TIM Input Capture measurement on in DMA mode.
<> 144:ef7eb2e8f9f7 1702 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1703 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1704 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1708 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1709 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 1710 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 1711 * @retval HAL status
<> 144:ef7eb2e8f9f7 1712 */
<> 144:ef7eb2e8f9f7 1713 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1714 {
<> 144:ef7eb2e8f9f7 1715 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1716 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1717 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1720 {
<> 144:ef7eb2e8f9f7 1721 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1722 }
<> 144:ef7eb2e8f9f7 1723 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1724 {
<> 151:5eaa88a5bcc7 1725 if((pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1726 {
<> 144:ef7eb2e8f9f7 1727 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1728 }
<> 144:ef7eb2e8f9f7 1729 else
<> 144:ef7eb2e8f9f7 1730 {
<> 144:ef7eb2e8f9f7 1731 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1732 }
<> 144:ef7eb2e8f9f7 1733 }
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 switch (Channel)
<> 144:ef7eb2e8f9f7 1736 {
<> 144:ef7eb2e8f9f7 1737 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1738 {
<> 144:ef7eb2e8f9f7 1739 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1740 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1743 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1744
<> 144:ef7eb2e8f9f7 1745 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1746 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1749 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1750 }
<> 144:ef7eb2e8f9f7 1751 break;
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1754 {
<> 144:ef7eb2e8f9f7 1755 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1756 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1759 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1762 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1765 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1766 }
<> 144:ef7eb2e8f9f7 1767 break;
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1770 {
<> 144:ef7eb2e8f9f7 1771 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1772 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1773
<> 144:ef7eb2e8f9f7 1774 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1775 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1776
<> 144:ef7eb2e8f9f7 1777 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1778 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1779
<> 144:ef7eb2e8f9f7 1780 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1781 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1782 }
<> 144:ef7eb2e8f9f7 1783 break;
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1786 {
<> 144:ef7eb2e8f9f7 1787 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1788 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1791 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1792
<> 144:ef7eb2e8f9f7 1793 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1794 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1797 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1798 }
<> 144:ef7eb2e8f9f7 1799 break;
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 default:
<> 144:ef7eb2e8f9f7 1802 break;
<> 144:ef7eb2e8f9f7 1803 }
<> 144:ef7eb2e8f9f7 1804
<> 144:ef7eb2e8f9f7 1805 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1806 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1809 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 /* Return function status */
<> 144:ef7eb2e8f9f7 1812 return HAL_OK;
<> 144:ef7eb2e8f9f7 1813 }
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /**
<> 144:ef7eb2e8f9f7 1816 * @brief Stops the TIM Input Capture measurement on in DMA mode.
<> 144:ef7eb2e8f9f7 1817 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1818 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1819 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1820 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1821 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1822 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1823 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1824 * @retval HAL status
<> 144:ef7eb2e8f9f7 1825 */
<> 144:ef7eb2e8f9f7 1826 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1827 {
<> 144:ef7eb2e8f9f7 1828 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1829 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1830 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1831
<> 144:ef7eb2e8f9f7 1832 switch (Channel)
<> 144:ef7eb2e8f9f7 1833 {
<> 144:ef7eb2e8f9f7 1834 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1835 {
<> 144:ef7eb2e8f9f7 1836 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1837 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1838 }
<> 144:ef7eb2e8f9f7 1839 break;
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1842 {
<> 144:ef7eb2e8f9f7 1843 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1844 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1845 }
<> 144:ef7eb2e8f9f7 1846 break;
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1849 {
<> 144:ef7eb2e8f9f7 1850 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1851 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1852 }
<> 144:ef7eb2e8f9f7 1853 break;
<> 144:ef7eb2e8f9f7 1854
<> 144:ef7eb2e8f9f7 1855 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1856 {
<> 144:ef7eb2e8f9f7 1857 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1858 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860 break;
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 default:
<> 144:ef7eb2e8f9f7 1863 break;
<> 144:ef7eb2e8f9f7 1864 }
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1867 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1868
<> 144:ef7eb2e8f9f7 1869 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1870 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1871
<> 144:ef7eb2e8f9f7 1872 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1873 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /* Return function status */
<> 144:ef7eb2e8f9f7 1876 return HAL_OK;
<> 144:ef7eb2e8f9f7 1877 }
<> 144:ef7eb2e8f9f7 1878
<> 144:ef7eb2e8f9f7 1879 /**
<> 144:ef7eb2e8f9f7 1880 * @}
<> 144:ef7eb2e8f9f7 1881 */
<> 144:ef7eb2e8f9f7 1882
<> 144:ef7eb2e8f9f7 1883 /** @addtogroup TIM_Exported_Functions_Group5
<> 144:ef7eb2e8f9f7 1884 * @brief Time One Pulse functions
<> 144:ef7eb2e8f9f7 1885 *
<> 144:ef7eb2e8f9f7 1886 @verbatim
<> 144:ef7eb2e8f9f7 1887 ==============================================================================
<> 144:ef7eb2e8f9f7 1888 ##### Timer One Pulse functions #####
<> 144:ef7eb2e8f9f7 1889 ==============================================================================
<> 144:ef7eb2e8f9f7 1890 [..]
<> 144:ef7eb2e8f9f7 1891 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1892 (+) Initialize and configure the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1893 (+) De-initialize the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1894 (+) Start the Timer One Pulse.
<> 144:ef7eb2e8f9f7 1895 (+) Stop the Timer One Pulse.
<> 144:ef7eb2e8f9f7 1896 (+) Start the Timer One Pulse and enable interrupt.
<> 144:ef7eb2e8f9f7 1897 (+) Stop the Timer One Pulse and disable interrupt.
<> 144:ef7eb2e8f9f7 1898 (+) Start the Timer One Pulse and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1899 (+) Stop the Timer One Pulse and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 @endverbatim
<> 144:ef7eb2e8f9f7 1902 * @{
<> 144:ef7eb2e8f9f7 1903 */
<> 144:ef7eb2e8f9f7 1904 /**
<> 144:ef7eb2e8f9f7 1905 * @brief Initializes the TIM One Pulse Time Base according to the specified
<> 144:ef7eb2e8f9f7 1906 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1907 * @param htim: TIM OnePulse handle
<> 144:ef7eb2e8f9f7 1908 * @param OnePulseMode: Select the One pulse mode.
<> 144:ef7eb2e8f9f7 1909 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1910 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<> 144:ef7eb2e8f9f7 1911 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
<> 144:ef7eb2e8f9f7 1912 * @retval HAL status
<> 144:ef7eb2e8f9f7 1913 */
<> 144:ef7eb2e8f9f7 1914 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<> 144:ef7eb2e8f9f7 1915 {
<> 144:ef7eb2e8f9f7 1916 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1917 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1918 {
<> 144:ef7eb2e8f9f7 1919 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1920 }
<> 144:ef7eb2e8f9f7 1921
<> 144:ef7eb2e8f9f7 1922 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1923 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1924 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1925 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1926 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<> 144:ef7eb2e8f9f7 1927 assert_param(IS_TIM_PERIOD(htim->Init.Period));
<> 144:ef7eb2e8f9f7 1928 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1931 {
<> 144:ef7eb2e8f9f7 1932 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1933 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1936 HAL_TIM_OnePulse_MspInit(htim);
<> 144:ef7eb2e8f9f7 1937 }
<> 144:ef7eb2e8f9f7 1938
<> 144:ef7eb2e8f9f7 1939 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1940 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 /* Configure the Time base in the One Pulse Mode */
<> 144:ef7eb2e8f9f7 1943 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1944
<> 144:ef7eb2e8f9f7 1945 /* Reset the OPM Bit */
<> 144:ef7eb2e8f9f7 1946 htim->Instance->CR1 &= ~TIM_CR1_OPM;
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /* Configure the OPM Mode */
<> 144:ef7eb2e8f9f7 1949 htim->Instance->CR1 |= OnePulseMode;
<> 144:ef7eb2e8f9f7 1950
<> 144:ef7eb2e8f9f7 1951 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1952 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 return HAL_OK;
<> 144:ef7eb2e8f9f7 1955 }
<> 144:ef7eb2e8f9f7 1956
<> 144:ef7eb2e8f9f7 1957 /**
<> 144:ef7eb2e8f9f7 1958 * @brief DeInitializes the TIM One Pulse
<> 144:ef7eb2e8f9f7 1959 * @param htim: TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1960 * @retval HAL status
<> 144:ef7eb2e8f9f7 1961 */
<> 144:ef7eb2e8f9f7 1962 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1963 {
<> 144:ef7eb2e8f9f7 1964 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1965 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1968
<> 144:ef7eb2e8f9f7 1969 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1970 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1971
<> 144:ef7eb2e8f9f7 1972 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 1973 HAL_TIM_OnePulse_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1974
<> 144:ef7eb2e8f9f7 1975 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1976 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1977
<> 144:ef7eb2e8f9f7 1978 /* Release Lock */
<> 144:ef7eb2e8f9f7 1979 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1980
<> 144:ef7eb2e8f9f7 1981 return HAL_OK;
<> 144:ef7eb2e8f9f7 1982 }
<> 144:ef7eb2e8f9f7 1983
<> 144:ef7eb2e8f9f7 1984 /**
<> 144:ef7eb2e8f9f7 1985 * @brief Initializes the TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 1986 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1987 * @retval None
<> 144:ef7eb2e8f9f7 1988 */
<> 144:ef7eb2e8f9f7 1989 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1990 {
<> 144:ef7eb2e8f9f7 1991 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1992 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1993
<> 144:ef7eb2e8f9f7 1994 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1995 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1996 */
<> 144:ef7eb2e8f9f7 1997 }
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /**
<> 144:ef7eb2e8f9f7 2000 * @brief DeInitializes TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2001 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2002 * @retval None
<> 144:ef7eb2e8f9f7 2003 */
<> 144:ef7eb2e8f9f7 2004 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2005 {
<> 144:ef7eb2e8f9f7 2006 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2007 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2008
<> 144:ef7eb2e8f9f7 2009 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2010 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2011 */
<> 144:ef7eb2e8f9f7 2012 }
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 /**
<> 144:ef7eb2e8f9f7 2015 * @brief Starts the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2016 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2017 * @param OutputChannel : TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2018 * This parameter is not used since both channels TIM_CHANNEL_1 and
<> 144:ef7eb2e8f9f7 2019 * TIM_CHANNEL_2 are automatically selected.
<> 144:ef7eb2e8f9f7 2020 * @retval HAL status
<> 144:ef7eb2e8f9f7 2021 */
<> 144:ef7eb2e8f9f7 2022 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2023 {
<> 144:ef7eb2e8f9f7 2024 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2025 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2026 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2027 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2028 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2031 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2034 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 /* Return function status */
<> 144:ef7eb2e8f9f7 2037 return HAL_OK;
<> 144:ef7eb2e8f9f7 2038 }
<> 144:ef7eb2e8f9f7 2039
<> 144:ef7eb2e8f9f7 2040 /**
<> 144:ef7eb2e8f9f7 2041 * @brief Stops the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2042 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2043 * @param OutputChannel : TIM Channels to be disable.
<> 144:ef7eb2e8f9f7 2044 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2045 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2046 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2047 * @retval HAL status
<> 144:ef7eb2e8f9f7 2048 */
<> 144:ef7eb2e8f9f7 2049 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2050 {
<> 144:ef7eb2e8f9f7 2051 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2052 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2053 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2054 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2055 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2056
<> 144:ef7eb2e8f9f7 2057 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2058 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2059
<> 144:ef7eb2e8f9f7 2060 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2061 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 /* Return function status */
<> 144:ef7eb2e8f9f7 2064 return HAL_OK;
<> 144:ef7eb2e8f9f7 2065 }
<> 144:ef7eb2e8f9f7 2066
<> 144:ef7eb2e8f9f7 2067 /**
<> 144:ef7eb2e8f9f7 2068 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2069 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2070 * @param OutputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2071 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2072 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2073 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2074 * @retval HAL status
<> 144:ef7eb2e8f9f7 2075 */
<> 144:ef7eb2e8f9f7 2076 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2077 {
<> 144:ef7eb2e8f9f7 2078 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2079 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2080 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2081 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2082 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2083
<> 144:ef7eb2e8f9f7 2084 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2085 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2088 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2089
<> 144:ef7eb2e8f9f7 2090 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2091 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2094 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 /* Return function status */
<> 144:ef7eb2e8f9f7 2097 return HAL_OK;
<> 144:ef7eb2e8f9f7 2098 }
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /**
<> 144:ef7eb2e8f9f7 2101 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2102 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2103 * @param OutputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2104 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2105 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2106 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2107 * @retval HAL status
<> 144:ef7eb2e8f9f7 2108 */
<> 144:ef7eb2e8f9f7 2109 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2110 {
<> 144:ef7eb2e8f9f7 2111 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2112 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2113
<> 144:ef7eb2e8f9f7 2114 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2115 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2116
<> 144:ef7eb2e8f9f7 2117 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2118 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2119 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2120 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2121 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2122 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2123 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2124
<> 144:ef7eb2e8f9f7 2125 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2126 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2127
<> 144:ef7eb2e8f9f7 2128 /* Return function status */
<> 144:ef7eb2e8f9f7 2129 return HAL_OK;
<> 144:ef7eb2e8f9f7 2130 }
<> 144:ef7eb2e8f9f7 2131
<> 144:ef7eb2e8f9f7 2132 /**
<> 144:ef7eb2e8f9f7 2133 * @}
<> 144:ef7eb2e8f9f7 2134 */
<> 144:ef7eb2e8f9f7 2135
<> 144:ef7eb2e8f9f7 2136 /** @addtogroup TIM_Exported_Functions_Group6
<> 144:ef7eb2e8f9f7 2137 * @brief Time Encoder functions
<> 144:ef7eb2e8f9f7 2138 *
<> 144:ef7eb2e8f9f7 2139 @verbatim
<> 144:ef7eb2e8f9f7 2140 ==============================================================================
<> 144:ef7eb2e8f9f7 2141 ##### Timer Encoder functions #####
<> 144:ef7eb2e8f9f7 2142 ==============================================================================
<> 144:ef7eb2e8f9f7 2143 [..]
<> 144:ef7eb2e8f9f7 2144 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2145 (+) Initialize and configure the TIM Encoder.
<> 144:ef7eb2e8f9f7 2146 (+) De-initialize the TIM Encoder.
<> 144:ef7eb2e8f9f7 2147 (+) Start the Timer Encoder.
<> 144:ef7eb2e8f9f7 2148 (+) Stop the Timer Encoder.
<> 144:ef7eb2e8f9f7 2149 (+) Start the Timer Encoder and enable interrupt.
<> 144:ef7eb2e8f9f7 2150 (+) Stop the Timer Encoder and disable interrupt.
<> 144:ef7eb2e8f9f7 2151 (+) Start the Timer Encoder and enable DMA transfer.
<> 144:ef7eb2e8f9f7 2152 (+) Stop the Timer Encoder and disable DMA transfer.
<> 144:ef7eb2e8f9f7 2153
<> 144:ef7eb2e8f9f7 2154 @endverbatim
<> 144:ef7eb2e8f9f7 2155 * @{
<> 144:ef7eb2e8f9f7 2156 */
<> 144:ef7eb2e8f9f7 2157 /**
<> 144:ef7eb2e8f9f7 2158 * @brief Initializes the TIM Encoder Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 2159 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2160 * @param sConfig: TIM Encoder Interface configuration structure
<> 144:ef7eb2e8f9f7 2161 * @retval HAL status
<> 144:ef7eb2e8f9f7 2162 */
<> 144:ef7eb2e8f9f7 2163 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 2164 {
<> 151:5eaa88a5bcc7 2165 uint32_t tmpsmcr = 0U;
<> 151:5eaa88a5bcc7 2166 uint32_t tmpccmr1 = 0U;
<> 151:5eaa88a5bcc7 2167 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 2168
<> 144:ef7eb2e8f9f7 2169 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2170 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2171 {
<> 144:ef7eb2e8f9f7 2172 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2173 }
<> 144:ef7eb2e8f9f7 2174
<> 144:ef7eb2e8f9f7 2175 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2176 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2177 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<> 144:ef7eb2e8f9f7 2178 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<> 144:ef7eb2e8f9f7 2179 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<> 144:ef7eb2e8f9f7 2180 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 2181 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<> 144:ef7eb2e8f9f7 2182 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 2183 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<> 144:ef7eb2e8f9f7 2184 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 2185 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<> 144:ef7eb2e8f9f7 2186 assert_param(IS_TIM_PERIOD(htim->Init.Period));
<> 144:ef7eb2e8f9f7 2187 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
<> 144:ef7eb2e8f9f7 2188
<> 144:ef7eb2e8f9f7 2189 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2190 {
<> 144:ef7eb2e8f9f7 2191 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2192 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2193
<> 144:ef7eb2e8f9f7 2194 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2195 HAL_TIM_Encoder_MspInit(htim);
<> 144:ef7eb2e8f9f7 2196 }
<> 144:ef7eb2e8f9f7 2197
<> 144:ef7eb2e8f9f7 2198 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2199 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2200
<> 144:ef7eb2e8f9f7 2201 /* Reset the SMS bits */
<> 144:ef7eb2e8f9f7 2202 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 2203
<> 144:ef7eb2e8f9f7 2204 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 2205 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2206
<> 144:ef7eb2e8f9f7 2207 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 2208 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 2209
<> 144:ef7eb2e8f9f7 2210 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2211 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 2212
<> 144:ef7eb2e8f9f7 2213 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2214 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 2215
<> 144:ef7eb2e8f9f7 2216 /* Set the encoder Mode */
<> 144:ef7eb2e8f9f7 2217 tmpsmcr |= sConfig->EncoderMode;
<> 144:ef7eb2e8f9f7 2218
<> 144:ef7eb2e8f9f7 2219 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
<> 144:ef7eb2e8f9f7 2220 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
<> 151:5eaa88a5bcc7 2221 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
<> 144:ef7eb2e8f9f7 2222
<> 144:ef7eb2e8f9f7 2223 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<> 144:ef7eb2e8f9f7 2224 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
<> 144:ef7eb2e8f9f7 2225 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
<> 151:5eaa88a5bcc7 2226 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
<> 151:5eaa88a5bcc7 2227 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
<> 144:ef7eb2e8f9f7 2228
<> 144:ef7eb2e8f9f7 2229 /* Set the TI1 and the TI2 Polarities */
<> 144:ef7eb2e8f9f7 2230 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
<> 144:ef7eb2e8f9f7 2231 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
<> 151:5eaa88a5bcc7 2232 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
<> 144:ef7eb2e8f9f7 2233
<> 144:ef7eb2e8f9f7 2234 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 2235 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 2238 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 2239
<> 144:ef7eb2e8f9f7 2240 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2241 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2242
<> 144:ef7eb2e8f9f7 2243 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2244 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2245
<> 144:ef7eb2e8f9f7 2246 return HAL_OK;
<> 144:ef7eb2e8f9f7 2247 }
<> 144:ef7eb2e8f9f7 2248
<> 144:ef7eb2e8f9f7 2249 /**
<> 144:ef7eb2e8f9f7 2250 * @brief DeInitializes the TIM Encoder interface
<> 144:ef7eb2e8f9f7 2251 * @param htim: TIM Encoder handle
<> 144:ef7eb2e8f9f7 2252 * @retval HAL status
<> 144:ef7eb2e8f9f7 2253 */
<> 144:ef7eb2e8f9f7 2254 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2255 {
<> 144:ef7eb2e8f9f7 2256 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2257 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2258
<> 144:ef7eb2e8f9f7 2259 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2260
<> 144:ef7eb2e8f9f7 2261 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2262 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2263
<> 144:ef7eb2e8f9f7 2264 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2265 HAL_TIM_Encoder_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2266
<> 144:ef7eb2e8f9f7 2267 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2268 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2269
<> 144:ef7eb2e8f9f7 2270 /* Release Lock */
<> 144:ef7eb2e8f9f7 2271 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2272
<> 144:ef7eb2e8f9f7 2273 return HAL_OK;
<> 144:ef7eb2e8f9f7 2274 }
<> 144:ef7eb2e8f9f7 2275
<> 144:ef7eb2e8f9f7 2276
<> 144:ef7eb2e8f9f7 2277 /**
<> 144:ef7eb2e8f9f7 2278 * @brief Initializes the TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2279 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2280 * @retval None
<> 144:ef7eb2e8f9f7 2281 */
<> 144:ef7eb2e8f9f7 2282 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2283 {
<> 144:ef7eb2e8f9f7 2284 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2285 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2286
<> 144:ef7eb2e8f9f7 2287 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2288 the HAL_TIM_Encoder_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2289 */
<> 144:ef7eb2e8f9f7 2290 }
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292
<> 144:ef7eb2e8f9f7 2293 /**
<> 144:ef7eb2e8f9f7 2294 * @brief DeInitializes TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2295 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2296 * @retval None
<> 144:ef7eb2e8f9f7 2297 */
<> 144:ef7eb2e8f9f7 2298 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2299 {
<> 144:ef7eb2e8f9f7 2300 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2301 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2302
<> 144:ef7eb2e8f9f7 2303 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2304 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2305 */
<> 144:ef7eb2e8f9f7 2306 }
<> 144:ef7eb2e8f9f7 2307
<> 144:ef7eb2e8f9f7 2308 /**
<> 144:ef7eb2e8f9f7 2309 * @brief Starts the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2310 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2311 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2312 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2313 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2314 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2315 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2316 * @retval HAL status
<> 144:ef7eb2e8f9f7 2317 */
<> 144:ef7eb2e8f9f7 2318 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2319 {
<> 144:ef7eb2e8f9f7 2320 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2321 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2322
<> 144:ef7eb2e8f9f7 2323 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2324 switch (Channel)
<> 144:ef7eb2e8f9f7 2325 {
<> 144:ef7eb2e8f9f7 2326 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2327 {
<> 144:ef7eb2e8f9f7 2328 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2329 break;
<> 144:ef7eb2e8f9f7 2330 }
<> 144:ef7eb2e8f9f7 2331 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2332 {
<> 144:ef7eb2e8f9f7 2333 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2334 break;
<> 144:ef7eb2e8f9f7 2335 }
<> 144:ef7eb2e8f9f7 2336 default :
<> 144:ef7eb2e8f9f7 2337 {
<> 144:ef7eb2e8f9f7 2338 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2339 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2340 break;
<> 144:ef7eb2e8f9f7 2341 }
<> 144:ef7eb2e8f9f7 2342 }
<> 144:ef7eb2e8f9f7 2343 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2344 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2345
<> 144:ef7eb2e8f9f7 2346 /* Return function status */
<> 144:ef7eb2e8f9f7 2347 return HAL_OK;
<> 144:ef7eb2e8f9f7 2348 }
<> 144:ef7eb2e8f9f7 2349
<> 144:ef7eb2e8f9f7 2350 /**
<> 144:ef7eb2e8f9f7 2351 * @brief Stops the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2352 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2353 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 2354 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2355 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2356 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2357 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2358 * @retval HAL status
<> 144:ef7eb2e8f9f7 2359 */
<> 144:ef7eb2e8f9f7 2360 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2361 {
<> 144:ef7eb2e8f9f7 2362 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2363 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2364
<> 144:ef7eb2e8f9f7 2365 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2366 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2367 switch (Channel)
<> 144:ef7eb2e8f9f7 2368 {
<> 144:ef7eb2e8f9f7 2369 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2370 {
<> 144:ef7eb2e8f9f7 2371 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2372 break;
<> 144:ef7eb2e8f9f7 2373 }
<> 144:ef7eb2e8f9f7 2374 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2375 {
<> 144:ef7eb2e8f9f7 2376 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2377 break;
<> 144:ef7eb2e8f9f7 2378 }
<> 144:ef7eb2e8f9f7 2379 default :
<> 144:ef7eb2e8f9f7 2380 {
<> 144:ef7eb2e8f9f7 2381 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2382 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2383 break;
<> 144:ef7eb2e8f9f7 2384 }
<> 144:ef7eb2e8f9f7 2385 }
<> 144:ef7eb2e8f9f7 2386 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2387 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2388
<> 144:ef7eb2e8f9f7 2389 /* Return function status */
<> 144:ef7eb2e8f9f7 2390 return HAL_OK;
<> 144:ef7eb2e8f9f7 2391 }
<> 144:ef7eb2e8f9f7 2392
<> 144:ef7eb2e8f9f7 2393 /**
<> 144:ef7eb2e8f9f7 2394 * @brief Starts the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2395 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2396 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2397 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2398 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2399 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2400 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2401 * @retval HAL status
<> 144:ef7eb2e8f9f7 2402 */
<> 144:ef7eb2e8f9f7 2403 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2404 {
<> 144:ef7eb2e8f9f7 2405 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2406 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2407
<> 144:ef7eb2e8f9f7 2408 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2409 /* Enable the capture compare Interrupts 1 and/or 2 */
<> 144:ef7eb2e8f9f7 2410 switch (Channel)
<> 144:ef7eb2e8f9f7 2411 {
<> 144:ef7eb2e8f9f7 2412 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2413 {
<> 144:ef7eb2e8f9f7 2414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2415 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2416 break;
<> 144:ef7eb2e8f9f7 2417 }
<> 144:ef7eb2e8f9f7 2418 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2419 {
<> 144:ef7eb2e8f9f7 2420 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2421 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2422 break;
<> 144:ef7eb2e8f9f7 2423 }
<> 144:ef7eb2e8f9f7 2424 default :
<> 144:ef7eb2e8f9f7 2425 {
<> 144:ef7eb2e8f9f7 2426 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2427 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2428 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2429 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2430 break;
<> 144:ef7eb2e8f9f7 2431 }
<> 144:ef7eb2e8f9f7 2432 }
<> 144:ef7eb2e8f9f7 2433
<> 144:ef7eb2e8f9f7 2434 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2435 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2436
<> 144:ef7eb2e8f9f7 2437 /* Return function status */
<> 144:ef7eb2e8f9f7 2438 return HAL_OK;
<> 144:ef7eb2e8f9f7 2439 }
<> 144:ef7eb2e8f9f7 2440
<> 144:ef7eb2e8f9f7 2441 /**
<> 144:ef7eb2e8f9f7 2442 * @brief Stops the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2443 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2444 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 2445 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2446 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2447 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2448 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2449 * @retval HAL status
<> 144:ef7eb2e8f9f7 2450 */
<> 144:ef7eb2e8f9f7 2451 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2452 {
<> 144:ef7eb2e8f9f7 2453 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2454 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2455
<> 144:ef7eb2e8f9f7 2456 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2457 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2458 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2459 {
<> 144:ef7eb2e8f9f7 2460 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2461
<> 144:ef7eb2e8f9f7 2462 /* Disable the capture compare Interrupts 1 */
<> 144:ef7eb2e8f9f7 2463 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2464 }
<> 144:ef7eb2e8f9f7 2465 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2466 {
<> 144:ef7eb2e8f9f7 2467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2468
<> 144:ef7eb2e8f9f7 2469 /* Disable the capture compare Interrupts 2 */
<> 144:ef7eb2e8f9f7 2470 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2471 }
<> 144:ef7eb2e8f9f7 2472 else
<> 144:ef7eb2e8f9f7 2473 {
<> 144:ef7eb2e8f9f7 2474 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2475 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2476
<> 144:ef7eb2e8f9f7 2477 /* Disable the capture compare Interrupts 1 and 2 */
<> 144:ef7eb2e8f9f7 2478 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2479 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2480 }
<> 144:ef7eb2e8f9f7 2481
<> 144:ef7eb2e8f9f7 2482 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2483 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2484
<> 144:ef7eb2e8f9f7 2485 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2486 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2487
<> 144:ef7eb2e8f9f7 2488 /* Return function status */
<> 144:ef7eb2e8f9f7 2489 return HAL_OK;
<> 144:ef7eb2e8f9f7 2490 }
<> 144:ef7eb2e8f9f7 2491
<> 144:ef7eb2e8f9f7 2492 /**
<> 144:ef7eb2e8f9f7 2493 * @brief Starts the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2494 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2495 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2496 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2497 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2498 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2499 * @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected
<> 144:ef7eb2e8f9f7 2500 * @param pData1: The destination Buffer address for IC1.
<> 144:ef7eb2e8f9f7 2501 * @param pData2: The destination Buffer address for IC2.
<> 144:ef7eb2e8f9f7 2502 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 2503 * @retval HAL status
<> 144:ef7eb2e8f9f7 2504 */
<> 144:ef7eb2e8f9f7 2505 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
<> 144:ef7eb2e8f9f7 2506 {
<> 144:ef7eb2e8f9f7 2507 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2508 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2509
<> 144:ef7eb2e8f9f7 2510 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 2511 {
<> 144:ef7eb2e8f9f7 2512 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2513 }
<> 144:ef7eb2e8f9f7 2514 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 2515 {
<> 151:5eaa88a5bcc7 2516 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
<> 144:ef7eb2e8f9f7 2517 {
<> 144:ef7eb2e8f9f7 2518 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2519 }
<> 144:ef7eb2e8f9f7 2520 else
<> 144:ef7eb2e8f9f7 2521 {
<> 144:ef7eb2e8f9f7 2522 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2523 }
<> 144:ef7eb2e8f9f7 2524 }
<> 144:ef7eb2e8f9f7 2525
<> 144:ef7eb2e8f9f7 2526 switch (Channel)
<> 144:ef7eb2e8f9f7 2527 {
<> 144:ef7eb2e8f9f7 2528 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2529 {
<> 144:ef7eb2e8f9f7 2530 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2531 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2532
<> 144:ef7eb2e8f9f7 2533 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2534 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2535
<> 144:ef7eb2e8f9f7 2536 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2537 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<> 144:ef7eb2e8f9f7 2538
<> 144:ef7eb2e8f9f7 2539 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2540 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2541
<> 144:ef7eb2e8f9f7 2542 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2543 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2544
<> 144:ef7eb2e8f9f7 2545 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2546 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2547 }
<> 144:ef7eb2e8f9f7 2548 break;
<> 144:ef7eb2e8f9f7 2549
<> 144:ef7eb2e8f9f7 2550 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2551 {
<> 144:ef7eb2e8f9f7 2552 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2553 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2554
<> 144:ef7eb2e8f9f7 2555 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2556 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 2557 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2558 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2559
<> 144:ef7eb2e8f9f7 2560 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2561 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2562
<> 144:ef7eb2e8f9f7 2563 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2564 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2565
<> 144:ef7eb2e8f9f7 2566 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2567 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2568 }
<> 144:ef7eb2e8f9f7 2569 break;
<> 144:ef7eb2e8f9f7 2570
<> 144:ef7eb2e8f9f7 2571 case TIM_CHANNEL_ALL:
<> 144:ef7eb2e8f9f7 2572 {
<> 144:ef7eb2e8f9f7 2573 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2574 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2575
<> 144:ef7eb2e8f9f7 2576 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2577 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2578
<> 144:ef7eb2e8f9f7 2579 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2580 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<> 144:ef7eb2e8f9f7 2581
<> 144:ef7eb2e8f9f7 2582 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2583 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2584
<> 144:ef7eb2e8f9f7 2585 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2586 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2587
<> 144:ef7eb2e8f9f7 2588 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2589 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2590
<> 144:ef7eb2e8f9f7 2591 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2592 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2593
<> 144:ef7eb2e8f9f7 2594 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2595 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2596 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2597
<> 144:ef7eb2e8f9f7 2598 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2599 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2600 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2601 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2602 }
<> 144:ef7eb2e8f9f7 2603 break;
<> 144:ef7eb2e8f9f7 2604
<> 144:ef7eb2e8f9f7 2605 default:
<> 144:ef7eb2e8f9f7 2606 break;
<> 144:ef7eb2e8f9f7 2607 }
<> 144:ef7eb2e8f9f7 2608 /* Return function status */
<> 144:ef7eb2e8f9f7 2609 return HAL_OK;
<> 144:ef7eb2e8f9f7 2610 }
<> 144:ef7eb2e8f9f7 2611
<> 144:ef7eb2e8f9f7 2612 /**
<> 144:ef7eb2e8f9f7 2613 * @brief Stops the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2614 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2615 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2616 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2617 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2618 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2619 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2620 * @retval HAL status
<> 144:ef7eb2e8f9f7 2621 */
<> 144:ef7eb2e8f9f7 2622 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2623 {
<> 144:ef7eb2e8f9f7 2624 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2625 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2626
<> 144:ef7eb2e8f9f7 2627 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2628 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2629 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2630 {
<> 144:ef7eb2e8f9f7 2631 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2632
<> 144:ef7eb2e8f9f7 2633 /* Disable the capture compare DMA Request 1 */
<> 144:ef7eb2e8f9f7 2634 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2635 }
<> 144:ef7eb2e8f9f7 2636 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2637 {
<> 144:ef7eb2e8f9f7 2638 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2639
<> 144:ef7eb2e8f9f7 2640 /* Disable the capture compare DMA Request 2 */
<> 144:ef7eb2e8f9f7 2641 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2642 }
<> 144:ef7eb2e8f9f7 2643 else
<> 144:ef7eb2e8f9f7 2644 {
<> 144:ef7eb2e8f9f7 2645 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2646 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2647
<> 144:ef7eb2e8f9f7 2648 /* Disable the capture compare DMA Request 1 and 2 */
<> 144:ef7eb2e8f9f7 2649 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2650 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2651 }
<> 144:ef7eb2e8f9f7 2652
<> 144:ef7eb2e8f9f7 2653 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2654 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2655
<> 144:ef7eb2e8f9f7 2656 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2657 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2658
<> 144:ef7eb2e8f9f7 2659 /* Return function status */
<> 144:ef7eb2e8f9f7 2660 return HAL_OK;
<> 144:ef7eb2e8f9f7 2661 }
<> 144:ef7eb2e8f9f7 2662
<> 144:ef7eb2e8f9f7 2663 /**
<> 144:ef7eb2e8f9f7 2664 * @}
<> 144:ef7eb2e8f9f7 2665 */
<> 144:ef7eb2e8f9f7 2666
<> 144:ef7eb2e8f9f7 2667 /** @addtogroup TIM_Exported_Functions_Group7
<> 144:ef7eb2e8f9f7 2668 * @brief IRQ handler management
<> 144:ef7eb2e8f9f7 2669 *
<> 144:ef7eb2e8f9f7 2670 @verbatim
<> 144:ef7eb2e8f9f7 2671 ==============================================================================
<> 144:ef7eb2e8f9f7 2672 ##### IRQ handler management #####
<> 144:ef7eb2e8f9f7 2673 ==============================================================================
<> 144:ef7eb2e8f9f7 2674 [..]
<> 144:ef7eb2e8f9f7 2675 This section provides Timer IRQ handler function.
<> 144:ef7eb2e8f9f7 2676
<> 144:ef7eb2e8f9f7 2677 @endverbatim
<> 144:ef7eb2e8f9f7 2678 * @{
<> 144:ef7eb2e8f9f7 2679 */
<> 144:ef7eb2e8f9f7 2680 /**
<> 144:ef7eb2e8f9f7 2681 * @brief This function handles TIM interrupts requests.
<> 144:ef7eb2e8f9f7 2682 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 2683 * @retval None
<> 144:ef7eb2e8f9f7 2684 */
<> 144:ef7eb2e8f9f7 2685 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2686 {
<> 144:ef7eb2e8f9f7 2687 /* Capture compare 1 event */
<> 144:ef7eb2e8f9f7 2688 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<> 144:ef7eb2e8f9f7 2689 {
<> 144:ef7eb2e8f9f7 2690 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<> 144:ef7eb2e8f9f7 2691 {
<> 144:ef7eb2e8f9f7 2692 {
<> 144:ef7eb2e8f9f7 2693 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2694 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 2695
<> 144:ef7eb2e8f9f7 2696 /* Input capture event */
<> 151:5eaa88a5bcc7 2697 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
<> 144:ef7eb2e8f9f7 2698 {
<> 144:ef7eb2e8f9f7 2699 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2700 }
<> 144:ef7eb2e8f9f7 2701 /* Output compare event */
<> 144:ef7eb2e8f9f7 2702 else
<> 144:ef7eb2e8f9f7 2703 {
<> 144:ef7eb2e8f9f7 2704 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2705 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2706 }
<> 144:ef7eb2e8f9f7 2707 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2708 }
<> 144:ef7eb2e8f9f7 2709 }
<> 144:ef7eb2e8f9f7 2710 }
<> 144:ef7eb2e8f9f7 2711 /* Capture compare 2 event */
<> 144:ef7eb2e8f9f7 2712 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<> 144:ef7eb2e8f9f7 2713 {
<> 144:ef7eb2e8f9f7 2714 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<> 144:ef7eb2e8f9f7 2715 {
<> 144:ef7eb2e8f9f7 2716 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2717 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 2718 /* Input capture event */
<> 151:5eaa88a5bcc7 2719 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
<> 144:ef7eb2e8f9f7 2720 {
<> 144:ef7eb2e8f9f7 2721 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2722 }
<> 144:ef7eb2e8f9f7 2723 /* Output compare event */
<> 144:ef7eb2e8f9f7 2724 else
<> 144:ef7eb2e8f9f7 2725 {
<> 144:ef7eb2e8f9f7 2726 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2727 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2728 }
<> 144:ef7eb2e8f9f7 2729 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2730 }
<> 144:ef7eb2e8f9f7 2731 }
<> 144:ef7eb2e8f9f7 2732 /* Capture compare 3 event */
<> 144:ef7eb2e8f9f7 2733 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<> 144:ef7eb2e8f9f7 2734 {
<> 144:ef7eb2e8f9f7 2735 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<> 144:ef7eb2e8f9f7 2736 {
<> 144:ef7eb2e8f9f7 2737 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 2738 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 2739 /* Input capture event */
<> 151:5eaa88a5bcc7 2740 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
<> 144:ef7eb2e8f9f7 2741 {
<> 144:ef7eb2e8f9f7 2742 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2743 }
<> 144:ef7eb2e8f9f7 2744 /* Output compare event */
<> 144:ef7eb2e8f9f7 2745 else
<> 144:ef7eb2e8f9f7 2746 {
<> 144:ef7eb2e8f9f7 2747 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2748 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2749 }
<> 144:ef7eb2e8f9f7 2750 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2751 }
<> 144:ef7eb2e8f9f7 2752 }
<> 144:ef7eb2e8f9f7 2753 /* Capture compare 4 event */
<> 144:ef7eb2e8f9f7 2754 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<> 144:ef7eb2e8f9f7 2755 {
<> 144:ef7eb2e8f9f7 2756 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<> 144:ef7eb2e8f9f7 2757 {
<> 144:ef7eb2e8f9f7 2758 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 2759 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 2760 /* Input capture event */
<> 151:5eaa88a5bcc7 2761 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
<> 144:ef7eb2e8f9f7 2762 {
<> 144:ef7eb2e8f9f7 2763 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2764 }
<> 144:ef7eb2e8f9f7 2765 /* Output compare event */
<> 144:ef7eb2e8f9f7 2766 else
<> 144:ef7eb2e8f9f7 2767 {
<> 144:ef7eb2e8f9f7 2768 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2769 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2770 }
<> 144:ef7eb2e8f9f7 2771 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2772 }
<> 144:ef7eb2e8f9f7 2773 }
<> 144:ef7eb2e8f9f7 2774 /* TIM Update event */
<> 144:ef7eb2e8f9f7 2775 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<> 144:ef7eb2e8f9f7 2776 {
<> 144:ef7eb2e8f9f7 2777 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<> 144:ef7eb2e8f9f7 2778 {
<> 144:ef7eb2e8f9f7 2779 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 2780 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2781 }
<> 144:ef7eb2e8f9f7 2782 }
<> 144:ef7eb2e8f9f7 2783 /* TIM Trigger detection event */
<> 144:ef7eb2e8f9f7 2784 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<> 144:ef7eb2e8f9f7 2785 {
<> 144:ef7eb2e8f9f7 2786 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<> 144:ef7eb2e8f9f7 2787 {
<> 144:ef7eb2e8f9f7 2788 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 2789 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 2790 }
<> 144:ef7eb2e8f9f7 2791 }
<> 144:ef7eb2e8f9f7 2792 }
<> 144:ef7eb2e8f9f7 2793
<> 144:ef7eb2e8f9f7 2794 /**
<> 144:ef7eb2e8f9f7 2795 * @}
<> 144:ef7eb2e8f9f7 2796 */
<> 144:ef7eb2e8f9f7 2797
<> 144:ef7eb2e8f9f7 2798 /** @addtogroup TIM_Exported_Functions_Group8
<> 144:ef7eb2e8f9f7 2799 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 2800 *
<> 144:ef7eb2e8f9f7 2801 @verbatim
<> 144:ef7eb2e8f9f7 2802 ==============================================================================
<> 144:ef7eb2e8f9f7 2803 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 2804 ==============================================================================
<> 144:ef7eb2e8f9f7 2805 [..]
<> 144:ef7eb2e8f9f7 2806 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2807 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 2808 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 2809 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 2810 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 2811
<> 144:ef7eb2e8f9f7 2812 @endverbatim
<> 144:ef7eb2e8f9f7 2813 * @{
<> 144:ef7eb2e8f9f7 2814 */
<> 144:ef7eb2e8f9f7 2815 /**
<> 144:ef7eb2e8f9f7 2816 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 2817 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2818 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2819 * @param sConfig: TIM Output Compare configuration structure
<> 151:5eaa88a5bcc7 2820 * @param Channel: TIM Channel to be configure.
<> 144:ef7eb2e8f9f7 2821 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2822 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2823 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2824 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2825 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2826 * @retval HAL status
<> 144:ef7eb2e8f9f7 2827 */
<> 144:ef7eb2e8f9f7 2828 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2829 {
<> 144:ef7eb2e8f9f7 2830 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2831 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2832 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2833 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2834
<> 151:5eaa88a5bcc7 2835 /* Process lock */
<> 144:ef7eb2e8f9f7 2836 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2837
<> 144:ef7eb2e8f9f7 2838 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2839
<> 144:ef7eb2e8f9f7 2840 switch (Channel)
<> 144:ef7eb2e8f9f7 2841 {
<> 144:ef7eb2e8f9f7 2842 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2843 {
<> 144:ef7eb2e8f9f7 2844 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2845 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 2846 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2847 }
<> 144:ef7eb2e8f9f7 2848 break;
<> 144:ef7eb2e8f9f7 2849
<> 144:ef7eb2e8f9f7 2850 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2851 {
<> 144:ef7eb2e8f9f7 2852 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2853 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 2854 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2855 }
<> 144:ef7eb2e8f9f7 2856 break;
<> 144:ef7eb2e8f9f7 2857
<> 144:ef7eb2e8f9f7 2858 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 2859 {
<> 144:ef7eb2e8f9f7 2860 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2861 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 2862 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2863 }
<> 144:ef7eb2e8f9f7 2864 break;
<> 144:ef7eb2e8f9f7 2865
<> 144:ef7eb2e8f9f7 2866 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 2867 {
<> 144:ef7eb2e8f9f7 2868 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2869 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 2870 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2871 }
<> 144:ef7eb2e8f9f7 2872 break;
<> 144:ef7eb2e8f9f7 2873
<> 144:ef7eb2e8f9f7 2874 default:
<> 144:ef7eb2e8f9f7 2875 break;
<> 144:ef7eb2e8f9f7 2876 }
<> 144:ef7eb2e8f9f7 2877 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2878
<> 144:ef7eb2e8f9f7 2879 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2880
<> 144:ef7eb2e8f9f7 2881 return HAL_OK;
<> 144:ef7eb2e8f9f7 2882 }
<> 144:ef7eb2e8f9f7 2883
<> 144:ef7eb2e8f9f7 2884 /**
<> 144:ef7eb2e8f9f7 2885 * @brief Initializes the TIM Input Capture Channels according to the specified
<> 144:ef7eb2e8f9f7 2886 * parameters in the TIM_IC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2887 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2888 * @param sConfig: TIM Input Capture configuration structure
<> 144:ef7eb2e8f9f7 2889 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2890 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2891 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2892 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2893 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2894 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2895 * @retval HAL status
<> 144:ef7eb2e8f9f7 2896 */
<> 144:ef7eb2e8f9f7 2897 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2898 {
<> 144:ef7eb2e8f9f7 2899 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2900 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2901 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<> 144:ef7eb2e8f9f7 2902 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<> 144:ef7eb2e8f9f7 2903 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<> 144:ef7eb2e8f9f7 2904 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<> 144:ef7eb2e8f9f7 2905
<> 144:ef7eb2e8f9f7 2906 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2907
<> 144:ef7eb2e8f9f7 2908 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2909
<> 144:ef7eb2e8f9f7 2910 if (Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2911 {
<> 144:ef7eb2e8f9f7 2912 /* TI1 Configuration */
<> 144:ef7eb2e8f9f7 2913 TIM_TI1_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 2914 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 2915 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 2916 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 2917
<> 144:ef7eb2e8f9f7 2918 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 2919 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 2920
<> 144:ef7eb2e8f9f7 2921 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 2922 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 2923 }
<> 144:ef7eb2e8f9f7 2924 else if (Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2925 {
<> 144:ef7eb2e8f9f7 2926 /* TI2 Configuration */
<> 144:ef7eb2e8f9f7 2927 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2928
<> 144:ef7eb2e8f9f7 2929 TIM_TI2_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 2930 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 2931 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 2932 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 2933
<> 144:ef7eb2e8f9f7 2934 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 2935 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 2936
<> 144:ef7eb2e8f9f7 2937 /* Set the IC2PSC value */
<> 151:5eaa88a5bcc7 2938 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 2939 }
<> 144:ef7eb2e8f9f7 2940 else if (Channel == TIM_CHANNEL_3)
<> 144:ef7eb2e8f9f7 2941 {
<> 144:ef7eb2e8f9f7 2942 /* TI3 Configuration */
<> 144:ef7eb2e8f9f7 2943 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2944
<> 144:ef7eb2e8f9f7 2945 TIM_TI3_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 2946 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 2947 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 2948 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 2949
<> 144:ef7eb2e8f9f7 2950 /* Reset the IC3PSC Bits */
<> 144:ef7eb2e8f9f7 2951 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<> 144:ef7eb2e8f9f7 2952
<> 144:ef7eb2e8f9f7 2953 /* Set the IC3PSC value */
<> 144:ef7eb2e8f9f7 2954 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 2955 }
<> 144:ef7eb2e8f9f7 2956 else
<> 144:ef7eb2e8f9f7 2957 {
<> 144:ef7eb2e8f9f7 2958 /* TI4 Configuration */
<> 144:ef7eb2e8f9f7 2959 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2960
<> 144:ef7eb2e8f9f7 2961 TIM_TI4_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 2962 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 2963 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 2964 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 2965
<> 144:ef7eb2e8f9f7 2966 /* Reset the IC4PSC Bits */
<> 144:ef7eb2e8f9f7 2967 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<> 144:ef7eb2e8f9f7 2968
<> 144:ef7eb2e8f9f7 2969 /* Set the IC4PSC value */
<> 151:5eaa88a5bcc7 2970 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 2971 }
<> 144:ef7eb2e8f9f7 2972
<> 144:ef7eb2e8f9f7 2973 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2974
<> 144:ef7eb2e8f9f7 2975 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2976
<> 144:ef7eb2e8f9f7 2977 return HAL_OK;
<> 144:ef7eb2e8f9f7 2978 }
<> 144:ef7eb2e8f9f7 2979
<> 144:ef7eb2e8f9f7 2980 /**
<> 144:ef7eb2e8f9f7 2981 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 2982 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2983 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2984 * @param sConfig: TIM PWM configuration structure
<> 151:5eaa88a5bcc7 2985 * @param Channel: TIM Channel to be configured.
<> 144:ef7eb2e8f9f7 2986 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2987 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2988 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2989 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2990 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2991 * @retval HAL status
<> 144:ef7eb2e8f9f7 2992 */
<> 144:ef7eb2e8f9f7 2993 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2994 {
<> 144:ef7eb2e8f9f7 2995 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2996
<> 144:ef7eb2e8f9f7 2997 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2998 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2999 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 3000 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 3001 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 3002
<> 144:ef7eb2e8f9f7 3003 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3004
<> 144:ef7eb2e8f9f7 3005 switch (Channel)
<> 144:ef7eb2e8f9f7 3006 {
<> 144:ef7eb2e8f9f7 3007 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3008 {
<> 144:ef7eb2e8f9f7 3009 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3010 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 3011 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3012
<> 144:ef7eb2e8f9f7 3013 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 3014 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 3015
<> 144:ef7eb2e8f9f7 3016 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3017 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 3018 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3019 }
<> 144:ef7eb2e8f9f7 3020 break;
<> 144:ef7eb2e8f9f7 3021
<> 144:ef7eb2e8f9f7 3022 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3023 {
<> 144:ef7eb2e8f9f7 3024 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3025 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 3026 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3027
<> 144:ef7eb2e8f9f7 3028 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 3029 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 3030
<> 144:ef7eb2e8f9f7 3031 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3032 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 151:5eaa88a5bcc7 3033 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3034 }
<> 144:ef7eb2e8f9f7 3035 break;
<> 144:ef7eb2e8f9f7 3036
<> 144:ef7eb2e8f9f7 3037 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3038 {
<> 144:ef7eb2e8f9f7 3039 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3040 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 3041 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3042
<> 144:ef7eb2e8f9f7 3043 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 3044 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 3045
<> 144:ef7eb2e8f9f7 3046 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3047 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 3048 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3049 }
<> 144:ef7eb2e8f9f7 3050 break;
<> 144:ef7eb2e8f9f7 3051
<> 144:ef7eb2e8f9f7 3052 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3053 {
<> 144:ef7eb2e8f9f7 3054 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3055 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 3056 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3057
<> 144:ef7eb2e8f9f7 3058 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 3059 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 3060
<> 144:ef7eb2e8f9f7 3061 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3062 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 151:5eaa88a5bcc7 3063 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3064 }
<> 144:ef7eb2e8f9f7 3065 break;
<> 144:ef7eb2e8f9f7 3066
<> 144:ef7eb2e8f9f7 3067 default:
<> 144:ef7eb2e8f9f7 3068 break;
<> 144:ef7eb2e8f9f7 3069 }
<> 144:ef7eb2e8f9f7 3070
<> 144:ef7eb2e8f9f7 3071 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3072
<> 144:ef7eb2e8f9f7 3073 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3074
<> 144:ef7eb2e8f9f7 3075 return HAL_OK;
<> 144:ef7eb2e8f9f7 3076 }
<> 144:ef7eb2e8f9f7 3077
<> 144:ef7eb2e8f9f7 3078 /**
<> 144:ef7eb2e8f9f7 3079 * @brief Initializes the TIM One Pulse Channels according to the specified
<> 144:ef7eb2e8f9f7 3080 * parameters in the TIM_OnePulse_InitTypeDef.
<> 144:ef7eb2e8f9f7 3081 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3082 * @param sConfig: TIM One Pulse configuration structure
<> 144:ef7eb2e8f9f7 3083 * @param OutputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3084 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3085 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3086 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3087 * @param InputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3088 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3089 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3090 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3091 * @retval HAL status
<> 144:ef7eb2e8f9f7 3092 */
<> 144:ef7eb2e8f9f7 3093 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<> 144:ef7eb2e8f9f7 3094 {
<> 144:ef7eb2e8f9f7 3095 TIM_OC_InitTypeDef temp1;
<> 144:ef7eb2e8f9f7 3096
<> 144:ef7eb2e8f9f7 3097 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3098 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<> 144:ef7eb2e8f9f7 3099 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<> 144:ef7eb2e8f9f7 3100
<> 144:ef7eb2e8f9f7 3101 if(OutputChannel != InputChannel)
<> 144:ef7eb2e8f9f7 3102 {
<> 144:ef7eb2e8f9f7 3103 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3104
<> 144:ef7eb2e8f9f7 3105 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3106
<> 144:ef7eb2e8f9f7 3107 /* Extract the Ouput compare configuration from sConfig structure */
<> 144:ef7eb2e8f9f7 3108 temp1.OCMode = sConfig->OCMode;
<> 144:ef7eb2e8f9f7 3109 temp1.Pulse = sConfig->Pulse;
<> 144:ef7eb2e8f9f7 3110 temp1.OCPolarity = sConfig->OCPolarity;
<> 144:ef7eb2e8f9f7 3111
<> 144:ef7eb2e8f9f7 3112 switch (OutputChannel)
<> 144:ef7eb2e8f9f7 3113 {
<> 144:ef7eb2e8f9f7 3114 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3115 {
<> 144:ef7eb2e8f9f7 3116 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3117
<> 144:ef7eb2e8f9f7 3118 TIM_OC1_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3119 }
<> 144:ef7eb2e8f9f7 3120 break;
<> 144:ef7eb2e8f9f7 3121 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3122 {
<> 144:ef7eb2e8f9f7 3123 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3124
<> 144:ef7eb2e8f9f7 3125 TIM_OC2_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3126 }
<> 144:ef7eb2e8f9f7 3127 break;
<> 144:ef7eb2e8f9f7 3128 default:
<> 144:ef7eb2e8f9f7 3129 break;
<> 144:ef7eb2e8f9f7 3130 }
<> 144:ef7eb2e8f9f7 3131 switch (InputChannel)
<> 144:ef7eb2e8f9f7 3132 {
<> 144:ef7eb2e8f9f7 3133 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3134 {
<> 144:ef7eb2e8f9f7 3135 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3136
<> 144:ef7eb2e8f9f7 3137 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3138 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3139
<> 144:ef7eb2e8f9f7 3140 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3141 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3142
<> 144:ef7eb2e8f9f7 3143 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3144 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3145 htim->Instance->SMCR |= TIM_TS_TI1FP1;
<> 144:ef7eb2e8f9f7 3146
<> 144:ef7eb2e8f9f7 3147 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3148 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3149 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3150 }
<> 144:ef7eb2e8f9f7 3151 break;
<> 144:ef7eb2e8f9f7 3152 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3153 {
<> 144:ef7eb2e8f9f7 3154 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3155
<> 144:ef7eb2e8f9f7 3156 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3157 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3158
<> 144:ef7eb2e8f9f7 3159 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3160 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3161
<> 144:ef7eb2e8f9f7 3162 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3163 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3164 htim->Instance->SMCR |= TIM_TS_TI2FP2;
<> 144:ef7eb2e8f9f7 3165
<> 144:ef7eb2e8f9f7 3166 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3167 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3168 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3169 }
<> 144:ef7eb2e8f9f7 3170 break;
<> 144:ef7eb2e8f9f7 3171
<> 144:ef7eb2e8f9f7 3172 default:
<> 144:ef7eb2e8f9f7 3173 break;
<> 144:ef7eb2e8f9f7 3174 }
<> 144:ef7eb2e8f9f7 3175
<> 144:ef7eb2e8f9f7 3176 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3177
<> 144:ef7eb2e8f9f7 3178 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3179
<> 144:ef7eb2e8f9f7 3180 return HAL_OK;
<> 144:ef7eb2e8f9f7 3181 }
<> 144:ef7eb2e8f9f7 3182 else
<> 144:ef7eb2e8f9f7 3183 {
<> 144:ef7eb2e8f9f7 3184 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3185 }
<> 144:ef7eb2e8f9f7 3186 }
<> 144:ef7eb2e8f9f7 3187
<> 144:ef7eb2e8f9f7 3188 /**
<> 144:ef7eb2e8f9f7 3189 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<> 144:ef7eb2e8f9f7 3190 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3191 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
<> 144:ef7eb2e8f9f7 3192 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3193 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3194 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3195 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3196 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3197 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3198 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3199 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3200 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3201 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3202 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3203 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3204 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3205 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3206 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3207 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3208 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3209 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3210 * @param BurstRequestSrc: TIM DMA Request sources.
<> 144:ef7eb2e8f9f7 3211 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3212 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3213 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3214 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3215 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3216 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3217 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3218 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3219 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3220 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
<> 144:ef7eb2e8f9f7 3221 * @retval HAL status
<> 144:ef7eb2e8f9f7 3222 */
<> 144:ef7eb2e8f9f7 3223 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3224 uint32_t* BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3225 {
<> 144:ef7eb2e8f9f7 3226 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3227 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3228 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3229 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3230 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3231
<> 144:ef7eb2e8f9f7 3232 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3233 {
<> 144:ef7eb2e8f9f7 3234 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3235 }
<> 144:ef7eb2e8f9f7 3236 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3237 {
<> 151:5eaa88a5bcc7 3238 if((BurstBuffer == 0U ) && (BurstLength > 0U))
<> 144:ef7eb2e8f9f7 3239 {
<> 144:ef7eb2e8f9f7 3240 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3241 }
<> 144:ef7eb2e8f9f7 3242 else
<> 144:ef7eb2e8f9f7 3243 {
<> 144:ef7eb2e8f9f7 3244 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3245 }
<> 144:ef7eb2e8f9f7 3246 }
<> 144:ef7eb2e8f9f7 3247 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3248 {
<> 144:ef7eb2e8f9f7 3249 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3250 {
<> 144:ef7eb2e8f9f7 3251 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3252 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3253
<> 144:ef7eb2e8f9f7 3254 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3255 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3256
<> 144:ef7eb2e8f9f7 3257 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3258 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3259 }
<> 144:ef7eb2e8f9f7 3260 break;
<> 144:ef7eb2e8f9f7 3261 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3262 {
<> 144:ef7eb2e8f9f7 3263 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3264 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3265
<> 144:ef7eb2e8f9f7 3266 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3267 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3268
<> 144:ef7eb2e8f9f7 3269 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3270 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3271 }
<> 144:ef7eb2e8f9f7 3272 break;
<> 144:ef7eb2e8f9f7 3273 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3274 {
<> 144:ef7eb2e8f9f7 3275 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3276 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3277
<> 144:ef7eb2e8f9f7 3278 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3279 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3280
<> 144:ef7eb2e8f9f7 3281 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3282 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3283 }
<> 144:ef7eb2e8f9f7 3284 break;
<> 144:ef7eb2e8f9f7 3285 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3286 {
<> 144:ef7eb2e8f9f7 3287 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3288 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3289
<> 144:ef7eb2e8f9f7 3290 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3291 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3292
<> 144:ef7eb2e8f9f7 3293 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3294 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3295 }
<> 144:ef7eb2e8f9f7 3296 break;
<> 144:ef7eb2e8f9f7 3297 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3298 {
<> 144:ef7eb2e8f9f7 3299 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3300 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3301
<> 144:ef7eb2e8f9f7 3302 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3303 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3304
<> 144:ef7eb2e8f9f7 3305 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3306 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3307 }
<> 144:ef7eb2e8f9f7 3308 break;
<> 144:ef7eb2e8f9f7 3309 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3310 {
<> 144:ef7eb2e8f9f7 3311 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3312 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3313
<> 144:ef7eb2e8f9f7 3314 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3315 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3316
<> 144:ef7eb2e8f9f7 3317 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3318 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3319 }
<> 144:ef7eb2e8f9f7 3320 break;
<> 144:ef7eb2e8f9f7 3321 default:
<> 144:ef7eb2e8f9f7 3322 break;
<> 144:ef7eb2e8f9f7 3323 }
<> 144:ef7eb2e8f9f7 3324 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3325 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3326
<> 144:ef7eb2e8f9f7 3327 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3328 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3329
<> 144:ef7eb2e8f9f7 3330 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3331
<> 144:ef7eb2e8f9f7 3332 /* Return function status */
<> 144:ef7eb2e8f9f7 3333 return HAL_OK;
<> 144:ef7eb2e8f9f7 3334 }
<> 144:ef7eb2e8f9f7 3335
<> 144:ef7eb2e8f9f7 3336 /**
<> 144:ef7eb2e8f9f7 3337 * @brief Stops the TIM DMA Burst mode
<> 144:ef7eb2e8f9f7 3338 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3339 * @param BurstRequestSrc: TIM DMA Request sources to disable
<> 144:ef7eb2e8f9f7 3340 * @retval HAL status
<> 144:ef7eb2e8f9f7 3341 */
<> 144:ef7eb2e8f9f7 3342 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3343 {
<> 144:ef7eb2e8f9f7 3344 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3345 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3346
<> 144:ef7eb2e8f9f7 3347 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3348 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3349 {
<> 144:ef7eb2e8f9f7 3350 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3351 {
<> 144:ef7eb2e8f9f7 3352 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3353 }
<> 144:ef7eb2e8f9f7 3354 break;
<> 144:ef7eb2e8f9f7 3355 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3356 {
<> 144:ef7eb2e8f9f7 3357 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3358 }
<> 144:ef7eb2e8f9f7 3359 break;
<> 144:ef7eb2e8f9f7 3360 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3361 {
<> 144:ef7eb2e8f9f7 3362 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3363 }
<> 144:ef7eb2e8f9f7 3364 break;
<> 144:ef7eb2e8f9f7 3365 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3366 {
<> 144:ef7eb2e8f9f7 3367 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3368 }
<> 144:ef7eb2e8f9f7 3369 break;
<> 144:ef7eb2e8f9f7 3370 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3371 {
<> 144:ef7eb2e8f9f7 3372 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3373 }
<> 144:ef7eb2e8f9f7 3374 break;
<> 144:ef7eb2e8f9f7 3375 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3376 {
<> 144:ef7eb2e8f9f7 3377 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3378 }
<> 144:ef7eb2e8f9f7 3379 break;
<> 144:ef7eb2e8f9f7 3380 default:
<> 144:ef7eb2e8f9f7 3381 break;
<> 144:ef7eb2e8f9f7 3382 }
<> 144:ef7eb2e8f9f7 3383 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3384 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3385
<> 144:ef7eb2e8f9f7 3386 /* Return function status */
<> 144:ef7eb2e8f9f7 3387 return HAL_OK;
<> 144:ef7eb2e8f9f7 3388 }
<> 144:ef7eb2e8f9f7 3389
<> 144:ef7eb2e8f9f7 3390 /**
<> 144:ef7eb2e8f9f7 3391 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<> 144:ef7eb2e8f9f7 3392 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3393 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
<> 144:ef7eb2e8f9f7 3394 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3395 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3396 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3397 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3398 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3399 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3400 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3401 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3402 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3403 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3404 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3405 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3406 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3407 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3408 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3409 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3410 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3411 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3412 * @param BurstRequestSrc: TIM DMA Request sources.
<> 144:ef7eb2e8f9f7 3413 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3414 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3415 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3416 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3417 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3418 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3419 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3420 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3421 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3422 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
<> 144:ef7eb2e8f9f7 3423 * @retval HAL status
<> 144:ef7eb2e8f9f7 3424 */
<> 144:ef7eb2e8f9f7 3425 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3426 uint32_t *BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3427 {
<> 144:ef7eb2e8f9f7 3428 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3429 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3430 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3431 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3432 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3433
<> 144:ef7eb2e8f9f7 3434 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3435 {
<> 144:ef7eb2e8f9f7 3436 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3437 }
<> 144:ef7eb2e8f9f7 3438 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3439 {
<> 151:5eaa88a5bcc7 3440 if((BurstBuffer == 0U ) && (BurstLength > 0U))
<> 144:ef7eb2e8f9f7 3441 {
<> 144:ef7eb2e8f9f7 3442 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3443 }
<> 144:ef7eb2e8f9f7 3444 else
<> 144:ef7eb2e8f9f7 3445 {
<> 144:ef7eb2e8f9f7 3446 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3447 }
<> 144:ef7eb2e8f9f7 3448 }
<> 144:ef7eb2e8f9f7 3449 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3450 {
<> 144:ef7eb2e8f9f7 3451 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3452 {
<> 144:ef7eb2e8f9f7 3453 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3454 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3455
<> 144:ef7eb2e8f9f7 3456 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3457 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3458
<> 144:ef7eb2e8f9f7 3459 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3460 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3461 }
<> 144:ef7eb2e8f9f7 3462 break;
<> 144:ef7eb2e8f9f7 3463 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3464 {
<> 144:ef7eb2e8f9f7 3465 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3466 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3467
<> 144:ef7eb2e8f9f7 3468 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3469 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3470
<> 144:ef7eb2e8f9f7 3471 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3472 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3473 }
<> 144:ef7eb2e8f9f7 3474 break;
<> 144:ef7eb2e8f9f7 3475 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3476 {
<> 144:ef7eb2e8f9f7 3477 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3478 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3479
<> 144:ef7eb2e8f9f7 3480 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3481 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3482
<> 144:ef7eb2e8f9f7 3483 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3484 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3485 }
<> 144:ef7eb2e8f9f7 3486 break;
<> 144:ef7eb2e8f9f7 3487 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3488 {
<> 144:ef7eb2e8f9f7 3489 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3490 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3491
<> 144:ef7eb2e8f9f7 3492 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3493 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3494
<> 144:ef7eb2e8f9f7 3495 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3496 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3497 }
<> 144:ef7eb2e8f9f7 3498 break;
<> 144:ef7eb2e8f9f7 3499 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3500 {
<> 144:ef7eb2e8f9f7 3501 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3502 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3503
<> 144:ef7eb2e8f9f7 3504 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3505 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3506
<> 144:ef7eb2e8f9f7 3507 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3508 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3509 }
<> 144:ef7eb2e8f9f7 3510 break;
<> 144:ef7eb2e8f9f7 3511 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3512 {
<> 144:ef7eb2e8f9f7 3513 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3514 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3515
<> 144:ef7eb2e8f9f7 3516 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3517 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3518
<> 144:ef7eb2e8f9f7 3519 /* Enable the DMA Stream */
<> 151:5eaa88a5bcc7 3520 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<> 144:ef7eb2e8f9f7 3521 }
<> 144:ef7eb2e8f9f7 3522 break;
<> 144:ef7eb2e8f9f7 3523 default:
<> 144:ef7eb2e8f9f7 3524 break;
<> 144:ef7eb2e8f9f7 3525 }
<> 144:ef7eb2e8f9f7 3526
<> 144:ef7eb2e8f9f7 3527 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3528 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3529
<> 144:ef7eb2e8f9f7 3530 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3531 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3532
<> 144:ef7eb2e8f9f7 3533 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3534
<> 144:ef7eb2e8f9f7 3535 /* Return function status */
<> 144:ef7eb2e8f9f7 3536 return HAL_OK;
<> 144:ef7eb2e8f9f7 3537 }
<> 144:ef7eb2e8f9f7 3538
<> 144:ef7eb2e8f9f7 3539 /**
<> 144:ef7eb2e8f9f7 3540 * @brief Stop the DMA burst reading
<> 144:ef7eb2e8f9f7 3541 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3542 * @param BurstRequestSrc: TIM DMA Request sources to disable.
<> 144:ef7eb2e8f9f7 3543 * @retval HAL status
<> 144:ef7eb2e8f9f7 3544 */
<> 144:ef7eb2e8f9f7 3545 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3546 {
<> 144:ef7eb2e8f9f7 3547 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3548 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3549
<> 144:ef7eb2e8f9f7 3550 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3551 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3552 {
<> 144:ef7eb2e8f9f7 3553 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3554 {
<> 144:ef7eb2e8f9f7 3555 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3556 }
<> 144:ef7eb2e8f9f7 3557 break;
<> 144:ef7eb2e8f9f7 3558 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3559 {
<> 144:ef7eb2e8f9f7 3560 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3561 }
<> 144:ef7eb2e8f9f7 3562 break;
<> 144:ef7eb2e8f9f7 3563 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3564 {
<> 144:ef7eb2e8f9f7 3565 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3566 }
<> 144:ef7eb2e8f9f7 3567 break;
<> 144:ef7eb2e8f9f7 3568 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3569 {
<> 144:ef7eb2e8f9f7 3570 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3571 }
<> 144:ef7eb2e8f9f7 3572 break;
<> 144:ef7eb2e8f9f7 3573 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3574 {
<> 144:ef7eb2e8f9f7 3575 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3576 }
<> 144:ef7eb2e8f9f7 3577 break;
<> 144:ef7eb2e8f9f7 3578 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3579 {
<> 144:ef7eb2e8f9f7 3580 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3581 }
<> 144:ef7eb2e8f9f7 3582 break;
<> 144:ef7eb2e8f9f7 3583 default:
<> 144:ef7eb2e8f9f7 3584 break;
<> 144:ef7eb2e8f9f7 3585 }
<> 144:ef7eb2e8f9f7 3586
<> 144:ef7eb2e8f9f7 3587 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3588 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3589
<> 144:ef7eb2e8f9f7 3590 /* Return function status */
<> 144:ef7eb2e8f9f7 3591 return HAL_OK;
<> 144:ef7eb2e8f9f7 3592 }
<> 144:ef7eb2e8f9f7 3593
<> 144:ef7eb2e8f9f7 3594 /**
<> 144:ef7eb2e8f9f7 3595 * @brief Generate a software event
<> 144:ef7eb2e8f9f7 3596 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3597 * @param EventSource: specifies the event source.
<> 144:ef7eb2e8f9f7 3598 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3599 * @arg TIM_EventSource_Update: Timer update Event source
<> 144:ef7eb2e8f9f7 3600 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<> 144:ef7eb2e8f9f7 3601 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
<> 144:ef7eb2e8f9f7 3602 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
<> 144:ef7eb2e8f9f7 3603 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
<> 144:ef7eb2e8f9f7 3604 * @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source
<> 144:ef7eb2e8f9f7 3605 * @note TIM6 can only generate an update event.
<> 144:ef7eb2e8f9f7 3606 * @retval HAL status
<> 144:ef7eb2e8f9f7 3607 */
<> 144:ef7eb2e8f9f7 3608
<> 144:ef7eb2e8f9f7 3609 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<> 144:ef7eb2e8f9f7 3610 {
<> 144:ef7eb2e8f9f7 3611 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3612 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3613 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<> 144:ef7eb2e8f9f7 3614
<> 144:ef7eb2e8f9f7 3615 /* Process Locked */
<> 144:ef7eb2e8f9f7 3616 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3617
<> 144:ef7eb2e8f9f7 3618 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3619 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3620
<> 144:ef7eb2e8f9f7 3621 /* Set the event sources */
<> 144:ef7eb2e8f9f7 3622 htim->Instance->EGR = EventSource;
<> 144:ef7eb2e8f9f7 3623
<> 144:ef7eb2e8f9f7 3624 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3625 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3626
<> 144:ef7eb2e8f9f7 3627 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3628
<> 144:ef7eb2e8f9f7 3629 /* Return function status */
<> 144:ef7eb2e8f9f7 3630 return HAL_OK;
<> 144:ef7eb2e8f9f7 3631 }
<> 144:ef7eb2e8f9f7 3632
<> 144:ef7eb2e8f9f7 3633 /**
<> 144:ef7eb2e8f9f7 3634 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 3635 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3636 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3637 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3638 * @param Channel: specifies the TIM Channel.
<> 144:ef7eb2e8f9f7 3639 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3640 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3641 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3642 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3643 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3644 * @retval HAL status
<> 144:ef7eb2e8f9f7 3645 */
<> 144:ef7eb2e8f9f7 3646 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3647 {
<> 144:ef7eb2e8f9f7 3648 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3649 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3650 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3651 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 3652 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 3653 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 3654 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 3655
<> 144:ef7eb2e8f9f7 3656 /* Process Locked */
<> 144:ef7eb2e8f9f7 3657 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3658
<> 144:ef7eb2e8f9f7 3659 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3660
<> 144:ef7eb2e8f9f7 3661 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
<> 144:ef7eb2e8f9f7 3662 {
<> 144:ef7eb2e8f9f7 3663 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3664 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 3665 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 3666 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 3667
<> 144:ef7eb2e8f9f7 3668 /* Set the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 3669 htim->Instance->SMCR |= TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 3670 }
<> 144:ef7eb2e8f9f7 3671
<> 144:ef7eb2e8f9f7 3672 switch (Channel)
<> 144:ef7eb2e8f9f7 3673 {
<> 144:ef7eb2e8f9f7 3674 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3675 {
<> 144:ef7eb2e8f9f7 3676 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3677 {
<> 144:ef7eb2e8f9f7 3678 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3679 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3680 }
<> 144:ef7eb2e8f9f7 3681 else
<> 144:ef7eb2e8f9f7 3682 {
<> 144:ef7eb2e8f9f7 3683 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3684 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3685 }
<> 144:ef7eb2e8f9f7 3686 }
<> 144:ef7eb2e8f9f7 3687 break;
<> 144:ef7eb2e8f9f7 3688 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3689 {
<> 144:ef7eb2e8f9f7 3690 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3691 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3692 {
<> 144:ef7eb2e8f9f7 3693 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3694 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3695 }
<> 144:ef7eb2e8f9f7 3696 else
<> 144:ef7eb2e8f9f7 3697 {
<> 144:ef7eb2e8f9f7 3698 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3699 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3700 }
<> 144:ef7eb2e8f9f7 3701 }
<> 144:ef7eb2e8f9f7 3702 break;
<> 144:ef7eb2e8f9f7 3703 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3704 {
<> 144:ef7eb2e8f9f7 3705 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3706 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3707 {
<> 144:ef7eb2e8f9f7 3708 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3709 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3710 }
<> 144:ef7eb2e8f9f7 3711 else
<> 144:ef7eb2e8f9f7 3712 {
<> 144:ef7eb2e8f9f7 3713 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3714 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3715 }
<> 144:ef7eb2e8f9f7 3716 }
<> 144:ef7eb2e8f9f7 3717 break;
<> 144:ef7eb2e8f9f7 3718 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3719 {
<> 144:ef7eb2e8f9f7 3720 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3721 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3722 {
<> 144:ef7eb2e8f9f7 3723 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3724 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3725 }
<> 144:ef7eb2e8f9f7 3726 else
<> 144:ef7eb2e8f9f7 3727 {
<> 144:ef7eb2e8f9f7 3728 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3729 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3730 }
<> 144:ef7eb2e8f9f7 3731 }
<> 144:ef7eb2e8f9f7 3732 break;
<> 144:ef7eb2e8f9f7 3733 default:
<> 144:ef7eb2e8f9f7 3734 break;
<> 144:ef7eb2e8f9f7 3735 }
<> 144:ef7eb2e8f9f7 3736
<> 144:ef7eb2e8f9f7 3737 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3738
<> 144:ef7eb2e8f9f7 3739 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3740
<> 144:ef7eb2e8f9f7 3741 return HAL_OK;
<> 144:ef7eb2e8f9f7 3742 }
<> 144:ef7eb2e8f9f7 3743
<> 144:ef7eb2e8f9f7 3744 /**
<> 144:ef7eb2e8f9f7 3745 * @brief Configures the clock source to be used
<> 144:ef7eb2e8f9f7 3746 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3747 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3748 * contains the clock source information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3749 * @retval HAL status
<> 144:ef7eb2e8f9f7 3750 */
<> 144:ef7eb2e8f9f7 3751 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
<> 144:ef7eb2e8f9f7 3752 {
<> 151:5eaa88a5bcc7 3753 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 3754
<> 144:ef7eb2e8f9f7 3755 /* Process Locked */
<> 144:ef7eb2e8f9f7 3756 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3757
<> 144:ef7eb2e8f9f7 3758 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3759
<> 144:ef7eb2e8f9f7 3760 /* Check the clock source */
<> 144:ef7eb2e8f9f7 3761 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<> 144:ef7eb2e8f9f7 3762
<> 144:ef7eb2e8f9f7 3763 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<> 144:ef7eb2e8f9f7 3764 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3765 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3766 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 3767 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3768
<> 144:ef7eb2e8f9f7 3769 switch (sClockSourceConfig->ClockSource)
<> 144:ef7eb2e8f9f7 3770 {
<> 144:ef7eb2e8f9f7 3771 case TIM_CLOCKSOURCE_INTERNAL:
<> 144:ef7eb2e8f9f7 3772 {
<> 144:ef7eb2e8f9f7 3773 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3774 /* Disable slave mode to clock the prescaler directly with the internal clock */
<> 144:ef7eb2e8f9f7 3775 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3776 }
<> 144:ef7eb2e8f9f7 3777 break;
<> 144:ef7eb2e8f9f7 3778
<> 144:ef7eb2e8f9f7 3779 case TIM_CLOCKSOURCE_ETRMODE1:
<> 144:ef7eb2e8f9f7 3780 {
<> 144:ef7eb2e8f9f7 3781 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3782 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3783 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3784 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3785 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3786 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3787 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3788 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3789 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3790 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 3791 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3792 /* Reset the SMS and TS Bits */
<> 144:ef7eb2e8f9f7 3793 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3794 /* Select the External clock mode1 and the ETRF trigger */
<> 144:ef7eb2e8f9f7 3795 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
<> 144:ef7eb2e8f9f7 3796 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 3797 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3798 }
<> 144:ef7eb2e8f9f7 3799 break;
<> 144:ef7eb2e8f9f7 3800
<> 144:ef7eb2e8f9f7 3801 case TIM_CLOCKSOURCE_ETRMODE2:
<> 144:ef7eb2e8f9f7 3802 {
<> 144:ef7eb2e8f9f7 3803 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3804 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3805 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3806 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3807 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3808 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3809 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3810 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3811 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3812 /* Enable the External clock mode2 */
<> 144:ef7eb2e8f9f7 3813 htim->Instance->SMCR |= TIM_SMCR_ECE;
<> 144:ef7eb2e8f9f7 3814 }
<> 144:ef7eb2e8f9f7 3815 break;
<> 144:ef7eb2e8f9f7 3816
<> 144:ef7eb2e8f9f7 3817 case TIM_CLOCKSOURCE_TI1:
<> 144:ef7eb2e8f9f7 3818 {
<> 144:ef7eb2e8f9f7 3819 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3820 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3821 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3822 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 3823 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3824 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3825 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<> 144:ef7eb2e8f9f7 3826 }
<> 144:ef7eb2e8f9f7 3827 break;
<> 144:ef7eb2e8f9f7 3828 case TIM_CLOCKSOURCE_TI2:
<> 144:ef7eb2e8f9f7 3829 {
<> 144:ef7eb2e8f9f7 3830 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3831 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3832 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3833 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 3834 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3835 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3836 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<> 144:ef7eb2e8f9f7 3837 }
<> 144:ef7eb2e8f9f7 3838 break;
<> 144:ef7eb2e8f9f7 3839 case TIM_CLOCKSOURCE_TI1ED:
<> 144:ef7eb2e8f9f7 3840 {
<> 144:ef7eb2e8f9f7 3841 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3842 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3843 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3844 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 3845 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3846 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3847 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<> 144:ef7eb2e8f9f7 3848 }
<> 144:ef7eb2e8f9f7 3849 break;
<> 144:ef7eb2e8f9f7 3850 case TIM_CLOCKSOURCE_ITR0:
<> 144:ef7eb2e8f9f7 3851 {
<> 144:ef7eb2e8f9f7 3852 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3853 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<> 144:ef7eb2e8f9f7 3854 }
<> 144:ef7eb2e8f9f7 3855 break;
<> 144:ef7eb2e8f9f7 3856 case TIM_CLOCKSOURCE_ITR1:
<> 144:ef7eb2e8f9f7 3857 {
<> 144:ef7eb2e8f9f7 3858 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3859 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<> 144:ef7eb2e8f9f7 3860 }
<> 144:ef7eb2e8f9f7 3861 break;
<> 144:ef7eb2e8f9f7 3862 case TIM_CLOCKSOURCE_ITR2:
<> 144:ef7eb2e8f9f7 3863 {
<> 144:ef7eb2e8f9f7 3864 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3865 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<> 144:ef7eb2e8f9f7 3866 }
<> 144:ef7eb2e8f9f7 3867 break;
<> 144:ef7eb2e8f9f7 3868 case TIM_CLOCKSOURCE_ITR3:
<> 144:ef7eb2e8f9f7 3869 {
<> 144:ef7eb2e8f9f7 3870 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3871 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<> 144:ef7eb2e8f9f7 3872 }
<> 144:ef7eb2e8f9f7 3873 break;
<> 144:ef7eb2e8f9f7 3874
<> 144:ef7eb2e8f9f7 3875 default:
<> 144:ef7eb2e8f9f7 3876 break;
<> 144:ef7eb2e8f9f7 3877 }
<> 144:ef7eb2e8f9f7 3878 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3879
<> 144:ef7eb2e8f9f7 3880 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3881
<> 144:ef7eb2e8f9f7 3882 return HAL_OK;
<> 144:ef7eb2e8f9f7 3883 }
<> 144:ef7eb2e8f9f7 3884
<> 144:ef7eb2e8f9f7 3885 /**
<> 144:ef7eb2e8f9f7 3886 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
<> 144:ef7eb2e8f9f7 3887 * or a XOR combination between CH1_input, CH2_input & CH3_input
<> 144:ef7eb2e8f9f7 3888 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3889 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
<> 144:ef7eb2e8f9f7 3890 * output of a XOR gate.
<> 144:ef7eb2e8f9f7 3891 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3892 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<> 144:ef7eb2e8f9f7 3893 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<> 144:ef7eb2e8f9f7 3894 * pins are connected to the TI1 input (XOR combination)
<> 144:ef7eb2e8f9f7 3895 * @retval HAL status
<> 144:ef7eb2e8f9f7 3896 */
<> 144:ef7eb2e8f9f7 3897 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<> 144:ef7eb2e8f9f7 3898 {
<> 151:5eaa88a5bcc7 3899 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 3900
<> 144:ef7eb2e8f9f7 3901 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3902 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3903 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<> 144:ef7eb2e8f9f7 3904
<> 144:ef7eb2e8f9f7 3905 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 3906 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 3907
<> 144:ef7eb2e8f9f7 3908 /* Reset the TI1 selection */
<> 144:ef7eb2e8f9f7 3909 tmpcr2 &= ~TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 3910
<> 144:ef7eb2e8f9f7 3911 /* Set the the TI1 selection */
<> 144:ef7eb2e8f9f7 3912 tmpcr2 |= TI1_Selection;
<> 144:ef7eb2e8f9f7 3913
<> 144:ef7eb2e8f9f7 3914 /* Write to TIMxCR2 */
<> 144:ef7eb2e8f9f7 3915 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 3916
<> 144:ef7eb2e8f9f7 3917 return HAL_OK;
<> 144:ef7eb2e8f9f7 3918 }
<> 144:ef7eb2e8f9f7 3919
<> 144:ef7eb2e8f9f7 3920 /**
<> 144:ef7eb2e8f9f7 3921 * @brief Configures the TIM in Slave mode
<> 144:ef7eb2e8f9f7 3922 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3923 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3924 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 3925 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 3926 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 3927 * @retval HAL status
<> 144:ef7eb2e8f9f7 3928 */
<> 144:ef7eb2e8f9f7 3929 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 3930 {
<> 144:ef7eb2e8f9f7 3931 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3932 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3933 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 3934 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 3935
<> 144:ef7eb2e8f9f7 3936 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3937
<> 144:ef7eb2e8f9f7 3938 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3939
<> 144:ef7eb2e8f9f7 3940 /* Configuration in slave mode */
<> 144:ef7eb2e8f9f7 3941 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 3942
<> 144:ef7eb2e8f9f7 3943 /* Disable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 3944 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 3945
<> 144:ef7eb2e8f9f7 3946 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 3947 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 3948
<> 144:ef7eb2e8f9f7 3949 /* Set the new state */
<> 144:ef7eb2e8f9f7 3950 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3951
<> 144:ef7eb2e8f9f7 3952 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3953
<> 144:ef7eb2e8f9f7 3954 return HAL_OK;
<> 144:ef7eb2e8f9f7 3955 }
<> 144:ef7eb2e8f9f7 3956
<> 144:ef7eb2e8f9f7 3957 /**
<> 144:ef7eb2e8f9f7 3958 * @brief Configures the TIM in Slave mode in interrupt mode
<> 144:ef7eb2e8f9f7 3959 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 3960 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3961 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 3962 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 3963 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 3964 * @retval HAL status
<> 144:ef7eb2e8f9f7 3965 */
<> 144:ef7eb2e8f9f7 3966 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 3967 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 3968 {
<> 144:ef7eb2e8f9f7 3969 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3970 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3971 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 3972 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 3973
<> 144:ef7eb2e8f9f7 3974 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3975
<> 144:ef7eb2e8f9f7 3976 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3977
<> 144:ef7eb2e8f9f7 3978 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 3979
<> 144:ef7eb2e8f9f7 3980 /* Enable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 3981 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 3982
<> 144:ef7eb2e8f9f7 3983 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 3984 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 3985
<> 144:ef7eb2e8f9f7 3986 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3987
<> 144:ef7eb2e8f9f7 3988 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3989
<> 144:ef7eb2e8f9f7 3990 return HAL_OK;
<> 144:ef7eb2e8f9f7 3991 }
<> 144:ef7eb2e8f9f7 3992
<> 144:ef7eb2e8f9f7 3993 /**
<> 144:ef7eb2e8f9f7 3994 * @brief Read the captured value from Capture Compare unit
<> 144:ef7eb2e8f9f7 3995 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3996 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3997 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3998 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3999 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 4000 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 4001 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 4002 * @retval Captured value
<> 144:ef7eb2e8f9f7 4003 */
<> 144:ef7eb2e8f9f7 4004 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 4005 {
<> 151:5eaa88a5bcc7 4006 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 4007
<> 144:ef7eb2e8f9f7 4008 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4009
<> 144:ef7eb2e8f9f7 4010 switch (Channel)
<> 144:ef7eb2e8f9f7 4011 {
<> 144:ef7eb2e8f9f7 4012 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 4013 {
<> 144:ef7eb2e8f9f7 4014 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4015 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4016
<> 144:ef7eb2e8f9f7 4017 /* Return the capture 1 value */
<> 144:ef7eb2e8f9f7 4018 tmpreg = htim->Instance->CCR1;
<> 144:ef7eb2e8f9f7 4019
<> 144:ef7eb2e8f9f7 4020 break;
<> 144:ef7eb2e8f9f7 4021 }
<> 144:ef7eb2e8f9f7 4022 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 4023 {
<> 144:ef7eb2e8f9f7 4024 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4025 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4026
<> 144:ef7eb2e8f9f7 4027 /* Return the capture 2 value */
<> 144:ef7eb2e8f9f7 4028 tmpreg = htim->Instance->CCR2;
<> 144:ef7eb2e8f9f7 4029
<> 144:ef7eb2e8f9f7 4030 break;
<> 144:ef7eb2e8f9f7 4031 }
<> 144:ef7eb2e8f9f7 4032
<> 144:ef7eb2e8f9f7 4033 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 4034 {
<> 144:ef7eb2e8f9f7 4035 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4036 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4037
<> 144:ef7eb2e8f9f7 4038 /* Return the capture 3 value */
<> 144:ef7eb2e8f9f7 4039 tmpreg = htim->Instance->CCR3;
<> 144:ef7eb2e8f9f7 4040
<> 144:ef7eb2e8f9f7 4041 break;
<> 144:ef7eb2e8f9f7 4042 }
<> 144:ef7eb2e8f9f7 4043
<> 144:ef7eb2e8f9f7 4044 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 4045 {
<> 144:ef7eb2e8f9f7 4046 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4047 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4048
<> 144:ef7eb2e8f9f7 4049 /* Return the capture 4 value */
<> 144:ef7eb2e8f9f7 4050 tmpreg = htim->Instance->CCR4;
<> 144:ef7eb2e8f9f7 4051
<> 144:ef7eb2e8f9f7 4052 break;
<> 144:ef7eb2e8f9f7 4053 }
<> 144:ef7eb2e8f9f7 4054
<> 144:ef7eb2e8f9f7 4055 default:
<> 144:ef7eb2e8f9f7 4056 break;
<> 144:ef7eb2e8f9f7 4057 }
<> 144:ef7eb2e8f9f7 4058
<> 144:ef7eb2e8f9f7 4059 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4060 return tmpreg;
<> 144:ef7eb2e8f9f7 4061 }
<> 144:ef7eb2e8f9f7 4062
<> 144:ef7eb2e8f9f7 4063 /**
<> 144:ef7eb2e8f9f7 4064 * @}
<> 144:ef7eb2e8f9f7 4065 */
<> 144:ef7eb2e8f9f7 4066
<> 144:ef7eb2e8f9f7 4067 /** @addtogroup TIM_Exported_Functions_Group9
<> 144:ef7eb2e8f9f7 4068 * @brief TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4069 *
<> 144:ef7eb2e8f9f7 4070 @verbatim
<> 144:ef7eb2e8f9f7 4071 ==============================================================================
<> 144:ef7eb2e8f9f7 4072 ##### TIM Callbacks functions #####
<> 144:ef7eb2e8f9f7 4073 ==============================================================================
<> 144:ef7eb2e8f9f7 4074 [..]
<> 144:ef7eb2e8f9f7 4075 This section provides TIM callback functions:
<> 144:ef7eb2e8f9f7 4076 (+) Timer Period elapsed callback
<> 144:ef7eb2e8f9f7 4077 (+) Timer Output Compare callback
<> 144:ef7eb2e8f9f7 4078 (+) Timer Input capture callback
<> 144:ef7eb2e8f9f7 4079 (+) Timer Trigger callback
<> 144:ef7eb2e8f9f7 4080 (+) Timer Error callback
<> 144:ef7eb2e8f9f7 4081
<> 144:ef7eb2e8f9f7 4082 @endverbatim
<> 144:ef7eb2e8f9f7 4083 * @{
<> 144:ef7eb2e8f9f7 4084 */
<> 144:ef7eb2e8f9f7 4085
<> 144:ef7eb2e8f9f7 4086 /**
<> 144:ef7eb2e8f9f7 4087 * @brief Period elapsed callback in non blocking mode
<> 144:ef7eb2e8f9f7 4088 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4089 * @retval None
<> 144:ef7eb2e8f9f7 4090 */
<> 144:ef7eb2e8f9f7 4091 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4092 {
<> 144:ef7eb2e8f9f7 4093 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4094 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4095
<> 144:ef7eb2e8f9f7 4096 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4097 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4098 */
<> 144:ef7eb2e8f9f7 4099
<> 144:ef7eb2e8f9f7 4100 }
<> 144:ef7eb2e8f9f7 4101 /**
<> 144:ef7eb2e8f9f7 4102 * @brief Output Compare callback in non blocking mode
<> 144:ef7eb2e8f9f7 4103 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4104 * @retval None
<> 144:ef7eb2e8f9f7 4105 */
<> 144:ef7eb2e8f9f7 4106 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4107 {
<> 144:ef7eb2e8f9f7 4108 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4109 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4110
<> 144:ef7eb2e8f9f7 4111 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4112 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4113 */
<> 144:ef7eb2e8f9f7 4114 }
<> 144:ef7eb2e8f9f7 4115 /**
<> 144:ef7eb2e8f9f7 4116 * @brief Input Capture callback in non blocking mode
<> 144:ef7eb2e8f9f7 4117 * @param htim: TIM IC handle
<> 144:ef7eb2e8f9f7 4118 * @retval None
<> 144:ef7eb2e8f9f7 4119 */
<> 144:ef7eb2e8f9f7 4120 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4121 {
<> 144:ef7eb2e8f9f7 4122 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4123 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4124
<> 144:ef7eb2e8f9f7 4125 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4126 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4127 */
<> 144:ef7eb2e8f9f7 4128 }
<> 144:ef7eb2e8f9f7 4129
<> 144:ef7eb2e8f9f7 4130 /**
<> 144:ef7eb2e8f9f7 4131 * @brief PWM Pulse finished callback in non blocking mode
<> 144:ef7eb2e8f9f7 4132 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4133 * @retval None
<> 144:ef7eb2e8f9f7 4134 */
<> 144:ef7eb2e8f9f7 4135 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4136 {
<> 144:ef7eb2e8f9f7 4137 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4138 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4139
<> 144:ef7eb2e8f9f7 4140 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4141 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4142 */
<> 144:ef7eb2e8f9f7 4143 }
<> 144:ef7eb2e8f9f7 4144
<> 144:ef7eb2e8f9f7 4145 /**
<> 144:ef7eb2e8f9f7 4146 * @brief Hall Trigger detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 4147 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4148 * @retval None
<> 144:ef7eb2e8f9f7 4149 */
<> 144:ef7eb2e8f9f7 4150 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4151 {
<> 144:ef7eb2e8f9f7 4152 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4153 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4154
<> 144:ef7eb2e8f9f7 4155 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4156 the HAL_TIM_TriggerCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4157 */
<> 144:ef7eb2e8f9f7 4158 }
<> 144:ef7eb2e8f9f7 4159
<> 144:ef7eb2e8f9f7 4160 /**
<> 144:ef7eb2e8f9f7 4161 * @brief Timer error callback in non blocking mode
<> 144:ef7eb2e8f9f7 4162 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4163 * @retval None
<> 144:ef7eb2e8f9f7 4164 */
<> 144:ef7eb2e8f9f7 4165 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4166 {
<> 144:ef7eb2e8f9f7 4167 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4168 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4169
<> 144:ef7eb2e8f9f7 4170 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4171 the HAL_TIM_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4172 */
<> 144:ef7eb2e8f9f7 4173 }
<> 144:ef7eb2e8f9f7 4174
<> 144:ef7eb2e8f9f7 4175 /**
<> 144:ef7eb2e8f9f7 4176 * @}
<> 144:ef7eb2e8f9f7 4177 */
<> 144:ef7eb2e8f9f7 4178
<> 144:ef7eb2e8f9f7 4179 /** @addtogroup TIM_Exported_Functions_Group10
<> 144:ef7eb2e8f9f7 4180 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 4181 *
<> 144:ef7eb2e8f9f7 4182 @verbatim
<> 144:ef7eb2e8f9f7 4183 ==============================================================================
<> 144:ef7eb2e8f9f7 4184 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 4185 ==============================================================================
<> 144:ef7eb2e8f9f7 4186 [..]
<> 144:ef7eb2e8f9f7 4187 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 4188 and the data flow.
<> 144:ef7eb2e8f9f7 4189
<> 144:ef7eb2e8f9f7 4190 @endverbatim
<> 144:ef7eb2e8f9f7 4191 * @{
<> 144:ef7eb2e8f9f7 4192 */
<> 144:ef7eb2e8f9f7 4193
<> 144:ef7eb2e8f9f7 4194 /**
<> 144:ef7eb2e8f9f7 4195 * @brief Return the TIM Base state
<> 144:ef7eb2e8f9f7 4196 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4197 * @retval HAL state
<> 144:ef7eb2e8f9f7 4198 */
<> 144:ef7eb2e8f9f7 4199 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4200 {
<> 144:ef7eb2e8f9f7 4201 return htim->State;
<> 144:ef7eb2e8f9f7 4202 }
<> 144:ef7eb2e8f9f7 4203
<> 144:ef7eb2e8f9f7 4204 /**
<> 144:ef7eb2e8f9f7 4205 * @brief Return the TIM OC state
<> 144:ef7eb2e8f9f7 4206 * @param htim: TIM Ouput Compare handle
<> 144:ef7eb2e8f9f7 4207 * @retval HAL state
<> 144:ef7eb2e8f9f7 4208 */
<> 144:ef7eb2e8f9f7 4209 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4210 {
<> 144:ef7eb2e8f9f7 4211 return htim->State;
<> 144:ef7eb2e8f9f7 4212 }
<> 144:ef7eb2e8f9f7 4213
<> 144:ef7eb2e8f9f7 4214 /**
<> 144:ef7eb2e8f9f7 4215 * @brief Return the TIM PWM state
<> 144:ef7eb2e8f9f7 4216 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4217 * @retval HAL state
<> 144:ef7eb2e8f9f7 4218 */
<> 144:ef7eb2e8f9f7 4219 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4220 {
<> 144:ef7eb2e8f9f7 4221 return htim->State;
<> 144:ef7eb2e8f9f7 4222 }
<> 144:ef7eb2e8f9f7 4223
<> 144:ef7eb2e8f9f7 4224 /**
<> 144:ef7eb2e8f9f7 4225 * @brief Return the TIM Input Capture state
<> 144:ef7eb2e8f9f7 4226 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4227 * @retval HAL state
<> 144:ef7eb2e8f9f7 4228 */
<> 144:ef7eb2e8f9f7 4229 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4230 {
<> 144:ef7eb2e8f9f7 4231 return htim->State;
<> 144:ef7eb2e8f9f7 4232 }
<> 144:ef7eb2e8f9f7 4233
<> 144:ef7eb2e8f9f7 4234 /**
<> 144:ef7eb2e8f9f7 4235 * @brief Return the TIM One Pulse Mode state
<> 144:ef7eb2e8f9f7 4236 * @param htim: TIM OPM handle
<> 144:ef7eb2e8f9f7 4237 * @retval HAL state
<> 144:ef7eb2e8f9f7 4238 */
<> 144:ef7eb2e8f9f7 4239 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4240 {
<> 144:ef7eb2e8f9f7 4241 return htim->State;
<> 144:ef7eb2e8f9f7 4242 }
<> 144:ef7eb2e8f9f7 4243
<> 144:ef7eb2e8f9f7 4244 /**
<> 144:ef7eb2e8f9f7 4245 * @brief Return the TIM Encoder Mode state
<> 144:ef7eb2e8f9f7 4246 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4247 * @retval HAL state
<> 144:ef7eb2e8f9f7 4248 */
<> 144:ef7eb2e8f9f7 4249 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4250 {
<> 144:ef7eb2e8f9f7 4251 return htim->State;
<> 144:ef7eb2e8f9f7 4252 }
<> 144:ef7eb2e8f9f7 4253
<> 144:ef7eb2e8f9f7 4254
<> 144:ef7eb2e8f9f7 4255
<> 144:ef7eb2e8f9f7 4256 /**
<> 144:ef7eb2e8f9f7 4257 * @brief TIM DMA error callback
<> 144:ef7eb2e8f9f7 4258 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4259 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4260 * @retval None
<> 144:ef7eb2e8f9f7 4261 */
<> 144:ef7eb2e8f9f7 4262 void TIM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4263 {
<> 144:ef7eb2e8f9f7 4264 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4265
<> 144:ef7eb2e8f9f7 4266 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4267
<> 144:ef7eb2e8f9f7 4268 HAL_TIM_ErrorCallback(htim);
<> 144:ef7eb2e8f9f7 4269 }
<> 144:ef7eb2e8f9f7 4270
<> 144:ef7eb2e8f9f7 4271 /**
<> 144:ef7eb2e8f9f7 4272 * @brief TIM DMA Delay Pulse complete callback.
<> 144:ef7eb2e8f9f7 4273 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4274 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4275 * @retval None
<> 144:ef7eb2e8f9f7 4276 */
<> 144:ef7eb2e8f9f7 4277 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4278 {
<> 144:ef7eb2e8f9f7 4279 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4280
<> 144:ef7eb2e8f9f7 4281 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4282
<> 144:ef7eb2e8f9f7 4283 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4284 {
<> 144:ef7eb2e8f9f7 4285 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4286 }
<> 144:ef7eb2e8f9f7 4287 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4288 {
<> 144:ef7eb2e8f9f7 4289 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4290 }
<> 144:ef7eb2e8f9f7 4291 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4292 {
<> 144:ef7eb2e8f9f7 4293 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4294 }
<> 144:ef7eb2e8f9f7 4295 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4296 {
<> 144:ef7eb2e8f9f7 4297 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4298 }
<> 144:ef7eb2e8f9f7 4299 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 4300
<> 144:ef7eb2e8f9f7 4301 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4302 }
<> 144:ef7eb2e8f9f7 4303 /**
<> 144:ef7eb2e8f9f7 4304 * @brief TIM DMA Capture complete callback.
<> 144:ef7eb2e8f9f7 4305 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4306 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4307 * @retval None
<> 144:ef7eb2e8f9f7 4308 */
<> 144:ef7eb2e8f9f7 4309 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4310 {
<> 144:ef7eb2e8f9f7 4311 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4312
<> 144:ef7eb2e8f9f7 4313 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4314
<> 144:ef7eb2e8f9f7 4315 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4316 {
<> 144:ef7eb2e8f9f7 4317 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4318 }
<> 144:ef7eb2e8f9f7 4319 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4320 {
<> 144:ef7eb2e8f9f7 4321 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4322 }
<> 144:ef7eb2e8f9f7 4323 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4324 {
<> 144:ef7eb2e8f9f7 4325 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4326 }
<> 144:ef7eb2e8f9f7 4327 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4328 {
<> 144:ef7eb2e8f9f7 4329 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4330 }
<> 144:ef7eb2e8f9f7 4331
<> 144:ef7eb2e8f9f7 4332 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 4333
<> 144:ef7eb2e8f9f7 4334 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4335 }
<> 144:ef7eb2e8f9f7 4336
<> 144:ef7eb2e8f9f7 4337
<> 144:ef7eb2e8f9f7 4338 /**
<> 144:ef7eb2e8f9f7 4339 * @}
<> 144:ef7eb2e8f9f7 4340 */
<> 144:ef7eb2e8f9f7 4341
<> 144:ef7eb2e8f9f7 4342 /**
<> 144:ef7eb2e8f9f7 4343 * @}
<> 144:ef7eb2e8f9f7 4344 */
<> 144:ef7eb2e8f9f7 4345 /*************************************************************/
<> 144:ef7eb2e8f9f7 4346 /* Private functions */
<> 144:ef7eb2e8f9f7 4347 /*************************************************************/
<> 144:ef7eb2e8f9f7 4348
<> 144:ef7eb2e8f9f7 4349 /** @addtogroup TIM_Private TIM Private
<> 144:ef7eb2e8f9f7 4350 * @{
<> 144:ef7eb2e8f9f7 4351 */
<> 144:ef7eb2e8f9f7 4352 /**
<> 144:ef7eb2e8f9f7 4353 * @brief TIM DMA Period Elapse complete callback.
<> 144:ef7eb2e8f9f7 4354 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4355 * @retval None
<> 144:ef7eb2e8f9f7 4356 */
<> 144:ef7eb2e8f9f7 4357 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4358 {
<> 144:ef7eb2e8f9f7 4359 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4360
<> 144:ef7eb2e8f9f7 4361 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4362
<> 144:ef7eb2e8f9f7 4363 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 4364 }
<> 144:ef7eb2e8f9f7 4365
<> 144:ef7eb2e8f9f7 4366
<> 144:ef7eb2e8f9f7 4367 /**
<> 144:ef7eb2e8f9f7 4368 * @brief TIM DMA Trigger callback.
<> 144:ef7eb2e8f9f7 4369 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4370 * @retval None
<> 144:ef7eb2e8f9f7 4371 */
<> 144:ef7eb2e8f9f7 4372 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4373 {
<> 144:ef7eb2e8f9f7 4374 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4375
<> 144:ef7eb2e8f9f7 4376 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4377
<> 144:ef7eb2e8f9f7 4378 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 4379 }
<> 144:ef7eb2e8f9f7 4380
<> 144:ef7eb2e8f9f7 4381 /**
<> 144:ef7eb2e8f9f7 4382 * @brief Time Base configuration
<> 144:ef7eb2e8f9f7 4383 * @param TIMx : TIM peripheral
<> 144:ef7eb2e8f9f7 4384 * @param Structure : TIM Base configuration structure
<> 144:ef7eb2e8f9f7 4385 * @retval None
<> 144:ef7eb2e8f9f7 4386 */
<> 144:ef7eb2e8f9f7 4387 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
<> 144:ef7eb2e8f9f7 4388 {
<> 151:5eaa88a5bcc7 4389 uint32_t tmpcr1 = 0U;
<> 144:ef7eb2e8f9f7 4390 tmpcr1 = TIMx->CR1;
<> 144:ef7eb2e8f9f7 4391
<> 144:ef7eb2e8f9f7 4392 /* Set TIM Time Base Unit parameters ---------------------------------------*/
<> 144:ef7eb2e8f9f7 4393 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4394 {
<> 144:ef7eb2e8f9f7 4395 /* Select the Counter Mode */
<> 144:ef7eb2e8f9f7 4396 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
<> 144:ef7eb2e8f9f7 4397 tmpcr1 |= Structure->CounterMode;
<> 144:ef7eb2e8f9f7 4398 }
<> 144:ef7eb2e8f9f7 4399
<> 144:ef7eb2e8f9f7 4400 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4401 {
<> 144:ef7eb2e8f9f7 4402 /* Set the clock division */
<> 144:ef7eb2e8f9f7 4403 tmpcr1 &= ~TIM_CR1_CKD;
<> 144:ef7eb2e8f9f7 4404 tmpcr1 |= (uint32_t)Structure->ClockDivision;
<> 144:ef7eb2e8f9f7 4405 }
<> 144:ef7eb2e8f9f7 4406
<> 144:ef7eb2e8f9f7 4407 TIMx->CR1 = tmpcr1;
<> 144:ef7eb2e8f9f7 4408
<> 144:ef7eb2e8f9f7 4409 /* Set the Autoreload value */
<> 144:ef7eb2e8f9f7 4410 TIMx->ARR = (uint32_t)Structure->Period ;
<> 144:ef7eb2e8f9f7 4411
<> 144:ef7eb2e8f9f7 4412 /* Set the Prescaler value */
<> 144:ef7eb2e8f9f7 4413 TIMx->PSC = (uint32_t)Structure->Prescaler;
<> 144:ef7eb2e8f9f7 4414
<> 144:ef7eb2e8f9f7 4415 /* Generate an update event to reload the Prescaler value immediatly */
<> 144:ef7eb2e8f9f7 4416 TIMx->EGR = TIM_EGR_UG;
<> 144:ef7eb2e8f9f7 4417 }
<> 144:ef7eb2e8f9f7 4418
<> 144:ef7eb2e8f9f7 4419 /**
<> 144:ef7eb2e8f9f7 4420 * @brief Time Ouput Compare 1 configuration
<> 144:ef7eb2e8f9f7 4421 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4422 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4423 * @retval None
<> 144:ef7eb2e8f9f7 4424 */
<> 144:ef7eb2e8f9f7 4425 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4426 {
<> 151:5eaa88a5bcc7 4427 uint32_t tmpccmrx = 0U;
<> 151:5eaa88a5bcc7 4428 uint32_t tmpccer = 0U;
<> 151:5eaa88a5bcc7 4429 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4430
<> 144:ef7eb2e8f9f7 4431 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4432 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4433
<> 144:ef7eb2e8f9f7 4434 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4435 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4436 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4437 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4438
<> 144:ef7eb2e8f9f7 4439 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4440 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4441
<> 144:ef7eb2e8f9f7 4442 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 4443 tmpccmrx &= ~TIM_CCMR1_OC1M;
<> 144:ef7eb2e8f9f7 4444 tmpccmrx &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4445 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4446 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4447
<> 144:ef7eb2e8f9f7 4448 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4449 tmpccer &= ~TIM_CCER_CC1P;
<> 144:ef7eb2e8f9f7 4450 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4451 tmpccer |= OC_Config->OCPolarity;
<> 144:ef7eb2e8f9f7 4452
<> 144:ef7eb2e8f9f7 4453 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4454 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4455
<> 144:ef7eb2e8f9f7 4456 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4457 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4458
<> 144:ef7eb2e8f9f7 4459 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4460 TIMx->CCR1 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4461
<> 144:ef7eb2e8f9f7 4462 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4463 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4464 }
<> 144:ef7eb2e8f9f7 4465
<> 144:ef7eb2e8f9f7 4466 /**
<> 144:ef7eb2e8f9f7 4467 * @brief Time Ouput Compare 2 configuration
<> 144:ef7eb2e8f9f7 4468 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4469 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4470 * @retval None
<> 144:ef7eb2e8f9f7 4471 */
<> 144:ef7eb2e8f9f7 4472 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4473 {
<> 151:5eaa88a5bcc7 4474 uint32_t tmpccmrx = 0U;
<> 151:5eaa88a5bcc7 4475 uint32_t tmpccer = 0U;
<> 151:5eaa88a5bcc7 4476 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4477
<> 144:ef7eb2e8f9f7 4478 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4479 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4480
<> 144:ef7eb2e8f9f7 4481 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4482 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4483 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4484 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4485
<> 144:ef7eb2e8f9f7 4486 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4487 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4488
<> 144:ef7eb2e8f9f7 4489 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4490 tmpccmrx &= ~TIM_CCMR1_OC2M;
<> 144:ef7eb2e8f9f7 4491 tmpccmrx &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 4492
<> 144:ef7eb2e8f9f7 4493 /* Select the Output Compare Mode */
<> 151:5eaa88a5bcc7 4494 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4495
<> 144:ef7eb2e8f9f7 4496 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4497 tmpccer &= ~TIM_CCER_CC2P;
<> 144:ef7eb2e8f9f7 4498 /* Set the Output Compare Polarity */
<> 151:5eaa88a5bcc7 4499 tmpccer |= (OC_Config->OCPolarity << 4U);
<> 144:ef7eb2e8f9f7 4500
<> 144:ef7eb2e8f9f7 4501 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4502 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4503
<> 144:ef7eb2e8f9f7 4504 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4505 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4506
<> 144:ef7eb2e8f9f7 4507 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4508 TIMx->CCR2 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4509
<> 144:ef7eb2e8f9f7 4510 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4511 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4512 }
<> 144:ef7eb2e8f9f7 4513
<> 144:ef7eb2e8f9f7 4514 /**
<> 144:ef7eb2e8f9f7 4515 * @brief Time Ouput Compare 3 configuration
<> 144:ef7eb2e8f9f7 4516 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4517 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4518 * @retval None
<> 144:ef7eb2e8f9f7 4519 */
<> 144:ef7eb2e8f9f7 4520 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4521 {
<> 151:5eaa88a5bcc7 4522 uint32_t tmpccmrx = 0U;
<> 151:5eaa88a5bcc7 4523 uint32_t tmpccer = 0U;
<> 151:5eaa88a5bcc7 4524 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4525
<> 144:ef7eb2e8f9f7 4526 /* Disable the Channel 3: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4527 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 4528
<> 144:ef7eb2e8f9f7 4529 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4530 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4531 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4532 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4533
<> 144:ef7eb2e8f9f7 4534 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4535 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4536
<> 144:ef7eb2e8f9f7 4537 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4538 tmpccmrx &= ~TIM_CCMR2_OC3M;
<> 144:ef7eb2e8f9f7 4539 tmpccmrx &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 4540 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4541 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4542
<> 144:ef7eb2e8f9f7 4543 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4544 tmpccer &= ~TIM_CCER_CC3P;
<> 144:ef7eb2e8f9f7 4545 /* Set the Output Compare Polarity */
<> 151:5eaa88a5bcc7 4546 tmpccer |= (OC_Config->OCPolarity << 8U);
<> 144:ef7eb2e8f9f7 4547
<> 144:ef7eb2e8f9f7 4548 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4549 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4550
<> 144:ef7eb2e8f9f7 4551 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4552 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4553
<> 144:ef7eb2e8f9f7 4554 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4555 TIMx->CCR3 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4556
<> 144:ef7eb2e8f9f7 4557 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4558 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4559 }
<> 144:ef7eb2e8f9f7 4560
<> 144:ef7eb2e8f9f7 4561 /**
<> 144:ef7eb2e8f9f7 4562 * @brief Time Ouput Compare 4 configuration
<> 144:ef7eb2e8f9f7 4563 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4564 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4565 * @retval None
<> 144:ef7eb2e8f9f7 4566 */
<> 144:ef7eb2e8f9f7 4567 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4568 {
<> 151:5eaa88a5bcc7 4569 uint32_t tmpccmrx = 0U;
<> 151:5eaa88a5bcc7 4570 uint32_t tmpccer = 0U;
<> 151:5eaa88a5bcc7 4571 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4572
<> 144:ef7eb2e8f9f7 4573 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 4574 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 4575
<> 144:ef7eb2e8f9f7 4576 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4577 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4578 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4579 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4580
<> 144:ef7eb2e8f9f7 4581 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4582 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4583
<> 144:ef7eb2e8f9f7 4584 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4585 tmpccmrx &= ~TIM_CCMR2_OC4M;
<> 144:ef7eb2e8f9f7 4586 tmpccmrx &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 4587
<> 144:ef7eb2e8f9f7 4588 /* Select the Output Compare Mode */
<> 151:5eaa88a5bcc7 4589 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4590
<> 144:ef7eb2e8f9f7 4591 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4592 tmpccer &= ~TIM_CCER_CC4P;
<> 144:ef7eb2e8f9f7 4593 /* Set the Output Compare Polarity */
<> 151:5eaa88a5bcc7 4594 tmpccer |= (OC_Config->OCPolarity << 12U);
<> 144:ef7eb2e8f9f7 4595
<> 144:ef7eb2e8f9f7 4596 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4597 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4598
<> 144:ef7eb2e8f9f7 4599 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4600 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4601
<> 144:ef7eb2e8f9f7 4602 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4603 TIMx->CCR4 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4604
<> 144:ef7eb2e8f9f7 4605 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4606 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4607 }
<> 144:ef7eb2e8f9f7 4608
<> 144:ef7eb2e8f9f7 4609 /**
<> 144:ef7eb2e8f9f7 4610 * @brief Configure the TI1 as Input.
<> 144:ef7eb2e8f9f7 4611 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 4612 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4613 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4614 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 4615 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 4616 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 4617 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 4618 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4619 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 4620 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 4621 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 4622 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 4623 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 4624 * @retval None
<> 144:ef7eb2e8f9f7 4625 */
<> 144:ef7eb2e8f9f7 4626 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 4627 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 4628 {
<> 151:5eaa88a5bcc7 4629 uint32_t tmpccmr1 = 0U;
<> 151:5eaa88a5bcc7 4630 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4631
<> 144:ef7eb2e8f9f7 4632 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4633 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4634 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4635 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4636
<> 144:ef7eb2e8f9f7 4637 /* Select the Input */
<> 144:ef7eb2e8f9f7 4638 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4639 {
<> 144:ef7eb2e8f9f7 4640 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4641 tmpccmr1 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 4642 }
<> 144:ef7eb2e8f9f7 4643 else
<> 144:ef7eb2e8f9f7 4644 {
<> 144:ef7eb2e8f9f7 4645 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4646 tmpccmr1 |= TIM_CCMR1_CC1S_0;
<> 144:ef7eb2e8f9f7 4647 }
<> 144:ef7eb2e8f9f7 4648
<> 144:ef7eb2e8f9f7 4649 /* Set the filter */
<> 144:ef7eb2e8f9f7 4650 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 151:5eaa88a5bcc7 4651 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
<> 144:ef7eb2e8f9f7 4652
<> 144:ef7eb2e8f9f7 4653 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 4654 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 4655 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
<> 144:ef7eb2e8f9f7 4656
<> 144:ef7eb2e8f9f7 4657 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4658 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 4659 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4660 }
<> 144:ef7eb2e8f9f7 4661
<> 144:ef7eb2e8f9f7 4662 /**
<> 144:ef7eb2e8f9f7 4663 * @brief Configure the Polarity and Filter for TI1.
<> 144:ef7eb2e8f9f7 4664 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 4665 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4666 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4667 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 4668 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 4669 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 4670 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 4671 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 4672 * @retval None
<> 144:ef7eb2e8f9f7 4673 */
<> 144:ef7eb2e8f9f7 4674 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 4675 {
<> 151:5eaa88a5bcc7 4676 uint32_t tmpccmr1 = 0U;
<> 151:5eaa88a5bcc7 4677 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4678
<> 144:ef7eb2e8f9f7 4679 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4680 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4681 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4682 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4683
<> 144:ef7eb2e8f9f7 4684 /* Set the filter */
<> 144:ef7eb2e8f9f7 4685 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 151:5eaa88a5bcc7 4686 tmpccmr1 |= (TIM_ICFilter << 4U);
<> 144:ef7eb2e8f9f7 4687
<> 144:ef7eb2e8f9f7 4688 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 4689 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 4690 tmpccer |= TIM_ICPolarity;
<> 144:ef7eb2e8f9f7 4691
<> 144:ef7eb2e8f9f7 4692 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4693 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 4694 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4695 }
<> 144:ef7eb2e8f9f7 4696
<> 144:ef7eb2e8f9f7 4697 /**
<> 144:ef7eb2e8f9f7 4698 * @brief Configure the TI2 as Input.
<> 144:ef7eb2e8f9f7 4699 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4700 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4701 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4702 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 4703 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 4704 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 4705 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 4706 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4707 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 4708 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 4709 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 4710 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 4711 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 4712 * @retval None
<> 144:ef7eb2e8f9f7 4713 */
<> 144:ef7eb2e8f9f7 4714 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 4715 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 4716 {
<> 151:5eaa88a5bcc7 4717 uint32_t tmpccmr1 = 0U;
<> 151:5eaa88a5bcc7 4718 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4719
<> 144:ef7eb2e8f9f7 4720 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4721 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4722 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4723 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4724
<> 144:ef7eb2e8f9f7 4725 /* Select the Input */
<> 144:ef7eb2e8f9f7 4726 tmpccmr1 &= ~TIM_CCMR1_CC2S;
<> 151:5eaa88a5bcc7 4727 tmpccmr1 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 4728
<> 144:ef7eb2e8f9f7 4729 /* Set the filter */
<> 144:ef7eb2e8f9f7 4730 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 151:5eaa88a5bcc7 4731 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 4732
<> 144:ef7eb2e8f9f7 4733 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 4734 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 151:5eaa88a5bcc7 4735 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
<> 144:ef7eb2e8f9f7 4736
<> 144:ef7eb2e8f9f7 4737 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4738 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 4739 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4740 }
<> 144:ef7eb2e8f9f7 4741
<> 144:ef7eb2e8f9f7 4742 /**
<> 144:ef7eb2e8f9f7 4743 * @brief Configure the Polarity and Filter for TI2.
<> 144:ef7eb2e8f9f7 4744 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 4745 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4746 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4747 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 4748 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 4749 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 4750 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 4751 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 4752 * @retval None
<> 144:ef7eb2e8f9f7 4753 */
<> 144:ef7eb2e8f9f7 4754 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 4755 {
<> 151:5eaa88a5bcc7 4756 uint32_t tmpccmr1 = 0U;
<> 151:5eaa88a5bcc7 4757 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4758
<> 144:ef7eb2e8f9f7 4759 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4760 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4761 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4762 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4763
<> 144:ef7eb2e8f9f7 4764 /* Set the filter */
<> 144:ef7eb2e8f9f7 4765 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 151:5eaa88a5bcc7 4766 tmpccmr1 |= (TIM_ICFilter << 12U);
<> 144:ef7eb2e8f9f7 4767
<> 144:ef7eb2e8f9f7 4768 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 4769 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 151:5eaa88a5bcc7 4770 tmpccer |= (TIM_ICPolarity << 4U);
<> 144:ef7eb2e8f9f7 4771
<> 144:ef7eb2e8f9f7 4772 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4773 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 4774 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4775 }
<> 144:ef7eb2e8f9f7 4776
<> 144:ef7eb2e8f9f7 4777 /**
<> 144:ef7eb2e8f9f7 4778 * @brief Configure the TI3 as Input.
<> 144:ef7eb2e8f9f7 4779 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4780 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4781 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4782 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 4783 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 4784 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 4785 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 4786 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4787 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 4788 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 4789 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 4790 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 4791 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 4792 * @retval None
<> 144:ef7eb2e8f9f7 4793 */
<> 144:ef7eb2e8f9f7 4794 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 4795 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 4796 {
<> 151:5eaa88a5bcc7 4797 uint32_t tmpccmr2 = 0U;
<> 151:5eaa88a5bcc7 4798 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4799
<> 144:ef7eb2e8f9f7 4800 /* Disable the Channel 3: Reset the CC3E Bit */
<> 144:ef7eb2e8f9f7 4801 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 4802 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4803 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4804
<> 144:ef7eb2e8f9f7 4805 /* Select the Input */
<> 144:ef7eb2e8f9f7 4806 tmpccmr2 &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 4807 tmpccmr2 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 4808
<> 144:ef7eb2e8f9f7 4809 /* Set the filter */
<> 144:ef7eb2e8f9f7 4810 tmpccmr2 &= ~TIM_CCMR2_IC3F;
<> 151:5eaa88a5bcc7 4811 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
<> 144:ef7eb2e8f9f7 4812
<> 144:ef7eb2e8f9f7 4813 /* Select the Polarity and set the CC3E Bit */
<> 144:ef7eb2e8f9f7 4814 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
<> 151:5eaa88a5bcc7 4815 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
<> 144:ef7eb2e8f9f7 4816
<> 144:ef7eb2e8f9f7 4817 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 4818 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 4819 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4820 }
<> 144:ef7eb2e8f9f7 4821
<> 144:ef7eb2e8f9f7 4822 /**
<> 144:ef7eb2e8f9f7 4823 * @brief Configure the TI4 as Input.
<> 144:ef7eb2e8f9f7 4824 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4825 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4826 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4827 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 4828 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 4829 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 4830 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 4831 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4832 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 4833 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 4834 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 4835 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 4836 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 4837 * @retval None
<> 144:ef7eb2e8f9f7 4838 */
<> 144:ef7eb2e8f9f7 4839 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 4840 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 4841 {
<> 151:5eaa88a5bcc7 4842 uint32_t tmpccmr2 = 0U;
<> 151:5eaa88a5bcc7 4843 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4844
<> 144:ef7eb2e8f9f7 4845 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 4846 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 4847 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4848 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4849
<> 144:ef7eb2e8f9f7 4850 /* Select the Input */
<> 144:ef7eb2e8f9f7 4851 tmpccmr2 &= ~TIM_CCMR2_CC4S;
<> 151:5eaa88a5bcc7 4852 tmpccmr2 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 4853
<> 144:ef7eb2e8f9f7 4854 /* Set the filter */
<> 144:ef7eb2e8f9f7 4855 tmpccmr2 &= ~TIM_CCMR2_IC4F;
<> 151:5eaa88a5bcc7 4856 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
<> 144:ef7eb2e8f9f7 4857
<> 144:ef7eb2e8f9f7 4858 /* Select the Polarity and set the CC4E Bit */
<> 144:ef7eb2e8f9f7 4859 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
<> 151:5eaa88a5bcc7 4860 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
<> 144:ef7eb2e8f9f7 4861
<> 144:ef7eb2e8f9f7 4862 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 4863 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 4864 TIMx->CCER = tmpccer ;
<> 144:ef7eb2e8f9f7 4865 }
<> 144:ef7eb2e8f9f7 4866
<> 144:ef7eb2e8f9f7 4867 /**
<> 144:ef7eb2e8f9f7 4868 * @brief Selects the Input Trigger source
<> 144:ef7eb2e8f9f7 4869 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4870 * @param InputTriggerSource: The Input Trigger source.
<> 144:ef7eb2e8f9f7 4871 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4872 * @arg TIM_TS_ITR0: Internal Trigger 0
<> 144:ef7eb2e8f9f7 4873 * @arg TIM_TS_ITR1: Internal Trigger 1
<> 144:ef7eb2e8f9f7 4874 * @arg TIM_TS_ITR2: Internal Trigger 2
<> 144:ef7eb2e8f9f7 4875 * @arg TIM_TS_ITR3: Internal Trigger 3
<> 144:ef7eb2e8f9f7 4876 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
<> 144:ef7eb2e8f9f7 4877 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
<> 144:ef7eb2e8f9f7 4878 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
<> 144:ef7eb2e8f9f7 4879 * @arg TIM_TS_ETRF: External Trigger input
<> 144:ef7eb2e8f9f7 4880 * @retval None
<> 144:ef7eb2e8f9f7 4881 */
<> 144:ef7eb2e8f9f7 4882 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<> 144:ef7eb2e8f9f7 4883 {
<> 151:5eaa88a5bcc7 4884 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 4885
<> 144:ef7eb2e8f9f7 4886 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4887 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 4888 /* Reset the TS Bits */
<> 144:ef7eb2e8f9f7 4889 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 4890 /* Set the Input Trigger source and the slave mode*/
<> 144:ef7eb2e8f9f7 4891 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
<> 144:ef7eb2e8f9f7 4892 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4893 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4894 }
<> 144:ef7eb2e8f9f7 4895 /**
<> 144:ef7eb2e8f9f7 4896 * @brief Configures the TIMx External Trigger (ETR).
<> 144:ef7eb2e8f9f7 4897 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4898 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
<> 144:ef7eb2e8f9f7 4899 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4900 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
<> 144:ef7eb2e8f9f7 4901 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
<> 144:ef7eb2e8f9f7 4902 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
<> 144:ef7eb2e8f9f7 4903 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
<> 144:ef7eb2e8f9f7 4904 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
<> 144:ef7eb2e8f9f7 4905 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4906 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
<> 144:ef7eb2e8f9f7 4907 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
<> 144:ef7eb2e8f9f7 4908 * @param ExtTRGFilter: External Trigger Filter.
<> 144:ef7eb2e8f9f7 4909 * This parameter must be a value between 0x00 and 0x0F
<> 144:ef7eb2e8f9f7 4910 * @retval None
<> 144:ef7eb2e8f9f7 4911 */
<> 144:ef7eb2e8f9f7 4912 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 4913 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<> 144:ef7eb2e8f9f7 4914 {
<> 151:5eaa88a5bcc7 4915 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 4916
<> 144:ef7eb2e8f9f7 4917 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 4918
<> 144:ef7eb2e8f9f7 4919 /* Reset the ETR Bits */
<> 144:ef7eb2e8f9f7 4920 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 4921
<> 144:ef7eb2e8f9f7 4922 /* Set the Prescaler, the Filter value and the Polarity */
<> 144:ef7eb2e8f9f7 4923 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
<> 144:ef7eb2e8f9f7 4924
<> 144:ef7eb2e8f9f7 4925 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4926 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4927 }
<> 144:ef7eb2e8f9f7 4928
<> 144:ef7eb2e8f9f7 4929 /**
<> 144:ef7eb2e8f9f7 4930 * @brief Enables or disables the TIM Capture Compare Channel x.
<> 144:ef7eb2e8f9f7 4931 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4932 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 4933 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4934 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 4935 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 4936 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 4937 * @arg TIM_Channel_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 4938 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
<> 144:ef7eb2e8f9f7 4939 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<> 144:ef7eb2e8f9f7 4940 * @retval None
<> 144:ef7eb2e8f9f7 4941 */
<> 144:ef7eb2e8f9f7 4942 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<> 144:ef7eb2e8f9f7 4943 {
<> 151:5eaa88a5bcc7 4944 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 4945
<> 144:ef7eb2e8f9f7 4946 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4947 assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel));
<> 144:ef7eb2e8f9f7 4948
<> 144:ef7eb2e8f9f7 4949 tmp = TIM_CCER_CC1E << Channel;
<> 144:ef7eb2e8f9f7 4950
<> 144:ef7eb2e8f9f7 4951 /* Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 4952 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 4953
<> 144:ef7eb2e8f9f7 4954 /* Set or reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 4955 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
<> 144:ef7eb2e8f9f7 4956 }
<> 144:ef7eb2e8f9f7 4957 /**
<> 144:ef7eb2e8f9f7 4958 * @brief Set the slave timer configuration.
<> 144:ef7eb2e8f9f7 4959 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4960 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4961 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4962 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4963 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4964 * @retval None
<> 144:ef7eb2e8f9f7 4965 */
<> 144:ef7eb2e8f9f7 4966 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4967 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4968 {
<> 151:5eaa88a5bcc7 4969 uint32_t tmpsmcr = 0U;
<> 151:5eaa88a5bcc7 4970 uint32_t tmpccmr1 = 0U;
<> 151:5eaa88a5bcc7 4971 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4972
<> 144:ef7eb2e8f9f7 4973 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4974 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4975
<> 144:ef7eb2e8f9f7 4976 /* Reset the Trigger Selection Bits */
<> 144:ef7eb2e8f9f7 4977 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 4978 /* Set the Input Trigger source */
<> 144:ef7eb2e8f9f7 4979 tmpsmcr |= sSlaveConfig->InputTrigger;
<> 144:ef7eb2e8f9f7 4980
<> 144:ef7eb2e8f9f7 4981 /* Reset the slave mode Bits */
<> 144:ef7eb2e8f9f7 4982 tmpsmcr &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 4983 /* Set the slave mode */
<> 144:ef7eb2e8f9f7 4984 tmpsmcr |= sSlaveConfig->SlaveMode;
<> 144:ef7eb2e8f9f7 4985
<> 144:ef7eb2e8f9f7 4986 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4987 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4988
<> 144:ef7eb2e8f9f7 4989 /* Configure the trigger prescaler, filter, and polarity */
<> 144:ef7eb2e8f9f7 4990 switch (sSlaveConfig->InputTrigger)
<> 144:ef7eb2e8f9f7 4991 {
<> 144:ef7eb2e8f9f7 4992 case TIM_TS_ETRF:
<> 144:ef7eb2e8f9f7 4993 {
<> 144:ef7eb2e8f9f7 4994 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4995 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4996 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<> 144:ef7eb2e8f9f7 4997 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4998 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4999 /* Configure the ETR Trigger source */
<> 144:ef7eb2e8f9f7 5000 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 5001 sSlaveConfig->TriggerPrescaler,
<> 144:ef7eb2e8f9f7 5002 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5003 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5004 }
<> 144:ef7eb2e8f9f7 5005 break;
<> 144:ef7eb2e8f9f7 5006
<> 144:ef7eb2e8f9f7 5007 case TIM_TS_TI1F_ED:
<> 144:ef7eb2e8f9f7 5008 {
<> 144:ef7eb2e8f9f7 5009 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5010 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5011 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5012
<> 144:ef7eb2e8f9f7 5013 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5014 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 5015 htim->Instance->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5016 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 5017
<> 144:ef7eb2e8f9f7 5018 /* Set the filter */
<> 144:ef7eb2e8f9f7 5019 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 151:5eaa88a5bcc7 5020 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
<> 144:ef7eb2e8f9f7 5021
<> 144:ef7eb2e8f9f7 5022 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5023 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5024 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5025
<> 144:ef7eb2e8f9f7 5026 }
<> 144:ef7eb2e8f9f7 5027 break;
<> 144:ef7eb2e8f9f7 5028
<> 144:ef7eb2e8f9f7 5029 case TIM_TS_TI1FP1:
<> 144:ef7eb2e8f9f7 5030 {
<> 144:ef7eb2e8f9f7 5031 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5032 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5033 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5034 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5035
<> 144:ef7eb2e8f9f7 5036 /* Configure TI1 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5037 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5038 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5039 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5040 }
<> 144:ef7eb2e8f9f7 5041 break;
<> 144:ef7eb2e8f9f7 5042
<> 144:ef7eb2e8f9f7 5043 case TIM_TS_TI2FP2:
<> 144:ef7eb2e8f9f7 5044 {
<> 144:ef7eb2e8f9f7 5045 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5046 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5047 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5048 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5049
<> 144:ef7eb2e8f9f7 5050 /* Configure TI2 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5051 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5052 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5053 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5054 }
<> 144:ef7eb2e8f9f7 5055 break;
<> 144:ef7eb2e8f9f7 5056
<> 144:ef7eb2e8f9f7 5057 case TIM_TS_ITR0:
<> 144:ef7eb2e8f9f7 5058 {
<> 144:ef7eb2e8f9f7 5059 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5060 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5061 }
<> 144:ef7eb2e8f9f7 5062 break;
<> 144:ef7eb2e8f9f7 5063
<> 144:ef7eb2e8f9f7 5064 case TIM_TS_ITR1:
<> 144:ef7eb2e8f9f7 5065 {
<> 144:ef7eb2e8f9f7 5066 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5067 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5068 }
<> 144:ef7eb2e8f9f7 5069 break;
<> 144:ef7eb2e8f9f7 5070
<> 144:ef7eb2e8f9f7 5071 case TIM_TS_ITR2:
<> 144:ef7eb2e8f9f7 5072 {
<> 144:ef7eb2e8f9f7 5073 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5074 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5075 }
<> 144:ef7eb2e8f9f7 5076 break;
<> 144:ef7eb2e8f9f7 5077
<> 144:ef7eb2e8f9f7 5078 case TIM_TS_ITR3:
<> 144:ef7eb2e8f9f7 5079 {
<> 144:ef7eb2e8f9f7 5080 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5081 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5082 }
<> 144:ef7eb2e8f9f7 5083 break;
<> 144:ef7eb2e8f9f7 5084
<> 144:ef7eb2e8f9f7 5085 default:
<> 144:ef7eb2e8f9f7 5086 break;
<> 144:ef7eb2e8f9f7 5087 }
<> 144:ef7eb2e8f9f7 5088 }
<> 144:ef7eb2e8f9f7 5089
<> 144:ef7eb2e8f9f7 5090 /**
<> 144:ef7eb2e8f9f7 5091 * @}
<> 144:ef7eb2e8f9f7 5092 */
<> 144:ef7eb2e8f9f7 5093
<> 144:ef7eb2e8f9f7 5094 /**
<> 144:ef7eb2e8f9f7 5095 * @}
<> 144:ef7eb2e8f9f7 5096 */
<> 144:ef7eb2e8f9f7 5097
<> 144:ef7eb2e8f9f7 5098 /**
<> 144:ef7eb2e8f9f7 5099 * @}
<> 144:ef7eb2e8f9f7 5100 */
<> 144:ef7eb2e8f9f7 5101
<> 144:ef7eb2e8f9f7 5102 /**
<> 144:ef7eb2e8f9f7 5103 * @}
<> 144:ef7eb2e8f9f7 5104 */
<> 144:ef7eb2e8f9f7 5105
<> 144:ef7eb2e8f9f7 5106 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 5107
<> 144:ef7eb2e8f9f7 5108 /**
<> 144:ef7eb2e8f9f7 5109 * @}
<> 144:ef7eb2e8f9f7 5110 */
<> 144:ef7eb2e8f9f7 5111 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 5112