mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief SPI HAL module driver.
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
<> 144:ef7eb2e8f9f7 9 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + IO operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The SPI HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 21 SPI_HandleTypeDef hspi;
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
<> 144:ef7eb2e8f9f7 24 (##) Enable the SPIx interface clock
<> 144:ef7eb2e8f9f7 25 (##) SPI pins configuration
<> 144:ef7eb2e8f9f7 26 (+++) Enable the clock for the SPI GPIOs
<> 144:ef7eb2e8f9f7 27 (+++) Configure these SPI pins as alternate function push-pull
<> 144:ef7eb2e8f9f7 28 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 29 (+++) Configure the SPIx interrupt priority
<> 144:ef7eb2e8f9f7 30 (+++) Enable the NVIC SPI IRQ handle
<> 144:ef7eb2e8f9f7 31 (##) DMA Configuration if you need to use DMA process
<> 144:ef7eb2e8f9f7 32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
<> 144:ef7eb2e8f9f7 33 (+++) Enable the DMAx clock
<> 144:ef7eb2e8f9f7 34 (+++) Configure the DMA handle parameters
<> 144:ef7eb2e8f9f7 35 (+++) Configure the DMA Tx or Rx Channel
<> 144:ef7eb2e8f9f7 36 (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
<> 144:ef7eb2e8f9f7 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
<> 144:ef7eb2e8f9f7 40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<> 144:ef7eb2e8f9f7 43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 44 by calling the customed HAL_SPI_MspInit() API.
<> 144:ef7eb2e8f9f7 45 [..]
<> 144:ef7eb2e8f9f7 46 Circular mode restriction:
<> 144:ef7eb2e8f9f7 47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<> 144:ef7eb2e8f9f7 48 (##) Master 2Lines RxOnly
<> 144:ef7eb2e8f9f7 49 (##) Master 1Line Rx
<> 144:ef7eb2e8f9f7 50 (#) The CRC feature is not managed when the DMA circular mode is enabled
<> 144:ef7eb2e8f9f7 51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<> 144:ef7eb2e8f9f7 52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<> 144:ef7eb2e8f9f7 53
Anna Bridge 186:707f6e361f3e 54 @note
Anna Bridge 186:707f6e361f3e 55 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
Anna Bridge 186:707f6e361f3e 56 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
Anna Bridge 186:707f6e361f3e 57 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
Anna Bridge 186:707f6e361f3e 58
Anna Bridge 186:707f6e361f3e 59 @endverbatim
Anna Bridge 186:707f6e361f3e 60 ******************************************************************************
Anna Bridge 186:707f6e361f3e 61 * @attention
Anna Bridge 186:707f6e361f3e 62 *
Anna Bridge 186:707f6e361f3e 63 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Anna Bridge 186:707f6e361f3e 64 *
Anna Bridge 186:707f6e361f3e 65 * Redistribution and use in source and binary forms, with or without modification,
Anna Bridge 186:707f6e361f3e 66 * are permitted provided that the following conditions are met:
Anna Bridge 186:707f6e361f3e 67 * 1. Redistributions of source code must retain the above copyright notice,
Anna Bridge 186:707f6e361f3e 68 * this list of conditions and the following disclaimer.
Anna Bridge 186:707f6e361f3e 69 * 2. Redistributions in binary form must reproduce the above copyright notice,
Anna Bridge 186:707f6e361f3e 70 * this list of conditions and the following disclaimer in the documentation
Anna Bridge 186:707f6e361f3e 71 * and/or other materials provided with the distribution.
Anna Bridge 186:707f6e361f3e 72 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Anna Bridge 186:707f6e361f3e 73 * may be used to endorse or promote products derived from this software
Anna Bridge 186:707f6e361f3e 74 * without specific prior written permission.
Anna Bridge 186:707f6e361f3e 75 *
Anna Bridge 186:707f6e361f3e 76 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Anna Bridge 186:707f6e361f3e 77 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Anna Bridge 186:707f6e361f3e 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Anna Bridge 186:707f6e361f3e 79 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Anna Bridge 186:707f6e361f3e 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Anna Bridge 186:707f6e361f3e 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Anna Bridge 186:707f6e361f3e 82 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Anna Bridge 186:707f6e361f3e 83 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Anna Bridge 186:707f6e361f3e 84 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Anna Bridge 186:707f6e361f3e 85 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Anna Bridge 186:707f6e361f3e 86 *
Anna Bridge 186:707f6e361f3e 87 ******************************************************************************
Anna Bridge 186:707f6e361f3e 88 */
Anna Bridge 186:707f6e361f3e 89
Anna Bridge 186:707f6e361f3e 90 /*
Anna Bridge 186:707f6e361f3e 91 Additional Table:
Anna Bridge 186:707f6e361f3e 92
<> 144:ef7eb2e8f9f7 93 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
<> 144:ef7eb2e8f9f7 94 the following table resume the max SPI frequency reached with data size 8bits/16bits,
<> 144:ef7eb2e8f9f7 95 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 DataSize = SPI_DATASIZE_8BIT:
<> 144:ef7eb2e8f9f7 98 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 99 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 144:ef7eb2e8f9f7 100 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 144:ef7eb2e8f9f7 101 | | | Master | Slave | Master | Slave | Master | Slave |
<> 144:ef7eb2e8f9f7 102 |==============================================================================================|
<> 144:ef7eb2e8f9f7 103 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 104 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 105 | / | Interrupt | Fpclk/64 | Fpclk/64 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 106 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 107 | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 108 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 109 | | Polling | Fpclk/2 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 110 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 111 | R | Interrupt | Fpclk/64 | Fpclk/32 | Fpclk/32 | Fpclk/16 | Fpclk/32 | Fpclk/32 |
<> 144:ef7eb2e8f9f7 112 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 113 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 114 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 115 | | Polling | Fpclk/8 | Fpclk/8 | NA | NA | Fpclk/4 | Fpclk/16 |
<> 144:ef7eb2e8f9f7 116 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 117 | T | Interrupt | Fpclk/8 | Fpclk/32 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 144:ef7eb2e8f9f7 118 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 119 | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 120 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 DataSize = SPI_DATASIZE_16BIT:
<> 144:ef7eb2e8f9f7 123 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 124 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 144:ef7eb2e8f9f7 125 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 144:ef7eb2e8f9f7 126 | | | Master | Slave | Master | Slave | Master | Slave |
<> 144:ef7eb2e8f9f7 127 |==============================================================================================|
<> 144:ef7eb2e8f9f7 128 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 129 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 130 | / | Interrupt | Fpclk/32 | Fpclk/16 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 131 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 132 | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 133 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 134 | | Polling | Fpclk/2 | Fpclk/4 | Fpclk/8 | Fpclk/4 | Fpclk/2 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 135 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 136 | R | Interrupt | Fpclk/32 | Fpclk/8 | Fpclk/16 | Fpclk/16 | Fpclk/16 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 137 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 138 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/8 | Fpclk/2 | Fpclk/8 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 139 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 140 | | Polling | Fpclk/4 | Fpclk/4 | NA | NA | Fpclk/4 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 141 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 142 | T | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 143 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 144 | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 145 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 146 @note The max SPI frequency depend on SPI data size (8bits, 16bits),
<> 144:ef7eb2e8f9f7 147 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
Anna Bridge 186:707f6e361f3e 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 151 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 160 * @brief SPI HAL module driver
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 166 /** @addtogroup SPI_Private
<> 144:ef7eb2e8f9f7 167 * @{
<> 144:ef7eb2e8f9f7 168 */
<> 151:5eaa88a5bcc7 169 #define SPI_TIMEOUT_VALUE 10U
Anna Bridge 186:707f6e361f3e 170 #define SPI_DEFAULT_TIMEOUT 100U // MBED commit 64a037cc
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 174 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 175
Anna Bridge 186:707f6e361f3e 176 // MBED commit 64a037cc
<> 153:fa9ff456f731 177 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
<> 153:fa9ff456f731 178 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 179 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 180 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 181 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 182 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 183 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 184 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 185 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 186 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 187 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 188 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 189 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 190 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 191 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 192 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 193 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 194 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
<> 153:fa9ff456f731 195 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 196 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 197 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 198 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 199 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 200 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 201 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 202 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 203 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /** @addtogroup SPI_Exported_Functions SPI Exported Functions
<> 144:ef7eb2e8f9f7 211 * @{
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 215 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 216 *
<> 144:ef7eb2e8f9f7 217 @verbatim
<> 144:ef7eb2e8f9f7 218 ===============================================================================
<> 144:ef7eb2e8f9f7 219 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 220 ===============================================================================
<> 144:ef7eb2e8f9f7 221 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 222 de-initialiaze the SPIx peripheral:
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 (+) User must implement HAL_SPI_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 225 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 (+) Call the function HAL_SPI_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 228 the selected configuration:
<> 144:ef7eb2e8f9f7 229 (++) Mode
<> 144:ef7eb2e8f9f7 230 (++) Direction
<> 144:ef7eb2e8f9f7 231 (++) Data Size
<> 144:ef7eb2e8f9f7 232 (++) Clock Polarity and Phase
<> 144:ef7eb2e8f9f7 233 (++) NSS Management
<> 144:ef7eb2e8f9f7 234 (++) BaudRate Prescaler
<> 144:ef7eb2e8f9f7 235 (++) FirstBit
<> 144:ef7eb2e8f9f7 236 (++) TIMode
<> 144:ef7eb2e8f9f7 237 (++) CRC Calculation
<> 144:ef7eb2e8f9f7 238 (++) CRC Polynomial if CRC enabled
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 241 of the selected SPIx periperal.
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 @endverbatim
<> 144:ef7eb2e8f9f7 244 * @{
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @brief Initializes the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 249 * in the SPI_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 250 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 251 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 252 * @retval HAL status
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 257 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Check the parameters */
<> 144:ef7eb2e8f9f7 263 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 264 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 265 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 266 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 267 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 144:ef7eb2e8f9f7 268 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 144:ef7eb2e8f9f7 269 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 270 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 271 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 272 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 273 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 144:ef7eb2e8f9f7 274 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 if(hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 279 hspi->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 282 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Disble the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 288 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 291 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
<> 144:ef7eb2e8f9f7 292 Communication speed, First bit and CRC calculation state */
<> 144:ef7eb2e8f9f7 293 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
<> 144:ef7eb2e8f9f7 294 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 144:ef7eb2e8f9f7 295 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Configure : NSS management */
<> 151:5eaa88a5bcc7 298 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 301 /* Configure : CRC Polynomial */
<> 144:ef7eb2e8f9f7 302 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
<> 144:ef7eb2e8f9f7 305 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 144:ef7eb2e8f9f7 306 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 144:ef7eb2e8f9f7 307 #endif
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 310 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 return HAL_OK;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @brief DeInitializes the SPI peripheral
<> 144:ef7eb2e8f9f7 317 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 318 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 319 * @retval HAL status
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 324 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Disable the SPI Peripheral Clock */
<> 144:ef7eb2e8f9f7 332 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 335 HAL_SPI_MspDeInit(hspi);
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 338 hspi->State = HAL_SPI_STATE_RESET;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Release Lock */
<> 144:ef7eb2e8f9f7 341 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 return HAL_OK;
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @brief SPI MSP Init
<> 144:ef7eb2e8f9f7 348 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 349 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 350 * @retval None
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 355 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 358 the HAL_SPI_MspInit could be implenetd in the user file
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @brief SPI MSP DeInit
<> 144:ef7eb2e8f9f7 364 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 365 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 366 * @retval None
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 371 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 374 the HAL_SPI_MspDeInit could be implenetd in the user file
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @}
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @addtogroup SPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 383 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 384 *
<> 144:ef7eb2e8f9f7 385 @verbatim
<> 144:ef7eb2e8f9f7 386 ==============================================================================
<> 144:ef7eb2e8f9f7 387 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 388 ===============================================================================
<> 144:ef7eb2e8f9f7 389 This subsection provides a set of functions allowing to manage the SPI
<> 144:ef7eb2e8f9f7 390 data transfers.
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 [..] The SPI supports master and slave mode :
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 395 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 396 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 397 after finishing transfer.
<> 144:ef7eb2e8f9f7 398 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 399 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 400 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 401 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 402 using DMA mode.
<> 144:ef7eb2e8f9f7 403 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 404 will be executed respectivelly at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 405 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 (#) Blocking mode APIs are :
<> 144:ef7eb2e8f9f7 408 (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 409 (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 410 (++) HAL_SPI_TransmitReceive() in full duplex mode
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 (#) Non Blocking mode API's with Interrupt are :
<> 144:ef7eb2e8f9f7 413 (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 414 (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 415 (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
<> 144:ef7eb2e8f9f7 416 (++) HAL_SPI_IRQHandler()
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 (#) Non Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 419 (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 420 (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 421 (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 424 (++) HAL_SPI_TxCpltCallback()
<> 144:ef7eb2e8f9f7 425 (++) HAL_SPI_RxCpltCallback()
<> 144:ef7eb2e8f9f7 426 (++) HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 427 (++) HAL_SPI_TxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 428 (++) HAL_SPI_RxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 429 (++) HAL_SPI_TxRxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 430 (++) HAL_SPI_ErrorCallback()
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 @endverbatim
<> 144:ef7eb2e8f9f7 433 * @{
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /**
<> 144:ef7eb2e8f9f7 437 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 438 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 439 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 440 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 441 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 442 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 443 * @retval HAL status
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 449 {
<> 151:5eaa88a5bcc7 450 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Check the parameters */
<> 144:ef7eb2e8f9f7 456 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Process Locked */
<> 144:ef7eb2e8f9f7 459 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Configure communication */
<> 144:ef7eb2e8f9f7 462 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 463 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 hspi->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 466 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 467 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 470 hspi->TxISR = 0U;
<> 151:5eaa88a5bcc7 471 hspi->RxISR = 0U;
<> 144:ef7eb2e8f9f7 472 hspi->pRxBuffPtr = NULL;
<> 151:5eaa88a5bcc7 473 hspi->RxXferSize = 0U;
<> 151:5eaa88a5bcc7 474 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 477 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 485 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 489 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 492 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 496 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 497 {
<> 151:5eaa88a5bcc7 498 if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01U))
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 501 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
<> 151:5eaa88a5bcc7 504 while(hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 507 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 512 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 515 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 521 else
<> 144:ef7eb2e8f9f7 522 {
<> 151:5eaa88a5bcc7 523 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 151:5eaa88a5bcc7 526 hspi->pTxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 527 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529
<> 151:5eaa88a5bcc7 530 while(hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 533 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 151:5eaa88a5bcc7 538 hspi->pTxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 539 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 542 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 549 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 552 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 556 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 559 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<> 144:ef7eb2e8f9f7 563 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 571 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 return HAL_OK;
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 else
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 583 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 584 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 585 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 586 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 587 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 588 * @retval HAL status
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 591 {
<> 151:5eaa88a5bcc7 592 __IO uint16_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 595 {
<> 151:5eaa88a5bcc7 596 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Process Locked */
<> 144:ef7eb2e8f9f7 602 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Configure communication */
<> 144:ef7eb2e8f9f7 605 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 606 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 hspi->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 609 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 610 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 613 hspi->RxISR = 0U;
<> 151:5eaa88a5bcc7 614 hspi->TxISR = 0U;
<> 144:ef7eb2e8f9f7 615 hspi->pTxBuffPtr = NULL;
<> 151:5eaa88a5bcc7 616 hspi->TxXferSize = 0U;
<> 151:5eaa88a5bcc7 617 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 620 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 623 }
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 626 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 629 }
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 634 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 144:ef7eb2e8f9f7 637 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 641 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 642 {
<> 144:ef7eb2e8f9f7 643 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 644 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 648 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 649 {
<> 151:5eaa88a5bcc7 650 while(hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 653 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 659 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 /* Enable CRC Reception */
<> 144:ef7eb2e8f9f7 662 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 /* Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 668 else
<> 144:ef7eb2e8f9f7 669 {
<> 151:5eaa88a5bcc7 670 while(hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 /* Wait until RXNE flag is set to read data */
<> 144:ef7eb2e8f9f7 673 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 151:5eaa88a5bcc7 679 hspi->pRxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 680 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682 /* Enable CRC Reception */
<> 144:ef7eb2e8f9f7 683 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 690 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Receive last data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 696 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700 /* Receive last data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 701 else
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 151:5eaa88a5bcc7 704 hspi->pRxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* If CRC computation is enabled */
<> 144:ef7eb2e8f9f7 709 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 /* Wait until RXNE flag is set: CRC Received */
<> 144:ef7eb2e8f9f7 712 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 715 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Read CRC to clear RXNE flag */
<> 144:ef7eb2e8f9f7 719 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 720 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 726 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 732 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 737 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 740 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 746 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 return HAL_OK;
<> 144:ef7eb2e8f9f7 749 }
<> 144:ef7eb2e8f9f7 750 else
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /**
<> 144:ef7eb2e8f9f7 757 * @brief Transmit and Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 758 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 759 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 760 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 761 * @param pRxData: pointer to reception data buffer to be
<> 144:ef7eb2e8f9f7 762 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 763 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 764 * @retval HAL status
<> 144:ef7eb2e8f9f7 765 */
<> 144:ef7eb2e8f9f7 766 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 767 {
<> 151:5eaa88a5bcc7 768 __IO uint16_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX))
<> 144:ef7eb2e8f9f7 771 {
<> 151:5eaa88a5bcc7 772 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 775 }
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /* Check the parameters */
<> 144:ef7eb2e8f9f7 778 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /* Process Locked */
<> 144:ef7eb2e8f9f7 781 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 784 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Configure communication */
<> 144:ef7eb2e8f9f7 790 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 hspi->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 793 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 794 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 hspi->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 797 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 798 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 801 hspi->RxISR = 0U;
<> 151:5eaa88a5bcc7 802 hspi->TxISR = 0U;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 805 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 811 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 814 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Transmit and Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 818 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 819 {
<> 151:5eaa88a5bcc7 820 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01U)))
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 151:5eaa88a5bcc7 823 hspi->pTxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 824 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 825 }
<> 151:5eaa88a5bcc7 826 if(hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 827 {
<> 144:ef7eb2e8f9f7 828 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 829 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 835 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 151:5eaa88a5bcc7 841 hspi->pRxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 842 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844 else
<> 144:ef7eb2e8f9f7 845 {
<> 151:5eaa88a5bcc7 846 while(hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 849 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 151:5eaa88a5bcc7 855 hspi->pTxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 856 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Enable CRC Transmission */
<> 151:5eaa88a5bcc7 859 if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 865 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 151:5eaa88a5bcc7 871 hspi->pRxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 872 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 873 }
<> 144:ef7eb2e8f9f7 874 /* Receive the last byte */
<> 144:ef7eb2e8f9f7 875 if(hspi->Init.Mode == SPI_MODE_SLAVE)
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 878 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 151:5eaa88a5bcc7 884 hspi->pRxBuffPtr+=2U;
<> 144:ef7eb2e8f9f7 885 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889 /* Transmit and Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 890 else
<> 144:ef7eb2e8f9f7 891 {
<> 151:5eaa88a5bcc7 892 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01U)))
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 895 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 896 }
<> 151:5eaa88a5bcc7 897 if(hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 900 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 903 }
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 906 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 907 {
<> 144:ef7eb2e8f9f7 908 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 (*hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 912 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914 else
<> 144:ef7eb2e8f9f7 915 {
<> 151:5eaa88a5bcc7 916 while(hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 919 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 920 {
<> 144:ef7eb2e8f9f7 921 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 925 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* Enable CRC Transmission */
<> 151:5eaa88a5bcc7 928 if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 934 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 935 {
<> 144:ef7eb2e8f9f7 936 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 940 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942 if(hspi->Init.Mode == SPI_MODE_SLAVE)
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 945 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 951 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953 }
<> 144:ef7eb2e8f9f7 954 }
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /* Read CRC from DR to close CRC calculation process */
<> 144:ef7eb2e8f9f7 957 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 958 {
<> 144:ef7eb2e8f9f7 959 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 960 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 963 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 964 }
<> 144:ef7eb2e8f9f7 965 /* Read CRC */
<> 144:ef7eb2e8f9f7 966 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 967 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 971 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 974 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 980 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<> 144:ef7eb2e8f9f7 981 {
<> 144:ef7eb2e8f9f7 982 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 987 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 993 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 return HAL_OK;
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 else
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /**
<> 144:ef7eb2e8f9f7 1004 * @brief Transmit an amount of data in no-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1005 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1006 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1007 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1008 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1009 * @retval HAL status
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1012 {
<> 144:ef7eb2e8f9f7 1013 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1014 {
<> 151:5eaa88a5bcc7 1015 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1016 {
<> 144:ef7eb2e8f9f7 1017 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1021 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Process Locked */
<> 144:ef7eb2e8f9f7 1024 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Configure communication */
<> 144:ef7eb2e8f9f7 1027 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1028 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1029
Anna Bridge 186:707f6e361f3e 1030 // MBED commit 64a037cc
<> 153:fa9ff456f731 1031 /* Set the function for IT treatment */
<> 153:fa9ff456f731 1032 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<> 153:fa9ff456f731 1033 {
<> 153:fa9ff456f731 1034 hspi->TxISR = SPI_TxISR_16BIT;
<> 153:fa9ff456f731 1035 }
<> 153:fa9ff456f731 1036 else
<> 153:fa9ff456f731 1037 {
<> 153:fa9ff456f731 1038 hspi->TxISR = SPI_TxISR_8BIT;
<> 153:fa9ff456f731 1039 }
<> 153:fa9ff456f731 1040
<> 144:ef7eb2e8f9f7 1041 hspi->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1042 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1043 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 1046 hspi->RxISR = 0U;
<> 144:ef7eb2e8f9f7 1047 hspi->pRxBuffPtr = NULL;
<> 151:5eaa88a5bcc7 1048 hspi->RxXferSize = 0U;
<> 151:5eaa88a5bcc7 1049 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1052 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1053 {
<> 144:ef7eb2e8f9f7 1054 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1055 }
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1058 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 1064 {
<> 144:ef7eb2e8f9f7 1065 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
<> 144:ef7eb2e8f9f7 1066 }
<> 144:ef7eb2e8f9f7 1067 else
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1070 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1073 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1076 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1079 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 return HAL_OK;
<> 144:ef7eb2e8f9f7 1083 }
<> 144:ef7eb2e8f9f7 1084 else
<> 144:ef7eb2e8f9f7 1085 {
<> 144:ef7eb2e8f9f7 1086 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1087 }
<> 144:ef7eb2e8f9f7 1088 }
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /**
<> 144:ef7eb2e8f9f7 1091 * @brief Receive an amount of data in no-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1092 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1093 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1094 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1095 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1096 * @retval HAL status
<> 144:ef7eb2e8f9f7 1097 */
<> 144:ef7eb2e8f9f7 1098 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1099 {
<> 144:ef7eb2e8f9f7 1100 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1101 {
<> 151:5eaa88a5bcc7 1102 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Process Locked */
<> 144:ef7eb2e8f9f7 1108 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Configure communication */
<> 144:ef7eb2e8f9f7 1111 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1112 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1113
Anna Bridge 186:707f6e361f3e 1114 // MBED commit 64a037cc
<> 153:fa9ff456f731 1115 /* Set the function for IT treatment */
<> 153:fa9ff456f731 1116 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<> 153:fa9ff456f731 1117 {
<> 153:fa9ff456f731 1118 hspi->RxISR = SPI_RxISR_16BIT;
<> 153:fa9ff456f731 1119 }
<> 153:fa9ff456f731 1120 else
<> 153:fa9ff456f731 1121 {
<> 153:fa9ff456f731 1122 hspi->RxISR = SPI_RxISR_8BIT;
<> 153:fa9ff456f731 1123 }
<> 144:ef7eb2e8f9f7 1124 hspi->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1125 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1126 hspi->RxXferCount = Size ;
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 1129 hspi->TxISR = 0U;
<> 144:ef7eb2e8f9f7 1130 hspi->pTxBuffPtr = NULL;
<> 151:5eaa88a5bcc7 1131 hspi->TxXferSize = 0U;
<> 151:5eaa88a5bcc7 1132 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1135 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1136 {
<> 144:ef7eb2e8f9f7 1137 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1138 }
<> 144:ef7eb2e8f9f7 1139 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1142 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 144:ef7eb2e8f9f7 1145 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1149 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1152 }
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1155 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1158 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 /* Note : The SPI must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1161 to avoid the risk of SPI interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1162 process unlock */
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1165 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1166 {
<> 144:ef7eb2e8f9f7 1167 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1168 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 return HAL_OK;
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173 else
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177 }
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /**
<> 144:ef7eb2e8f9f7 1180 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1181 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1182 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1183 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1184 * @param pRxData: pointer to reception data buffer to be
<> 144:ef7eb2e8f9f7 1185 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1186 * @retval HAL status
<> 144:ef7eb2e8f9f7 1187 */
<> 144:ef7eb2e8f9f7 1188 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 if((hspi->State == HAL_SPI_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1192 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<> 144:ef7eb2e8f9f7 1193 {
<> 151:5eaa88a5bcc7 1194 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1200 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /* Process locked */
<> 144:ef7eb2e8f9f7 1203 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 1206 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1207 {
<> 144:ef7eb2e8f9f7 1208 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1209 }
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Configure communication */
<> 144:ef7eb2e8f9f7 1212 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 hspi->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 1215 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1216 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 hspi->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 1219 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1220 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1221
Anna Bridge 186:707f6e361f3e 1222 // MBED commit 64a037cc
<> 153:fa9ff456f731 1223 /* Set the function for IT treatment */
<> 153:fa9ff456f731 1224 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<> 153:fa9ff456f731 1225 {
<> 153:fa9ff456f731 1226 hspi->RxISR = SPI_2linesRxISR_16BIT;
<> 153:fa9ff456f731 1227 hspi->TxISR = SPI_2linesTxISR_16BIT;
<> 153:fa9ff456f731 1228 }
<> 153:fa9ff456f731 1229 else
<> 153:fa9ff456f731 1230 {
<> 153:fa9ff456f731 1231 hspi->RxISR = SPI_2linesRxISR_8BIT;
<> 153:fa9ff456f731 1232 hspi->TxISR = SPI_2linesTxISR_8BIT;
<> 153:fa9ff456f731 1233 }
<> 153:fa9ff456f731 1234
<> 144:ef7eb2e8f9f7 1235 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1236 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /* Enable TXE, RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1242 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1245 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1246
<> 144:ef7eb2e8f9f7 1247 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1248 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1249 {
<> 144:ef7eb2e8f9f7 1250 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1251 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 return HAL_OK;
<> 144:ef7eb2e8f9f7 1255 }
<> 144:ef7eb2e8f9f7 1256 else
<> 144:ef7eb2e8f9f7 1257 {
<> 144:ef7eb2e8f9f7 1258 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 /**
<> 144:ef7eb2e8f9f7 1263 * @brief Transmit an amount of data in no-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1264 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1265 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1266 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1267 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1268 * @retval HAL status
<> 144:ef7eb2e8f9f7 1269 */
<> 144:ef7eb2e8f9f7 1270 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1271 {
<> 144:ef7eb2e8f9f7 1272 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1273 {
<> 151:5eaa88a5bcc7 1274 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1277 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1278 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1279 }
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1282 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Process Locked */
<> 144:ef7eb2e8f9f7 1285 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Configure communication */
<> 144:ef7eb2e8f9f7 1288 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1289 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 hspi->pTxBuffPtr = (uint8_t*)pData;
<> 144:ef7eb2e8f9f7 1292 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1293 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 1296 hspi->TxISR = 0U;
<> 151:5eaa88a5bcc7 1297 hspi->RxISR = 0U;
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 hspi->pRxBuffPtr = NULL;
<> 151:5eaa88a5bcc7 1300 hspi->RxXferSize = 0U;
<> 151:5eaa88a5bcc7 1301 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1304 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1307 }
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1310 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1311 {
<> 144:ef7eb2e8f9f7 1312 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /* Set the SPI TxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1316 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /* Set the SPI TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1319 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1322 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Reset content of SPI RxDMA descriptor */
<> 144:ef7eb2e8f9f7 1325 hspi->hdmarx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1326 hspi->hdmarx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1327 hspi->hdmarx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 1330 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1333 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1334
<> 144:ef7eb2e8f9f7 1335 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1336 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1337
<> 144:ef7eb2e8f9f7 1338 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1339 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1340 {
<> 144:ef7eb2e8f9f7 1341 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1342 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1343 }
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 return HAL_OK;
<> 144:ef7eb2e8f9f7 1346 }
<> 144:ef7eb2e8f9f7 1347 else
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1350 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1351 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353 }
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /**
<> 144:ef7eb2e8f9f7 1356 * @brief Receive an amount of data in no-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1357 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1358 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1359 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1360 * @note When the CRC feature is enabled the pData Length must be Size + 1.
<> 144:ef7eb2e8f9f7 1361 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1362 * @retval HAL status
<> 144:ef7eb2e8f9f7 1363 */
<> 144:ef7eb2e8f9f7 1364 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1365 {
<> 144:ef7eb2e8f9f7 1366 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1367 {
<> 151:5eaa88a5bcc7 1368 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1369 {
<> 144:ef7eb2e8f9f7 1370 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1371 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1372 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /* Process Locked */
<> 144:ef7eb2e8f9f7 1376 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /* Configure communication */
<> 144:ef7eb2e8f9f7 1379 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1380 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 hspi->pRxBuffPtr = (uint8_t*)pData;
<> 144:ef7eb2e8f9f7 1383 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1384 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 1387 hspi->RxISR = 0U;
<> 151:5eaa88a5bcc7 1388 hspi->TxISR = 0U;
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 hspi->pTxBuffPtr = NULL;
<> 151:5eaa88a5bcc7 1391 hspi->TxXferSize = 0U;
<> 151:5eaa88a5bcc7 1392 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1395 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1396 {
<> 144:ef7eb2e8f9f7 1397 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 1400 {
<> 144:ef7eb2e8f9f7 1401 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1402 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1403
<> 144:ef7eb2e8f9f7 1404 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 144:ef7eb2e8f9f7 1405 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1409 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1412 }
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 /* Set the SPI RxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1415 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /* Set the SPI Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1418 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1421 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 /* Reset content of SPI TxDMA descriptor */
<> 144:ef7eb2e8f9f7 1424 hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1425 hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1426 hspi->hdmatx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 1429 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1432 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1435 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1438 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1439 {
<> 144:ef7eb2e8f9f7 1440 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1441 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1442 }
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 return HAL_OK;
<> 144:ef7eb2e8f9f7 1445 }
<> 144:ef7eb2e8f9f7 1446 else
<> 144:ef7eb2e8f9f7 1447 {
<> 144:ef7eb2e8f9f7 1448 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1449 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1450 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1451 }
<> 144:ef7eb2e8f9f7 1452 }
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 /**
<> 144:ef7eb2e8f9f7 1455 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1456 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1457 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1458 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1459 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1460 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
<> 144:ef7eb2e8f9f7 1461 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1462 * @retval HAL status
<> 144:ef7eb2e8f9f7 1463 */
<> 144:ef7eb2e8f9f7 1464 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1465 {
<> 144:ef7eb2e8f9f7 1466 if((hspi->State == HAL_SPI_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1467 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<> 144:ef7eb2e8f9f7 1468 {
<> 151:5eaa88a5bcc7 1469 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1470 {
<> 144:ef7eb2e8f9f7 1471 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1472 }
<> 144:ef7eb2e8f9f7 1473
<> 144:ef7eb2e8f9f7 1474 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1475 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1476
<> 144:ef7eb2e8f9f7 1477 /* Process locked */
<> 144:ef7eb2e8f9f7 1478 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 1481 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1482 {
<> 144:ef7eb2e8f9f7 1483 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1484 }
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 /* Configure communication */
<> 144:ef7eb2e8f9f7 1487 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 hspi->pTxBuffPtr = (uint8_t*)pTxData;
<> 144:ef7eb2e8f9f7 1490 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1491 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 hspi->pRxBuffPtr = (uint8_t*)pRxData;
<> 144:ef7eb2e8f9f7 1494 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1495 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /*Init field not used in handle to zero */
<> 151:5eaa88a5bcc7 1498 hspi->RxISR = 0U;
<> 151:5eaa88a5bcc7 1499 hspi->TxISR = 0U;
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1502 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1503 {
<> 144:ef7eb2e8f9f7 1504 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1505 }
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1508 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1509 {
<> 144:ef7eb2e8f9f7 1510 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1511 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1514 }
<> 144:ef7eb2e8f9f7 1515 else
<> 144:ef7eb2e8f9f7 1516 {
<> 144:ef7eb2e8f9f7 1517 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1518 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1521 }
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1524 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1525
<> 144:ef7eb2e8f9f7 1526 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 1527 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1530 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<> 144:ef7eb2e8f9f7 1533 is performed in DMA reception complete callback */
<> 144:ef7eb2e8f9f7 1534 hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1535 hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1538 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 1541 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1544 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1547 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1548 }
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1551 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1554 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 return HAL_OK;
<> 144:ef7eb2e8f9f7 1557 }
<> 144:ef7eb2e8f9f7 1558 else
<> 144:ef7eb2e8f9f7 1559 {
<> 144:ef7eb2e8f9f7 1560 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1561 }
<> 144:ef7eb2e8f9f7 1562 }
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 /**
<> 144:ef7eb2e8f9f7 1566 * @brief Pauses the DMA Transfer.
<> 144:ef7eb2e8f9f7 1567 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1568 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1569 * @retval HAL status
<> 144:ef7eb2e8f9f7 1570 */
<> 144:ef7eb2e8f9f7 1571 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1572 {
<> 144:ef7eb2e8f9f7 1573 /* Process Locked */
<> 144:ef7eb2e8f9f7 1574 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1577 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1578 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1581 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1582
<> 144:ef7eb2e8f9f7 1583 return HAL_OK;
<> 144:ef7eb2e8f9f7 1584 }
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 /**
<> 144:ef7eb2e8f9f7 1587 * @brief Resumes the DMA Transfer.
<> 144:ef7eb2e8f9f7 1588 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1589 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1590 * @retval HAL status
<> 144:ef7eb2e8f9f7 1591 */
<> 144:ef7eb2e8f9f7 1592 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1593 {
<> 144:ef7eb2e8f9f7 1594 /* Process Locked */
<> 144:ef7eb2e8f9f7 1595 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 /* Enable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1598 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1599 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1602 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 return HAL_OK;
<> 144:ef7eb2e8f9f7 1605 }
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /**
<> 144:ef7eb2e8f9f7 1608 * @brief Stops the DMA Transfer.
<> 144:ef7eb2e8f9f7 1609 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1610 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1611 * @retval HAL status
<> 144:ef7eb2e8f9f7 1612 */
<> 144:ef7eb2e8f9f7 1613 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1614 {
<> 144:ef7eb2e8f9f7 1615 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 1616 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<> 144:ef7eb2e8f9f7 1617 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 1618 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 1619 */
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /* Abort the SPI DMA tx Channel */
<> 144:ef7eb2e8f9f7 1622 if(hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1623 {
<> 144:ef7eb2e8f9f7 1624 HAL_DMA_Abort(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 1625 }
<> 144:ef7eb2e8f9f7 1626 /* Abort the SPI DMA rx Channel */
<> 144:ef7eb2e8f9f7 1627 if(hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1628 {
<> 144:ef7eb2e8f9f7 1629 HAL_DMA_Abort(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 1630 }
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1633 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1634 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 return HAL_OK;
<> 144:ef7eb2e8f9f7 1639 }
<> 144:ef7eb2e8f9f7 1640
<> 144:ef7eb2e8f9f7 1641 /**
<> 144:ef7eb2e8f9f7 1642 * @brief This function handles SPI interrupt request.
<> 144:ef7eb2e8f9f7 1643 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1644 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1645 * @retval HAL status
<> 144:ef7eb2e8f9f7 1646 */
<> 144:ef7eb2e8f9f7 1647 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1648 {
<> 144:ef7eb2e8f9f7 1649 /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
<> 144:ef7eb2e8f9f7 1650 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
<> 144:ef7eb2e8f9f7 1651 {
<> 144:ef7eb2e8f9f7 1652 hspi->RxISR(hspi);
<> 144:ef7eb2e8f9f7 1653 return;
<> 144:ef7eb2e8f9f7 1654 }
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656 /* SPI in mode Tramitter ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1657 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1658 {
<> 144:ef7eb2e8f9f7 1659 hspi->TxISR(hspi);
<> 144:ef7eb2e8f9f7 1660 return;
<> 144:ef7eb2e8f9f7 1661 }
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
<> 144:ef7eb2e8f9f7 1664 {
<> 144:ef7eb2e8f9f7 1665 /* SPI CRC error interrupt occurred ---------------------------------------*/
<> 144:ef7eb2e8f9f7 1666 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 1667 {
<> 144:ef7eb2e8f9f7 1668 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1669 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1670 }
<> 144:ef7eb2e8f9f7 1671 /* SPI Mode Fault error interrupt occurred --------------------------------*/
<> 144:ef7eb2e8f9f7 1672 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
<> 144:ef7eb2e8f9f7 1673 {
<> 144:ef7eb2e8f9f7 1674 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<> 144:ef7eb2e8f9f7 1675 __HAL_SPI_CLEAR_MODFFLAG(hspi);
<> 144:ef7eb2e8f9f7 1676 }
<> 144:ef7eb2e8f9f7 1677
<> 144:ef7eb2e8f9f7 1678 /* SPI Overrun error interrupt occurred -----------------------------------*/
<> 144:ef7eb2e8f9f7 1679 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1682 {
<> 144:ef7eb2e8f9f7 1683 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1684 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1685 }
<> 144:ef7eb2e8f9f7 1686 }
<> 144:ef7eb2e8f9f7 1687
<> 144:ef7eb2e8f9f7 1688 /* SPI Frame error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 1689 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
<> 144:ef7eb2e8f9f7 1690 {
<> 144:ef7eb2e8f9f7 1691 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<> 144:ef7eb2e8f9f7 1692 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 144:ef7eb2e8f9f7 1693 }
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1696 if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1697 {
<> 144:ef7eb2e8f9f7 1698 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 1699 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1700 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1701 }
<> 144:ef7eb2e8f9f7 1702 }
<> 144:ef7eb2e8f9f7 1703 }
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 /**
<> 144:ef7eb2e8f9f7 1706 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1707 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1708 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1709 * @retval None
<> 144:ef7eb2e8f9f7 1710 */
<> 144:ef7eb2e8f9f7 1711 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1712 {
<> 144:ef7eb2e8f9f7 1713 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1714 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1717 the HAL_SPI_TxCpltCallback could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1718 */
<> 144:ef7eb2e8f9f7 1719 }
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /**
<> 144:ef7eb2e8f9f7 1722 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1723 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1724 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1725 * @retval None
<> 144:ef7eb2e8f9f7 1726 */
<> 144:ef7eb2e8f9f7 1727 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1728 {
<> 144:ef7eb2e8f9f7 1729 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1730 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1733 the HAL_SPI_RxCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1734 */
<> 144:ef7eb2e8f9f7 1735 }
<> 144:ef7eb2e8f9f7 1736
<> 144:ef7eb2e8f9f7 1737 /**
<> 144:ef7eb2e8f9f7 1738 * @brief Tx and Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1739 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1740 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1741 * @retval None
<> 144:ef7eb2e8f9f7 1742 */
<> 144:ef7eb2e8f9f7 1743 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1744 {
<> 144:ef7eb2e8f9f7 1745 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1746 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1749 the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1750 */
<> 144:ef7eb2e8f9f7 1751 }
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 /**
<> 144:ef7eb2e8f9f7 1754 * @brief Tx Half Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1755 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1756 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1757 * @retval None
<> 144:ef7eb2e8f9f7 1758 */
<> 144:ef7eb2e8f9f7 1759 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1760 {
<> 144:ef7eb2e8f9f7 1761 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1762 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1765 the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1766 */
<> 144:ef7eb2e8f9f7 1767 }
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 /**
<> 144:ef7eb2e8f9f7 1770 * @brief Rx Half Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1771 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1772 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1773 * @retval None
<> 144:ef7eb2e8f9f7 1774 */
<> 144:ef7eb2e8f9f7 1775 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1776 {
<> 144:ef7eb2e8f9f7 1777 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1778 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1779
<> 144:ef7eb2e8f9f7 1780 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1781 the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1782 */
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 /**
<> 144:ef7eb2e8f9f7 1786 * @brief Tx and Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1787 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1788 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1789 * @retval None
<> 144:ef7eb2e8f9f7 1790 */
<> 144:ef7eb2e8f9f7 1791 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1792 {
<> 144:ef7eb2e8f9f7 1793 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1794 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1797 the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1798 */
<> 144:ef7eb2e8f9f7 1799 }
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 /**
<> 144:ef7eb2e8f9f7 1802 * @brief SPI error callbacks
<> 144:ef7eb2e8f9f7 1803 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1804 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1805 * @retval None
<> 144:ef7eb2e8f9f7 1806 */
<> 144:ef7eb2e8f9f7 1807 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1808 {
<> 144:ef7eb2e8f9f7 1809 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1810 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 /* NOTE : - This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1813 the HAL_SPI_ErrorCallback() could be implenetd in the user file.
<> 144:ef7eb2e8f9f7 1814 - The ErrorCode parameter in the hspi handle is updated by the SPI processes
<> 144:ef7eb2e8f9f7 1815 and user can use HAL_SPI_GetError() API to check the latest error occurred.
<> 144:ef7eb2e8f9f7 1816 */
<> 144:ef7eb2e8f9f7 1817 }
<> 144:ef7eb2e8f9f7 1818
<> 144:ef7eb2e8f9f7 1819 /**
<> 144:ef7eb2e8f9f7 1820 * @}
<> 144:ef7eb2e8f9f7 1821 */
<> 144:ef7eb2e8f9f7 1822
<> 144:ef7eb2e8f9f7 1823 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1824 * @brief SPI control functions
<> 144:ef7eb2e8f9f7 1825 *
<> 144:ef7eb2e8f9f7 1826 @verbatim
<> 144:ef7eb2e8f9f7 1827 ===============================================================================
<> 144:ef7eb2e8f9f7 1828 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1829 ===============================================================================
<> 144:ef7eb2e8f9f7 1830 [..]
<> 144:ef7eb2e8f9f7 1831 This subsection provides a set of functions allowing to control the SPI.
<> 144:ef7eb2e8f9f7 1832 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<> 144:ef7eb2e8f9f7 1833 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<> 144:ef7eb2e8f9f7 1834 @endverbatim
<> 144:ef7eb2e8f9f7 1835 * @{
<> 144:ef7eb2e8f9f7 1836 */
<> 144:ef7eb2e8f9f7 1837
<> 144:ef7eb2e8f9f7 1838 /**
<> 144:ef7eb2e8f9f7 1839 * @brief Return the SPI state
<> 144:ef7eb2e8f9f7 1840 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1841 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1842 * @retval SPI state
<> 144:ef7eb2e8f9f7 1843 */
<> 144:ef7eb2e8f9f7 1844 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1845 {
<> 144:ef7eb2e8f9f7 1846 return hspi->State;
<> 144:ef7eb2e8f9f7 1847 }
<> 144:ef7eb2e8f9f7 1848
<> 144:ef7eb2e8f9f7 1849 /**
<> 144:ef7eb2e8f9f7 1850 * @brief Return the SPI error code
<> 144:ef7eb2e8f9f7 1851 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1852 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1853 * @retval SPI Error Code
<> 144:ef7eb2e8f9f7 1854 */
<> 144:ef7eb2e8f9f7 1855 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1856 {
<> 144:ef7eb2e8f9f7 1857 return hspi->ErrorCode;
<> 144:ef7eb2e8f9f7 1858 }
<> 144:ef7eb2e8f9f7 1859
<> 144:ef7eb2e8f9f7 1860 /**
<> 144:ef7eb2e8f9f7 1861 * @}
<> 144:ef7eb2e8f9f7 1862 */
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 /** @addtogroup SPI_Private
<> 144:ef7eb2e8f9f7 1865 * @{
<> 144:ef7eb2e8f9f7 1866 */
<> 144:ef7eb2e8f9f7 1867
Anna Bridge 186:707f6e361f3e 1868 // MBED commit 64a037cc
Anna Bridge 186:707f6e361f3e 1869
<> 144:ef7eb2e8f9f7 1870 /**
<> 144:ef7eb2e8f9f7 1871 * @brief DMA SPI transmit process complete callback
<> 144:ef7eb2e8f9f7 1872 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1873 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1874 * @retval None
<> 144:ef7eb2e8f9f7 1875 */
<> 144:ef7eb2e8f9f7 1876 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1877 {
<> 144:ef7eb2e8f9f7 1878 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1879
<> 144:ef7eb2e8f9f7 1880
<> 144:ef7eb2e8f9f7 1881 /* DMA Normal Mode */
<> 151:5eaa88a5bcc7 1882 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1883 {
<> 144:ef7eb2e8f9f7 1884 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 1885 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1886 {
<> 144:ef7eb2e8f9f7 1887 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1888 }
<> 144:ef7eb2e8f9f7 1889
<> 144:ef7eb2e8f9f7 1890 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1891 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1892
<> 144:ef7eb2e8f9f7 1893 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 1894 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1895 {
<> 144:ef7eb2e8f9f7 1896 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1897 }
<> 144:ef7eb2e8f9f7 1898
<> 151:5eaa88a5bcc7 1899 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1900 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1901 }
<> 144:ef7eb2e8f9f7 1902
<> 144:ef7eb2e8f9f7 1903 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<> 144:ef7eb2e8f9f7 1904 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 1905 {
<> 144:ef7eb2e8f9f7 1906 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1907 }
<> 144:ef7eb2e8f9f7 1908
<> 144:ef7eb2e8f9f7 1909 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 1910 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1911 {
<> 144:ef7eb2e8f9f7 1912 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1913 }
<> 144:ef7eb2e8f9f7 1914 else
<> 144:ef7eb2e8f9f7 1915 {
<> 144:ef7eb2e8f9f7 1916 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1917 }
<> 144:ef7eb2e8f9f7 1918 }
<> 144:ef7eb2e8f9f7 1919
<> 144:ef7eb2e8f9f7 1920 /**
<> 144:ef7eb2e8f9f7 1921 * @brief DMA SPI receive process complete callback
<> 144:ef7eb2e8f9f7 1922 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1923 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1924 * @retval None
<> 144:ef7eb2e8f9f7 1925 */
<> 144:ef7eb2e8f9f7 1926 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1927 {
<> 151:5eaa88a5bcc7 1928 __IO uint16_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1931
<> 144:ef7eb2e8f9f7 1932 /* DMA Normal mode */
<> 151:5eaa88a5bcc7 1933 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1934 {
<> 144:ef7eb2e8f9f7 1935 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1936 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1937
<> 144:ef7eb2e8f9f7 1938 /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
<> 144:ef7eb2e8f9f7 1939 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1940
<> 144:ef7eb2e8f9f7 1941 /* CRC Calculation handling */
<> 144:ef7eb2e8f9f7 1942 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1943 {
<> 144:ef7eb2e8f9f7 1944 /* Wait until RXNE flag is set (CRC ready) */
<> 144:ef7eb2e8f9f7 1945 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1946 {
<> 144:ef7eb2e8f9f7 1947 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1948 }
<> 144:ef7eb2e8f9f7 1949
<> 144:ef7eb2e8f9f7 1950 /* Read CRC */
<> 144:ef7eb2e8f9f7 1951 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1952 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 /* Wait until RXNE flag is reset */
<> 144:ef7eb2e8f9f7 1955 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1956 {
<> 144:ef7eb2e8f9f7 1957 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1958 }
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 1961 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 1962 {
<> 144:ef7eb2e8f9f7 1963 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1964 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1965 }
<> 144:ef7eb2e8f9f7 1966 }
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 1969 {
<> 144:ef7eb2e8f9f7 1970 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 1971 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 1972 }
<> 144:ef7eb2e8f9f7 1973
<> 151:5eaa88a5bcc7 1974 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1975 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1976
<> 144:ef7eb2e8f9f7 1977 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 1978 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1979 {
<> 144:ef7eb2e8f9f7 1980 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1981 }
<> 144:ef7eb2e8f9f7 1982 else
<> 144:ef7eb2e8f9f7 1983 {
<> 144:ef7eb2e8f9f7 1984 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1985 }
<> 144:ef7eb2e8f9f7 1986 }
<> 144:ef7eb2e8f9f7 1987 else
<> 144:ef7eb2e8f9f7 1988 {
<> 144:ef7eb2e8f9f7 1989 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1990 }
<> 144:ef7eb2e8f9f7 1991 }
<> 144:ef7eb2e8f9f7 1992
<> 144:ef7eb2e8f9f7 1993 /**
<> 144:ef7eb2e8f9f7 1994 * @brief DMA SPI transmit receive process complete callback
<> 144:ef7eb2e8f9f7 1995 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1996 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1997 * @retval None
<> 144:ef7eb2e8f9f7 1998 */
<> 144:ef7eb2e8f9f7 1999 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2000 {
<> 151:5eaa88a5bcc7 2001 __IO uint16_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 2002
<> 144:ef7eb2e8f9f7 2003 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 151:5eaa88a5bcc7 2004 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 2005 {
<> 144:ef7eb2e8f9f7 2006 /* CRC Calculation handling */
<> 144:ef7eb2e8f9f7 2007 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2008 {
<> 144:ef7eb2e8f9f7 2009 /* Check if CRC is done on going (RXNE flag set) */
<> 144:ef7eb2e8f9f7 2010 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
<> 144:ef7eb2e8f9f7 2011 {
<> 144:ef7eb2e8f9f7 2012 /* Wait until RXNE flag is set to send data */
<> 144:ef7eb2e8f9f7 2013 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2014 {
<> 144:ef7eb2e8f9f7 2015 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2016 }
<> 144:ef7eb2e8f9f7 2017 }
<> 144:ef7eb2e8f9f7 2018 /* Read CRC */
<> 144:ef7eb2e8f9f7 2019 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2020 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
<> 144:ef7eb2e8f9f7 2021
<> 144:ef7eb2e8f9f7 2022 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 2023 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 2024 {
<> 144:ef7eb2e8f9f7 2025 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2026 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2027 }
<> 144:ef7eb2e8f9f7 2028 }
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 2031 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2032 {
<> 144:ef7eb2e8f9f7 2033 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2034 }
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 2037 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2038
<> 144:ef7eb2e8f9f7 2039 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 2040 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2041 {
<> 144:ef7eb2e8f9f7 2042 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2043 }
<> 144:ef7eb2e8f9f7 2044
<> 144:ef7eb2e8f9f7 2045 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 2046 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2047
<> 151:5eaa88a5bcc7 2048 hspi->TxXferCount = 0U;
<> 151:5eaa88a5bcc7 2049 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2050
<> 144:ef7eb2e8f9f7 2051 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 2054 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2055 {
<> 144:ef7eb2e8f9f7 2056 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2057 }
<> 144:ef7eb2e8f9f7 2058 else
<> 144:ef7eb2e8f9f7 2059 {
<> 144:ef7eb2e8f9f7 2060 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2061 }
<> 144:ef7eb2e8f9f7 2062 }
<> 144:ef7eb2e8f9f7 2063 else
<> 144:ef7eb2e8f9f7 2064 {
<> 144:ef7eb2e8f9f7 2065 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2066 }
<> 144:ef7eb2e8f9f7 2067 }
<> 144:ef7eb2e8f9f7 2068
<> 144:ef7eb2e8f9f7 2069 /**
<> 144:ef7eb2e8f9f7 2070 * @brief DMA SPI half transmit process complete callback
<> 144:ef7eb2e8f9f7 2071 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2072 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2073 * @retval None
<> 144:ef7eb2e8f9f7 2074 */
<> 144:ef7eb2e8f9f7 2075 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2076 {
<> 144:ef7eb2e8f9f7 2077 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2078
<> 144:ef7eb2e8f9f7 2079 HAL_SPI_TxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2080 }
<> 144:ef7eb2e8f9f7 2081
<> 144:ef7eb2e8f9f7 2082 /**
<> 144:ef7eb2e8f9f7 2083 * @brief DMA SPI half receive process complete callback
<> 144:ef7eb2e8f9f7 2084 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2085 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2086 * @retval None
<> 144:ef7eb2e8f9f7 2087 */
<> 144:ef7eb2e8f9f7 2088 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2089 {
<> 144:ef7eb2e8f9f7 2090 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2091
<> 144:ef7eb2e8f9f7 2092 HAL_SPI_RxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2093 }
<> 144:ef7eb2e8f9f7 2094
<> 144:ef7eb2e8f9f7 2095 /**
<> 144:ef7eb2e8f9f7 2096 * @brief DMA SPI Half transmit receive process complete callback
<> 144:ef7eb2e8f9f7 2097 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2098 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2099 * @retval None
<> 144:ef7eb2e8f9f7 2100 */
<> 144:ef7eb2e8f9f7 2101 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2102 {
<> 144:ef7eb2e8f9f7 2103 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2104
<> 144:ef7eb2e8f9f7 2105 HAL_SPI_TxRxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2106 }
<> 144:ef7eb2e8f9f7 2107
<> 144:ef7eb2e8f9f7 2108 /**
<> 144:ef7eb2e8f9f7 2109 * @brief DMA SPI communication error callback
<> 144:ef7eb2e8f9f7 2110 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2111 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2112 * @retval None
<> 144:ef7eb2e8f9f7 2113 */
<> 144:ef7eb2e8f9f7 2114 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2115 {
<> 144:ef7eb2e8f9f7 2116 SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 151:5eaa88a5bcc7 2117 hspi->TxXferCount = 0U;
<> 151:5eaa88a5bcc7 2118 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2119 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2120 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2121 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2122 }
<> 144:ef7eb2e8f9f7 2123
<> 144:ef7eb2e8f9f7 2124 /**
<> 144:ef7eb2e8f9f7 2125 * @brief This function handles SPI Communication Timeout.
<> 144:ef7eb2e8f9f7 2126 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2127 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2128 * @param Flag: SPI flag to check
<> 144:ef7eb2e8f9f7 2129 * @param Status: Flag status to check: RESET or set
<> 144:ef7eb2e8f9f7 2130 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 2131 * @retval HAL status
<> 144:ef7eb2e8f9f7 2132 */
<> 144:ef7eb2e8f9f7 2133 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2134 {
<> 151:5eaa88a5bcc7 2135 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 2136
<> 144:ef7eb2e8f9f7 2137 /* Get tick */
<> 144:ef7eb2e8f9f7 2138 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2139
<> 144:ef7eb2e8f9f7 2140 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 2141 if(Status == RESET)
<> 144:ef7eb2e8f9f7 2142 {
<> 144:ef7eb2e8f9f7 2143 while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
<> 144:ef7eb2e8f9f7 2144 {
<> 144:ef7eb2e8f9f7 2145 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2146 {
<> 151:5eaa88a5bcc7 2147 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 2148 {
<> 144:ef7eb2e8f9f7 2149 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 2150 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 2151 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 2152
<> 144:ef7eb2e8f9f7 2153 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 2154 __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2155
<> 144:ef7eb2e8f9f7 2156 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2157 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2158
<> 144:ef7eb2e8f9f7 2159 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 2160 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2161 {
<> 144:ef7eb2e8f9f7 2162 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 2163 }
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2168 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2169
<> 144:ef7eb2e8f9f7 2170 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2171 }
<> 144:ef7eb2e8f9f7 2172 }
<> 144:ef7eb2e8f9f7 2173 }
<> 144:ef7eb2e8f9f7 2174 }
<> 144:ef7eb2e8f9f7 2175 else
<> 144:ef7eb2e8f9f7 2176 {
<> 144:ef7eb2e8f9f7 2177 while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
<> 144:ef7eb2e8f9f7 2178 {
<> 144:ef7eb2e8f9f7 2179 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2180 {
<> 151:5eaa88a5bcc7 2181 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 2182 {
<> 144:ef7eb2e8f9f7 2183 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 2184 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 2185 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 2186
<> 144:ef7eb2e8f9f7 2187 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 2188 __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2189
<> 144:ef7eb2e8f9f7 2190 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2191 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2192
<> 144:ef7eb2e8f9f7 2193 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 2194 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2195 {
<> 144:ef7eb2e8f9f7 2196 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 2197 }
<> 144:ef7eb2e8f9f7 2198
<> 144:ef7eb2e8f9f7 2199 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2200
<> 144:ef7eb2e8f9f7 2201 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2202 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2203
<> 144:ef7eb2e8f9f7 2204 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2205 }
<> 144:ef7eb2e8f9f7 2206 }
<> 144:ef7eb2e8f9f7 2207 }
<> 144:ef7eb2e8f9f7 2208 }
<> 144:ef7eb2e8f9f7 2209 return HAL_OK;
<> 144:ef7eb2e8f9f7 2210 }
<> 144:ef7eb2e8f9f7 2211 /**
<> 144:ef7eb2e8f9f7 2212 * @}
<> 144:ef7eb2e8f9f7 2213 */
<> 144:ef7eb2e8f9f7 2214
<> 144:ef7eb2e8f9f7 2215 /**
<> 144:ef7eb2e8f9f7 2216 * @}
<> 144:ef7eb2e8f9f7 2217 */
<> 144:ef7eb2e8f9f7 2218
Anna Bridge 186:707f6e361f3e 2219 // MBED commit 64a037cc
<> 153:fa9ff456f731 2220 /**
<> 153:fa9ff456f731 2221 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 153:fa9ff456f731 2222 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2223 * the configuration information for SPI module.
<> 153:fa9ff456f731 2224 * @retval None
<> 153:fa9ff456f731 2225 */
<> 153:fa9ff456f731 2226 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2227 {
<> 153:fa9ff456f731 2228 /* Receive data in 8bit mode */
<> 153:fa9ff456f731 2229 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
<> 153:fa9ff456f731 2230 hspi->RxXferCount--;
<> 153:fa9ff456f731 2231
<> 153:fa9ff456f731 2232 /* check end of the reception */
<> 153:fa9ff456f731 2233 if(hspi->RxXferCount == 0U)
<> 153:fa9ff456f731 2234 {
<> 153:fa9ff456f731 2235 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2236 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2237 {
<> 153:fa9ff456f731 2238 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<> 153:fa9ff456f731 2239 return;
<> 153:fa9ff456f731 2240 }
<> 153:fa9ff456f731 2241 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2242
<> 153:fa9ff456f731 2243 /* Disable RXNE interrupt */
<> 153:fa9ff456f731 2244 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 153:fa9ff456f731 2245
<> 153:fa9ff456f731 2246 if(hspi->TxXferCount == 0U)
<> 153:fa9ff456f731 2247 {
<> 153:fa9ff456f731 2248 SPI_CloseRxTx_ISR(hspi);
<> 153:fa9ff456f731 2249 }
<> 153:fa9ff456f731 2250 }
<> 153:fa9ff456f731 2251 }
<> 153:fa9ff456f731 2252
<> 153:fa9ff456f731 2253 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2254 /**
<> 153:fa9ff456f731 2255 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 153:fa9ff456f731 2256 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2257 * the configuration information for SPI module.
<> 153:fa9ff456f731 2258 * @retval None
<> 153:fa9ff456f731 2259 */
<> 153:fa9ff456f731 2260 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2261 {
<> 153:fa9ff456f731 2262 __IO uint8_t tmpreg = 0U;
<> 153:fa9ff456f731 2263
<> 153:fa9ff456f731 2264 /* Read data register to flush CRC */
<> 153:fa9ff456f731 2265 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 153:fa9ff456f731 2266
<> 153:fa9ff456f731 2267 /* To avoid GCC warning */
<> 153:fa9ff456f731 2268
<> 153:fa9ff456f731 2269 UNUSED(tmpreg);
<> 153:fa9ff456f731 2270
<> 153:fa9ff456f731 2271 /* Disable RXNE interrupt */
<> 153:fa9ff456f731 2272 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 153:fa9ff456f731 2273
<> 153:fa9ff456f731 2274 if(hspi->TxXferCount == 0U)
<> 153:fa9ff456f731 2275 {
<> 153:fa9ff456f731 2276 SPI_CloseRxTx_ISR(hspi);
<> 153:fa9ff456f731 2277 }
<> 153:fa9ff456f731 2278 }
<> 153:fa9ff456f731 2279 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2280
<> 153:fa9ff456f731 2281 /**
<> 153:fa9ff456f731 2282 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 153:fa9ff456f731 2283 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2284 * the configuration information for SPI module.
<> 153:fa9ff456f731 2285 * @retval None
<> 153:fa9ff456f731 2286 */
<> 153:fa9ff456f731 2287 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2288 {
<> 153:fa9ff456f731 2289 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 153:fa9ff456f731 2290 hspi->TxXferCount--;
<> 153:fa9ff456f731 2291
<> 153:fa9ff456f731 2292 /* check the end of the transmission */
<> 153:fa9ff456f731 2293 if(hspi->TxXferCount == 0U)
<> 153:fa9ff456f731 2294 {
<> 153:fa9ff456f731 2295 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2296 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2297 {
<> 153:fa9ff456f731 2298 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 153:fa9ff456f731 2299 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 153:fa9ff456f731 2300 return;
<> 153:fa9ff456f731 2301 }
<> 153:fa9ff456f731 2302 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2303
<> 153:fa9ff456f731 2304 /* Disable TXE interrupt */
<> 153:fa9ff456f731 2305 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 153:fa9ff456f731 2306
<> 153:fa9ff456f731 2307 if(hspi->RxXferCount == 0U)
<> 153:fa9ff456f731 2308 {
<> 153:fa9ff456f731 2309 SPI_CloseRxTx_ISR(hspi);
<> 153:fa9ff456f731 2310 }
<> 153:fa9ff456f731 2311 }
<> 153:fa9ff456f731 2312 }
<> 153:fa9ff456f731 2313
<> 153:fa9ff456f731 2314 /**
<> 153:fa9ff456f731 2315 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 153:fa9ff456f731 2316 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2317 * the configuration information for SPI module.
<> 153:fa9ff456f731 2318 * @retval None
<> 153:fa9ff456f731 2319 */
<> 153:fa9ff456f731 2320 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2321 {
<> 153:fa9ff456f731 2322 /* Receive data in 16 Bit mode */
<> 153:fa9ff456f731 2323 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 153:fa9ff456f731 2324 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 153:fa9ff456f731 2325 hspi->RxXferCount--;
<> 153:fa9ff456f731 2326
<> 153:fa9ff456f731 2327 if(hspi->RxXferCount == 0U)
<> 153:fa9ff456f731 2328 {
<> 153:fa9ff456f731 2329 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2330 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2331 {
<> 153:fa9ff456f731 2332 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<> 153:fa9ff456f731 2333 return;
<> 153:fa9ff456f731 2334 }
<> 153:fa9ff456f731 2335 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2336
<> 153:fa9ff456f731 2337 /* Disable RXNE interrupt */
<> 153:fa9ff456f731 2338 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 153:fa9ff456f731 2339
<> 153:fa9ff456f731 2340 if(hspi->TxXferCount == 0U)
<> 153:fa9ff456f731 2341 {
<> 153:fa9ff456f731 2342 SPI_CloseRxTx_ISR(hspi);
<> 153:fa9ff456f731 2343 }
<> 153:fa9ff456f731 2344 }
<> 153:fa9ff456f731 2345 }
<> 153:fa9ff456f731 2346
<> 153:fa9ff456f731 2347 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2348 /**
<> 153:fa9ff456f731 2349 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
<> 153:fa9ff456f731 2350 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2351 * the configuration information for SPI module.
<> 153:fa9ff456f731 2352 * @retval None
<> 153:fa9ff456f731 2353 */
<> 153:fa9ff456f731 2354 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2355 {
<> 153:fa9ff456f731 2356 /* Receive data in 16 Bit mode */
<> 153:fa9ff456f731 2357 __IO uint16_t tmpreg = 0U;
<> 153:fa9ff456f731 2358
<> 153:fa9ff456f731 2359 /* Read data register to flush CRC */
<> 153:fa9ff456f731 2360 tmpreg = hspi->Instance->DR;
<> 153:fa9ff456f731 2361
<> 153:fa9ff456f731 2362 /* To avoid GCC warning */
<> 153:fa9ff456f731 2363 UNUSED(tmpreg);
<> 153:fa9ff456f731 2364
<> 153:fa9ff456f731 2365 /* Disable RXNE interrupt */
<> 153:fa9ff456f731 2366 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 153:fa9ff456f731 2367
<> 153:fa9ff456f731 2368 SPI_CloseRxTx_ISR(hspi);
<> 153:fa9ff456f731 2369 }
<> 153:fa9ff456f731 2370 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2371
<> 153:fa9ff456f731 2372 /**
<> 153:fa9ff456f731 2373 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 153:fa9ff456f731 2374 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2375 * the configuration information for SPI module.
<> 153:fa9ff456f731 2376 * @retval None
<> 153:fa9ff456f731 2377 */
<> 153:fa9ff456f731 2378 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2379 {
<> 153:fa9ff456f731 2380 /* Transmit data in 16 Bit mode */
<> 153:fa9ff456f731 2381 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 153:fa9ff456f731 2382 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 153:fa9ff456f731 2383 hspi->TxXferCount--;
<> 153:fa9ff456f731 2384
<> 153:fa9ff456f731 2385 /* Enable CRC Transmission */
<> 153:fa9ff456f731 2386 if(hspi->TxXferCount == 0U)
<> 153:fa9ff456f731 2387 {
<> 153:fa9ff456f731 2388 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2389 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2390 {
<> 153:fa9ff456f731 2391 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 153:fa9ff456f731 2392 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 153:fa9ff456f731 2393 return;
<> 153:fa9ff456f731 2394 }
<> 153:fa9ff456f731 2395 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2396
<> 153:fa9ff456f731 2397 /* Disable TXE interrupt */
<> 153:fa9ff456f731 2398 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 153:fa9ff456f731 2399
<> 153:fa9ff456f731 2400 if(hspi->RxXferCount == 0U)
<> 153:fa9ff456f731 2401 {
<> 153:fa9ff456f731 2402 SPI_CloseRxTx_ISR(hspi);
<> 153:fa9ff456f731 2403 }
<> 153:fa9ff456f731 2404 }
<> 153:fa9ff456f731 2405 }
<> 153:fa9ff456f731 2406
<> 153:fa9ff456f731 2407 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2408 /**
<> 153:fa9ff456f731 2409 * @brief Manage the CRC 8-bit receive in Interrupt context.
<> 153:fa9ff456f731 2410 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2411 * the configuration information for SPI module.
<> 153:fa9ff456f731 2412 * @retval None
<> 153:fa9ff456f731 2413 */
<> 153:fa9ff456f731 2414 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2415 {
<> 153:fa9ff456f731 2416 __IO uint8_t tmpreg = 0U;
<> 153:fa9ff456f731 2417
<> 153:fa9ff456f731 2418 /* Read data register to flush CRC */
<> 153:fa9ff456f731 2419 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
<> 153:fa9ff456f731 2420
<> 153:fa9ff456f731 2421 /* To avoid GCC warning */
<> 153:fa9ff456f731 2422 UNUSED(tmpreg);
<> 153:fa9ff456f731 2423
<> 153:fa9ff456f731 2424 SPI_CloseRx_ISR(hspi);
<> 153:fa9ff456f731 2425 }
<> 153:fa9ff456f731 2426 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2427
<> 153:fa9ff456f731 2428 /**
<> 153:fa9ff456f731 2429 * @brief Manage the receive 8-bit in Interrupt context.
<> 153:fa9ff456f731 2430 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2431 * the configuration information for SPI module.
<> 153:fa9ff456f731 2432 * @retval None
<> 153:fa9ff456f731 2433 */
<> 153:fa9ff456f731 2434 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2435 {
<> 153:fa9ff456f731 2436 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
<> 153:fa9ff456f731 2437 hspi->RxXferCount--;
<> 153:fa9ff456f731 2438
<> 153:fa9ff456f731 2439 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2440 /* Enable CRC Transmission */
<> 153:fa9ff456f731 2441 if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 153:fa9ff456f731 2442 {
<> 153:fa9ff456f731 2443 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 153:fa9ff456f731 2444 }
<> 153:fa9ff456f731 2445 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2446
<> 153:fa9ff456f731 2447 if(hspi->RxXferCount == 0U)
<> 153:fa9ff456f731 2448 {
<> 153:fa9ff456f731 2449 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2450 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2451 {
<> 153:fa9ff456f731 2452 hspi->RxISR = SPI_RxISR_8BITCRC;
<> 153:fa9ff456f731 2453 return;
<> 153:fa9ff456f731 2454 }
<> 153:fa9ff456f731 2455 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2456 SPI_CloseRx_ISR(hspi);
<> 153:fa9ff456f731 2457 }
<> 153:fa9ff456f731 2458 }
<> 153:fa9ff456f731 2459
<> 153:fa9ff456f731 2460 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2461 /**
<> 153:fa9ff456f731 2462 * @brief Manage the CRC 16-bit receive in Interrupt context.
<> 153:fa9ff456f731 2463 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2464 * the configuration information for SPI module.
<> 153:fa9ff456f731 2465 * @retval None
<> 153:fa9ff456f731 2466 */
<> 153:fa9ff456f731 2467 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2468 {
<> 153:fa9ff456f731 2469 __IO uint16_t tmpreg = 0U;
<> 153:fa9ff456f731 2470
<> 153:fa9ff456f731 2471 /* Read data register to flush CRC */
<> 153:fa9ff456f731 2472 tmpreg = hspi->Instance->DR;
<> 153:fa9ff456f731 2473
<> 153:fa9ff456f731 2474 /* To avoid GCC warning */
<> 153:fa9ff456f731 2475 UNUSED(tmpreg);
<> 153:fa9ff456f731 2476
<> 153:fa9ff456f731 2477 /* Disable RXNE and ERR interrupt */
<> 153:fa9ff456f731 2478 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 153:fa9ff456f731 2479
<> 153:fa9ff456f731 2480 SPI_CloseRx_ISR(hspi);
<> 153:fa9ff456f731 2481 }
<> 153:fa9ff456f731 2482 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2483
<> 153:fa9ff456f731 2484 /**
<> 153:fa9ff456f731 2485 * @brief Manage the 16-bit receive in Interrupt context.
<> 153:fa9ff456f731 2486 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2487 * the configuration information for SPI module.
<> 153:fa9ff456f731 2488 * @retval None
<> 153:fa9ff456f731 2489 */
<> 153:fa9ff456f731 2490 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2491 {
<> 153:fa9ff456f731 2492 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 153:fa9ff456f731 2493 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 153:fa9ff456f731 2494 hspi->RxXferCount--;
<> 153:fa9ff456f731 2495
<> 153:fa9ff456f731 2496 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2497 /* Enable CRC Transmission */
<> 153:fa9ff456f731 2498 if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 153:fa9ff456f731 2499 {
<> 153:fa9ff456f731 2500 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 153:fa9ff456f731 2501 }
<> 153:fa9ff456f731 2502 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2503
<> 153:fa9ff456f731 2504 if(hspi->RxXferCount == 0U)
<> 153:fa9ff456f731 2505 {
<> 153:fa9ff456f731 2506 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2507 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2508 {
<> 153:fa9ff456f731 2509 hspi->RxISR = SPI_RxISR_16BITCRC;
<> 153:fa9ff456f731 2510 return;
<> 153:fa9ff456f731 2511 }
<> 153:fa9ff456f731 2512 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2513 SPI_CloseRx_ISR(hspi);
<> 153:fa9ff456f731 2514 }
<> 153:fa9ff456f731 2515 }
<> 153:fa9ff456f731 2516
<> 153:fa9ff456f731 2517 /**
<> 153:fa9ff456f731 2518 * @brief Handle the data 8-bit transmit in Interrupt mode.
<> 153:fa9ff456f731 2519 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2520 * the configuration information for SPI module.
<> 153:fa9ff456f731 2521 * @retval None
<> 153:fa9ff456f731 2522 */
<> 153:fa9ff456f731 2523 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2524 {
<> 153:fa9ff456f731 2525 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 153:fa9ff456f731 2526 hspi->TxXferCount--;
<> 153:fa9ff456f731 2527
<> 153:fa9ff456f731 2528 if(hspi->TxXferCount == 0U)
<> 153:fa9ff456f731 2529 {
<> 153:fa9ff456f731 2530 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2531 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2532 {
<> 153:fa9ff456f731 2533 /* Enable CRC Transmission */
<> 153:fa9ff456f731 2534 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 153:fa9ff456f731 2535 }
<> 153:fa9ff456f731 2536 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2537 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<> 153:fa9ff456f731 2538 SPI_CloseTx_ISR(hspi);
<> 153:fa9ff456f731 2539 }
<> 153:fa9ff456f731 2540 }
<> 153:fa9ff456f731 2541
<> 153:fa9ff456f731 2542 /**
<> 153:fa9ff456f731 2543 * @brief Handle the data 16-bit transmit in Interrupt mode.
<> 153:fa9ff456f731 2544 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2545 * the configuration information for SPI module.
<> 153:fa9ff456f731 2546 * @retval None
<> 153:fa9ff456f731 2547 */
<> 153:fa9ff456f731 2548 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2549 {
<> 153:fa9ff456f731 2550 /* Transmit data in 16 Bit mode */
<> 153:fa9ff456f731 2551 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 153:fa9ff456f731 2552 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 153:fa9ff456f731 2553 hspi->TxXferCount--;
<> 153:fa9ff456f731 2554
<> 153:fa9ff456f731 2555 if(hspi->TxXferCount == 0U)
<> 153:fa9ff456f731 2556 {
<> 153:fa9ff456f731 2557 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2558 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2559 {
<> 153:fa9ff456f731 2560 /* Enable CRC Transmission */
<> 153:fa9ff456f731 2561 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 153:fa9ff456f731 2562 }
<> 153:fa9ff456f731 2563 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2564 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<> 153:fa9ff456f731 2565 SPI_CloseTx_ISR(hspi);
<> 153:fa9ff456f731 2566 }
<> 153:fa9ff456f731 2567 }
<> 153:fa9ff456f731 2568
<> 153:fa9ff456f731 2569 /**
<> 153:fa9ff456f731 2570 * @brief Handle SPI Communication Timeout.
<> 153:fa9ff456f731 2571 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2572 * the configuration information for SPI module.
<> 153:fa9ff456f731 2573 * @param Flag: SPI flag to check
<> 153:fa9ff456f731 2574 * @param State: flag state to check
<> 153:fa9ff456f731 2575 * @param Timeout: Timeout duration
<> 153:fa9ff456f731 2576 * @param Tickstart: tick start value
<> 153:fa9ff456f731 2577 * @retval HAL status
<> 153:fa9ff456f731 2578 */
<> 153:fa9ff456f731 2579 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
<> 153:fa9ff456f731 2580 {
<> 153:fa9ff456f731 2581 while((hspi->Instance->SR & Flag) != State)
<> 153:fa9ff456f731 2582 {
<> 153:fa9ff456f731 2583 if(Timeout != HAL_MAX_DELAY)
<> 153:fa9ff456f731 2584 {
<> 153:fa9ff456f731 2585 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
<> 153:fa9ff456f731 2586 {
<> 153:fa9ff456f731 2587 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 153:fa9ff456f731 2588 on both master and slave sides in order to resynchronize the master
<> 153:fa9ff456f731 2589 and slave for their respective CRC calculation */
<> 153:fa9ff456f731 2590
<> 153:fa9ff456f731 2591 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 153:fa9ff456f731 2592 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 153:fa9ff456f731 2593
<> 153:fa9ff456f731 2594 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 153:fa9ff456f731 2595 {
<> 153:fa9ff456f731 2596 /* Disable SPI peripheral */
<> 153:fa9ff456f731 2597 __HAL_SPI_DISABLE(hspi);
<> 153:fa9ff456f731 2598 }
<> 153:fa9ff456f731 2599
<> 153:fa9ff456f731 2600 /* Reset CRC Calculation */
<> 153:fa9ff456f731 2601 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 153:fa9ff456f731 2602 {
<> 153:fa9ff456f731 2603 SPI_RESET_CRC(hspi);
<> 153:fa9ff456f731 2604 }
<> 153:fa9ff456f731 2605
<> 153:fa9ff456f731 2606 hspi->State= HAL_SPI_STATE_READY;
<> 153:fa9ff456f731 2607
<> 153:fa9ff456f731 2608 /* Process Unlocked */
<> 153:fa9ff456f731 2609 __HAL_UNLOCK(hspi);
<> 153:fa9ff456f731 2610
<> 153:fa9ff456f731 2611 return HAL_TIMEOUT;
<> 153:fa9ff456f731 2612 }
<> 153:fa9ff456f731 2613 }
<> 153:fa9ff456f731 2614 }
<> 153:fa9ff456f731 2615
<> 153:fa9ff456f731 2616 return HAL_OK;
<> 153:fa9ff456f731 2617 }
<> 153:fa9ff456f731 2618
<> 153:fa9ff456f731 2619 /**
<> 153:fa9ff456f731 2620 * @brief Handle to check BSY flag before start a new transaction.
<> 153:fa9ff456f731 2621 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2622 * the configuration information for SPI module.
<> 153:fa9ff456f731 2623 * @param Timeout: Timeout duration
<> 153:fa9ff456f731 2624 * @param Tickstart: tick start value
<> 153:fa9ff456f731 2625 * @retval HAL status
<> 153:fa9ff456f731 2626 */
<> 153:fa9ff456f731 2627 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 153:fa9ff456f731 2628 {
<> 153:fa9ff456f731 2629 /* Control the BSY flag */
<> 153:fa9ff456f731 2630 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 153:fa9ff456f731 2631 {
<> 153:fa9ff456f731 2632 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 153:fa9ff456f731 2633 return HAL_TIMEOUT;
<> 153:fa9ff456f731 2634 }
<> 153:fa9ff456f731 2635 return HAL_OK;
<> 153:fa9ff456f731 2636 }
<> 153:fa9ff456f731 2637
<> 153:fa9ff456f731 2638 /**
<> 153:fa9ff456f731 2639 * @brief Handle the end of the RXTX transaction.
<> 153:fa9ff456f731 2640 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2641 * the configuration information for SPI module.
<> 153:fa9ff456f731 2642 * @retval None
<> 153:fa9ff456f731 2643 */
<> 153:fa9ff456f731 2644 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2645 {
<> 153:fa9ff456f731 2646 uint32_t tickstart = 0U;
<> 153:fa9ff456f731 2647 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
<> 153:fa9ff456f731 2648 /* Init tickstart for timeout managment*/
<> 153:fa9ff456f731 2649 tickstart = HAL_GetTick();
<> 153:fa9ff456f731 2650
<> 153:fa9ff456f731 2651 /* Disable ERR interrupt */
<> 153:fa9ff456f731 2652 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 153:fa9ff456f731 2653
<> 153:fa9ff456f731 2654 /* Wait until TXE flag is set */
<> 153:fa9ff456f731 2655 do
<> 153:fa9ff456f731 2656 {
<> 153:fa9ff456f731 2657 if(count-- == 0)
<> 153:fa9ff456f731 2658 {
<> 153:fa9ff456f731 2659 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 153:fa9ff456f731 2660 break;
<> 153:fa9ff456f731 2661 }
<> 153:fa9ff456f731 2662 }
<> 153:fa9ff456f731 2663 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
<> 153:fa9ff456f731 2664
<> 153:fa9ff456f731 2665 /* Check the end of the transaction */
<> 153:fa9ff456f731 2666 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
<> 153:fa9ff456f731 2667 {
<> 153:fa9ff456f731 2668 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 153:fa9ff456f731 2669 }
<> 153:fa9ff456f731 2670
<> 153:fa9ff456f731 2671 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 153:fa9ff456f731 2672 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 153:fa9ff456f731 2673 {
<> 153:fa9ff456f731 2674 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 153:fa9ff456f731 2675 }
<> 153:fa9ff456f731 2676
<> 153:fa9ff456f731 2677 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2678 /* Check if CRC error occurred */
<> 153:fa9ff456f731 2679 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 153:fa9ff456f731 2680 {
<> 153:fa9ff456f731 2681 hspi->State = HAL_SPI_STATE_READY;
<> 153:fa9ff456f731 2682 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 153:fa9ff456f731 2683 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 153:fa9ff456f731 2684 HAL_SPI_ErrorCallback(hspi);
<> 153:fa9ff456f731 2685 }
<> 153:fa9ff456f731 2686 else
<> 153:fa9ff456f731 2687 {
<> 153:fa9ff456f731 2688 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2689 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 153:fa9ff456f731 2690 {
<> 153:fa9ff456f731 2691 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 153:fa9ff456f731 2692 {
<> 153:fa9ff456f731 2693 hspi->State = HAL_SPI_STATE_READY;
<> 153:fa9ff456f731 2694 HAL_SPI_RxCpltCallback(hspi);
<> 153:fa9ff456f731 2695 }
<> 153:fa9ff456f731 2696 else
<> 153:fa9ff456f731 2697 {
<> 153:fa9ff456f731 2698 hspi->State = HAL_SPI_STATE_READY;
<> 153:fa9ff456f731 2699 HAL_SPI_TxRxCpltCallback(hspi);
<> 153:fa9ff456f731 2700 }
<> 153:fa9ff456f731 2701 }
<> 153:fa9ff456f731 2702 else
<> 153:fa9ff456f731 2703 {
<> 153:fa9ff456f731 2704 hspi->State = HAL_SPI_STATE_READY;
<> 153:fa9ff456f731 2705 HAL_SPI_ErrorCallback(hspi);
<> 153:fa9ff456f731 2706 }
<> 153:fa9ff456f731 2707 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2708 }
<> 153:fa9ff456f731 2709 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2710 }
<> 153:fa9ff456f731 2711
<> 153:fa9ff456f731 2712 /**
<> 153:fa9ff456f731 2713 * @brief Handle the end of the RX transaction.
<> 153:fa9ff456f731 2714 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2715 * the configuration information for SPI module.
<> 153:fa9ff456f731 2716 * @retval None
<> 153:fa9ff456f731 2717 */
<> 153:fa9ff456f731 2718 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2719 {
<> 153:fa9ff456f731 2720 /* Disable RXNE and ERR interrupt */
<> 153:fa9ff456f731 2721 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 153:fa9ff456f731 2722
<> 153:fa9ff456f731 2723 /* Check the end of the transaction */
<> 153:fa9ff456f731 2724 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 153:fa9ff456f731 2725 {
<> 153:fa9ff456f731 2726 /* Disable SPI peripheral */
<> 153:fa9ff456f731 2727 __HAL_SPI_DISABLE(hspi);
<> 153:fa9ff456f731 2728 }
<> 153:fa9ff456f731 2729
<> 153:fa9ff456f731 2730 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 153:fa9ff456f731 2731 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 153:fa9ff456f731 2732 {
<> 153:fa9ff456f731 2733 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 153:fa9ff456f731 2734 }
<> 153:fa9ff456f731 2735 hspi->State = HAL_SPI_STATE_READY;
<> 153:fa9ff456f731 2736
<> 153:fa9ff456f731 2737 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2738 /* Check if CRC error occurred */
<> 153:fa9ff456f731 2739 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 153:fa9ff456f731 2740 {
<> 153:fa9ff456f731 2741 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 153:fa9ff456f731 2742 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 153:fa9ff456f731 2743 HAL_SPI_ErrorCallback(hspi);
<> 153:fa9ff456f731 2744 }
<> 153:fa9ff456f731 2745 else
<> 153:fa9ff456f731 2746 {
<> 153:fa9ff456f731 2747 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2748 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 153:fa9ff456f731 2749 {
<> 153:fa9ff456f731 2750 HAL_SPI_RxCpltCallback(hspi);
<> 153:fa9ff456f731 2751 }
<> 153:fa9ff456f731 2752 else
<> 153:fa9ff456f731 2753 {
<> 153:fa9ff456f731 2754 HAL_SPI_ErrorCallback(hspi);
<> 153:fa9ff456f731 2755 }
<> 153:fa9ff456f731 2756 #if (USE_SPI_CRC != 0U)
<> 153:fa9ff456f731 2757 }
<> 153:fa9ff456f731 2758 #endif /* USE_SPI_CRC */
<> 153:fa9ff456f731 2759 }
<> 153:fa9ff456f731 2760
<> 153:fa9ff456f731 2761 /**
<> 153:fa9ff456f731 2762 * @brief Handle the end of the TX transaction.
<> 153:fa9ff456f731 2763 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 153:fa9ff456f731 2764 * the configuration information for SPI module.
<> 153:fa9ff456f731 2765 * @retval None
<> 153:fa9ff456f731 2766 */
<> 153:fa9ff456f731 2767 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<> 153:fa9ff456f731 2768 {
<> 153:fa9ff456f731 2769 uint32_t tickstart = 0U;
<> 153:fa9ff456f731 2770 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
<> 153:fa9ff456f731 2771
<> 153:fa9ff456f731 2772 /* Init tickstart for timeout management*/
<> 153:fa9ff456f731 2773 tickstart = HAL_GetTick();
<> 153:fa9ff456f731 2774
<> 153:fa9ff456f731 2775 /* Wait until TXE flag is set */
<> 153:fa9ff456f731 2776 do
<> 153:fa9ff456f731 2777 {
<> 153:fa9ff456f731 2778 if(count-- == 0)
<> 153:fa9ff456f731 2779 {
<> 153:fa9ff456f731 2780 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 153:fa9ff456f731 2781 break;
<> 153:fa9ff456f731 2782 }
<> 153:fa9ff456f731 2783 }
<> 153:fa9ff456f731 2784 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
<> 153:fa9ff456f731 2785
<> 153:fa9ff456f731 2786 /* Disable TXE and ERR interrupt */
<> 153:fa9ff456f731 2787 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 153:fa9ff456f731 2788
<> 153:fa9ff456f731 2789 /* Check Busy flag */
<> 153:fa9ff456f731 2790 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 153:fa9ff456f731 2791 {
<> 153:fa9ff456f731 2792 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 153:fa9ff456f731 2793 }
<> 153:fa9ff456f731 2794
<> 153:fa9ff456f731 2795 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 153:fa9ff456f731 2796 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 153:fa9ff456f731 2797 {
<> 153:fa9ff456f731 2798 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 153:fa9ff456f731 2799 }
<> 153:fa9ff456f731 2800
<> 153:fa9ff456f731 2801 hspi->State = HAL_SPI_STATE_READY;
<> 153:fa9ff456f731 2802 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 153:fa9ff456f731 2803 {
<> 153:fa9ff456f731 2804 HAL_SPI_ErrorCallback(hspi);
<> 153:fa9ff456f731 2805 }
<> 153:fa9ff456f731 2806 else
<> 153:fa9ff456f731 2807 {
<> 153:fa9ff456f731 2808 HAL_SPI_TxCpltCallback(hspi);
<> 153:fa9ff456f731 2809 }
<> 153:fa9ff456f731 2810 }
<> 153:fa9ff456f731 2811
<> 153:fa9ff456f731 2812 /**
<> 153:fa9ff456f731 2813 * @}
<> 153:fa9ff456f731 2814 */
<> 153:fa9ff456f731 2815
<> 144:ef7eb2e8f9f7 2816 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2817
<> 144:ef7eb2e8f9f7 2818 /**
<> 144:ef7eb2e8f9f7 2819 * @}
<> 144:ef7eb2e8f9f7 2820 */
<> 144:ef7eb2e8f9f7 2821
<> 144:ef7eb2e8f9f7 2822 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 2823