mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
113:b3775bf36a83 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief SPI HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The SPI HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SPI_HandleTypeDef hspi;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
<> 144:ef7eb2e8f9f7 26 (##) Enable the SPIx interface clock
<> 144:ef7eb2e8f9f7 27 (##) SPI pins configuration
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the SPI GPIOs
<> 144:ef7eb2e8f9f7 29 (+++) Configure these SPI pins as alternate function push-pull
<> 144:ef7eb2e8f9f7 30 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 31 (+++) Configure the SPIx interrupt priority
<> 144:ef7eb2e8f9f7 32 (+++) Enable the NVIC SPI IRQ handle
<> 144:ef7eb2e8f9f7 33 (##) DMA Configuration if you need to use DMA process
<> 144:ef7eb2e8f9f7 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
<> 144:ef7eb2e8f9f7 35 (+++) Enable the DMAx clock
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA handle parameters
<> 144:ef7eb2e8f9f7 37 (+++) Configure the DMA Tx or Rx Channel
<> 144:ef7eb2e8f9f7 38 (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
<> 144:ef7eb2e8f9f7 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
<> 144:ef7eb2e8f9f7 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<> 144:ef7eb2e8f9f7 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 46 by calling the customed HAL_SPI_MspInit() API.
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 Circular mode restriction:
<> 144:ef7eb2e8f9f7 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<> 144:ef7eb2e8f9f7 50 (##) Master 2Lines RxOnly
<> 144:ef7eb2e8f9f7 51 (##) Master 1Line Rx
<> 144:ef7eb2e8f9f7 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
<> 144:ef7eb2e8f9f7 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<> 144:ef7eb2e8f9f7 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 [..]
<> 144:ef7eb2e8f9f7 57 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
<> 144:ef7eb2e8f9f7 58 the following table resume the max SPI frequency reached with data size 8bits/16bits,
<> 144:ef7eb2e8f9f7 59 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 DataSize = SPI_DATASIZE_8BIT:
<> 144:ef7eb2e8f9f7 62 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 63 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 144:ef7eb2e8f9f7 64 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 144:ef7eb2e8f9f7 65 | | | Master | Slave | Master | Slave | Master | Slave |
<> 144:ef7eb2e8f9f7 66 |==============================================================================================|
<> 144:ef7eb2e8f9f7 67 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 68 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 69 | / | Interrupt | Fpclk/64 | Fpclk/64 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 70 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 71 | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 72 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 73 | | Polling | Fpclk/2 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 74 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 75 | R | Interrupt | Fpclk/64 | Fpclk/32 | Fpclk/32 | Fpclk/16 | Fpclk/32 | Fpclk/32 |
<> 144:ef7eb2e8f9f7 76 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 77 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 78 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 79 | | Polling | Fpclk/8 | Fpclk/8 | NA | NA | Fpclk/4 | Fpclk/16 |
<> 144:ef7eb2e8f9f7 80 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 81 | T | Interrupt | Fpclk/8 | Fpclk/32 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 144:ef7eb2e8f9f7 82 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 83 | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 84 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 DataSize = SPI_DATASIZE_16BIT:
<> 144:ef7eb2e8f9f7 87 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 88 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 144:ef7eb2e8f9f7 89 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 144:ef7eb2e8f9f7 90 | | | Master | Slave | Master | Slave | Master | Slave |
<> 144:ef7eb2e8f9f7 91 |==============================================================================================|
<> 144:ef7eb2e8f9f7 92 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 93 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 94 | / | Interrupt | Fpclk/32 | Fpclk/16 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 95 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 96 | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA |
<> 144:ef7eb2e8f9f7 97 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 98 | | Polling | Fpclk/2 | Fpclk/4 | Fpclk/8 | Fpclk/4 | Fpclk/2 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 99 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 100 | R | Interrupt | Fpclk/32 | Fpclk/8 | Fpclk/16 | Fpclk/16 | Fpclk/16 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 101 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 102 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/8 | Fpclk/2 | Fpclk/8 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 103 |=========|================|==========|==========|===========|==========|===========|==========|
<> 144:ef7eb2e8f9f7 104 | | Polling | Fpclk/4 | Fpclk/4 | NA | NA | Fpclk/4 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 105 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 106 | T | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 144:ef7eb2e8f9f7 107 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 144:ef7eb2e8f9f7 108 | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 |
<> 144:ef7eb2e8f9f7 109 +----------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 110 @note The max SPI frequency depend on SPI data size (8bits, 16bits),
<> 144:ef7eb2e8f9f7 111 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
<> 144:ef7eb2e8f9f7 112 @note
<> 144:ef7eb2e8f9f7 113 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
<> 144:ef7eb2e8f9f7 114 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
<> 144:ef7eb2e8f9f7 115 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 @endverbatim
<> 144:ef7eb2e8f9f7 118 ******************************************************************************
<> 144:ef7eb2e8f9f7 119 * @attention
<> 144:ef7eb2e8f9f7 120 *
<> 144:ef7eb2e8f9f7 121 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 124 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 125 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 126 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 127 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 128 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 129 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 130 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 131 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 132 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 135 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 136 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 137 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 138 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 139 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 140 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 141 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 142 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 143 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 144 *
<> 144:ef7eb2e8f9f7 145 ******************************************************************************
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 158 * @brief SPI HAL module driver
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 163 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 164 /** @addtogroup SPI_Private
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 #define SPI_TIMEOUT_VALUE 10
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 170 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 171 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 174 static void SPI_TxISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 175 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 176 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 177 static void SPI_RxISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 178 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 179 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 180 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 181 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 182 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 183 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 184 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 185 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 186 /**
<> 144:ef7eb2e8f9f7 187 * @}
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /** @addtogroup SPI_Exported_Functions SPI Exported Functions
<> 144:ef7eb2e8f9f7 193 * @{
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 197 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 198 *
<> 144:ef7eb2e8f9f7 199 @verbatim
<> 144:ef7eb2e8f9f7 200 ===============================================================================
<> 144:ef7eb2e8f9f7 201 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 202 ===============================================================================
<> 144:ef7eb2e8f9f7 203 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 204 de-initialiaze the SPIx peripheral:
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 (+) User must implement HAL_SPI_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 207 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 (+) Call the function HAL_SPI_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 210 the selected configuration:
<> 144:ef7eb2e8f9f7 211 (++) Mode
<> 144:ef7eb2e8f9f7 212 (++) Direction
<> 144:ef7eb2e8f9f7 213 (++) Data Size
<> 144:ef7eb2e8f9f7 214 (++) Clock Polarity and Phase
<> 144:ef7eb2e8f9f7 215 (++) NSS Management
<> 144:ef7eb2e8f9f7 216 (++) BaudRate Prescaler
<> 144:ef7eb2e8f9f7 217 (++) FirstBit
<> 144:ef7eb2e8f9f7 218 (++) TIMode
<> 144:ef7eb2e8f9f7 219 (++) CRC Calculation
<> 144:ef7eb2e8f9f7 220 (++) CRC Polynomial if CRC enabled
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 223 of the selected SPIx periperal.
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 @endverbatim
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /**
<> 144:ef7eb2e8f9f7 230 * @brief Initializes the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 231 * in the SPI_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 232 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 233 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 234 * @retval HAL status
<> 144:ef7eb2e8f9f7 235 */
<> 144:ef7eb2e8f9f7 236 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 239 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Check the parameters */
<> 144:ef7eb2e8f9f7 245 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 246 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 247 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 248 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 249 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 144:ef7eb2e8f9f7 250 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 144:ef7eb2e8f9f7 251 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 252 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 253 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 254 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 255 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 144:ef7eb2e8f9f7 256 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 if(hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 261 hspi->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 264 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Disble the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 270 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 273 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
<> 144:ef7eb2e8f9f7 274 Communication speed, First bit and CRC calculation state */
<> 144:ef7eb2e8f9f7 275 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
<> 144:ef7eb2e8f9f7 276 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 144:ef7eb2e8f9f7 277 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Configure : NSS management */
<> 144:ef7eb2e8f9f7 280 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 283 /* Configure : CRC Polynomial */
<> 144:ef7eb2e8f9f7 284 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
<> 144:ef7eb2e8f9f7 287 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 144:ef7eb2e8f9f7 288 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 144:ef7eb2e8f9f7 289 #endif
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 292 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 return HAL_OK;
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @brief DeInitializes the SPI peripheral
<> 144:ef7eb2e8f9f7 299 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 300 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 301 * @retval HAL status
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 306 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Disable the SPI Peripheral Clock */
<> 144:ef7eb2e8f9f7 314 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 317 HAL_SPI_MspDeInit(hspi);
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 320 hspi->State = HAL_SPI_STATE_RESET;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Release Lock */
<> 144:ef7eb2e8f9f7 323 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 return HAL_OK;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @brief SPI MSP Init
<> 144:ef7eb2e8f9f7 330 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 331 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 332 * @retval None
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 337 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 340 the HAL_SPI_MspInit could be implenetd in the user file
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief SPI MSP DeInit
<> 144:ef7eb2e8f9f7 346 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 347 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 348 * @retval None
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 351 {
<> 144:ef7eb2e8f9f7 352 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 353 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 356 the HAL_SPI_MspDeInit could be implenetd in the user file
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @}
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /** @addtogroup SPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 365 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 366 *
<> 144:ef7eb2e8f9f7 367 @verbatim
<> 144:ef7eb2e8f9f7 368 ==============================================================================
<> 144:ef7eb2e8f9f7 369 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 370 ===============================================================================
<> 144:ef7eb2e8f9f7 371 This subsection provides a set of functions allowing to manage the SPI
<> 144:ef7eb2e8f9f7 372 data transfers.
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 [..] The SPI supports master and slave mode :
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 377 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 378 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 379 after finishing transfer.
<> 144:ef7eb2e8f9f7 380 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 381 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 382 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 383 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 384 using DMA mode.
<> 144:ef7eb2e8f9f7 385 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 386 will be executed respectivelly at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 387 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 (#) Blocking mode APIs are :
<> 144:ef7eb2e8f9f7 390 (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 391 (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 392 (++) HAL_SPI_TransmitReceive() in full duplex mode
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 (#) Non Blocking mode API's with Interrupt are :
<> 144:ef7eb2e8f9f7 395 (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 396 (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 397 (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
<> 144:ef7eb2e8f9f7 398 (++) HAL_SPI_IRQHandler()
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 (#) Non Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 401 (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 402 (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
<> 144:ef7eb2e8f9f7 403 (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 406 (++) HAL_SPI_TxCpltCallback()
<> 144:ef7eb2e8f9f7 407 (++) HAL_SPI_RxCpltCallback()
<> 144:ef7eb2e8f9f7 408 (++) HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 409 (++) HAL_SPI_TxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 410 (++) HAL_SPI_RxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 411 (++) HAL_SPI_TxRxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 412 (++) HAL_SPI_ErrorCallback()
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 @endverbatim
<> 144:ef7eb2e8f9f7 415 * @{
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 420 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 421 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 422 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 423 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 424 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 425 * @retval HAL status
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /* Check the parameters */
<> 144:ef7eb2e8f9f7 438 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Process Locked */
<> 144:ef7eb2e8f9f7 441 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Configure communication */
<> 144:ef7eb2e8f9f7 444 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 445 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 hspi->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 448 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 449 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 452 hspi->TxISR = 0;
<> 144:ef7eb2e8f9f7 453 hspi->RxISR = 0;
<> 144:ef7eb2e8f9f7 454 hspi->pRxBuffPtr = NULL;
<> 144:ef7eb2e8f9f7 455 hspi->RxXferSize = 0;
<> 144:ef7eb2e8f9f7 456 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 459 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 467 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 471 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 474 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 478 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 483 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 while(hspi->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 489 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 494 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 497 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 503 else
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 508 hspi->pTxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 509 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 while(hspi->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 515 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 520 hspi->pTxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 521 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 524 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 531 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 534 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 538 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 541 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<> 144:ef7eb2e8f9f7 545 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 553 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 return HAL_OK;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 else
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 565 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 566 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 567 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 568 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 569 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 570 * @retval HAL status
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 __IO uint16_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Process Locked */
<> 144:ef7eb2e8f9f7 584 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Configure communication */
<> 144:ef7eb2e8f9f7 587 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 588 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 hspi->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 591 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 592 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 595 hspi->RxISR = 0;
<> 144:ef7eb2e8f9f7 596 hspi->TxISR = 0;
<> 144:ef7eb2e8f9f7 597 hspi->pTxBuffPtr = NULL;
<> 144:ef7eb2e8f9f7 598 hspi->TxXferSize = 0;
<> 144:ef7eb2e8f9f7 599 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 602 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 608 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 611 }
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 616 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 144:ef7eb2e8f9f7 619 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 623 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 626 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 630 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 while(hspi->RxXferCount > 1)
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 635 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 641 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 /* Enable CRC Reception */
<> 144:ef7eb2e8f9f7 644 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649 /* Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 650 else
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 while(hspi->RxXferCount > 1)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 /* Wait until RXNE flag is set to read data */
<> 144:ef7eb2e8f9f7 655 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 661 hspi->pRxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 662 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 /* Enable CRC Reception */
<> 144:ef7eb2e8f9f7 665 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 672 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Receive last data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 678 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682 /* Receive last data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 683 else
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 686 hspi->pRxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* If CRC computation is enabled */
<> 144:ef7eb2e8f9f7 691 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 692 {
<> 144:ef7eb2e8f9f7 693 /* Wait until RXNE flag is set: CRC Received */
<> 144:ef7eb2e8f9f7 694 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 697 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Read CRC to clear RXNE flag */
<> 144:ef7eb2e8f9f7 701 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 702 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 706 {
<> 144:ef7eb2e8f9f7 707 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 708 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 714 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 719 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 722 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 728 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 return HAL_OK;
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732 else
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @brief Transmit and Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 740 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 741 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 742 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 743 * @param pRxData: pointer to reception data buffer to be
<> 144:ef7eb2e8f9f7 744 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 745 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 746 * @retval HAL status
<> 144:ef7eb2e8f9f7 747 */
<> 144:ef7eb2e8f9f7 748 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 __IO uint16_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX))
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Check the parameters */
<> 144:ef7eb2e8f9f7 760 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Process Locked */
<> 144:ef7eb2e8f9f7 763 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 766 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Configure communication */
<> 144:ef7eb2e8f9f7 772 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 hspi->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 775 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 776 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 hspi->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 779 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 780 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 783 hspi->RxISR = 0;
<> 144:ef7eb2e8f9f7 784 hspi->TxISR = 0;
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 787 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 793 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 796 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Transmit and Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 800 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 805 hspi->pTxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 806 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 811 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 817 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 823 hspi->pRxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 824 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 else
<> 144:ef7eb2e8f9f7 827 {
<> 144:ef7eb2e8f9f7 828 while(hspi->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 831 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 837 hspi->pTxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 838 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 841 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 847 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 853 hspi->pRxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 854 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856 /* Receive the last byte */
<> 144:ef7eb2e8f9f7 857 if(hspi->Init.Mode == SPI_MODE_SLAVE)
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 860 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 866 hspi->pRxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 867 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871 /* Transmit and Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 872 else
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 877 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 878 }
<> 144:ef7eb2e8f9f7 879 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 882 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 888 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 (*hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 894 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896 else
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 while(hspi->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 899 {
<> 144:ef7eb2e8f9f7 900 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 901 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 907 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 910 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 916 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 922 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924 if(hspi->Init.Mode == SPI_MODE_SLAVE)
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 927 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 928 {
<> 144:ef7eb2e8f9f7 929 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 930 }
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 933 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Read CRC from DR to close CRC calculation process */
<> 144:ef7eb2e8f9f7 939 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 942 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 945 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947 /* Read CRC */
<> 144:ef7eb2e8f9f7 948 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 949 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 953 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 956 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 962 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<> 144:ef7eb2e8f9f7 963 {
<> 144:ef7eb2e8f9f7 964 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 969 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 972 }
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 975 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 return HAL_OK;
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979 else
<> 144:ef7eb2e8f9f7 980 {
<> 144:ef7eb2e8f9f7 981 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 982 }
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /**
<> 144:ef7eb2e8f9f7 986 * @brief Transmit an amount of data in no-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 987 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 988 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 989 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 990 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 991 * @retval HAL status
<> 144:ef7eb2e8f9f7 992 */
<> 144:ef7eb2e8f9f7 993 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 996 {
<> 144:ef7eb2e8f9f7 997 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1003 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /* Process Locked */
<> 144:ef7eb2e8f9f7 1006 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Configure communication */
<> 144:ef7eb2e8f9f7 1009 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1010 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 hspi->TxISR = &SPI_TxISR;
<> 144:ef7eb2e8f9f7 1013 hspi->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1014 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1015 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1018 hspi->RxISR = 0;
<> 144:ef7eb2e8f9f7 1019 hspi->pRxBuffPtr = NULL;
<> 144:ef7eb2e8f9f7 1020 hspi->RxXferSize = 0;
<> 144:ef7eb2e8f9f7 1021 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1024 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1027 }
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1030 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 1036 {
<> 144:ef7eb2e8f9f7 1037 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
<> 144:ef7eb2e8f9f7 1038 }
<> 144:ef7eb2e8f9f7 1039 else
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1042 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1045 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1048 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1051 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1052 }
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 return HAL_OK;
<> 144:ef7eb2e8f9f7 1055 }
<> 144:ef7eb2e8f9f7 1056 else
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060 }
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /**
<> 144:ef7eb2e8f9f7 1063 * @brief Receive an amount of data in no-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1064 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1065 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1066 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1067 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1068 * @retval HAL status
<> 144:ef7eb2e8f9f7 1069 */
<> 144:ef7eb2e8f9f7 1070 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1075 {
<> 144:ef7eb2e8f9f7 1076 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1077 }
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /* Process Locked */
<> 144:ef7eb2e8f9f7 1080 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* Configure communication */
<> 144:ef7eb2e8f9f7 1083 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1084 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 hspi->RxISR = &SPI_RxISR;
<> 144:ef7eb2e8f9f7 1087 hspi->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1088 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1089 hspi->RxXferCount = Size ;
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1092 hspi->TxISR = 0;
<> 144:ef7eb2e8f9f7 1093 hspi->pTxBuffPtr = NULL;
<> 144:ef7eb2e8f9f7 1094 hspi->TxXferSize = 0;
<> 144:ef7eb2e8f9f7 1095 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1098 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1099 {
<> 144:ef7eb2e8f9f7 1100 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1101 }
<> 144:ef7eb2e8f9f7 1102 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1105 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 144:ef7eb2e8f9f7 1108 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1112 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1115 }
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1118 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1121 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /* Note : The SPI must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1124 to avoid the risk of SPI interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1125 process unlock */
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1128 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1131 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1132 }
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 return HAL_OK;
<> 144:ef7eb2e8f9f7 1135 }
<> 144:ef7eb2e8f9f7 1136 else
<> 144:ef7eb2e8f9f7 1137 {
<> 144:ef7eb2e8f9f7 1138 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140 }
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /**
<> 144:ef7eb2e8f9f7 1143 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1144 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1145 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1146 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1147 * @param pRxData: pointer to reception data buffer to be
<> 144:ef7eb2e8f9f7 1148 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1149 * @retval HAL status
<> 144:ef7eb2e8f9f7 1150 */
<> 144:ef7eb2e8f9f7 1151 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1152 {
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 if((hspi->State == HAL_SPI_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1155 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<> 144:ef7eb2e8f9f7 1156 {
<> 144:ef7eb2e8f9f7 1157 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 1158 {
<> 144:ef7eb2e8f9f7 1159 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1160 }
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1163 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* Process locked */
<> 144:ef7eb2e8f9f7 1166 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 1169 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1170 {
<> 144:ef7eb2e8f9f7 1171 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Configure communication */
<> 144:ef7eb2e8f9f7 1175 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 hspi->TxISR = &SPI_TxISR;
<> 144:ef7eb2e8f9f7 1178 hspi->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 1179 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1180 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 hspi->RxISR = &SPI_2LinesRxISR;
<> 144:ef7eb2e8f9f7 1183 hspi->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 1184 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1185 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1188 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* Enable TXE, RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1194 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1197 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1200 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1201 {
<> 144:ef7eb2e8f9f7 1202 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1203 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1204 }
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 return HAL_OK;
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208 else
<> 144:ef7eb2e8f9f7 1209 {
<> 144:ef7eb2e8f9f7 1210 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1211 }
<> 144:ef7eb2e8f9f7 1212 }
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 /**
<> 144:ef7eb2e8f9f7 1215 * @brief Transmit an amount of data in no-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1216 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1217 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1218 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1219 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1220 * @retval HAL status
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1223 {
<> 144:ef7eb2e8f9f7 1224 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1225 {
<> 144:ef7eb2e8f9f7 1226 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1227 {
<> 144:ef7eb2e8f9f7 1228 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1229 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1230 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1231 }
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1234 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /* Process Locked */
<> 144:ef7eb2e8f9f7 1237 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /* Configure communication */
<> 144:ef7eb2e8f9f7 1240 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1241 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 hspi->pTxBuffPtr = (uint8_t*)pData;
<> 144:ef7eb2e8f9f7 1244 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1245 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1246
<> 144:ef7eb2e8f9f7 1247 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1248 hspi->TxISR = 0;
<> 144:ef7eb2e8f9f7 1249 hspi->RxISR = 0;
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 hspi->pRxBuffPtr = NULL;
<> 144:ef7eb2e8f9f7 1252 hspi->RxXferSize = 0;
<> 144:ef7eb2e8f9f7 1253 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1256 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1257 {
<> 144:ef7eb2e8f9f7 1258 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1262 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1263 {
<> 144:ef7eb2e8f9f7 1264 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 /* Set the SPI TxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1268 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /* Set the SPI TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1271 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1274 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Reset content of SPI RxDMA descriptor */
<> 144:ef7eb2e8f9f7 1277 hspi->hdmarx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1278 hspi->hdmarx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1279 hspi->hdmarx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 1282 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1285 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1288 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1291 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1292 {
<> 144:ef7eb2e8f9f7 1293 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1294 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1295 }
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 return HAL_OK;
<> 144:ef7eb2e8f9f7 1298 }
<> 144:ef7eb2e8f9f7 1299 else
<> 144:ef7eb2e8f9f7 1300 {
<> 144:ef7eb2e8f9f7 1301 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1302 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1303 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1304 }
<> 144:ef7eb2e8f9f7 1305 }
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /**
<> 144:ef7eb2e8f9f7 1308 * @brief Receive an amount of data in no-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1309 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1310 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1311 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1312 * @note When the CRC feature is enabled the pData Length must be Size + 1.
<> 144:ef7eb2e8f9f7 1313 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1314 * @retval HAL status
<> 144:ef7eb2e8f9f7 1315 */
<> 144:ef7eb2e8f9f7 1316 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 if(hspi->State == HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1319 {
<> 144:ef7eb2e8f9f7 1320 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1321 {
<> 144:ef7eb2e8f9f7 1322 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1323 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1324 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1325 }
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Process Locked */
<> 144:ef7eb2e8f9f7 1328 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /* Configure communication */
<> 144:ef7eb2e8f9f7 1331 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1332 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 hspi->pRxBuffPtr = (uint8_t*)pData;
<> 144:ef7eb2e8f9f7 1335 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1336 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1337
<> 144:ef7eb2e8f9f7 1338 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1339 hspi->RxISR = 0;
<> 144:ef7eb2e8f9f7 1340 hspi->TxISR = 0;
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 hspi->pTxBuffPtr = NULL;
<> 144:ef7eb2e8f9f7 1343 hspi->TxXferSize = 0;
<> 144:ef7eb2e8f9f7 1344 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1347 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1350 }
<> 144:ef7eb2e8f9f7 1351 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 1352 {
<> 144:ef7eb2e8f9f7 1353 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1354 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 144:ef7eb2e8f9f7 1357 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<> 144:ef7eb2e8f9f7 1358 }
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1361 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1362 {
<> 144:ef7eb2e8f9f7 1363 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1364 }
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 /* Set the SPI RxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1367 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Set the SPI Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1370 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1373 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /* Reset content of SPI TxDMA descriptor */
<> 144:ef7eb2e8f9f7 1376 hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1377 hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1378 hspi->hdmatx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 1381 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1384 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1387 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1390 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1391 {
<> 144:ef7eb2e8f9f7 1392 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1393 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1394 }
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 return HAL_OK;
<> 144:ef7eb2e8f9f7 1397 }
<> 144:ef7eb2e8f9f7 1398 else
<> 144:ef7eb2e8f9f7 1399 {
<> 144:ef7eb2e8f9f7 1400 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1401 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1402 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1403 }
<> 144:ef7eb2e8f9f7 1404 }
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /**
<> 144:ef7eb2e8f9f7 1407 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1408 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1409 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1410 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1411 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1412 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
<> 144:ef7eb2e8f9f7 1413 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1414 * @retval HAL status
<> 144:ef7eb2e8f9f7 1415 */
<> 144:ef7eb2e8f9f7 1416 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1417 {
<> 144:ef7eb2e8f9f7 1418 if((hspi->State == HAL_SPI_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1419 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<> 144:ef7eb2e8f9f7 1420 {
<> 144:ef7eb2e8f9f7 1421 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 1422 {
<> 144:ef7eb2e8f9f7 1423 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1424 }
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1427 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 /* Process locked */
<> 144:ef7eb2e8f9f7 1430 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 1433 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1434 {
<> 144:ef7eb2e8f9f7 1435 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1436 }
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 /* Configure communication */
<> 144:ef7eb2e8f9f7 1439 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 hspi->pTxBuffPtr = (uint8_t*)pTxData;
<> 144:ef7eb2e8f9f7 1442 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1443 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 hspi->pRxBuffPtr = (uint8_t*)pRxData;
<> 144:ef7eb2e8f9f7 1446 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1447 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1450 hspi->RxISR = 0;
<> 144:ef7eb2e8f9f7 1451 hspi->TxISR = 0;
<> 144:ef7eb2e8f9f7 1452
<> 144:ef7eb2e8f9f7 1453 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1454 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1455 {
<> 144:ef7eb2e8f9f7 1456 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1457 }
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1460 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1461 {
<> 144:ef7eb2e8f9f7 1462 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1463 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1466 }
<> 144:ef7eb2e8f9f7 1467 else
<> 144:ef7eb2e8f9f7 1468 {
<> 144:ef7eb2e8f9f7 1469 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1470 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1473 }
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1476 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 1479 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1482 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<> 144:ef7eb2e8f9f7 1485 is performed in DMA reception complete callback */
<> 144:ef7eb2e8f9f7 1486 hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1487 hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1490 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 1493 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1496 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1497 {
<> 144:ef7eb2e8f9f7 1498 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1499 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1500 }
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1503 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1506 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 return HAL_OK;
<> 144:ef7eb2e8f9f7 1509 }
<> 144:ef7eb2e8f9f7 1510 else
<> 144:ef7eb2e8f9f7 1511 {
<> 144:ef7eb2e8f9f7 1512 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1513 }
<> 144:ef7eb2e8f9f7 1514 }
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /**
<> 144:ef7eb2e8f9f7 1518 * @brief Pauses the DMA Transfer.
<> 144:ef7eb2e8f9f7 1519 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1520 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1521 * @retval HAL status
<> 144:ef7eb2e8f9f7 1522 */
<> 144:ef7eb2e8f9f7 1523 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1524 {
<> 144:ef7eb2e8f9f7 1525 /* Process Locked */
<> 144:ef7eb2e8f9f7 1526 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1529 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1530 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1533 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 return HAL_OK;
<> 144:ef7eb2e8f9f7 1536 }
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 /**
<> 144:ef7eb2e8f9f7 1539 * @brief Resumes the DMA Transfer.
<> 144:ef7eb2e8f9f7 1540 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1541 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1542 * @retval HAL status
<> 144:ef7eb2e8f9f7 1543 */
<> 144:ef7eb2e8f9f7 1544 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 /* Process Locked */
<> 144:ef7eb2e8f9f7 1547 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 /* Enable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1550 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1551 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1554 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 return HAL_OK;
<> 144:ef7eb2e8f9f7 1557 }
<> 144:ef7eb2e8f9f7 1558
<> 144:ef7eb2e8f9f7 1559 /**
<> 144:ef7eb2e8f9f7 1560 * @brief Stops the DMA Transfer.
<> 144:ef7eb2e8f9f7 1561 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1562 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1563 * @retval HAL status
<> 144:ef7eb2e8f9f7 1564 */
<> 144:ef7eb2e8f9f7 1565 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1566 {
<> 144:ef7eb2e8f9f7 1567 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 1568 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<> 144:ef7eb2e8f9f7 1569 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 1570 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 1571 */
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 /* Abort the SPI DMA tx Channel */
<> 144:ef7eb2e8f9f7 1574 if(hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1575 {
<> 144:ef7eb2e8f9f7 1576 HAL_DMA_Abort(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 1577 }
<> 144:ef7eb2e8f9f7 1578 /* Abort the SPI DMA rx Channel */
<> 144:ef7eb2e8f9f7 1579 if(hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1580 {
<> 144:ef7eb2e8f9f7 1581 HAL_DMA_Abort(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 1582 }
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1585 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1586 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 return HAL_OK;
<> 144:ef7eb2e8f9f7 1591 }
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 /**
<> 144:ef7eb2e8f9f7 1594 * @brief This function handles SPI interrupt request.
<> 144:ef7eb2e8f9f7 1595 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1596 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1597 * @retval HAL status
<> 144:ef7eb2e8f9f7 1598 */
<> 144:ef7eb2e8f9f7 1599 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1600 {
<> 144:ef7eb2e8f9f7 1601 /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
<> 144:ef7eb2e8f9f7 1602 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
<> 144:ef7eb2e8f9f7 1603 {
<> 144:ef7eb2e8f9f7 1604 hspi->RxISR(hspi);
<> 144:ef7eb2e8f9f7 1605 return;
<> 144:ef7eb2e8f9f7 1606 }
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 /* SPI in mode Tramitter ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1609 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1610 {
<> 144:ef7eb2e8f9f7 1611 hspi->TxISR(hspi);
<> 144:ef7eb2e8f9f7 1612 return;
<> 144:ef7eb2e8f9f7 1613 }
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
<> 144:ef7eb2e8f9f7 1616 {
<> 144:ef7eb2e8f9f7 1617 /* SPI CRC error interrupt occurred ---------------------------------------*/
<> 144:ef7eb2e8f9f7 1618 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 1619 {
<> 144:ef7eb2e8f9f7 1620 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1621 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1622 }
<> 144:ef7eb2e8f9f7 1623 /* SPI Mode Fault error interrupt occurred --------------------------------*/
<> 144:ef7eb2e8f9f7 1624 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
<> 144:ef7eb2e8f9f7 1625 {
<> 144:ef7eb2e8f9f7 1626 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<> 144:ef7eb2e8f9f7 1627 __HAL_SPI_CLEAR_MODFFLAG(hspi);
<> 144:ef7eb2e8f9f7 1628 }
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 /* SPI Overrun error interrupt occurred -----------------------------------*/
<> 144:ef7eb2e8f9f7 1631 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
<> 144:ef7eb2e8f9f7 1632 {
<> 144:ef7eb2e8f9f7 1633 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1634 {
<> 144:ef7eb2e8f9f7 1635 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1636 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1637 }
<> 144:ef7eb2e8f9f7 1638 }
<> 144:ef7eb2e8f9f7 1639
<> 144:ef7eb2e8f9f7 1640 /* SPI Frame error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 1641 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
<> 144:ef7eb2e8f9f7 1642 {
<> 144:ef7eb2e8f9f7 1643 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<> 144:ef7eb2e8f9f7 1644 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 144:ef7eb2e8f9f7 1645 }
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1648 if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1649 {
<> 144:ef7eb2e8f9f7 1650 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 1651 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1652 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1653 }
<> 144:ef7eb2e8f9f7 1654 }
<> 144:ef7eb2e8f9f7 1655 }
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /**
<> 144:ef7eb2e8f9f7 1658 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1659 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1660 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1661 * @retval None
<> 144:ef7eb2e8f9f7 1662 */
<> 144:ef7eb2e8f9f7 1663 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1664 {
<> 144:ef7eb2e8f9f7 1665 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1666 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1667
<> 144:ef7eb2e8f9f7 1668 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1669 the HAL_SPI_TxCpltCallback could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1670 */
<> 144:ef7eb2e8f9f7 1671 }
<> 144:ef7eb2e8f9f7 1672
<> 144:ef7eb2e8f9f7 1673 /**
<> 144:ef7eb2e8f9f7 1674 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1675 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1676 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1677 * @retval None
<> 144:ef7eb2e8f9f7 1678 */
<> 144:ef7eb2e8f9f7 1679 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1682 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1685 the HAL_SPI_RxCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1686 */
<> 144:ef7eb2e8f9f7 1687 }
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /**
<> 144:ef7eb2e8f9f7 1690 * @brief Tx and Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1691 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1692 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1693 * @retval None
<> 144:ef7eb2e8f9f7 1694 */
<> 144:ef7eb2e8f9f7 1695 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1696 {
<> 144:ef7eb2e8f9f7 1697 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1698 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1701 the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1702 */
<> 144:ef7eb2e8f9f7 1703 }
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 /**
<> 144:ef7eb2e8f9f7 1706 * @brief Tx Half Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1707 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1708 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1709 * @retval None
<> 144:ef7eb2e8f9f7 1710 */
<> 144:ef7eb2e8f9f7 1711 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1712 {
<> 144:ef7eb2e8f9f7 1713 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1714 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1717 the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1718 */
<> 144:ef7eb2e8f9f7 1719 }
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /**
<> 144:ef7eb2e8f9f7 1722 * @brief Rx Half Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1723 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1724 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1725 * @retval None
<> 144:ef7eb2e8f9f7 1726 */
<> 144:ef7eb2e8f9f7 1727 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1728 {
<> 144:ef7eb2e8f9f7 1729 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1730 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1733 the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1734 */
<> 144:ef7eb2e8f9f7 1735 }
<> 144:ef7eb2e8f9f7 1736
<> 144:ef7eb2e8f9f7 1737 /**
<> 144:ef7eb2e8f9f7 1738 * @brief Tx and Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1739 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1740 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1741 * @retval None
<> 144:ef7eb2e8f9f7 1742 */
<> 144:ef7eb2e8f9f7 1743 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1744 {
<> 144:ef7eb2e8f9f7 1745 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1746 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1749 the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
<> 144:ef7eb2e8f9f7 1750 */
<> 144:ef7eb2e8f9f7 1751 }
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 /**
<> 144:ef7eb2e8f9f7 1754 * @brief SPI error callbacks
<> 144:ef7eb2e8f9f7 1755 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1756 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1757 * @retval None
<> 144:ef7eb2e8f9f7 1758 */
<> 144:ef7eb2e8f9f7 1759 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1760 {
<> 144:ef7eb2e8f9f7 1761 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1762 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* NOTE : - This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1765 the HAL_SPI_ErrorCallback() could be implenetd in the user file.
<> 144:ef7eb2e8f9f7 1766 - The ErrorCode parameter in the hspi handle is updated by the SPI processes
<> 144:ef7eb2e8f9f7 1767 and user can use HAL_SPI_GetError() API to check the latest error occurred.
<> 144:ef7eb2e8f9f7 1768 */
<> 144:ef7eb2e8f9f7 1769 }
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 /**
<> 144:ef7eb2e8f9f7 1772 * @}
<> 144:ef7eb2e8f9f7 1773 */
<> 144:ef7eb2e8f9f7 1774
<> 144:ef7eb2e8f9f7 1775 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1776 * @brief SPI control functions
<> 144:ef7eb2e8f9f7 1777 *
<> 144:ef7eb2e8f9f7 1778 @verbatim
<> 144:ef7eb2e8f9f7 1779 ===============================================================================
<> 144:ef7eb2e8f9f7 1780 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1781 ===============================================================================
<> 144:ef7eb2e8f9f7 1782 [..]
<> 144:ef7eb2e8f9f7 1783 This subsection provides a set of functions allowing to control the SPI.
<> 144:ef7eb2e8f9f7 1784 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<> 144:ef7eb2e8f9f7 1785 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<> 144:ef7eb2e8f9f7 1786 @endverbatim
<> 144:ef7eb2e8f9f7 1787 * @{
<> 144:ef7eb2e8f9f7 1788 */
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /**
<> 144:ef7eb2e8f9f7 1791 * @brief Return the SPI state
<> 144:ef7eb2e8f9f7 1792 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1793 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1794 * @retval SPI state
<> 144:ef7eb2e8f9f7 1795 */
<> 144:ef7eb2e8f9f7 1796 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1797 {
<> 144:ef7eb2e8f9f7 1798 return hspi->State;
<> 144:ef7eb2e8f9f7 1799 }
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 /**
<> 144:ef7eb2e8f9f7 1802 * @brief Return the SPI error code
<> 144:ef7eb2e8f9f7 1803 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1804 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1805 * @retval SPI Error Code
<> 144:ef7eb2e8f9f7 1806 */
<> 144:ef7eb2e8f9f7 1807 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1808 {
<> 144:ef7eb2e8f9f7 1809 return hspi->ErrorCode;
<> 144:ef7eb2e8f9f7 1810 }
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 /**
<> 144:ef7eb2e8f9f7 1813 * @}
<> 144:ef7eb2e8f9f7 1814 */
<> 144:ef7eb2e8f9f7 1815
<> 144:ef7eb2e8f9f7 1816 /**
<> 144:ef7eb2e8f9f7 1817 * @}
<> 144:ef7eb2e8f9f7 1818 */
<> 144:ef7eb2e8f9f7 1819
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 /** @addtogroup SPI_Private
<> 144:ef7eb2e8f9f7 1823 * @{
<> 144:ef7eb2e8f9f7 1824 */
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826
<> 144:ef7eb2e8f9f7 1827 /**
<> 144:ef7eb2e8f9f7 1828 * @brief Interrupt Handler to close Tx transfer
<> 144:ef7eb2e8f9f7 1829 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1830 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1831 * @retval void
<> 144:ef7eb2e8f9f7 1832 */
<> 144:ef7eb2e8f9f7 1833 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1834 {
<> 144:ef7eb2e8f9f7 1835 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 1836 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1837 {
<> 144:ef7eb2e8f9f7 1838 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1839 }
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 1842 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 /* Disable ERR interrupt if Receive process is finished */
<> 144:ef7eb2e8f9f7 1845 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
<> 144:ef7eb2e8f9f7 1846 {
<> 144:ef7eb2e8f9f7 1847 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1848
<> 144:ef7eb2e8f9f7 1849 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 1850 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1851 {
<> 144:ef7eb2e8f9f7 1852 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1853 }
<> 144:ef7eb2e8f9f7 1854
<> 144:ef7eb2e8f9f7 1855 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<> 144:ef7eb2e8f9f7 1856 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 1857 {
<> 144:ef7eb2e8f9f7 1858 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 1862 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1863 {
<> 144:ef7eb2e8f9f7 1864 /* Check if we are in Tx or in Rx/Tx Mode */
<> 144:ef7eb2e8f9f7 1865 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1866 {
<> 144:ef7eb2e8f9f7 1867 /* Set state to READY before run the Callback Complete */
<> 144:ef7eb2e8f9f7 1868 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1869 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1870 }
<> 144:ef7eb2e8f9f7 1871 else
<> 144:ef7eb2e8f9f7 1872 {
<> 144:ef7eb2e8f9f7 1873 /* Set state to READY before run the Callback Complete */
<> 144:ef7eb2e8f9f7 1874 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1875 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1876 }
<> 144:ef7eb2e8f9f7 1877 }
<> 144:ef7eb2e8f9f7 1878 else
<> 144:ef7eb2e8f9f7 1879 {
<> 144:ef7eb2e8f9f7 1880 /* Set state to READY before run the Callback Complete */
<> 144:ef7eb2e8f9f7 1881 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1882 /* Call Error call back in case of Error */
<> 144:ef7eb2e8f9f7 1883 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1884 }
<> 144:ef7eb2e8f9f7 1885 }
<> 144:ef7eb2e8f9f7 1886 }
<> 144:ef7eb2e8f9f7 1887
<> 144:ef7eb2e8f9f7 1888 /**
<> 144:ef7eb2e8f9f7 1889 * @brief Interrupt Handler to transmit amount of data in no-blocking mode
<> 144:ef7eb2e8f9f7 1890 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1891 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1892 * @retval void
<> 144:ef7eb2e8f9f7 1893 */
<> 144:ef7eb2e8f9f7 1894 static void SPI_TxISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1895 {
<> 144:ef7eb2e8f9f7 1896 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 1897 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1898 {
<> 144:ef7eb2e8f9f7 1899 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1900 }
<> 144:ef7eb2e8f9f7 1901 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 1902 else
<> 144:ef7eb2e8f9f7 1903 {
<> 144:ef7eb2e8f9f7 1904 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 1905 hspi->pTxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 1906 }
<> 144:ef7eb2e8f9f7 1907 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 1908
<> 144:ef7eb2e8f9f7 1909 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1910 {
<> 144:ef7eb2e8f9f7 1911 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1912 {
<> 144:ef7eb2e8f9f7 1913 /* calculate and transfer CRC on Tx line */
<> 144:ef7eb2e8f9f7 1914 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1915 }
<> 144:ef7eb2e8f9f7 1916 SPI_TxCloseIRQHandler(hspi);
<> 144:ef7eb2e8f9f7 1917 }
<> 144:ef7eb2e8f9f7 1918 }
<> 144:ef7eb2e8f9f7 1919
<> 144:ef7eb2e8f9f7 1920 /**
<> 144:ef7eb2e8f9f7 1921 * @brief Interrupt Handler to close Rx transfer
<> 144:ef7eb2e8f9f7 1922 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1923 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1924 * @retval void
<> 144:ef7eb2e8f9f7 1925 */
<> 144:ef7eb2e8f9f7 1926 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1927 {
<> 144:ef7eb2e8f9f7 1928 __IO uint16_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1931 {
<> 144:ef7eb2e8f9f7 1932 /* Wait until RXNE flag is set to read CRC data */
<> 144:ef7eb2e8f9f7 1933 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1934 {
<> 144:ef7eb2e8f9f7 1935 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1936 }
<> 144:ef7eb2e8f9f7 1937
<> 144:ef7eb2e8f9f7 1938 /* Read CRC to reset RXNE flag */
<> 144:ef7eb2e8f9f7 1939 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1940 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 /* Wait until RXNE flag is reset */
<> 144:ef7eb2e8f9f7 1943 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 1944 {
<> 144:ef7eb2e8f9f7 1945 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 1946 }
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 1949 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 1950 {
<> 144:ef7eb2e8f9f7 1951 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1952
<> 144:ef7eb2e8f9f7 1953 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1954 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1955 }
<> 144:ef7eb2e8f9f7 1956 }
<> 144:ef7eb2e8f9f7 1957
<> 144:ef7eb2e8f9f7 1958 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 1959 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961 /* if Transmit process is finished */
<> 144:ef7eb2e8f9f7 1962 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
<> 144:ef7eb2e8f9f7 1963 {
<> 144:ef7eb2e8f9f7 1964 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1965 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 1968 {
<> 144:ef7eb2e8f9f7 1969 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 1970 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 1971 }
<> 144:ef7eb2e8f9f7 1972
<> 144:ef7eb2e8f9f7 1973 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 1974 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1975 {
<> 144:ef7eb2e8f9f7 1976 /* Check if we are in Rx or in Rx/Tx Mode */
<> 144:ef7eb2e8f9f7 1977 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1978 {
<> 144:ef7eb2e8f9f7 1979 /* Set state to READY before run the Callback Complete */
<> 144:ef7eb2e8f9f7 1980 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1981 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1982 }
<> 144:ef7eb2e8f9f7 1983 else
<> 144:ef7eb2e8f9f7 1984 {
<> 144:ef7eb2e8f9f7 1985 /* Set state to READY before run the Callback Complete */
<> 144:ef7eb2e8f9f7 1986 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1987 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1988 }
<> 144:ef7eb2e8f9f7 1989 }
<> 144:ef7eb2e8f9f7 1990 else
<> 144:ef7eb2e8f9f7 1991 {
<> 144:ef7eb2e8f9f7 1992 /* Set state to READY before run the Callback Complete */
<> 144:ef7eb2e8f9f7 1993 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1994 /* Call Error call back in case of Error */
<> 144:ef7eb2e8f9f7 1995 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1996 }
<> 144:ef7eb2e8f9f7 1997 }
<> 144:ef7eb2e8f9f7 1998 }
<> 144:ef7eb2e8f9f7 1999
<> 144:ef7eb2e8f9f7 2000 /**
<> 144:ef7eb2e8f9f7 2001 * @brief Interrupt Handler to receive amount of data in 2Lines mode
<> 144:ef7eb2e8f9f7 2002 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2003 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2004 * @retval void
<> 144:ef7eb2e8f9f7 2005 */
<> 144:ef7eb2e8f9f7 2006 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2007 {
<> 144:ef7eb2e8f9f7 2008 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 2009 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 2010 {
<> 144:ef7eb2e8f9f7 2011 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2012 }
<> 144:ef7eb2e8f9f7 2013 /* Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 2014 else
<> 144:ef7eb2e8f9f7 2015 {
<> 144:ef7eb2e8f9f7 2016 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2017 hspi->pRxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 2018 }
<> 144:ef7eb2e8f9f7 2019 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 2020
<> 144:ef7eb2e8f9f7 2021 if(hspi->RxXferCount==0)
<> 144:ef7eb2e8f9f7 2022 {
<> 144:ef7eb2e8f9f7 2023 SPI_RxCloseIRQHandler(hspi);
<> 144:ef7eb2e8f9f7 2024 }
<> 144:ef7eb2e8f9f7 2025 }
<> 144:ef7eb2e8f9f7 2026
<> 144:ef7eb2e8f9f7 2027 /**
<> 144:ef7eb2e8f9f7 2028 * @brief Interrupt Handler to receive amount of data in no-blocking mode
<> 144:ef7eb2e8f9f7 2029 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2030 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2031 * @retval void
<> 144:ef7eb2e8f9f7 2032 */
<> 144:ef7eb2e8f9f7 2033 static void SPI_RxISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2034 {
<> 144:ef7eb2e8f9f7 2035 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 2036 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 2037 {
<> 144:ef7eb2e8f9f7 2038 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2039 }
<> 144:ef7eb2e8f9f7 2040 /* Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 2041 else
<> 144:ef7eb2e8f9f7 2042 {
<> 144:ef7eb2e8f9f7 2043 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2044 hspi->pRxBuffPtr+=2;
<> 144:ef7eb2e8f9f7 2045 }
<> 144:ef7eb2e8f9f7 2046 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 2047
<> 144:ef7eb2e8f9f7 2048 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 2049 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 2050 {
<> 144:ef7eb2e8f9f7 2051 /* Set CRC Next to calculate CRC on Rx side */
<> 144:ef7eb2e8f9f7 2052 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 2053 }
<> 144:ef7eb2e8f9f7 2054
<> 144:ef7eb2e8f9f7 2055 if(hspi->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2056 {
<> 144:ef7eb2e8f9f7 2057 SPI_RxCloseIRQHandler(hspi);
<> 144:ef7eb2e8f9f7 2058 }
<> 144:ef7eb2e8f9f7 2059 }
<> 144:ef7eb2e8f9f7 2060
<> 144:ef7eb2e8f9f7 2061 /**
<> 144:ef7eb2e8f9f7 2062 * @brief DMA SPI transmit process complete callback
<> 144:ef7eb2e8f9f7 2063 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2064 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2065 * @retval None
<> 144:ef7eb2e8f9f7 2066 */
<> 144:ef7eb2e8f9f7 2067 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2068 {
<> 144:ef7eb2e8f9f7 2069 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2070
<> 144:ef7eb2e8f9f7 2071
<> 144:ef7eb2e8f9f7 2072 /* DMA Normal Mode */
<> 144:ef7eb2e8f9f7 2073 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 2074 {
<> 144:ef7eb2e8f9f7 2075 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 2076 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2077 {
<> 144:ef7eb2e8f9f7 2078 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2079 }
<> 144:ef7eb2e8f9f7 2080
<> 144:ef7eb2e8f9f7 2081 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 2082 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2083
<> 144:ef7eb2e8f9f7 2084 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 2085 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2086 {
<> 144:ef7eb2e8f9f7 2087 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2088 }
<> 144:ef7eb2e8f9f7 2089
<> 144:ef7eb2e8f9f7 2090 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 2091 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2092 }
<> 144:ef7eb2e8f9f7 2093
<> 144:ef7eb2e8f9f7 2094 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<> 144:ef7eb2e8f9f7 2095 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 2096 {
<> 144:ef7eb2e8f9f7 2097 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2098 }
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 2101 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2102 {
<> 144:ef7eb2e8f9f7 2103 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2104 }
<> 144:ef7eb2e8f9f7 2105 else
<> 144:ef7eb2e8f9f7 2106 {
<> 144:ef7eb2e8f9f7 2107 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2108 }
<> 144:ef7eb2e8f9f7 2109 }
<> 144:ef7eb2e8f9f7 2110
<> 144:ef7eb2e8f9f7 2111 /**
<> 144:ef7eb2e8f9f7 2112 * @brief DMA SPI receive process complete callback
<> 144:ef7eb2e8f9f7 2113 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2114 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2115 * @retval None
<> 144:ef7eb2e8f9f7 2116 */
<> 144:ef7eb2e8f9f7 2117 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2118 {
<> 144:ef7eb2e8f9f7 2119 __IO uint16_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 2120
<> 144:ef7eb2e8f9f7 2121 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2122
<> 144:ef7eb2e8f9f7 2123 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 2124 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 2125 {
<> 144:ef7eb2e8f9f7 2126 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 2127 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2128
<> 144:ef7eb2e8f9f7 2129 /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
<> 144:ef7eb2e8f9f7 2130 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2131
<> 144:ef7eb2e8f9f7 2132 /* CRC Calculation handling */
<> 144:ef7eb2e8f9f7 2133 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2134 {
<> 144:ef7eb2e8f9f7 2135 /* Wait until RXNE flag is set (CRC ready) */
<> 144:ef7eb2e8f9f7 2136 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2137 {
<> 144:ef7eb2e8f9f7 2138 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2139 }
<> 144:ef7eb2e8f9f7 2140
<> 144:ef7eb2e8f9f7 2141 /* Read CRC */
<> 144:ef7eb2e8f9f7 2142 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2143 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 /* Wait until RXNE flag is reset */
<> 144:ef7eb2e8f9f7 2146 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2147 {
<> 144:ef7eb2e8f9f7 2148 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2149 }
<> 144:ef7eb2e8f9f7 2150
<> 144:ef7eb2e8f9f7 2151 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 2152 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 2153 {
<> 144:ef7eb2e8f9f7 2154 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2155 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2156 }
<> 144:ef7eb2e8f9f7 2157 }
<> 144:ef7eb2e8f9f7 2158
<> 144:ef7eb2e8f9f7 2159 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 2160 {
<> 144:ef7eb2e8f9f7 2161 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2162 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2163 }
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 2166 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 2169 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2170 {
<> 144:ef7eb2e8f9f7 2171 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2172 }
<> 144:ef7eb2e8f9f7 2173 else
<> 144:ef7eb2e8f9f7 2174 {
<> 144:ef7eb2e8f9f7 2175 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2176 }
<> 144:ef7eb2e8f9f7 2177 }
<> 144:ef7eb2e8f9f7 2178 else
<> 144:ef7eb2e8f9f7 2179 {
<> 144:ef7eb2e8f9f7 2180 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2181 }
<> 144:ef7eb2e8f9f7 2182 }
<> 144:ef7eb2e8f9f7 2183
<> 144:ef7eb2e8f9f7 2184 /**
<> 144:ef7eb2e8f9f7 2185 * @brief DMA SPI transmit receive process complete callback
<> 144:ef7eb2e8f9f7 2186 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2187 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2188 * @retval None
<> 144:ef7eb2e8f9f7 2189 */
<> 144:ef7eb2e8f9f7 2190 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2191 {
<> 144:ef7eb2e8f9f7 2192 __IO uint16_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 2193
<> 144:ef7eb2e8f9f7 2194 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2195 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 2196 {
<> 144:ef7eb2e8f9f7 2197 /* CRC Calculation handling */
<> 144:ef7eb2e8f9f7 2198 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2199 {
<> 144:ef7eb2e8f9f7 2200 /* Check if CRC is done on going (RXNE flag set) */
<> 144:ef7eb2e8f9f7 2201 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
<> 144:ef7eb2e8f9f7 2202 {
<> 144:ef7eb2e8f9f7 2203 /* Wait until RXNE flag is set to send data */
<> 144:ef7eb2e8f9f7 2204 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2205 {
<> 144:ef7eb2e8f9f7 2206 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2207 }
<> 144:ef7eb2e8f9f7 2208 }
<> 144:ef7eb2e8f9f7 2209 /* Read CRC */
<> 144:ef7eb2e8f9f7 2210 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2211 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
<> 144:ef7eb2e8f9f7 2212
<> 144:ef7eb2e8f9f7 2213 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 2214 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 2215 {
<> 144:ef7eb2e8f9f7 2216 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2217 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2218 }
<> 144:ef7eb2e8f9f7 2219 }
<> 144:ef7eb2e8f9f7 2220
<> 144:ef7eb2e8f9f7 2221 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 2222 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2223 {
<> 144:ef7eb2e8f9f7 2224 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2225 }
<> 144:ef7eb2e8f9f7 2226
<> 144:ef7eb2e8f9f7 2227 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 2228 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2229
<> 144:ef7eb2e8f9f7 2230 /* Wait until Busy flag is reset before disabling SPI */
<> 144:ef7eb2e8f9f7 2231 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2232 {
<> 144:ef7eb2e8f9f7 2233 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2234 }
<> 144:ef7eb2e8f9f7 2235
<> 144:ef7eb2e8f9f7 2236 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 2237 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2238
<> 144:ef7eb2e8f9f7 2239 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 2240 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 2241
<> 144:ef7eb2e8f9f7 2242 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2243
<> 144:ef7eb2e8f9f7 2244 /* Check if Errors has been detected during transfer */
<> 144:ef7eb2e8f9f7 2245 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2246 {
<> 144:ef7eb2e8f9f7 2247 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2248 }
<> 144:ef7eb2e8f9f7 2249 else
<> 144:ef7eb2e8f9f7 2250 {
<> 144:ef7eb2e8f9f7 2251 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2252 }
<> 144:ef7eb2e8f9f7 2253 }
<> 144:ef7eb2e8f9f7 2254 else
<> 144:ef7eb2e8f9f7 2255 {
<> 144:ef7eb2e8f9f7 2256 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2257 }
<> 144:ef7eb2e8f9f7 2258 }
<> 144:ef7eb2e8f9f7 2259
<> 144:ef7eb2e8f9f7 2260 /**
<> 144:ef7eb2e8f9f7 2261 * @brief DMA SPI half transmit process complete callback
<> 144:ef7eb2e8f9f7 2262 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2263 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2264 * @retval None
<> 144:ef7eb2e8f9f7 2265 */
<> 144:ef7eb2e8f9f7 2266 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2267 {
<> 144:ef7eb2e8f9f7 2268 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2269
<> 144:ef7eb2e8f9f7 2270 HAL_SPI_TxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2271 }
<> 144:ef7eb2e8f9f7 2272
<> 144:ef7eb2e8f9f7 2273 /**
<> 144:ef7eb2e8f9f7 2274 * @brief DMA SPI half receive process complete callback
<> 144:ef7eb2e8f9f7 2275 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2276 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2277 * @retval None
<> 144:ef7eb2e8f9f7 2278 */
<> 144:ef7eb2e8f9f7 2279 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2280 {
<> 144:ef7eb2e8f9f7 2281 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2282
<> 144:ef7eb2e8f9f7 2283 HAL_SPI_RxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2284 }
<> 144:ef7eb2e8f9f7 2285
<> 144:ef7eb2e8f9f7 2286 /**
<> 144:ef7eb2e8f9f7 2287 * @brief DMA SPI Half transmit receive process complete callback
<> 144:ef7eb2e8f9f7 2288 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2289 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2290 * @retval None
<> 144:ef7eb2e8f9f7 2291 */
<> 144:ef7eb2e8f9f7 2292 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2293 {
<> 144:ef7eb2e8f9f7 2294 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2295
<> 144:ef7eb2e8f9f7 2296 HAL_SPI_TxRxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2297 }
<> 144:ef7eb2e8f9f7 2298
<> 144:ef7eb2e8f9f7 2299 /**
<> 144:ef7eb2e8f9f7 2300 * @brief DMA SPI communication error callback
<> 144:ef7eb2e8f9f7 2301 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2302 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2303 * @retval None
<> 144:ef7eb2e8f9f7 2304 */
<> 144:ef7eb2e8f9f7 2305 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2306 {
<> 144:ef7eb2e8f9f7 2307 SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2308 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 2309 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 2310 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2311 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2312 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2313 }
<> 144:ef7eb2e8f9f7 2314
<> 144:ef7eb2e8f9f7 2315 /**
<> 144:ef7eb2e8f9f7 2316 * @brief This function handles SPI Communication Timeout.
<> 144:ef7eb2e8f9f7 2317 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2318 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2319 * @param Flag: SPI flag to check
<> 144:ef7eb2e8f9f7 2320 * @param Status: Flag status to check: RESET or set
<> 144:ef7eb2e8f9f7 2321 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 2322 * @retval HAL status
<> 144:ef7eb2e8f9f7 2323 */
<> 144:ef7eb2e8f9f7 2324 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2325 {
<> 144:ef7eb2e8f9f7 2326 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 2327
<> 144:ef7eb2e8f9f7 2328 /* Get tick */
<> 144:ef7eb2e8f9f7 2329 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2330
<> 144:ef7eb2e8f9f7 2331 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 2332 if(Status == RESET)
<> 144:ef7eb2e8f9f7 2333 {
<> 144:ef7eb2e8f9f7 2334 while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
<> 144:ef7eb2e8f9f7 2335 {
<> 144:ef7eb2e8f9f7 2336 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2337 {
<> 144:ef7eb2e8f9f7 2338 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 2339 {
<> 144:ef7eb2e8f9f7 2340 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 2341 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 2342 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 2343
<> 144:ef7eb2e8f9f7 2344 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 2345 __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2346
<> 144:ef7eb2e8f9f7 2347 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2348 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2349
<> 144:ef7eb2e8f9f7 2350 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 2351 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2352 {
<> 144:ef7eb2e8f9f7 2353 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 2354 }
<> 144:ef7eb2e8f9f7 2355
<> 144:ef7eb2e8f9f7 2356 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2359 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2360
<> 144:ef7eb2e8f9f7 2361 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2362 }
<> 144:ef7eb2e8f9f7 2363 }
<> 144:ef7eb2e8f9f7 2364 }
<> 144:ef7eb2e8f9f7 2365 }
<> 144:ef7eb2e8f9f7 2366 else
<> 144:ef7eb2e8f9f7 2367 {
<> 144:ef7eb2e8f9f7 2368 while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
<> 144:ef7eb2e8f9f7 2369 {
<> 144:ef7eb2e8f9f7 2370 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2371 {
<> 144:ef7eb2e8f9f7 2372 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 2373 {
<> 144:ef7eb2e8f9f7 2374 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 2375 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 2376 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 2377
<> 144:ef7eb2e8f9f7 2378 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 2379 __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2380
<> 144:ef7eb2e8f9f7 2381 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2382 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2383
<> 144:ef7eb2e8f9f7 2384 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 2385 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2386 {
<> 144:ef7eb2e8f9f7 2387 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 2388 }
<> 144:ef7eb2e8f9f7 2389
<> 144:ef7eb2e8f9f7 2390 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2391
<> 144:ef7eb2e8f9f7 2392 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2393 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2394
<> 144:ef7eb2e8f9f7 2395 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2396 }
<> 144:ef7eb2e8f9f7 2397 }
<> 144:ef7eb2e8f9f7 2398 }
<> 144:ef7eb2e8f9f7 2399 }
<> 144:ef7eb2e8f9f7 2400 return HAL_OK;
<> 144:ef7eb2e8f9f7 2401 }
<> 144:ef7eb2e8f9f7 2402 /**
<> 144:ef7eb2e8f9f7 2403 * @}
<> 144:ef7eb2e8f9f7 2404 */
<> 144:ef7eb2e8f9f7 2405
<> 144:ef7eb2e8f9f7 2406 /**
<> 144:ef7eb2e8f9f7 2407 * @}
<> 144:ef7eb2e8f9f7 2408 */
<> 144:ef7eb2e8f9f7 2409
<> 144:ef7eb2e8f9f7 2410 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2411
<> 144:ef7eb2e8f9f7 2412 /**
<> 144:ef7eb2e8f9f7 2413 * @}
<> 144:ef7eb2e8f9f7 2414 */
<> 144:ef7eb2e8f9f7 2415
<> 144:ef7eb2e8f9f7 2416 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 2417