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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_dac_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Extended DAC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of DAC extension peripheral:
<> 144:ef7eb2e8f9f7 8 * + Extended features functions
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
<> 144:ef7eb2e8f9f7 17 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
<> 144:ef7eb2e8f9f7 18 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
<> 144:ef7eb2e8f9f7 19 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
<> 144:ef7eb2e8f9f7 20 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 @endverbatim
<> 144:ef7eb2e8f9f7 23 ******************************************************************************
<> 144:ef7eb2e8f9f7 24 * @attention
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 29 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 30 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 31 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 33 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 34 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 36 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 37 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 49 *
<> 144:ef7eb2e8f9f7 50 ******************************************************************************
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
<> 144:ef7eb2e8f9f7 55 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 59 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @addtogroup DACEx DACEx
<> 144:ef7eb2e8f9f7 64 * @brief DAC driver modules
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /** @addtogroup DACEx_Private
<> 144:ef7eb2e8f9f7 69 * @{
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 73 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 74 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 80 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 81 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 82 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 83 #endif
<> 144:ef7eb2e8f9f7 84 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 85 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 86 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @}
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /** @addtogroup DACEx_Exported_Functions
<> 144:ef7eb2e8f9f7 92 * @{
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @addtogroup DACEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 96 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 105 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 106 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 107 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 110 {
<> 151:5eaa88a5bcc7 111 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 114
<> 151:5eaa88a5bcc7 115 tmp |= hdac->Instance->DOR2 << 16U;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 118 return tmp;
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120 #endif
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 124 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 125 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 126 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 127 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 128 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 129 * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
<> 144:ef7eb2e8f9f7 130 * @param Amplitude: Select max triangle amplitude.
<> 144:ef7eb2e8f9f7 131 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 132 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
<> 144:ef7eb2e8f9f7 133 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
<> 144:ef7eb2e8f9f7 134 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
<> 144:ef7eb2e8f9f7 135 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
<> 144:ef7eb2e8f9f7 136 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
<> 144:ef7eb2e8f9f7 137 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
<> 144:ef7eb2e8f9f7 138 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
<> 144:ef7eb2e8f9f7 139 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
<> 144:ef7eb2e8f9f7 140 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
<> 144:ef7eb2e8f9f7 141 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
<> 144:ef7eb2e8f9f7 142 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
<> 144:ef7eb2e8f9f7 143 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
<> 144:ef7eb2e8f9f7 144 * @retval HAL status
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 /* Check the parameters */
<> 144:ef7eb2e8f9f7 149 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 150 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /* Process locked */
<> 144:ef7eb2e8f9f7 153 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Change DAC state */
<> 144:ef7eb2e8f9f7 156 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Enable the triangle wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 159 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Change DAC state */
<> 144:ef7eb2e8f9f7 163 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Process unlocked */
<> 144:ef7eb2e8f9f7 166 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Return function status */
<> 144:ef7eb2e8f9f7 169 return HAL_OK;
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 174 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 175 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 176 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 177 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 178 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 179 * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
<> 144:ef7eb2e8f9f7 180 * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
<> 144:ef7eb2e8f9f7 181 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 182 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
<> 144:ef7eb2e8f9f7 183 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
<> 144:ef7eb2e8f9f7 184 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
<> 144:ef7eb2e8f9f7 185 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
<> 144:ef7eb2e8f9f7 186 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
<> 144:ef7eb2e8f9f7 187 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
<> 144:ef7eb2e8f9f7 188 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
<> 144:ef7eb2e8f9f7 189 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
<> 144:ef7eb2e8f9f7 190 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
<> 144:ef7eb2e8f9f7 191 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
<> 144:ef7eb2e8f9f7 192 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
<> 144:ef7eb2e8f9f7 193 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
<> 144:ef7eb2e8f9f7 194 * @retval HAL status
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 /* Check the parameters */
<> 144:ef7eb2e8f9f7 199 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 200 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Process locked */
<> 144:ef7eb2e8f9f7 203 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Change DAC state */
<> 144:ef7eb2e8f9f7 206 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Enable the noise wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 209 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Change DAC state */
<> 144:ef7eb2e8f9f7 212 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Process unlocked */
<> 144:ef7eb2e8f9f7 215 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Return function status */
<> 144:ef7eb2e8f9f7 218 return HAL_OK;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief Set the specified data holding register value for dual DAC channel.
<> 144:ef7eb2e8f9f7 224 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 225 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 226 * @param Alignment: Specifies the data alignment for dual channel DAC.
<> 144:ef7eb2e8f9f7 227 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 228 * DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 229 * DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 230 * DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 231 * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 232 * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 233 * @note In dual mode, a unique register access is required to write in both
<> 144:ef7eb2e8f9f7 234 * DAC channels at the same time.
<> 144:ef7eb2e8f9f7 235 * @retval HAL status
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
<> 144:ef7eb2e8f9f7 238 {
<> 151:5eaa88a5bcc7 239 uint32_t data = 0U, tmp = 0U;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Check the parameters */
<> 144:ef7eb2e8f9f7 242 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 243 assert_param(IS_DAC_DATA(Data1));
<> 144:ef7eb2e8f9f7 244 assert_param(IS_DAC_DATA(Data2));
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Calculate and set dual DAC data holding register value */
<> 144:ef7eb2e8f9f7 247 if (Alignment == DAC_ALIGN_8B_R)
<> 144:ef7eb2e8f9f7 248 {
<> 151:5eaa88a5bcc7 249 data = ((uint32_t)Data2 << 8U) | Data1;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 else
<> 144:ef7eb2e8f9f7 252 {
<> 151:5eaa88a5bcc7 253 data = ((uint32_t)Data2 << 16U) | Data1;
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 257 tmp += DAC_DHR12RD_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Set the dual DAC selected data holding register */
<> 144:ef7eb2e8f9f7 260 *(__IO uint32_t *)tmp = data;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Return function status */
<> 144:ef7eb2e8f9f7 263 return HAL_OK;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @brief Conversion complete callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 269 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 270 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 271 * @retval None
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 276 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 279 the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 285 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 286 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 287 * @retval None
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 292 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 295 the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @brief Error DAC callback for Channel2.
<> 144:ef7eb2e8f9f7 301 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 302 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 303 * @retval None
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 308 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 311 the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @brief DMA underrun DAC callback for channel2.
<> 144:ef7eb2e8f9f7 317 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 318 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 319 * @retval None
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 324 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 327 the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 333 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 334 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 335 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 336 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 337 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 338 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 339 * @retval HAL status
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 342 {
<> 151:5eaa88a5bcc7 343 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 346 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Process locked */
<> 144:ef7eb2e8f9f7 349 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Change DAC state */
<> 144:ef7eb2e8f9f7 352 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 355 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
<> 144:ef7eb2e8f9f7 360 tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
<> 144:ef7eb2e8f9f7 361 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 362 if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 363 {
<> 144:ef7eb2e8f9f7 364 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 365 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368 else
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
<> 144:ef7eb2e8f9f7 371 tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
<> 144:ef7eb2e8f9f7 372 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 373 if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 376 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Change DAC state */
<> 144:ef7eb2e8f9f7 381 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Process unlocked */
<> 144:ef7eb2e8f9f7 384 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Return function status */
<> 144:ef7eb2e8f9f7 387 return HAL_OK;
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief Enables DAC and starts conversion of channel using DMA.
<> 144:ef7eb2e8f9f7 392 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 393 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 394 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 395 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 396 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 397 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 398 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 399 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 400 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 401 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 402 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 403 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 404 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 405 * @retval HAL status
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 408 {
<> 151:5eaa88a5bcc7 409 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Check the parameters */
<> 144:ef7eb2e8f9f7 412 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 413 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Process locked */
<> 144:ef7eb2e8f9f7 416 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Change DAC state */
<> 144:ef7eb2e8f9f7 419 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 422 {
<> 144:ef7eb2e8f9f7 423 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 424 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 427 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 430 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 433 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 436 switch(Alignment)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 439 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 440 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 441 break;
<> 144:ef7eb2e8f9f7 442 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 443 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 444 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 445 break;
<> 144:ef7eb2e8f9f7 446 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 447 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 448 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 449 break;
<> 144:ef7eb2e8f9f7 450 default:
<> 144:ef7eb2e8f9f7 451 break;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455 else
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 458 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 461 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 464 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 467 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 470 switch(Alignment)
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 473 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 474 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 475 break;
<> 144:ef7eb2e8f9f7 476 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 477 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 478 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 479 break;
<> 144:ef7eb2e8f9f7 480 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 481 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 482 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 483 break;
<> 144:ef7eb2e8f9f7 484 default:
<> 144:ef7eb2e8f9f7 485 break;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 490 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 493 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 496 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498 else
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 501 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 504 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 508 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 511 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Return function status */
<> 144:ef7eb2e8f9f7 514 return HAL_OK;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 519 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 520 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 521 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 522 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 523 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 524 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 525 * @retval HAL status
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Check the parameters */
<> 144:ef7eb2e8f9f7 532 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 535 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Disable the Peripharal */
<> 144:ef7eb2e8f9f7 538 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 541 /* Channel1 is used */
<> 144:ef7eb2e8f9f7 542 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546 else /* Channel2 is used for */
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 status = HAL_DMA_Abort(hdac->DMA_Handle2);
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 552 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 /* Update DAC state machine to error */
<> 144:ef7eb2e8f9f7 555 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 else
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* Change DAC state */
<> 144:ef7eb2e8f9f7 560 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Return function status */
<> 144:ef7eb2e8f9f7 564 return status;
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 569 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 570 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 571 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 572 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 573 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 574 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 575 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 /* Check the parameters */
<> 144:ef7eb2e8f9f7 580 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 583 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587 else
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591 }
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /**
<> 144:ef7eb2e8f9f7 594 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 595 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 596 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 597 * @retval None
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Check underrun flag of DAC channel 1 */
<> 144:ef7eb2e8f9f7 602 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 605 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 608 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 611 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 614 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Error callback */
<> 144:ef7eb2e8f9f7 617 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 618 }
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Check underrun flag of DAC channel 2 */
<> 144:ef7eb2e8f9f7 621 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 624 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Set DAC error code to channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 627 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 630 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 633 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Error callback */
<> 144:ef7eb2e8f9f7 636 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /**
<> 144:ef7eb2e8f9f7 642 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 643 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 644 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 645 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 646 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 647 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 648 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 649 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 650 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 651 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 652 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 653 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 654 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 655 * @retval HAL status
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 658 {
<> 151:5eaa88a5bcc7 659 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Check the parameters */
<> 144:ef7eb2e8f9f7 662 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 663 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 664 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 667 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671 else
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 tmp += DAC_DHR12R2_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Set the DAC channel selected data holding register */
<> 144:ef7eb2e8f9f7 677 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /* Return function status */
<> 144:ef7eb2e8f9f7 680 return HAL_OK;
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682 #else /* All products with only one channel */
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /**
<> 144:ef7eb2e8f9f7 685 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 686 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 687 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 688 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 689 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 690 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 691 * @retval HAL status
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 694 {
<> 151:5eaa88a5bcc7 695 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Check the parameters */
<> 144:ef7eb2e8f9f7 698 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Process locked */
<> 144:ef7eb2e8f9f7 701 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Change DAC state */
<> 144:ef7eb2e8f9f7 704 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 707 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
<> 144:ef7eb2e8f9f7 710 tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
<> 144:ef7eb2e8f9f7 711 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 712 if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 715 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Change DAC state */
<> 144:ef7eb2e8f9f7 719 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Process unlocked */
<> 144:ef7eb2e8f9f7 722 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Return function status */
<> 144:ef7eb2e8f9f7 725 return HAL_OK;
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @brief Enables DAC and starts conversion of channel using DMA.
<> 144:ef7eb2e8f9f7 730 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 731 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 732 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 733 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 734 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 735 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 736 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 737 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 738 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 739 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 740 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 741 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 742 * @retval HAL status
<> 144:ef7eb2e8f9f7 743 */
<> 144:ef7eb2e8f9f7 744 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 745 {
<> 151:5eaa88a5bcc7 746 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Check the parameters */
<> 144:ef7eb2e8f9f7 749 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 750 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Process locked */
<> 144:ef7eb2e8f9f7 753 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Change DAC state */
<> 144:ef7eb2e8f9f7 756 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 759 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 762 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 765 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 768 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 771 switch(Alignment)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 774 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 775 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 776 break;
<> 144:ef7eb2e8f9f7 777 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 778 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 779 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 780 break;
<> 144:ef7eb2e8f9f7 781 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 782 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 783 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 784 break;
<> 144:ef7eb2e8f9f7 785 default:
<> 144:ef7eb2e8f9f7 786 break;
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 791 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 792 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 795 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 798 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 801 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* Return function status */
<> 144:ef7eb2e8f9f7 804 return HAL_OK;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /**
<> 144:ef7eb2e8f9f7 808 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 809 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 810 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 811 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 812 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 813 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 814 * @retval HAL status
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Check the parameters */
<> 144:ef7eb2e8f9f7 821 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 824 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /* Disable the Peripharal */
<> 144:ef7eb2e8f9f7 827 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 830 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 833 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 /* Update DAC state machine to error */
<> 144:ef7eb2e8f9f7 836 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 else
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Change DAC state */
<> 144:ef7eb2e8f9f7 841 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Return function status */
<> 144:ef7eb2e8f9f7 845 return status;
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /**
<> 144:ef7eb2e8f9f7 849 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 850 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 851 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 852 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 853 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 854 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 855 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 /* Check the parameters */
<> 144:ef7eb2e8f9f7 860 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 863 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /**
<> 144:ef7eb2e8f9f7 867 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 868 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 869 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 870 * @retval None
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 /* Check underrun flag of DAC channel 1 */
<> 144:ef7eb2e8f9f7 875 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 878 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 881 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 884 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 887 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /* Error callback */
<> 144:ef7eb2e8f9f7 890 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /**
<> 144:ef7eb2e8f9f7 895 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 896 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 897 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 898 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 899 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 900 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 901 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 902 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 903 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 904 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 905 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 906 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 907 * @retval HAL status
<> 144:ef7eb2e8f9f7 908 */
<> 144:ef7eb2e8f9f7 909 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 910 {
<> 151:5eaa88a5bcc7 911 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* Check the parameters */
<> 144:ef7eb2e8f9f7 914 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 915 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 916 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 919 tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Set the DAC channel selected data holding register */
<> 144:ef7eb2e8f9f7 922 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Return function status */
<> 144:ef7eb2e8f9f7 925 return HAL_OK;
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /**
<> 144:ef7eb2e8f9f7 931 * @}
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /**
<> 144:ef7eb2e8f9f7 935 * @}
<> 144:ef7eb2e8f9f7 936 */
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /** @addtogroup DACEx_Private
<> 144:ef7eb2e8f9f7 939 * @{
<> 144:ef7eb2e8f9f7 940 */
<> 144:ef7eb2e8f9f7 941 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 942 /**
<> 144:ef7eb2e8f9f7 943 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 944 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 945 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 946 * @retval None
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 949 {
<> 144:ef7eb2e8f9f7 950 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 HAL_DACEx_ConvCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /**
<> 144:ef7eb2e8f9f7 958 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 959 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 960 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 961 * @retval None
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 966 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 967 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /**
<> 144:ef7eb2e8f9f7 971 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 972 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 973 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 974 * @retval None
<> 144:ef7eb2e8f9f7 975 */
<> 144:ef7eb2e8f9f7 976 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 981 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 HAL_DACEx_ErrorCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 986 }
<> 144:ef7eb2e8f9f7 987 #endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 /**
<> 144:ef7eb2e8f9f7 990 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 991 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 992 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 993 * @retval None
<> 144:ef7eb2e8f9f7 994 */
<> 144:ef7eb2e8f9f7 995 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 996 {
<> 144:ef7eb2e8f9f7 997 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1002 }
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /**
<> 144:ef7eb2e8f9f7 1005 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 1006 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1007 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1008 * @retval None
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1013 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1014 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /**
<> 144:ef7eb2e8f9f7 1018 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 1019 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1020 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1021 * @retval None
<> 144:ef7eb2e8f9f7 1022 */
<> 144:ef7eb2e8f9f7 1023 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1024 {
<> 144:ef7eb2e8f9f7 1025 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 1028 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /**
<> 144:ef7eb2e8f9f7 1036 * @}
<> 144:ef7eb2e8f9f7 1037 */
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /**
<> 144:ef7eb2e8f9f7 1040 * @}
<> 144:ef7eb2e8f9f7 1041 */
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /**
<> 144:ef7eb2e8f9f7 1044 * @}
<> 144:ef7eb2e8f9f7 1045 */
<> 144:ef7eb2e8f9f7 1046 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1047 #endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
<> 144:ef7eb2e8f9f7 1048 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1049