mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c@151:5eaa88a5bcc7, 2016-11-24 (annotated)

Committer:
<>
Date:
Thu Nov 24 17:03:03 2016 +0000
Revision:
151:5eaa88a5bcc7
Parent:
149:156823d33999
Child:
186:707f6e361f3e
This updates the lib to the mbed lib v130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_dac_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended DAC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of DAC extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended features functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
<> 144:ef7eb2e8f9f7 19 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
<> 144:ef7eb2e8f9f7 20 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
<> 144:ef7eb2e8f9f7 21 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
<> 144:ef7eb2e8f9f7 22 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 @endverbatim
<> 144:ef7eb2e8f9f7 25 ******************************************************************************
<> 144:ef7eb2e8f9f7 26 * @attention
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 31 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 32 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 33 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 35 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 36 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 38 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 39 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 51 *
<> 144:ef7eb2e8f9f7 52 ******************************************************************************
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
<> 144:ef7eb2e8f9f7 57 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 61 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /** @addtogroup DACEx DACEx
<> 144:ef7eb2e8f9f7 66 * @brief DAC driver modules
<> 144:ef7eb2e8f9f7 67 * @{
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @addtogroup DACEx_Private
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 82 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 83 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 84 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 85 #endif
<> 144:ef7eb2e8f9f7 86 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 87 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 88 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 89 /**
<> 144:ef7eb2e8f9f7 90 * @}
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /** @addtogroup DACEx_Exported_Functions
<> 144:ef7eb2e8f9f7 94 * @{
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** @addtogroup DACEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 98 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 * @{
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 107 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 108 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 109 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 112 {
<> 151:5eaa88a5bcc7 113 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 116
<> 151:5eaa88a5bcc7 117 tmp |= hdac->Instance->DOR2 << 16U;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 120 return tmp;
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122 #endif
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 126 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 127 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 128 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 129 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 130 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 131 * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
<> 144:ef7eb2e8f9f7 132 * @param Amplitude: Select max triangle amplitude.
<> 144:ef7eb2e8f9f7 133 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 134 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
<> 144:ef7eb2e8f9f7 135 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
<> 144:ef7eb2e8f9f7 136 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
<> 144:ef7eb2e8f9f7 137 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
<> 144:ef7eb2e8f9f7 138 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
<> 144:ef7eb2e8f9f7 139 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
<> 144:ef7eb2e8f9f7 140 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
<> 144:ef7eb2e8f9f7 141 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
<> 144:ef7eb2e8f9f7 142 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
<> 144:ef7eb2e8f9f7 143 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
<> 144:ef7eb2e8f9f7 144 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
<> 144:ef7eb2e8f9f7 145 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
<> 144:ef7eb2e8f9f7 146 * @retval HAL status
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 149 {
<> 144:ef7eb2e8f9f7 150 /* Check the parameters */
<> 144:ef7eb2e8f9f7 151 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 152 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Process locked */
<> 144:ef7eb2e8f9f7 155 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Change DAC state */
<> 144:ef7eb2e8f9f7 158 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Enable the triangle wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 161 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Change DAC state */
<> 144:ef7eb2e8f9f7 165 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Process unlocked */
<> 144:ef7eb2e8f9f7 168 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Return function status */
<> 144:ef7eb2e8f9f7 171 return HAL_OK;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 176 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 177 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 178 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 179 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 180 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 181 * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
<> 144:ef7eb2e8f9f7 182 * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
<> 144:ef7eb2e8f9f7 183 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 184 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
<> 144:ef7eb2e8f9f7 185 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
<> 144:ef7eb2e8f9f7 186 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
<> 144:ef7eb2e8f9f7 187 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
<> 144:ef7eb2e8f9f7 188 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
<> 144:ef7eb2e8f9f7 189 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
<> 144:ef7eb2e8f9f7 190 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
<> 144:ef7eb2e8f9f7 191 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
<> 144:ef7eb2e8f9f7 192 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
<> 144:ef7eb2e8f9f7 193 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
<> 144:ef7eb2e8f9f7 194 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
<> 144:ef7eb2e8f9f7 195 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
<> 144:ef7eb2e8f9f7 196 * @retval HAL status
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 /* Check the parameters */
<> 144:ef7eb2e8f9f7 201 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 202 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Process locked */
<> 144:ef7eb2e8f9f7 205 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Change DAC state */
<> 144:ef7eb2e8f9f7 208 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Enable the noise wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 211 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Change DAC state */
<> 144:ef7eb2e8f9f7 214 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Process unlocked */
<> 144:ef7eb2e8f9f7 217 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Return function status */
<> 144:ef7eb2e8f9f7 220 return HAL_OK;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief Set the specified data holding register value for dual DAC channel.
<> 144:ef7eb2e8f9f7 226 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 227 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 228 * @param Alignment: Specifies the data alignment for dual channel DAC.
<> 144:ef7eb2e8f9f7 229 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 230 * DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 231 * DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 232 * DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 233 * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 234 * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 235 * @note In dual mode, a unique register access is required to write in both
<> 144:ef7eb2e8f9f7 236 * DAC channels at the same time.
<> 144:ef7eb2e8f9f7 237 * @retval HAL status
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
<> 144:ef7eb2e8f9f7 240 {
<> 151:5eaa88a5bcc7 241 uint32_t data = 0U, tmp = 0U;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Check the parameters */
<> 144:ef7eb2e8f9f7 244 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 245 assert_param(IS_DAC_DATA(Data1));
<> 144:ef7eb2e8f9f7 246 assert_param(IS_DAC_DATA(Data2));
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Calculate and set dual DAC data holding register value */
<> 144:ef7eb2e8f9f7 249 if (Alignment == DAC_ALIGN_8B_R)
<> 144:ef7eb2e8f9f7 250 {
<> 151:5eaa88a5bcc7 251 data = ((uint32_t)Data2 << 8U) | Data1;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 else
<> 144:ef7eb2e8f9f7 254 {
<> 151:5eaa88a5bcc7 255 data = ((uint32_t)Data2 << 16U) | Data1;
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 259 tmp += DAC_DHR12RD_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Set the dual DAC selected data holding register */
<> 144:ef7eb2e8f9f7 262 *(__IO uint32_t *)tmp = data;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Return function status */
<> 144:ef7eb2e8f9f7 265 return HAL_OK;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @brief Conversion complete callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 271 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 272 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 273 * @retval None
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 278 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 281 the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 287 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 288 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 289 * @retval None
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 294 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 297 the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @brief Error DAC callback for Channel2.
<> 144:ef7eb2e8f9f7 303 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 304 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 305 * @retval None
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 310 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 313 the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief DMA underrun DAC callback for channel2.
<> 144:ef7eb2e8f9f7 319 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 320 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 321 * @retval None
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 326 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 329 the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 335 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 336 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 337 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 338 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 339 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 340 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 341 * @retval HAL status
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 344 {
<> 151:5eaa88a5bcc7 345 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Check the parameters */
<> 144:ef7eb2e8f9f7 348 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Process locked */
<> 144:ef7eb2e8f9f7 351 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Change DAC state */
<> 144:ef7eb2e8f9f7 354 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 357 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
<> 144:ef7eb2e8f9f7 362 tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
<> 144:ef7eb2e8f9f7 363 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 364 if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 367 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369 }
<> 144:ef7eb2e8f9f7 370 else
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
<> 144:ef7eb2e8f9f7 373 tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
<> 144:ef7eb2e8f9f7 374 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 375 if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 378 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Change DAC state */
<> 144:ef7eb2e8f9f7 383 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Process unlocked */
<> 144:ef7eb2e8f9f7 386 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Return function status */
<> 144:ef7eb2e8f9f7 389 return HAL_OK;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /**
<> 144:ef7eb2e8f9f7 393 * @brief Enables DAC and starts conversion of channel using DMA.
<> 144:ef7eb2e8f9f7 394 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 395 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 396 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 397 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 398 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 399 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 400 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 401 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 402 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 403 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 404 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 405 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 406 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 407 * @retval HAL status
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 410 {
<> 151:5eaa88a5bcc7 411 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Check the parameters */
<> 144:ef7eb2e8f9f7 414 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 415 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Process locked */
<> 144:ef7eb2e8f9f7 418 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Change DAC state */
<> 144:ef7eb2e8f9f7 421 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 426 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 429 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 432 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 435 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 438 switch(Alignment)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 441 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 442 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 443 break;
<> 144:ef7eb2e8f9f7 444 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 445 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 446 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 447 break;
<> 144:ef7eb2e8f9f7 448 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 449 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 450 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 451 break;
<> 144:ef7eb2e8f9f7 452 default:
<> 144:ef7eb2e8f9f7 453 break;
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457 else
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 460 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 463 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 466 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 469 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 472 switch(Alignment)
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 475 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 476 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 477 break;
<> 144:ef7eb2e8f9f7 478 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 479 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 480 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 481 break;
<> 144:ef7eb2e8f9f7 482 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 483 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 484 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 485 break;
<> 144:ef7eb2e8f9f7 486 default:
<> 144:ef7eb2e8f9f7 487 break;
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 492 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 495 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 498 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 else
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 503 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 506 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 510 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 513 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Return function status */
<> 144:ef7eb2e8f9f7 516 return HAL_OK;
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /**
<> 144:ef7eb2e8f9f7 520 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 521 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 522 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 523 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 524 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 525 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 526 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 527 * @retval HAL status
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Check the parameters */
<> 144:ef7eb2e8f9f7 534 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 537 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Disable the Peripharal */
<> 144:ef7eb2e8f9f7 540 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 543 /* Channel1 is used */
<> 144:ef7eb2e8f9f7 544 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548 else /* Channel2 is used for */
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 status = HAL_DMA_Abort(hdac->DMA_Handle2);
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 554 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Update DAC state machine to error */
<> 144:ef7eb2e8f9f7 557 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 else
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 /* Change DAC state */
<> 144:ef7eb2e8f9f7 562 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Return function status */
<> 144:ef7eb2e8f9f7 566 return status;
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 571 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 572 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 573 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 574 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 575 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 576 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 577 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 /* Check the parameters */
<> 144:ef7eb2e8f9f7 582 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 585 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 else
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 597 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 598 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 599 * @retval None
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 /* Check underrun flag of DAC channel 1 */
<> 144:ef7eb2e8f9f7 604 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 605 {
<> 144:ef7eb2e8f9f7 606 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 607 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 610 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 613 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 616 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Error callback */
<> 144:ef7eb2e8f9f7 619 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Check underrun flag of DAC channel 2 */
<> 144:ef7eb2e8f9f7 623 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 626 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Set DAC error code to channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 629 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 632 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 635 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /* Error callback */
<> 144:ef7eb2e8f9f7 638 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /**
<> 144:ef7eb2e8f9f7 644 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 645 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 646 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 647 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 648 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 649 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 650 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 651 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 652 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 653 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 654 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 655 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 656 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 657 * @retval HAL status
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 660 {
<> 151:5eaa88a5bcc7 661 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Check the parameters */
<> 144:ef7eb2e8f9f7 664 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 665 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 666 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 669 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673 else
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 tmp += DAC_DHR12R2_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Set the DAC channel selected data holding register */
<> 144:ef7eb2e8f9f7 679 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Return function status */
<> 144:ef7eb2e8f9f7 682 return HAL_OK;
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684 #else /* All products with only one channel */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 688 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 689 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 690 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 691 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 692 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 693 * @retval HAL status
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 696 {
<> 151:5eaa88a5bcc7 697 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Check the parameters */
<> 144:ef7eb2e8f9f7 700 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Process locked */
<> 144:ef7eb2e8f9f7 703 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Change DAC state */
<> 144:ef7eb2e8f9f7 706 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 709 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
<> 144:ef7eb2e8f9f7 712 tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
<> 144:ef7eb2e8f9f7 713 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 714 if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 717 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Change DAC state */
<> 144:ef7eb2e8f9f7 721 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Process unlocked */
<> 144:ef7eb2e8f9f7 724 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Return function status */
<> 144:ef7eb2e8f9f7 727 return HAL_OK;
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /**
<> 144:ef7eb2e8f9f7 731 * @brief Enables DAC and starts conversion of channel using DMA.
<> 144:ef7eb2e8f9f7 732 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 733 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 734 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 735 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 736 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 737 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 738 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 739 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 740 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 741 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 742 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 743 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 744 * @retval HAL status
<> 144:ef7eb2e8f9f7 745 */
<> 144:ef7eb2e8f9f7 746 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 747 {
<> 151:5eaa88a5bcc7 748 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Check the parameters */
<> 144:ef7eb2e8f9f7 751 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 752 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Process locked */
<> 144:ef7eb2e8f9f7 755 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Change DAC state */
<> 144:ef7eb2e8f9f7 758 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 761 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 764 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 767 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 770 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 773 switch(Alignment)
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 776 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 777 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 778 break;
<> 144:ef7eb2e8f9f7 779 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 780 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 781 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 782 break;
<> 144:ef7eb2e8f9f7 783 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 784 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 785 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 786 break;
<> 144:ef7eb2e8f9f7 787 default:
<> 144:ef7eb2e8f9f7 788 break;
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 793 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 794 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 797 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 800 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 803 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Return function status */
<> 144:ef7eb2e8f9f7 806 return HAL_OK;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 811 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 812 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 813 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 814 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 815 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 816 * @retval HAL status
<> 144:ef7eb2e8f9f7 817 */
<> 144:ef7eb2e8f9f7 818 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 819 {
<> 144:ef7eb2e8f9f7 820 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Check the parameters */
<> 144:ef7eb2e8f9f7 823 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 826 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Disable the Peripharal */
<> 144:ef7eb2e8f9f7 829 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 832 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 835 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 /* Update DAC state machine to error */
<> 144:ef7eb2e8f9f7 838 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 else
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 /* Change DAC state */
<> 144:ef7eb2e8f9f7 843 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Return function status */
<> 144:ef7eb2e8f9f7 847 return status;
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 852 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 853 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 854 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 855 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 856 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 857 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Check the parameters */
<> 144:ef7eb2e8f9f7 862 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 865 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /**
<> 144:ef7eb2e8f9f7 869 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 870 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 871 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 872 * @retval None
<> 144:ef7eb2e8f9f7 873 */
<> 144:ef7eb2e8f9f7 874 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 /* Check underrun flag of DAC channel 1 */
<> 144:ef7eb2e8f9f7 877 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 880 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 883 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 886 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 889 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /* Error callback */
<> 144:ef7eb2e8f9f7 892 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 893 }
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 898 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 899 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 900 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 901 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 902 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 903 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 904 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 905 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 906 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 907 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 908 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 909 * @retval HAL status
<> 144:ef7eb2e8f9f7 910 */
<> 144:ef7eb2e8f9f7 911 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 912 {
<> 151:5eaa88a5bcc7 913 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Check the parameters */
<> 144:ef7eb2e8f9f7 916 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 917 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 918 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 921 tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 /* Set the DAC channel selected data holding register */
<> 144:ef7eb2e8f9f7 924 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /* Return function status */
<> 144:ef7eb2e8f9f7 927 return HAL_OK;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /**
<> 144:ef7eb2e8f9f7 933 * @}
<> 144:ef7eb2e8f9f7 934 */
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /**
<> 144:ef7eb2e8f9f7 937 * @}
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /** @addtogroup DACEx_Private
<> 144:ef7eb2e8f9f7 941 * @{
<> 144:ef7eb2e8f9f7 942 */
<> 144:ef7eb2e8f9f7 943 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 944 /**
<> 144:ef7eb2e8f9f7 945 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 946 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 947 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 948 * @retval None
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 951 {
<> 144:ef7eb2e8f9f7 952 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 HAL_DACEx_ConvCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /**
<> 144:ef7eb2e8f9f7 960 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 961 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 962 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 963 * @retval None
<> 144:ef7eb2e8f9f7 964 */
<> 144:ef7eb2e8f9f7 965 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 968 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 969 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 970 }
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /**
<> 144:ef7eb2e8f9f7 973 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 974 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 975 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 976 * @retval None
<> 144:ef7eb2e8f9f7 977 */
<> 144:ef7eb2e8f9f7 978 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 983 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 HAL_DACEx_ErrorCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989 #endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /**
<> 144:ef7eb2e8f9f7 992 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 993 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 994 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 995 * @retval None
<> 144:ef7eb2e8f9f7 996 */
<> 144:ef7eb2e8f9f7 997 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /**
<> 144:ef7eb2e8f9f7 1007 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 1008 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1009 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1010 * @retval None
<> 144:ef7eb2e8f9f7 1011 */
<> 144:ef7eb2e8f9f7 1012 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1013 {
<> 144:ef7eb2e8f9f7 1014 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1015 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1016 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /**
<> 144:ef7eb2e8f9f7 1020 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 1021 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1022 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1023 * @retval None
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 1030 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /**
<> 144:ef7eb2e8f9f7 1038 * @}
<> 144:ef7eb2e8f9f7 1039 */
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /**
<> 144:ef7eb2e8f9f7 1042 * @}
<> 144:ef7eb2e8f9f7 1043 */
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /**
<> 144:ef7eb2e8f9f7 1046 * @}
<> 144:ef7eb2e8f9f7 1047 */
<> 144:ef7eb2e8f9f7 1048 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1049 #endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
<> 144:ef7eb2e8f9f7 1050 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1051