mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 186:707f6e361f3e
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32l0xx_hal_adc.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 6 | * functionalities of the Analog to Digital Convertor (ADC) |
<> | 144:ef7eb2e8f9f7 | 7 | * peripheral: |
<> | 144:ef7eb2e8f9f7 | 8 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 9 | * ++ Initialization and Configuration of ADC |
<> | 144:ef7eb2e8f9f7 | 10 | * + Operation functions |
Anna Bridge |
186:707f6e361f3e | 11 | * ++ Start, stop, get result of conversions of regular |
Anna Bridge |
186:707f6e361f3e | 12 | * group, using 3 possible modes: polling, interruption or DMA. |
<> | 144:ef7eb2e8f9f7 | 13 | * + Control functions |
<> | 144:ef7eb2e8f9f7 | 14 | * ++ Channels configuration on regular group |
<> | 144:ef7eb2e8f9f7 | 15 | * ++ Analog Watchdog configuration |
<> | 144:ef7eb2e8f9f7 | 16 | * + State functions |
<> | 144:ef7eb2e8f9f7 | 17 | * ++ ADC state machine management |
<> | 144:ef7eb2e8f9f7 | 18 | * ++ Interrupts and flags management |
<> | 144:ef7eb2e8f9f7 | 19 | * Other functions (extended functions) are available in file |
<> | 144:ef7eb2e8f9f7 | 20 | * "stm32l0xx_hal_adc_ex.c". |
Anna Bridge |
186:707f6e361f3e | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 23 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 24 | ##### ADC peripheral features ##### |
<> | 144:ef7eb2e8f9f7 | 25 | ============================================================================== |
Anna Bridge |
186:707f6e361f3e | 26 | [..] |
Anna Bridge |
186:707f6e361f3e | 27 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | (+) Interrupt generation at the end of regular conversion and in case of |
<> | 144:ef7eb2e8f9f7 | 30 | analog watchdog or overrun events. |
Anna Bridge |
186:707f6e361f3e | 31 | |
<> | 144:ef7eb2e8f9f7 | 32 | (+) Single and continuous conversion modes. |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | (+) Scan mode for conversion of several channels sequentially. |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | (+) Data alignment with in-built data coherency. |
Anna Bridge |
186:707f6e361f3e | 37 | |
Anna Bridge |
186:707f6e361f3e | 38 | (+) Programmable sampling time (common for all channels) |
Anna Bridge |
186:707f6e361f3e | 39 | |
Anna Bridge |
186:707f6e361f3e | 40 | (+) External trigger (timer or EXTI) with configurable polarity |
Anna Bridge |
186:707f6e361f3e | 41 | |
Anna Bridge |
186:707f6e361f3e | 42 | (+) DMA request generation for transfer of conversions data of regular group. |
<> | 144:ef7eb2e8f9f7 | 43 | |
Anna Bridge |
186:707f6e361f3e | 44 | (+) ADC calibration |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | (+) ADC conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 47 | |
Anna Bridge |
186:707f6e361f3e | 48 | (+) ADC supply requirements: 1.62 V to 3.6 V. |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
<> | 144:ef7eb2e8f9f7 | 51 | Vdda or to an external voltage reference). |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 55 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 56 | [..] |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | *** Configuration of top level parameters related to ADC *** |
<> | 144:ef7eb2e8f9f7 | 59 | ============================================================ |
<> | 144:ef7eb2e8f9f7 | 60 | [..] |
<> | 144:ef7eb2e8f9f7 | 61 | |
Anna Bridge |
186:707f6e361f3e | 62 | (#) Enable the ADC interface |
Anna Bridge |
186:707f6e361f3e | 63 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
Anna Bridge |
186:707f6e361f3e | 64 | Caution: On STM32L0, ADC clock frequency max is 16MHz (refer |
Anna Bridge |
186:707f6e361f3e | 65 | to device datasheet). |
Anna Bridge |
186:707f6e361f3e | 66 | Therefore, ADC clock prescaler must be configured in |
Anna Bridge |
186:707f6e361f3e | 67 | function of ADC clock source frequency to remain below |
Anna Bridge |
186:707f6e361f3e | 68 | this maximum frequency. |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | (++) Two clock settings are mandatory: |
<> | 144:ef7eb2e8f9f7 | 71 | (+++) ADC clock (core clock, also possibly conversion clock). |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | (+++) ADC clock (conversions clock). |
<> | 144:ef7eb2e8f9f7 | 74 | Two possible clock sources: synchronous clock derived from APB clock |
<> | 144:ef7eb2e8f9f7 | 75 | or asynchronous clock derived from ADC dedicated HSI RC oscillator |
<> | 144:ef7eb2e8f9f7 | 76 | 16MHz. |
<> | 144:ef7eb2e8f9f7 | 77 | If asynchronous clock is selected, parameter "HSIState" must be set either: |
<> | 144:ef7eb2e8f9f7 | 78 | - to "...HSIState = RCC_HSI_ON" to maintain the HSI16 oscillator |
<> | 144:ef7eb2e8f9f7 | 79 | always enabled: can be used to supply the main system clock. |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | (+++) Example: |
<> | 144:ef7eb2e8f9f7 | 82 | Into HAL_ADC_MspInit() (recommended code location) or with |
<> | 144:ef7eb2e8f9f7 | 83 | other device clock parameters configuration: |
Anna Bridge |
186:707f6e361f3e | 84 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) |
<> | 144:ef7eb2e8f9f7 | 85 | |
Anna Bridge |
186:707f6e361f3e | 86 | HSI enable (optional: if asynchronous clock selected) |
<> | 144:ef7eb2e8f9f7 | 87 | (+++) RCC_OscInitTypeDef RCC_OscInitStructure; |
<> | 144:ef7eb2e8f9f7 | 88 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
<> | 144:ef7eb2e8f9f7 | 89 | (+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
<> | 144:ef7eb2e8f9f7 | 90 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON; |
<> | 144:ef7eb2e8f9f7 | 91 | (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) |
<> | 144:ef7eb2e8f9f7 | 92 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | (++) ADC clock source and clock prescaler are configured at ADC level with |
<> | 144:ef7eb2e8f9f7 | 95 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | (#) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 98 | (++) Enable the clock for the ADC GPIOs |
<> | 144:ef7eb2e8f9f7 | 99 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 100 | (++) Configure these ADC pins in analog mode |
<> | 144:ef7eb2e8f9f7 | 101 | using function HAL_GPIO_Init() |
<> | 144:ef7eb2e8f9f7 | 102 | |
<> | 144:ef7eb2e8f9f7 | 103 | (#) Optionally, in case of usage of ADC with interruptions: |
<> | 144:ef7eb2e8f9f7 | 104 | (++) Configure the NVIC for ADC |
<> | 144:ef7eb2e8f9f7 | 105 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 106 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 107 | into the function of corresponding ADC interruption vector |
<> | 144:ef7eb2e8f9f7 | 108 | ADCx_IRQHandler(). |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | (#) Optionally, in case of usage of DMA: |
<> | 144:ef7eb2e8f9f7 | 111 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
<> | 144:ef7eb2e8f9f7 | 112 | using function HAL_DMA_Init(). |
<> | 144:ef7eb2e8f9f7 | 113 | (++) Configure the NVIC for DMA |
<> | 144:ef7eb2e8f9f7 | 114 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 115 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 116 | into the function of corresponding DMA interruption vector |
<> | 144:ef7eb2e8f9f7 | 117 | DMAx_Channelx_IRQHandler(). |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | *** Configuration of ADC, group regular, channels parameters *** |
<> | 144:ef7eb2e8f9f7 | 120 | ================================================================ |
<> | 144:ef7eb2e8f9f7 | 121 | [..] |
<> | 144:ef7eb2e8f9f7 | 122 | |
Anna Bridge |
186:707f6e361f3e | 123 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
<> | 144:ef7eb2e8f9f7 | 124 | and regular group parameters (conversion trigger, sequencer, ...) |
<> | 144:ef7eb2e8f9f7 | 125 | using function HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 126 | |
<> | 144:ef7eb2e8f9f7 | 127 | (#) Configure the channels for regular group parameters (channel number, |
<> | 144:ef7eb2e8f9f7 | 128 | channel rank into sequencer, ..., into regular group) |
<> | 144:ef7eb2e8f9f7 | 129 | using function HAL_ADC_ConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | (#) Optionally, configure the analog watchdog parameters (channels |
<> | 144:ef7eb2e8f9f7 | 132 | monitored, thresholds, ...) |
<> | 144:ef7eb2e8f9f7 | 133 | using function HAL_ADC_AnalogWDGConfig(). |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | (#) When device is in mode low-power (low-power run, low-power sleep or stop mode), |
<> | 144:ef7eb2e8f9f7 | 137 | function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 138 | In case of internal temperature sensor to be measured: |
<> | 144:ef7eb2e8f9f7 | 139 | function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | *** Execution of ADC conversions *** |
<> | 144:ef7eb2e8f9f7 | 142 | ==================================== |
<> | 144:ef7eb2e8f9f7 | 143 | [..] |
<> | 144:ef7eb2e8f9f7 | 144 | |
<> | 144:ef7eb2e8f9f7 | 145 | (#) Optionally, perform an automatic ADC calibration to improve the |
<> | 144:ef7eb2e8f9f7 | 146 | conversion accuracy |
<> | 144:ef7eb2e8f9f7 | 147 | using function HAL_ADCEx_Calibration_Start(). |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | (#) ADC driver can be used among three modes: polling, interruption, |
<> | 144:ef7eb2e8f9f7 | 150 | transfer by DMA. |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | (++) ADC conversion by polling: |
<> | 144:ef7eb2e8f9f7 | 153 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 154 | using function HAL_ADC_Start() |
<> | 144:ef7eb2e8f9f7 | 155 | (+++) Wait for ADC conversion completion |
<> | 144:ef7eb2e8f9f7 | 156 | using function HAL_ADC_PollForConversion() |
<> | 144:ef7eb2e8f9f7 | 157 | (+++) Retrieve conversion results |
<> | 144:ef7eb2e8f9f7 | 158 | using function HAL_ADC_GetValue() |
<> | 144:ef7eb2e8f9f7 | 159 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 160 | using function HAL_ADC_Stop() |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | (++) ADC conversion by interruption: |
<> | 144:ef7eb2e8f9f7 | 163 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 164 | using function HAL_ADC_Start_IT() |
<> | 144:ef7eb2e8f9f7 | 165 | (+++) Wait for ADC conversion completion by call of function |
<> | 144:ef7eb2e8f9f7 | 166 | HAL_ADC_ConvCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 167 | (this function must be implemented in user program) |
<> | 144:ef7eb2e8f9f7 | 168 | (+++) Retrieve conversion results |
<> | 144:ef7eb2e8f9f7 | 169 | using function HAL_ADC_GetValue() |
<> | 144:ef7eb2e8f9f7 | 170 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 171 | using function HAL_ADC_Stop_IT() |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | (++) ADC conversion with transfer by DMA: |
<> | 144:ef7eb2e8f9f7 | 174 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 175 | using function HAL_ADC_Start_DMA() |
<> | 144:ef7eb2e8f9f7 | 176 | (+++) Wait for ADC conversion completion by call of function |
<> | 144:ef7eb2e8f9f7 | 177 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 178 | (these functions must be implemented in user program) |
<> | 144:ef7eb2e8f9f7 | 179 | (+++) Conversion results are automatically transferred by DMA into |
<> | 144:ef7eb2e8f9f7 | 180 | destination variable address. |
<> | 144:ef7eb2e8f9f7 | 181 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 182 | using function HAL_ADC_Stop_DMA() |
Anna Bridge |
186:707f6e361f3e | 183 | |
Anna Bridge |
186:707f6e361f3e | 184 | [..] |
Anna Bridge |
186:707f6e361f3e | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | (@) Callback functions must be implemented in user program: |
<> | 144:ef7eb2e8f9f7 | 187 | (+@) HAL_ADC_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 188 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
<> | 144:ef7eb2e8f9f7 | 189 | (+@) HAL_ADC_ConvCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 190 | (+@) HAL_ADC_ConvHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | *** Deinitialization of ADC *** |
<> | 144:ef7eb2e8f9f7 | 193 | ============================================================ |
<> | 144:ef7eb2e8f9f7 | 194 | [..] |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | (#) Disable the ADC interface |
<> | 144:ef7eb2e8f9f7 | 197 | (++) ADC clock can be hard reset and disabled at RCC top level. |
<> | 144:ef7eb2e8f9f7 | 198 | (++) Hard reset of ADC peripherals |
<> | 144:ef7eb2e8f9f7 | 199 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
<> | 144:ef7eb2e8f9f7 | 200 | (++) ADC clock disable |
<> | 144:ef7eb2e8f9f7 | 201 | using the equivalent macro/functions as configuration step. |
<> | 144:ef7eb2e8f9f7 | 202 | (+++) Example: |
<> | 144:ef7eb2e8f9f7 | 203 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
<> | 144:ef7eb2e8f9f7 | 204 | other device clock parameters configuration: |
<> | 144:ef7eb2e8f9f7 | 205 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
<> | 144:ef7eb2e8f9f7 | 206 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) |
<> | 144:ef7eb2e8f9f7 | 207 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
<> | 144:ef7eb2e8f9f7 | 208 | |
<> | 144:ef7eb2e8f9f7 | 209 | (#) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 210 | (++) Disable the clock for the ADC GPIOs |
<> | 144:ef7eb2e8f9f7 | 211 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
<> | 144:ef7eb2e8f9f7 | 212 | |
<> | 144:ef7eb2e8f9f7 | 213 | (#) Optionally, in case of usage of ADC with interruptions: |
<> | 144:ef7eb2e8f9f7 | 214 | (++) Disable the NVIC for ADC |
<> | 144:ef7eb2e8f9f7 | 215 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 216 | |
<> | 144:ef7eb2e8f9f7 | 217 | (#) Optionally, in case of usage of DMA: |
<> | 144:ef7eb2e8f9f7 | 218 | (++) Deinitialize the DMA |
<> | 144:ef7eb2e8f9f7 | 219 | using function HAL_DMA_Init(). |
<> | 144:ef7eb2e8f9f7 | 220 | (++) Disable the NVIC for DMA |
<> | 144:ef7eb2e8f9f7 | 221 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 222 | |
<> | 144:ef7eb2e8f9f7 | 223 | [..] |
<> | 144:ef7eb2e8f9f7 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 226 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 227 | * @attention |
<> | 144:ef7eb2e8f9f7 | 228 | * |
<> | 144:ef7eb2e8f9f7 | 229 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 230 | * |
<> | 144:ef7eb2e8f9f7 | 231 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 232 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 233 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 234 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 235 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 236 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 237 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 238 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 239 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 240 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 241 | * |
<> | 144:ef7eb2e8f9f7 | 242 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 243 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 244 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 245 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 246 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 247 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 248 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 249 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 250 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 251 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 252 | * |
<> | 144:ef7eb2e8f9f7 | 253 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 254 | */ |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 257 | #include "stm32l0xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | /** @addtogroup STM32L0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 260 | * @{ |
<> | 144:ef7eb2e8f9f7 | 261 | */ |
<> | 144:ef7eb2e8f9f7 | 262 | |
Anna Bridge |
186:707f6e361f3e | 263 | /** @defgroup ADC ADC |
Anna Bridge |
186:707f6e361f3e | 264 | * @brief ADC HAL module driver |
Anna Bridge |
186:707f6e361f3e | 265 | * @{ |
Anna Bridge |
186:707f6e361f3e | 266 | */ |
Anna Bridge |
186:707f6e361f3e | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | #ifdef HAL_ADC_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 269 | |
Anna Bridge |
186:707f6e361f3e | 270 | /* Private typedef -----------------------------------------------------------*/ |
Anna Bridge |
186:707f6e361f3e | 271 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 272 | |
Anna Bridge |
186:707f6e361f3e | 273 | /** @defgroup ADC_Private_Constants ADC Private Constants |
<> | 144:ef7eb2e8f9f7 | 274 | * @{ |
<> | 144:ef7eb2e8f9f7 | 275 | */ |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | /* Delay for ADC stabilization time. */ |
<> | 144:ef7eb2e8f9f7 | 278 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */ |
<> | 144:ef7eb2e8f9f7 | 279 | /* Unit: us */ |
<> | 151:5eaa88a5bcc7 | 280 | #define ADC_STAB_DELAY_US ((uint32_t) 1U) |
<> | 144:ef7eb2e8f9f7 | 281 | |
<> | 144:ef7eb2e8f9f7 | 282 | /* Delay for temperature sensor stabilization time. */ |
<> | 144:ef7eb2e8f9f7 | 283 | /* Unit: us */ |
AnnaBridge | 189:f392fc9709a3 | 284 | #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 20000U) |
<> | 144:ef7eb2e8f9f7 | 285 | /** |
<> | 144:ef7eb2e8f9f7 | 286 | * @} |
<> | 144:ef7eb2e8f9f7 | 287 | */ |
<> | 144:ef7eb2e8f9f7 | 288 | |
<> | 144:ef7eb2e8f9f7 | 289 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 290 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 291 | /* Private function prototypes -----------------------------------------------*/ |
Anna Bridge |
186:707f6e361f3e | 292 | /** @defgroup ADC_Private_Functions ADC Private Functions |
<> | 144:ef7eb2e8f9f7 | 293 | * @{ |
Anna Bridge |
186:707f6e361f3e | 294 | */ |
<> | 144:ef7eb2e8f9f7 | 295 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
<> | 144:ef7eb2e8f9f7 | 296 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); |
<> | 144:ef7eb2e8f9f7 | 297 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); |
<> | 144:ef7eb2e8f9f7 | 298 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 299 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 300 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 301 | static void ADC_DelayMicroSecond(uint32_t microSecond); |
<> | 144:ef7eb2e8f9f7 | 302 | /** |
<> | 144:ef7eb2e8f9f7 | 303 | * @} |
<> | 144:ef7eb2e8f9f7 | 304 | */ |
<> | 144:ef7eb2e8f9f7 | 305 | |
Anna Bridge |
186:707f6e361f3e | 306 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 307 | |
Anna Bridge |
186:707f6e361f3e | 308 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
Anna Bridge |
186:707f6e361f3e | 309 | * @{ |
Anna Bridge |
186:707f6e361f3e | 310 | */ |
Anna Bridge |
186:707f6e361f3e | 311 | |
Anna Bridge |
186:707f6e361f3e | 312 | /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions |
Anna Bridge |
186:707f6e361f3e | 313 | * @brief ADC Initialization and Configuration functions |
Anna Bridge |
186:707f6e361f3e | 314 | * |
<> | 144:ef7eb2e8f9f7 | 315 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 316 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 317 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 318 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 319 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 320 | (+) Initialize and configure the ADC. |
Anna Bridge |
186:707f6e361f3e | 321 | (+) De-initialize the ADC. |
<> | 144:ef7eb2e8f9f7 | 322 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 323 | * @{ |
<> | 144:ef7eb2e8f9f7 | 324 | */ |
<> | 144:ef7eb2e8f9f7 | 325 | |
<> | 144:ef7eb2e8f9f7 | 326 | /** |
Anna Bridge |
186:707f6e361f3e | 327 | * @brief Initialize the ADC peripheral and regular group according to |
<> | 144:ef7eb2e8f9f7 | 328 | * parameters specified in structure "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 329 | * @note As prerequisite, ADC clock must be configured at RCC top level |
Anna Bridge |
186:707f6e361f3e | 330 | * depending on possible clock sources: APB clock of HSI clock. |
Anna Bridge |
186:707f6e361f3e | 331 | * See commented example code below that can be copied and uncommented |
<> | 144:ef7eb2e8f9f7 | 332 | * into HAL_ADC_MspInit(). |
<> | 144:ef7eb2e8f9f7 | 333 | * @note Possibility to update parameters on the fly: |
<> | 144:ef7eb2e8f9f7 | 334 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
<> | 144:ef7eb2e8f9f7 | 335 | * coming from ADC state reset. Following calls to this function can |
<> | 144:ef7eb2e8f9f7 | 336 | * be used to reconfigure some parameters of ADC_InitTypeDef |
<> | 144:ef7eb2e8f9f7 | 337 | * structure on the fly, without modifying MSP configuration. If ADC |
<> | 144:ef7eb2e8f9f7 | 338 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
<> | 144:ef7eb2e8f9f7 | 339 | * before HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 340 | * The setting of these parameters is conditioned to ADC state. |
<> | 144:ef7eb2e8f9f7 | 341 | * For parameters constraints, see comments of structure |
<> | 144:ef7eb2e8f9f7 | 342 | * "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 343 | * @note This function configures the ADC within 2 scopes: scope of entire |
<> | 144:ef7eb2e8f9f7 | 344 | * ADC and scope of regular group. For parameters details, see comments |
<> | 144:ef7eb2e8f9f7 | 345 | * of structure "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 346 | * @note When device is in mode low-power (low-power run, low-power sleep or stop mode), |
<> | 144:ef7eb2e8f9f7 | 347 | * function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init() |
<> | 144:ef7eb2e8f9f7 | 348 | * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first). |
<> | 144:ef7eb2e8f9f7 | 349 | * In case of internal temperature sensor to be measured: |
<> | 144:ef7eb2e8f9f7 | 350 | * function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly. |
<> | 144:ef7eb2e8f9f7 | 351 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 352 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 353 | */ |
<> | 144:ef7eb2e8f9f7 | 354 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 355 | { |
<> | 144:ef7eb2e8f9f7 | 356 | |
<> | 144:ef7eb2e8f9f7 | 357 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 358 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 359 | { |
<> | 144:ef7eb2e8f9f7 | 360 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 361 | } |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 364 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 365 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
<> | 144:ef7eb2e8f9f7 | 366 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
Anna Bridge |
186:707f6e361f3e | 367 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
Anna Bridge |
186:707f6e361f3e | 368 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
<> | 151:5eaa88a5bcc7 | 369 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 370 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 371 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
Anna Bridge |
186:707f6e361f3e | 372 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
<> | 151:5eaa88a5bcc7 | 373 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
Anna Bridge |
186:707f6e361f3e | 374 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
<> | 151:5eaa88a5bcc7 | 375 | assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); |
<> | 144:ef7eb2e8f9f7 | 376 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); |
<> | 144:ef7eb2e8f9f7 | 377 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode)); |
<> | 144:ef7eb2e8f9f7 | 378 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); |
Anna Bridge |
186:707f6e361f3e | 379 | assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime)); |
<> | 144:ef7eb2e8f9f7 | 380 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
<> | 144:ef7eb2e8f9f7 | 383 | /* at RCC top level depending on both possible clock sources: */ |
<> | 144:ef7eb2e8f9f7 | 384 | /* APB clock or HSI clock. */ |
<> | 144:ef7eb2e8f9f7 | 385 | /* Refer to header of this file for more details on clock enabling procedure*/ |
<> | 144:ef7eb2e8f9f7 | 386 | |
<> | 144:ef7eb2e8f9f7 | 387 | /* Actions performed only if ADC is coming from state reset: */ |
<> | 144:ef7eb2e8f9f7 | 388 | /* - Initialization of ADC MSP */ |
<> | 144:ef7eb2e8f9f7 | 389 | /* - ADC voltage regulator enable */ |
<> | 144:ef7eb2e8f9f7 | 390 | if(hadc->State == HAL_ADC_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 391 | { |
<> | 144:ef7eb2e8f9f7 | 392 | /* Initialize ADC error code */ |
<> | 144:ef7eb2e8f9f7 | 393 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 394 | |
<> | 144:ef7eb2e8f9f7 | 395 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 396 | hadc->Lock = HAL_UNLOCKED; |
Anna Bridge |
186:707f6e361f3e | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | /* Init the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 399 | HAL_ADC_MspInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 400 | } |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 403 | /* correctly completed. */ |
Anna Bridge |
186:707f6e361f3e | 404 | /* and if there is no conversion on going on regular group (ADC can be */ |
<> | 144:ef7eb2e8f9f7 | 405 | /* enabled anyway, in case of call of this function to update a parameter */ |
<> | 144:ef7eb2e8f9f7 | 406 | /* on the fly). */ |
<> | 144:ef7eb2e8f9f7 | 407 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) || |
<> | 144:ef7eb2e8f9f7 | 408 | (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) ) |
<> | 144:ef7eb2e8f9f7 | 409 | { |
<> | 144:ef7eb2e8f9f7 | 410 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 411 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 412 | |
<> | 144:ef7eb2e8f9f7 | 413 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 414 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 415 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 416 | } |
<> | 144:ef7eb2e8f9f7 | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 419 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 420 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 421 | HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 422 | |
<> | 144:ef7eb2e8f9f7 | 423 | /* Parameters update conditioned to ADC state: */ |
<> | 144:ef7eb2e8f9f7 | 424 | /* Parameters that can be updated only when ADC is disabled: */ |
<> | 144:ef7eb2e8f9f7 | 425 | /* - ADC clock mode */ |
<> | 144:ef7eb2e8f9f7 | 426 | /* - ADC clock prescaler */ |
<> | 144:ef7eb2e8f9f7 | 427 | /* - ADC Resolution */ |
<> | 144:ef7eb2e8f9f7 | 428 | if (ADC_IS_ENABLE(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 429 | { |
<> | 144:ef7eb2e8f9f7 | 430 | /* Some parameters of this register are not reset, since they are set */ |
<> | 144:ef7eb2e8f9f7 | 431 | /* by other functions and must be kept in case of usage of this */ |
<> | 144:ef7eb2e8f9f7 | 432 | /* function on the fly (update of a parameter of ADC_InitTypeDef */ |
<> | 144:ef7eb2e8f9f7 | 433 | /* without needing to reconfigure all other ADC groups/channels */ |
<> | 144:ef7eb2e8f9f7 | 434 | /* parameters): */ |
<> | 144:ef7eb2e8f9f7 | 435 | /* - internal measurement paths: Vbat, temperature sensor, Vref */ |
<> | 144:ef7eb2e8f9f7 | 436 | /* (set into HAL_ADC_ConfigChannel() ) */ |
<> | 144:ef7eb2e8f9f7 | 437 | |
<> | 144:ef7eb2e8f9f7 | 438 | /* Configuration of ADC clock: clock source PCLK or asynchronous with |
<> | 144:ef7eb2e8f9f7 | 439 | selectable prescaler */ |
<> | 144:ef7eb2e8f9f7 | 440 | __HAL_ADC_CLOCK_PRESCALER(hadc); |
<> | 144:ef7eb2e8f9f7 | 441 | |
<> | 144:ef7eb2e8f9f7 | 442 | /* Configuration of ADC: */ |
<> | 144:ef7eb2e8f9f7 | 443 | /* - Resolution */ |
<> | 144:ef7eb2e8f9f7 | 444 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES); |
<> | 144:ef7eb2e8f9f7 | 445 | hadc->Instance->CFGR1 |= hadc->Init.Resolution; |
<> | 144:ef7eb2e8f9f7 | 446 | } |
<> | 144:ef7eb2e8f9f7 | 447 | |
<> | 144:ef7eb2e8f9f7 | 448 | /* Set the Low Frequency mode */ |
<> | 144:ef7eb2e8f9f7 | 449 | ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN; |
<> | 144:ef7eb2e8f9f7 | 450 | ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode); |
<> | 144:ef7eb2e8f9f7 | 451 | |
<> | 144:ef7eb2e8f9f7 | 452 | /* Enable voltage regulator (if disabled at this step) */ |
<> | 144:ef7eb2e8f9f7 | 453 | if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) |
<> | 144:ef7eb2e8f9f7 | 454 | { |
<> | 144:ef7eb2e8f9f7 | 455 | /* Set ADVREGEN bit */ |
<> | 144:ef7eb2e8f9f7 | 456 | hadc->Instance->CR |= ADC_CR_ADVREGEN; |
<> | 144:ef7eb2e8f9f7 | 457 | } |
<> | 144:ef7eb2e8f9f7 | 458 | |
<> | 144:ef7eb2e8f9f7 | 459 | /* Configuration of ADC: */ |
<> | 144:ef7eb2e8f9f7 | 460 | /* - Resolution */ |
<> | 144:ef7eb2e8f9f7 | 461 | /* - Data alignment */ |
<> | 144:ef7eb2e8f9f7 | 462 | /* - Scan direction */ |
<> | 144:ef7eb2e8f9f7 | 463 | /* - External trigger to start conversion */ |
<> | 144:ef7eb2e8f9f7 | 464 | /* - External trigger polarity */ |
<> | 144:ef7eb2e8f9f7 | 465 | /* - Continuous conversion mode */ |
<> | 144:ef7eb2e8f9f7 | 466 | /* - DMA continuous request */ |
<> | 144:ef7eb2e8f9f7 | 467 | /* - Overrun */ |
<> | 144:ef7eb2e8f9f7 | 468 | /* - AutoDelay feature */ |
<> | 144:ef7eb2e8f9f7 | 469 | /* - Discontinuous mode */ |
Anna Bridge |
186:707f6e361f3e | 470 | hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN | |
Anna Bridge |
186:707f6e361f3e | 471 | ADC_CFGR1_SCANDIR | |
Anna Bridge |
186:707f6e361f3e | 472 | ADC_CFGR1_EXTSEL | |
Anna Bridge |
186:707f6e361f3e | 473 | ADC_CFGR1_EXTEN | |
Anna Bridge |
186:707f6e361f3e | 474 | ADC_CFGR1_CONT | |
Anna Bridge |
186:707f6e361f3e | 475 | ADC_CFGR1_DMACFG | |
Anna Bridge |
186:707f6e361f3e | 476 | ADC_CFGR1_OVRMOD | |
Anna Bridge |
186:707f6e361f3e | 477 | ADC_CFGR1_AUTDLY | |
Anna Bridge |
186:707f6e361f3e | 478 | ADC_CFGR1_AUTOFF | |
Anna Bridge |
186:707f6e361f3e | 479 | ADC_CFGR1_DISCEN ); |
<> | 144:ef7eb2e8f9f7 | 480 | |
<> | 144:ef7eb2e8f9f7 | 481 | hadc->Instance->CFGR1 |= (hadc->Init.DataAlign | |
<> | 144:ef7eb2e8f9f7 | 482 | ADC_SCANDIR(hadc->Init.ScanConvMode) | |
Anna Bridge |
186:707f6e361f3e | 483 | ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) | |
<> | 144:ef7eb2e8f9f7 | 484 | ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) | |
<> | 144:ef7eb2e8f9f7 | 485 | hadc->Init.Overrun | |
<> | 144:ef7eb2e8f9f7 | 486 | __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) | |
<> | 144:ef7eb2e8f9f7 | 487 | __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff)); |
<> | 144:ef7eb2e8f9f7 | 488 | |
<> | 144:ef7eb2e8f9f7 | 489 | /* Enable external trigger if trigger selection is different of software */ |
<> | 144:ef7eb2e8f9f7 | 490 | /* start. */ |
<> | 144:ef7eb2e8f9f7 | 491 | /* Note: This configuration keeps the hardware feature of parameter */ |
<> | 144:ef7eb2e8f9f7 | 492 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
<> | 144:ef7eb2e8f9f7 | 493 | /* software start. */ |
<> | 144:ef7eb2e8f9f7 | 494 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
<> | 144:ef7eb2e8f9f7 | 495 | { |
<> | 144:ef7eb2e8f9f7 | 496 | hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv | |
<> | 144:ef7eb2e8f9f7 | 497 | hadc->Init.ExternalTrigConvEdge; |
<> | 144:ef7eb2e8f9f7 | 498 | } |
<> | 144:ef7eb2e8f9f7 | 499 | |
<> | 144:ef7eb2e8f9f7 | 500 | /* Enable discontinuous mode only if continuous mode is disabled */ |
<> | 144:ef7eb2e8f9f7 | 501 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 502 | { |
<> | 144:ef7eb2e8f9f7 | 503 | if (hadc->Init.ContinuousConvMode == DISABLE) |
<> | 144:ef7eb2e8f9f7 | 504 | { |
<> | 144:ef7eb2e8f9f7 | 505 | /* Enable the selected ADC group regular discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 506 | hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN); |
<> | 144:ef7eb2e8f9f7 | 507 | } |
<> | 144:ef7eb2e8f9f7 | 508 | else |
<> | 144:ef7eb2e8f9f7 | 509 | { |
<> | 144:ef7eb2e8f9f7 | 510 | /* ADC regular group discontinuous was intended to be enabled, */ |
<> | 144:ef7eb2e8f9f7 | 511 | /* but ADC regular group modes continuous and sequencer discontinuous */ |
<> | 144:ef7eb2e8f9f7 | 512 | /* cannot be enabled simultaneously. */ |
<> | 144:ef7eb2e8f9f7 | 513 | |
<> | 144:ef7eb2e8f9f7 | 514 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 515 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 516 | |
<> | 144:ef7eb2e8f9f7 | 517 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 518 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 519 | } |
<> | 144:ef7eb2e8f9f7 | 520 | } |
<> | 144:ef7eb2e8f9f7 | 521 | |
<> | 144:ef7eb2e8f9f7 | 522 | if (hadc->Init.OversamplingMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 523 | { |
<> | 144:ef7eb2e8f9f7 | 524 | assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversample.Ratio)); |
<> | 144:ef7eb2e8f9f7 | 525 | assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversample.RightBitShift)); |
<> | 144:ef7eb2e8f9f7 | 526 | assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversample.TriggeredMode)); |
<> | 144:ef7eb2e8f9f7 | 527 | |
<> | 144:ef7eb2e8f9f7 | 528 | /* Configuration of Oversampler: */ |
<> | 144:ef7eb2e8f9f7 | 529 | /* - Oversampling Ratio */ |
<> | 144:ef7eb2e8f9f7 | 530 | /* - Right bit shift */ |
<> | 144:ef7eb2e8f9f7 | 531 | /* - Triggered mode */ |
<> | 144:ef7eb2e8f9f7 | 532 | |
<> | 144:ef7eb2e8f9f7 | 533 | hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR | |
<> | 144:ef7eb2e8f9f7 | 534 | ADC_CFGR2_OVSS | |
<> | 144:ef7eb2e8f9f7 | 535 | ADC_CFGR2_TOVS ); |
<> | 144:ef7eb2e8f9f7 | 536 | |
<> | 144:ef7eb2e8f9f7 | 537 | hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio | |
<> | 144:ef7eb2e8f9f7 | 538 | hadc->Init.Oversample.RightBitShift | |
<> | 144:ef7eb2e8f9f7 | 539 | hadc->Init.Oversample.TriggeredMode ); |
<> | 144:ef7eb2e8f9f7 | 540 | |
<> | 144:ef7eb2e8f9f7 | 541 | /* Enable OverSampling mode */ |
<> | 144:ef7eb2e8f9f7 | 542 | hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE; |
<> | 144:ef7eb2e8f9f7 | 543 | } |
<> | 144:ef7eb2e8f9f7 | 544 | else |
<> | 144:ef7eb2e8f9f7 | 545 | { |
<> | 144:ef7eb2e8f9f7 | 546 | if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE)) |
<> | 144:ef7eb2e8f9f7 | 547 | { |
<> | 144:ef7eb2e8f9f7 | 548 | /* Disable OverSampling mode if needed */ |
<> | 144:ef7eb2e8f9f7 | 549 | hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE; |
<> | 144:ef7eb2e8f9f7 | 550 | } |
<> | 144:ef7eb2e8f9f7 | 551 | } |
<> | 144:ef7eb2e8f9f7 | 552 | |
<> | 144:ef7eb2e8f9f7 | 553 | /* Clear the old sampling time */ |
<> | 144:ef7eb2e8f9f7 | 554 | hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR); |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | /* Set the new sample time */ |
<> | 144:ef7eb2e8f9f7 | 557 | hadc->Instance->SMPR |= hadc->Init.SamplingTime; |
<> | 144:ef7eb2e8f9f7 | 558 | |
<> | 144:ef7eb2e8f9f7 | 559 | /* Clear ADC error code */ |
<> | 144:ef7eb2e8f9f7 | 560 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 561 | |
<> | 144:ef7eb2e8f9f7 | 562 | /* Set the ADC state */ |
<> | 144:ef7eb2e8f9f7 | 563 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 564 | HAL_ADC_STATE_BUSY_INTERNAL, |
<> | 144:ef7eb2e8f9f7 | 565 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 566 | |
<> | 144:ef7eb2e8f9f7 | 567 | |
<> | 144:ef7eb2e8f9f7 | 568 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 569 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 570 | } |
<> | 144:ef7eb2e8f9f7 | 571 | |
<> | 144:ef7eb2e8f9f7 | 572 | /** |
<> | 144:ef7eb2e8f9f7 | 573 | * @brief Deinitialize the ADC peripheral registers to their default reset |
<> | 144:ef7eb2e8f9f7 | 574 | * values, with deinitialization of the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 575 | * @note For devices with several ADCs: reset of ADC common registers is done |
<> | 144:ef7eb2e8f9f7 | 576 | * only if all ADCs sharing the same common group are disabled. |
<> | 144:ef7eb2e8f9f7 | 577 | * If this is not the case, reset of these common parameters reset is |
<> | 151:5eaa88a5bcc7 | 578 | * bypassed without error reporting: it can be the intended behavior in |
<> | 144:ef7eb2e8f9f7 | 579 | * case of reset of a single ADC while the other ADCs sharing the same |
<> | 144:ef7eb2e8f9f7 | 580 | * common group is still running. |
<> | 144:ef7eb2e8f9f7 | 581 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 582 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 583 | */ |
<> | 144:ef7eb2e8f9f7 | 584 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 585 | { |
<> | 144:ef7eb2e8f9f7 | 586 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 587 | |
<> | 144:ef7eb2e8f9f7 | 588 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 589 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 590 | { |
Anna Bridge |
186:707f6e361f3e | 591 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 592 | } |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 595 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 596 | |
<> | 144:ef7eb2e8f9f7 | 597 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 598 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | /* Stop potential conversion on going, on regular group */ |
<> | 144:ef7eb2e8f9f7 | 601 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 604 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 605 | { |
<> | 144:ef7eb2e8f9f7 | 606 | /* Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 607 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 608 | |
<> | 144:ef7eb2e8f9f7 | 609 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 610 | if (tmp_hal_status != HAL_ERROR) |
<> | 144:ef7eb2e8f9f7 | 611 | { |
<> | 144:ef7eb2e8f9f7 | 612 | /* Change ADC state */ |
<> | 144:ef7eb2e8f9f7 | 613 | hadc->State = HAL_ADC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 614 | } |
Anna Bridge |
186:707f6e361f3e | 615 | } |
<> | 144:ef7eb2e8f9f7 | 616 | |
<> | 144:ef7eb2e8f9f7 | 617 | |
<> | 144:ef7eb2e8f9f7 | 618 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 619 | /* correctly completed. */ |
<> | 144:ef7eb2e8f9f7 | 620 | if (tmp_hal_status != HAL_ERROR) |
<> | 144:ef7eb2e8f9f7 | 621 | { |
<> | 144:ef7eb2e8f9f7 | 622 | |
<> | 144:ef7eb2e8f9f7 | 623 | /* ========== Reset ADC registers ========== */ |
<> | 144:ef7eb2e8f9f7 | 624 | /* Reset register IER */ |
<> | 144:ef7eb2e8f9f7 | 625 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS | \ |
<> | 144:ef7eb2e8f9f7 | 626 | ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP )); |
<> | 144:ef7eb2e8f9f7 | 627 | |
<> | 144:ef7eb2e8f9f7 | 628 | |
<> | 144:ef7eb2e8f9f7 | 629 | /* Reset register ISR */ |
<> | 144:ef7eb2e8f9f7 | 630 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS | \ |
<> | 144:ef7eb2e8f9f7 | 631 | ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); |
<> | 144:ef7eb2e8f9f7 | 632 | |
<> | 144:ef7eb2e8f9f7 | 633 | |
<> | 144:ef7eb2e8f9f7 | 634 | /* Reset register CR */ |
<> | 144:ef7eb2e8f9f7 | 635 | /* Disable voltage regulator */ |
<> | 144:ef7eb2e8f9f7 | 636 | /* Note: Regulator disable useful for power saving */ |
<> | 144:ef7eb2e8f9f7 | 637 | /* Reset ADVREGEN bit */ |
<> | 144:ef7eb2e8f9f7 | 638 | hadc->Instance->CR &= ~ADC_CR_ADVREGEN; |
<> | 144:ef7eb2e8f9f7 | 639 | |
<> | 144:ef7eb2e8f9f7 | 640 | /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable */ |
<> | 144:ef7eb2e8f9f7 | 641 | /* No action */ |
<> | 144:ef7eb2e8f9f7 | 642 | |
<> | 144:ef7eb2e8f9f7 | 643 | /* Reset register CFGR1 */ |
<> | 144:ef7eb2e8f9f7 | 644 | hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | \ |
<> | 144:ef7eb2e8f9f7 | 645 | ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \ |
<> | 144:ef7eb2e8f9f7 | 646 | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | \ |
<> | 144:ef7eb2e8f9f7 | 647 | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | \ |
<> | 144:ef7eb2e8f9f7 | 648 | ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN); |
<> | 144:ef7eb2e8f9f7 | 649 | |
<> | 144:ef7eb2e8f9f7 | 650 | /* Reset register CFGR2 */ |
<> | 144:ef7eb2e8f9f7 | 651 | hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | \ |
<> | 144:ef7eb2e8f9f7 | 652 | ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE ); |
<> | 144:ef7eb2e8f9f7 | 653 | |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | /* Reset register SMPR */ |
<> | 144:ef7eb2e8f9f7 | 656 | hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR); |
<> | 144:ef7eb2e8f9f7 | 657 | |
<> | 144:ef7eb2e8f9f7 | 658 | /* Reset register TR */ |
<> | 144:ef7eb2e8f9f7 | 659 | hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT); |
<> | 144:ef7eb2e8f9f7 | 660 | |
<> | 144:ef7eb2e8f9f7 | 661 | /* Reset register CALFACT */ |
<> | 144:ef7eb2e8f9f7 | 662 | hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT); |
<> | 144:ef7eb2e8f9f7 | 663 | |
<> | 144:ef7eb2e8f9f7 | 664 | |
<> | 144:ef7eb2e8f9f7 | 665 | |
<> | 144:ef7eb2e8f9f7 | 666 | |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | /* Reset register DR */ |
<> | 144:ef7eb2e8f9f7 | 669 | /* bits in access mode read only, no direct reset applicable*/ |
<> | 144:ef7eb2e8f9f7 | 670 | |
<> | 144:ef7eb2e8f9f7 | 671 | /* Reset register CALFACT */ |
<> | 144:ef7eb2e8f9f7 | 672 | hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT); |
<> | 144:ef7eb2e8f9f7 | 673 | |
<> | 144:ef7eb2e8f9f7 | 674 | /* ========== Hard reset ADC peripheral ========== */ |
<> | 144:ef7eb2e8f9f7 | 675 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
<> | 144:ef7eb2e8f9f7 | 676 | /* forced to a similar state after device power-on. */ |
<> | 144:ef7eb2e8f9f7 | 677 | /* If needed, copy-paste and uncomment the following reset code into */ |
<> | 144:ef7eb2e8f9f7 | 678 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
<> | 144:ef7eb2e8f9f7 | 679 | /* */ |
<> | 144:ef7eb2e8f9f7 | 680 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
<> | 144:ef7eb2e8f9f7 | 681 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | /* DeInit the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 684 | HAL_ADC_MspDeInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 685 | |
<> | 144:ef7eb2e8f9f7 | 686 | /* Set ADC error code to none */ |
<> | 144:ef7eb2e8f9f7 | 687 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 688 | |
Anna Bridge |
186:707f6e361f3e | 689 | /* Set ADC state */ |
Anna Bridge |
186:707f6e361f3e | 690 | hadc->State = HAL_ADC_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 691 | } |
<> | 144:ef7eb2e8f9f7 | 692 | |
<> | 144:ef7eb2e8f9f7 | 693 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 694 | __HAL_UNLOCK(hadc); |
Anna Bridge |
186:707f6e361f3e | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 697 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 698 | } |
<> | 144:ef7eb2e8f9f7 | 699 | |
<> | 144:ef7eb2e8f9f7 | 700 | /** |
Anna Bridge |
186:707f6e361f3e | 701 | * @brief Initialize the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 702 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 703 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 704 | */ |
<> | 144:ef7eb2e8f9f7 | 705 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 706 | { |
<> | 144:ef7eb2e8f9f7 | 707 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 708 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 709 | |
Anna Bridge |
186:707f6e361f3e | 710 | /* NOTE : This function should not be modified. When the callback is needed, |
Anna Bridge |
186:707f6e361f3e | 711 | function HAL_ADC_MspInit must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 712 | */ |
<> | 144:ef7eb2e8f9f7 | 713 | } |
<> | 144:ef7eb2e8f9f7 | 714 | |
<> | 144:ef7eb2e8f9f7 | 715 | /** |
Anna Bridge |
186:707f6e361f3e | 716 | * @brief DeInitialize the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 717 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 718 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 719 | */ |
<> | 144:ef7eb2e8f9f7 | 720 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 721 | { |
<> | 144:ef7eb2e8f9f7 | 722 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 723 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 724 | |
<> | 144:ef7eb2e8f9f7 | 725 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 726 | function HAL_ADC_MspDeInit must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 727 | */ |
<> | 144:ef7eb2e8f9f7 | 728 | } |
<> | 144:ef7eb2e8f9f7 | 729 | |
<> | 144:ef7eb2e8f9f7 | 730 | /** |
<> | 144:ef7eb2e8f9f7 | 731 | * @} |
<> | 144:ef7eb2e8f9f7 | 732 | */ |
<> | 144:ef7eb2e8f9f7 | 733 | |
Anna Bridge |
186:707f6e361f3e | 734 | /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions |
Anna Bridge |
186:707f6e361f3e | 735 | * @brief ADC IO operation functions |
<> | 144:ef7eb2e8f9f7 | 736 | * |
<> | 144:ef7eb2e8f9f7 | 737 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 738 | =============================================================================== |
Anna Bridge |
186:707f6e361f3e | 739 | ##### IO operation functions ##### |
Anna Bridge |
186:707f6e361f3e | 740 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 741 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 742 | (+) Start conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 743 | (+) Stop conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 744 | (+) Poll for conversion complete on regular group. |
Anna Bridge |
186:707f6e361f3e | 745 | (+) Poll for conversion event. |
<> | 144:ef7eb2e8f9f7 | 746 | (+) Get result of regular channel conversion. |
<> | 144:ef7eb2e8f9f7 | 747 | (+) Start conversion of regular group and enable interruptions. |
<> | 144:ef7eb2e8f9f7 | 748 | (+) Stop conversion of regular group and disable interruptions. |
<> | 144:ef7eb2e8f9f7 | 749 | (+) Handle ADC interrupt request |
<> | 144:ef7eb2e8f9f7 | 750 | (+) Start conversion of regular group and enable DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 751 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 752 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 753 | * @{ |
<> | 144:ef7eb2e8f9f7 | 754 | */ |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /** |
Anna Bridge |
186:707f6e361f3e | 757 | * @brief Enable ADC, start conversion of regular group. |
Anna Bridge |
186:707f6e361f3e | 758 | * @note Interruptions enabled in this function: None. |
<> | 144:ef7eb2e8f9f7 | 759 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 760 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 761 | */ |
<> | 144:ef7eb2e8f9f7 | 762 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 763 | { |
<> | 144:ef7eb2e8f9f7 | 764 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 767 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 768 | |
<> | 144:ef7eb2e8f9f7 | 769 | /* Perform ADC enable and conversion start if no conversion is on going */ |
<> | 144:ef7eb2e8f9f7 | 770 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 771 | { |
<> | 144:ef7eb2e8f9f7 | 772 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 773 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 774 | |
<> | 144:ef7eb2e8f9f7 | 775 | /* Enable the ADC peripheral */ |
Anna Bridge |
186:707f6e361f3e | 776 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
Anna Bridge |
186:707f6e361f3e | 777 | /* performed automatically by hardware. */ |
<> | 144:ef7eb2e8f9f7 | 778 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
<> | 144:ef7eb2e8f9f7 | 779 | { |
<> | 144:ef7eb2e8f9f7 | 780 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 781 | } |
<> | 144:ef7eb2e8f9f7 | 782 | |
<> | 144:ef7eb2e8f9f7 | 783 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 784 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 785 | { |
<> | 144:ef7eb2e8f9f7 | 786 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 787 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 788 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 789 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 790 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 791 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 792 | |
<> | 144:ef7eb2e8f9f7 | 793 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 794 | ADC_CLEAR_ERRORCODE(hadc); |
Anna Bridge |
186:707f6e361f3e | 795 | |
Anna Bridge |
186:707f6e361f3e | 796 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 797 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 798 | /* interruption, to let the process to ADC IRQ Handler. */ |
Anna Bridge |
186:707f6e361f3e | 799 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 800 | |
<> | 144:ef7eb2e8f9f7 | 801 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 802 | /* (To ensure of no unknown state from potential previous ADC */ |
<> | 144:ef7eb2e8f9f7 | 803 | /* operations) */ |
<> | 144:ef7eb2e8f9f7 | 804 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
<> | 144:ef7eb2e8f9f7 | 805 | |
<> | 144:ef7eb2e8f9f7 | 806 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 807 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 808 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 809 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 810 | hadc->Instance->CR |= ADC_CR_ADSTART; |
<> | 144:ef7eb2e8f9f7 | 811 | } |
<> | 144:ef7eb2e8f9f7 | 812 | } |
<> | 144:ef7eb2e8f9f7 | 813 | else |
<> | 144:ef7eb2e8f9f7 | 814 | { |
<> | 144:ef7eb2e8f9f7 | 815 | tmp_hal_status = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 816 | } |
<> | 144:ef7eb2e8f9f7 | 817 | |
<> | 144:ef7eb2e8f9f7 | 818 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 819 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 820 | } |
<> | 144:ef7eb2e8f9f7 | 821 | |
<> | 144:ef7eb2e8f9f7 | 822 | /** |
Anna Bridge |
186:707f6e361f3e | 823 | * @brief Stop ADC conversion of regular group (and injected channels in |
Anna Bridge |
186:707f6e361f3e | 824 | * case of auto_injection mode), disable ADC peripheral. |
<> | 144:ef7eb2e8f9f7 | 825 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 826 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 827 | */ |
<> | 144:ef7eb2e8f9f7 | 828 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 829 | { |
<> | 144:ef7eb2e8f9f7 | 830 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 831 | |
<> | 144:ef7eb2e8f9f7 | 832 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 833 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 834 | |
<> | 144:ef7eb2e8f9f7 | 835 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 836 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 837 | |
Anna Bridge |
186:707f6e361f3e | 838 | /* 1. Stop potential conversion on going, on ADC group regular */ |
<> | 144:ef7eb2e8f9f7 | 839 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 840 | |
<> | 144:ef7eb2e8f9f7 | 841 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 842 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 843 | { |
<> | 144:ef7eb2e8f9f7 | 844 | /* 2. Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 845 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 846 | |
<> | 144:ef7eb2e8f9f7 | 847 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 848 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 849 | { |
<> | 144:ef7eb2e8f9f7 | 850 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 851 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 852 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 853 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 854 | } |
Anna Bridge |
186:707f6e361f3e | 855 | } |
<> | 144:ef7eb2e8f9f7 | 856 | |
<> | 144:ef7eb2e8f9f7 | 857 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 858 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 859 | |
<> | 144:ef7eb2e8f9f7 | 860 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 861 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 862 | } |
<> | 144:ef7eb2e8f9f7 | 863 | |
<> | 144:ef7eb2e8f9f7 | 864 | /** |
<> | 144:ef7eb2e8f9f7 | 865 | * @brief Wait for regular group conversion to be completed. |
<> | 144:ef7eb2e8f9f7 | 866 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
<> | 144:ef7eb2e8f9f7 | 867 | * conversion) are cleared by this function, with an exception: |
<> | 144:ef7eb2e8f9f7 | 868 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
<> | 144:ef7eb2e8f9f7 | 869 | * not cleared to not interfere with this feature until data register |
<> | 144:ef7eb2e8f9f7 | 870 | * is read using function HAL_ADC_GetValue(). |
<> | 144:ef7eb2e8f9f7 | 871 | * @note This function cannot be used in a particular setup: ADC configured |
<> | 144:ef7eb2e8f9f7 | 872 | * in DMA mode and polling for end of each conversion (ADC init |
<> | 144:ef7eb2e8f9f7 | 873 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
<> | 144:ef7eb2e8f9f7 | 874 | * In this case, DMA resets the flag EOC and polling cannot be |
<> | 144:ef7eb2e8f9f7 | 875 | * performed on each conversion. Nevertheless, polling can still |
<> | 144:ef7eb2e8f9f7 | 876 | * be performed on the complete sequence (ADC init |
<> | 144:ef7eb2e8f9f7 | 877 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
<> | 144:ef7eb2e8f9f7 | 878 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 879 | * @param Timeout: Timeout value in millisecond. |
<> | 144:ef7eb2e8f9f7 | 880 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 881 | */ |
<> | 144:ef7eb2e8f9f7 | 882 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 883 | { |
Anna Bridge |
186:707f6e361f3e | 884 | uint32_t tickstart = 0; |
Anna Bridge |
186:707f6e361f3e | 885 | uint32_t tmp_Flag_EOC = 0x00; |
Anna Bridge |
186:707f6e361f3e | 886 | |
<> | 144:ef7eb2e8f9f7 | 887 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 888 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
Anna Bridge |
186:707f6e361f3e | 889 | |
Anna Bridge |
186:707f6e361f3e | 890 | /* If end of conversion selected to end of sequence conversions */ |
<> | 144:ef7eb2e8f9f7 | 891 | if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) |
<> | 144:ef7eb2e8f9f7 | 892 | { |
<> | 144:ef7eb2e8f9f7 | 893 | tmp_Flag_EOC = ADC_FLAG_EOS; |
<> | 144:ef7eb2e8f9f7 | 894 | } |
Anna Bridge |
186:707f6e361f3e | 895 | /* If end of conversion selected to end of unitary conversion */ |
<> | 144:ef7eb2e8f9f7 | 896 | else /* ADC_EOC_SINGLE_CONV */ |
<> | 144:ef7eb2e8f9f7 | 897 | { |
<> | 144:ef7eb2e8f9f7 | 898 | /* Verification that ADC configuration is compliant with polling for */ |
<> | 144:ef7eb2e8f9f7 | 899 | /* each conversion: */ |
<> | 144:ef7eb2e8f9f7 | 900 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
<> | 144:ef7eb2e8f9f7 | 901 | /* several ranks and polling for end of each conversion. */ |
<> | 144:ef7eb2e8f9f7 | 902 | /* For code simplicity sake, this particular case is generalized to */ |
<> | 144:ef7eb2e8f9f7 | 903 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
<> | 144:ef7eb2e8f9f7 | 904 | if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) |
<> | 144:ef7eb2e8f9f7 | 905 | { |
<> | 144:ef7eb2e8f9f7 | 906 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 907 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 908 | |
<> | 144:ef7eb2e8f9f7 | 909 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 910 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 911 | |
<> | 144:ef7eb2e8f9f7 | 912 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 913 | } |
<> | 144:ef7eb2e8f9f7 | 914 | else |
<> | 144:ef7eb2e8f9f7 | 915 | { |
<> | 144:ef7eb2e8f9f7 | 916 | tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); |
<> | 144:ef7eb2e8f9f7 | 917 | } |
<> | 144:ef7eb2e8f9f7 | 918 | } |
<> | 144:ef7eb2e8f9f7 | 919 | |
<> | 144:ef7eb2e8f9f7 | 920 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 921 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 922 | |
Anna Bridge |
186:707f6e361f3e | 923 | /* Wait until End of unitary conversion or sequence conversions flag is raised */ |
<> | 144:ef7eb2e8f9f7 | 924 | while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) |
<> | 144:ef7eb2e8f9f7 | 925 | { |
<> | 144:ef7eb2e8f9f7 | 926 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 927 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 928 | { |
<> | 151:5eaa88a5bcc7 | 929 | if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 930 | { |
<> | 144:ef7eb2e8f9f7 | 931 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 932 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 933 | |
<> | 144:ef7eb2e8f9f7 | 934 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 935 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 936 | |
<> | 144:ef7eb2e8f9f7 | 937 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 938 | } |
<> | 144:ef7eb2e8f9f7 | 939 | } |
<> | 144:ef7eb2e8f9f7 | 940 | } |
<> | 144:ef7eb2e8f9f7 | 941 | |
<> | 144:ef7eb2e8f9f7 | 942 | /* Update ADC state machine */ |
<> | 144:ef7eb2e8f9f7 | 943 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 944 | |
<> | 144:ef7eb2e8f9f7 | 945 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 946 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 947 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 948 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 949 | { |
<> | 144:ef7eb2e8f9f7 | 950 | /* If End of Sequence is reached, disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 951 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
<> | 144:ef7eb2e8f9f7 | 952 | { |
<> | 144:ef7eb2e8f9f7 | 953 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
<> | 144:ef7eb2e8f9f7 | 954 | /* ADSTART==0 (no conversion on going) */ |
<> | 144:ef7eb2e8f9f7 | 955 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 956 | { |
<> | 144:ef7eb2e8f9f7 | 957 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 958 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 959 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 960 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 961 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
<> | 144:ef7eb2e8f9f7 | 962 | |
<> | 144:ef7eb2e8f9f7 | 963 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 964 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 965 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 966 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 967 | } |
<> | 144:ef7eb2e8f9f7 | 968 | else |
<> | 144:ef7eb2e8f9f7 | 969 | { |
<> | 144:ef7eb2e8f9f7 | 970 | /* Change ADC state to error state */ |
<> | 144:ef7eb2e8f9f7 | 971 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 972 | |
<> | 144:ef7eb2e8f9f7 | 973 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 974 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 975 | } |
<> | 144:ef7eb2e8f9f7 | 976 | } |
<> | 144:ef7eb2e8f9f7 | 977 | } |
<> | 144:ef7eb2e8f9f7 | 978 | |
<> | 144:ef7eb2e8f9f7 | 979 | /* Clear end of conversion flag of regular group if low power feature */ |
<> | 144:ef7eb2e8f9f7 | 980 | /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ |
<> | 144:ef7eb2e8f9f7 | 981 | /* until data register is read using function HAL_ADC_GetValue(). */ |
<> | 144:ef7eb2e8f9f7 | 982 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
<> | 144:ef7eb2e8f9f7 | 983 | { |
<> | 144:ef7eb2e8f9f7 | 984 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 985 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); |
<> | 144:ef7eb2e8f9f7 | 986 | } |
<> | 144:ef7eb2e8f9f7 | 987 | |
Anna Bridge |
186:707f6e361f3e | 988 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 989 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 990 | } |
<> | 144:ef7eb2e8f9f7 | 991 | |
<> | 144:ef7eb2e8f9f7 | 992 | /** |
Anna Bridge |
186:707f6e361f3e | 993 | * @brief Poll for ADC event. |
<> | 144:ef7eb2e8f9f7 | 994 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 995 | * @param EventType: the ADC event type. |
<> | 144:ef7eb2e8f9f7 | 996 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 997 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event |
<> | 144:ef7eb2e8f9f7 | 998 | * @arg ADC_OVR_EVENT: ADC Overrun event |
<> | 144:ef7eb2e8f9f7 | 999 | * @param Timeout: Timeout value in millisecond. |
Anna Bridge |
186:707f6e361f3e | 1000 | * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. |
Anna Bridge |
186:707f6e361f3e | 1001 | * Indeed, the latter is reset only if hadc->Init.Overrun field is set |
Anna Bridge |
186:707f6e361f3e | 1002 | * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten |
Anna Bridge |
186:707f6e361f3e | 1003 | * by a new converted data as soon as OVR is cleared. |
Anna Bridge |
186:707f6e361f3e | 1004 | * To reset OVR flag once the preserved data is retrieved, the user can resort |
Anna Bridge |
186:707f6e361f3e | 1005 | * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1006 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1007 | */ |
<> | 144:ef7eb2e8f9f7 | 1008 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1009 | { |
<> | 151:5eaa88a5bcc7 | 1010 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1011 | |
<> | 144:ef7eb2e8f9f7 | 1012 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1013 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1014 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
<> | 144:ef7eb2e8f9f7 | 1015 | |
<> | 144:ef7eb2e8f9f7 | 1016 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 1017 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1018 | |
<> | 144:ef7eb2e8f9f7 | 1019 | /* Check selected event flag */ |
<> | 144:ef7eb2e8f9f7 | 1020 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1021 | { |
<> | 144:ef7eb2e8f9f7 | 1022 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 1023 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1024 | { |
Anna Bridge |
186:707f6e361f3e | 1025 | if((Timeout == 0U) ||((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1026 | { |
<> | 144:ef7eb2e8f9f7 | 1027 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 1028 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 144:ef7eb2e8f9f7 | 1030 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1031 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1032 | |
<> | 144:ef7eb2e8f9f7 | 1033 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1034 | } |
<> | 144:ef7eb2e8f9f7 | 1035 | } |
<> | 144:ef7eb2e8f9f7 | 1036 | } |
<> | 144:ef7eb2e8f9f7 | 1037 | |
<> | 144:ef7eb2e8f9f7 | 1038 | switch(EventType) |
<> | 144:ef7eb2e8f9f7 | 1039 | { |
<> | 144:ef7eb2e8f9f7 | 1040 | /* Analog watchdog (level out of window) event */ |
<> | 144:ef7eb2e8f9f7 | 1041 | case ADC_AWD_EVENT: |
<> | 144:ef7eb2e8f9f7 | 1042 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1043 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 1044 | |
<> | 144:ef7eb2e8f9f7 | 1045 | /* Clear ADC analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 1046 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 1047 | break; |
<> | 144:ef7eb2e8f9f7 | 1048 | |
<> | 144:ef7eb2e8f9f7 | 1049 | /* Overrun event */ |
<> | 144:ef7eb2e8f9f7 | 1050 | default: /* Case ADC_OVR_EVENT */ |
<> | 144:ef7eb2e8f9f7 | 1051 | /* If overrun is set to overwrite previous data, overrun event is not */ |
<> | 144:ef7eb2e8f9f7 | 1052 | /* considered as an error. */ |
<> | 144:ef7eb2e8f9f7 | 1053 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
<> | 144:ef7eb2e8f9f7 | 1054 | /* overrun ") */ |
<> | 144:ef7eb2e8f9f7 | 1055 | if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) |
<> | 144:ef7eb2e8f9f7 | 1056 | { |
<> | 144:ef7eb2e8f9f7 | 1057 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1058 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1059 | |
<> | 144:ef7eb2e8f9f7 | 1060 | /* Set ADC error code to overrun */ |
<> | 144:ef7eb2e8f9f7 | 1061 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
<> | 144:ef7eb2e8f9f7 | 1062 | } |
<> | 144:ef7eb2e8f9f7 | 1063 | |
<> | 144:ef7eb2e8f9f7 | 1064 | /* Clear ADC Overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1065 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1066 | break; |
<> | 144:ef7eb2e8f9f7 | 1067 | } |
<> | 144:ef7eb2e8f9f7 | 1068 | |
Anna Bridge |
186:707f6e361f3e | 1069 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1070 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1071 | } |
<> | 144:ef7eb2e8f9f7 | 1072 | |
<> | 144:ef7eb2e8f9f7 | 1073 | /** |
Anna Bridge |
186:707f6e361f3e | 1074 | * @brief Enable ADC, start conversion of regular group with interruption. |
Anna Bridge |
186:707f6e361f3e | 1075 | * @note Interruptions enabled in this function according to initialization |
Anna Bridge |
186:707f6e361f3e | 1076 | * setting : EOC (end of conversion), EOS (end of sequence), |
Anna Bridge |
186:707f6e361f3e | 1077 | * OVR overrun. |
<> | 144:ef7eb2e8f9f7 | 1078 | * Each of these interruptions has its dedicated callback function. |
Anna Bridge |
186:707f6e361f3e | 1079 | * @note To guarantee a proper reset of all interruptions once all the needed |
Anna Bridge |
186:707f6e361f3e | 1080 | * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure |
Anna Bridge |
186:707f6e361f3e | 1081 | * a correct stop of the IT-based conversions. |
Anna Bridge |
186:707f6e361f3e | 1082 | * @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling |
Anna Bridge |
186:707f6e361f3e | 1083 | * interruption. If required (e.g. in case of oversampling with trigger |
Anna Bridge |
186:707f6e361f3e | 1084 | * mode), the user must: |
Anna Bridge |
186:707f6e361f3e | 1085 | * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) |
Anna Bridge |
186:707f6e361f3e | 1086 | * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) |
Anna Bridge |
186:707f6e361f3e | 1087 | * before calling HAL_ADC_Start_IT(). |
<> | 144:ef7eb2e8f9f7 | 1088 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1089 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1090 | */ |
<> | 144:ef7eb2e8f9f7 | 1091 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1092 | { |
<> | 144:ef7eb2e8f9f7 | 1093 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
Anna Bridge |
186:707f6e361f3e | 1094 | |
<> | 144:ef7eb2e8f9f7 | 1095 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1096 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1097 | |
<> | 144:ef7eb2e8f9f7 | 1098 | /* Perform ADC enable and conversion start if no conversion is on going */ |
<> | 144:ef7eb2e8f9f7 | 1099 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1100 | { |
<> | 144:ef7eb2e8f9f7 | 1101 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1102 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1103 | |
<> | 144:ef7eb2e8f9f7 | 1104 | /* Enable the ADC peripheral */ |
Anna Bridge |
186:707f6e361f3e | 1105 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
Anna Bridge |
186:707f6e361f3e | 1106 | /* performed automatically by hardware. */ |
<> | 144:ef7eb2e8f9f7 | 1107 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1108 | { |
<> | 144:ef7eb2e8f9f7 | 1109 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1110 | } |
<> | 144:ef7eb2e8f9f7 | 1111 | |
<> | 144:ef7eb2e8f9f7 | 1112 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1113 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1114 | { |
<> | 144:ef7eb2e8f9f7 | 1115 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1116 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 1117 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 1118 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1119 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 1120 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1121 | |
<> | 144:ef7eb2e8f9f7 | 1122 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 1123 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1124 | |
<> | 144:ef7eb2e8f9f7 | 1125 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1126 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 1127 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 1128 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1129 | |
<> | 144:ef7eb2e8f9f7 | 1130 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1131 | /* (To ensure of no unknown state from potential previous ADC */ |
<> | 144:ef7eb2e8f9f7 | 1132 | /* operations) */ |
<> | 144:ef7eb2e8f9f7 | 1133 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1134 | |
<> | 144:ef7eb2e8f9f7 | 1135 | /* Enable ADC end of conversion interrupt */ |
Anna Bridge |
186:707f6e361f3e | 1136 | /* Enable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1137 | switch(hadc->Init.EOCSelection) |
<> | 144:ef7eb2e8f9f7 | 1138 | { |
<> | 144:ef7eb2e8f9f7 | 1139 | case ADC_EOC_SEQ_CONV: |
<> | 144:ef7eb2e8f9f7 | 1140 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 1141 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1142 | break; |
<> | 144:ef7eb2e8f9f7 | 1143 | /* case ADC_EOC_SINGLE_CONV */ |
<> | 144:ef7eb2e8f9f7 | 1144 | default: |
<> | 144:ef7eb2e8f9f7 | 1145 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1146 | break; |
<> | 144:ef7eb2e8f9f7 | 1147 | } |
<> | 144:ef7eb2e8f9f7 | 1148 | |
<> | 144:ef7eb2e8f9f7 | 1149 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 1150 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 1151 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 1152 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 1153 | hadc->Instance->CR |= ADC_CR_ADSTART; |
<> | 144:ef7eb2e8f9f7 | 1154 | } |
<> | 144:ef7eb2e8f9f7 | 1155 | } |
<> | 144:ef7eb2e8f9f7 | 1156 | else |
<> | 144:ef7eb2e8f9f7 | 1157 | { |
<> | 144:ef7eb2e8f9f7 | 1158 | tmp_hal_status = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1159 | } |
Anna Bridge |
186:707f6e361f3e | 1160 | |
<> | 144:ef7eb2e8f9f7 | 1161 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1162 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1163 | } |
<> | 144:ef7eb2e8f9f7 | 1164 | |
<> | 144:ef7eb2e8f9f7 | 1165 | /** |
Anna Bridge |
186:707f6e361f3e | 1166 | * @brief Stop ADC conversion of regular group (and injected group in |
Anna Bridge |
186:707f6e361f3e | 1167 | * case of auto_injection mode), disable interrution of |
<> | 144:ef7eb2e8f9f7 | 1168 | * end-of-conversion, disable ADC peripheral. |
<> | 144:ef7eb2e8f9f7 | 1169 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1170 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1171 | */ |
<> | 144:ef7eb2e8f9f7 | 1172 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1173 | { |
<> | 144:ef7eb2e8f9f7 | 1174 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1175 | |
<> | 144:ef7eb2e8f9f7 | 1176 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1177 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
Anna Bridge |
186:707f6e361f3e | 1178 | |
<> | 144:ef7eb2e8f9f7 | 1179 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1180 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1181 | |
Anna Bridge |
186:707f6e361f3e | 1182 | /* 1. Stop potential conversion on going, on ADC group regular */ |
<> | 144:ef7eb2e8f9f7 | 1183 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 1184 | |
<> | 144:ef7eb2e8f9f7 | 1185 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 1186 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1187 | { |
<> | 144:ef7eb2e8f9f7 | 1188 | /* Disable ADC end of conversion interrupt for regular group */ |
<> | 144:ef7eb2e8f9f7 | 1189 | /* Disable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1190 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1191 | |
<> | 144:ef7eb2e8f9f7 | 1192 | /* 2. Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1193 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1194 | |
<> | 144:ef7eb2e8f9f7 | 1195 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1196 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1197 | { |
<> | 144:ef7eb2e8f9f7 | 1198 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1199 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1200 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1201 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1202 | } |
<> | 144:ef7eb2e8f9f7 | 1203 | } |
<> | 144:ef7eb2e8f9f7 | 1204 | |
<> | 144:ef7eb2e8f9f7 | 1205 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1206 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1207 | |
<> | 144:ef7eb2e8f9f7 | 1208 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1209 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1210 | } |
<> | 144:ef7eb2e8f9f7 | 1211 | |
<> | 144:ef7eb2e8f9f7 | 1212 | /** |
Anna Bridge |
186:707f6e361f3e | 1213 | * @brief Enable ADC, start conversion of regular group and transfer result through DMA. |
Anna Bridge |
186:707f6e361f3e | 1214 | * @note Interruptions enabled in this function: |
Anna Bridge |
186:707f6e361f3e | 1215 | * overrun (if applicable), DMA half transfer, DMA transfer complete. |
<> | 144:ef7eb2e8f9f7 | 1216 | * Each of these interruptions has its dedicated callback function. |
<> | 144:ef7eb2e8f9f7 | 1217 | * @param hadc: ADC handle |
Anna Bridge |
186:707f6e361f3e | 1218 | * @param pData: Destination Buffer address. |
Anna Bridge |
186:707f6e361f3e | 1219 | * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes) |
Anna Bridge |
186:707f6e361f3e | 1220 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1221 | */ |
<> | 144:ef7eb2e8f9f7 | 1222 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
<> | 144:ef7eb2e8f9f7 | 1223 | { |
<> | 144:ef7eb2e8f9f7 | 1224 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1225 | |
<> | 144:ef7eb2e8f9f7 | 1226 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1227 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1228 | |
<> | 144:ef7eb2e8f9f7 | 1229 | /* Perform ADC enable and conversion start if no conversion is on going */ |
<> | 144:ef7eb2e8f9f7 | 1230 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1231 | { |
<> | 144:ef7eb2e8f9f7 | 1232 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1233 | __HAL_LOCK(hadc); |
Anna Bridge |
186:707f6e361f3e | 1234 | |
Anna Bridge |
186:707f6e361f3e | 1235 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1236 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
<> | 144:ef7eb2e8f9f7 | 1237 | /* performed automatically by hardware. */ |
<> | 144:ef7eb2e8f9f7 | 1238 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1239 | { |
<> | 144:ef7eb2e8f9f7 | 1240 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1241 | } |
<> | 144:ef7eb2e8f9f7 | 1242 | |
<> | 144:ef7eb2e8f9f7 | 1243 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1244 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1245 | { |
<> | 144:ef7eb2e8f9f7 | 1246 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1247 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 1248 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 1249 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1250 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 1251 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1252 | |
<> | 144:ef7eb2e8f9f7 | 1253 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 1254 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1255 | |
<> | 144:ef7eb2e8f9f7 | 1256 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1257 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 1258 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 1259 | __HAL_UNLOCK(hadc); |
Anna Bridge |
186:707f6e361f3e | 1260 | |
<> | 144:ef7eb2e8f9f7 | 1261 | /* Set the DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1262 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
Anna Bridge |
186:707f6e361f3e | 1263 | |
<> | 144:ef7eb2e8f9f7 | 1264 | /* Set the DMA half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1265 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
<> | 144:ef7eb2e8f9f7 | 1266 | |
<> | 144:ef7eb2e8f9f7 | 1267 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1268 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1269 | |
<> | 144:ef7eb2e8f9f7 | 1270 | |
<> | 144:ef7eb2e8f9f7 | 1271 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
<> | 144:ef7eb2e8f9f7 | 1272 | /* start (in case of SW start): */ |
<> | 144:ef7eb2e8f9f7 | 1273 | |
<> | 144:ef7eb2e8f9f7 | 1274 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1275 | /* (To ensure of no unknown state from potential previous ADC */ |
<> | 144:ef7eb2e8f9f7 | 1276 | /* operations) */ |
<> | 144:ef7eb2e8f9f7 | 1277 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1278 | |
<> | 144:ef7eb2e8f9f7 | 1279 | /* Enable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1280 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
<> | 144:ef7eb2e8f9f7 | 1281 | |
<> | 144:ef7eb2e8f9f7 | 1282 | /* Enable ADC DMA mode */ |
<> | 144:ef7eb2e8f9f7 | 1283 | hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; |
<> | 144:ef7eb2e8f9f7 | 1284 | |
<> | 144:ef7eb2e8f9f7 | 1285 | /* Start the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1286 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
Anna Bridge |
186:707f6e361f3e | 1287 | |
<> | 144:ef7eb2e8f9f7 | 1288 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 1289 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 1290 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 1291 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 1292 | hadc->Instance->CR |= ADC_CR_ADSTART; |
<> | 144:ef7eb2e8f9f7 | 1293 | } |
<> | 144:ef7eb2e8f9f7 | 1294 | } |
<> | 144:ef7eb2e8f9f7 | 1295 | else |
<> | 144:ef7eb2e8f9f7 | 1296 | { |
<> | 144:ef7eb2e8f9f7 | 1297 | tmp_hal_status = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1298 | } |
<> | 144:ef7eb2e8f9f7 | 1299 | |
<> | 144:ef7eb2e8f9f7 | 1300 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1301 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1302 | } |
<> | 144:ef7eb2e8f9f7 | 1303 | |
<> | 144:ef7eb2e8f9f7 | 1304 | /** |
Anna Bridge |
186:707f6e361f3e | 1305 | * @brief Stop ADC conversion of regular group (and injected group in |
Anna Bridge |
186:707f6e361f3e | 1306 | * case of auto_injection mode), disable ADC DMA transfer, disable |
<> | 144:ef7eb2e8f9f7 | 1307 | * ADC peripheral. |
<> | 144:ef7eb2e8f9f7 | 1308 | * Each of these interruptions has its dedicated callback function. |
<> | 144:ef7eb2e8f9f7 | 1309 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1310 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1311 | */ |
<> | 144:ef7eb2e8f9f7 | 1312 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1313 | { |
<> | 144:ef7eb2e8f9f7 | 1314 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1315 | |
<> | 144:ef7eb2e8f9f7 | 1316 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1317 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1318 | |
<> | 144:ef7eb2e8f9f7 | 1319 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1320 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1321 | |
Anna Bridge |
186:707f6e361f3e | 1322 | /* 1. Stop potential ADC group regular conversion on going */ |
<> | 144:ef7eb2e8f9f7 | 1323 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 1324 | |
<> | 144:ef7eb2e8f9f7 | 1325 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 1326 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1327 | { |
<> | 144:ef7eb2e8f9f7 | 1328 | /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ |
Anna Bridge |
186:707f6e361f3e | 1329 | CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); |
<> | 144:ef7eb2e8f9f7 | 1330 | |
Anna Bridge |
186:707f6e361f3e | 1331 | /* Disable the DMA channel (in case of DMA in circular mode or stop */ |
<> | 144:ef7eb2e8f9f7 | 1332 | /* while DMA transfer is on going) */ |
Anna Bridge |
186:707f6e361f3e | 1333 | tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); |
<> | 144:ef7eb2e8f9f7 | 1334 | |
<> | 144:ef7eb2e8f9f7 | 1335 | /* Check if DMA channel effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1336 | if (tmp_hal_status != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1337 | { |
<> | 144:ef7eb2e8f9f7 | 1338 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1339 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 1340 | } |
<> | 144:ef7eb2e8f9f7 | 1341 | |
<> | 144:ef7eb2e8f9f7 | 1342 | /* Disable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1343 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
<> | 144:ef7eb2e8f9f7 | 1344 | |
<> | 144:ef7eb2e8f9f7 | 1345 | /* 2. Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1346 | /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ |
<> | 144:ef7eb2e8f9f7 | 1347 | /* in memory a potential failing status. */ |
<> | 144:ef7eb2e8f9f7 | 1348 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1349 | { |
<> | 144:ef7eb2e8f9f7 | 1350 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1351 | } |
<> | 144:ef7eb2e8f9f7 | 1352 | else |
<> | 144:ef7eb2e8f9f7 | 1353 | { |
<> | 144:ef7eb2e8f9f7 | 1354 | ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1355 | } |
<> | 144:ef7eb2e8f9f7 | 1356 | |
<> | 144:ef7eb2e8f9f7 | 1357 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1358 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1359 | { |
<> | 144:ef7eb2e8f9f7 | 1360 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1361 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1362 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1363 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1364 | } |
Anna Bridge |
186:707f6e361f3e | 1365 | |
Anna Bridge |
186:707f6e361f3e | 1366 | } |
<> | 144:ef7eb2e8f9f7 | 1367 | |
<> | 144:ef7eb2e8f9f7 | 1368 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1369 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1370 | |
<> | 144:ef7eb2e8f9f7 | 1371 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1372 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1373 | } |
<> | 144:ef7eb2e8f9f7 | 1374 | |
<> | 144:ef7eb2e8f9f7 | 1375 | /** |
<> | 144:ef7eb2e8f9f7 | 1376 | * @brief Get ADC regular group conversion result. |
Anna Bridge |
186:707f6e361f3e | 1377 | * @note Reading register DR automatically clears ADC flag EOC |
Anna Bridge |
186:707f6e361f3e | 1378 | * (ADC group regular end of unitary conversion). |
Anna Bridge |
186:707f6e361f3e | 1379 | * @note This function does not clear ADC flag EOS |
<> | 144:ef7eb2e8f9f7 | 1380 | * (ADC group regular end of sequence conversion). |
<> | 144:ef7eb2e8f9f7 | 1381 | * Occurrence of flag EOS rising: |
<> | 144:ef7eb2e8f9f7 | 1382 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
<> | 144:ef7eb2e8f9f7 | 1383 | * to flag EOC. |
<> | 144:ef7eb2e8f9f7 | 1384 | * - If sequencer is composed of several ranks, during the scan |
<> | 144:ef7eb2e8f9f7 | 1385 | * sequence flag EOC only is raised, at the end of the scan sequence |
<> | 144:ef7eb2e8f9f7 | 1386 | * both flags EOC and EOS are raised. |
<> | 144:ef7eb2e8f9f7 | 1387 | * To clear this flag, either use function: |
<> | 144:ef7eb2e8f9f7 | 1388 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
<> | 144:ef7eb2e8f9f7 | 1389 | * model polling: @ref HAL_ADC_PollForConversion() |
<> | 144:ef7eb2e8f9f7 | 1390 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
<> | 144:ef7eb2e8f9f7 | 1391 | * @param hadc: ADC handle |
Anna Bridge |
186:707f6e361f3e | 1392 | * @retval ADC group regular conversion data |
<> | 144:ef7eb2e8f9f7 | 1393 | */ |
<> | 144:ef7eb2e8f9f7 | 1394 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
Anna Bridge |
186:707f6e361f3e | 1395 | { |
<> | 144:ef7eb2e8f9f7 | 1396 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1397 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1398 | |
<> | 144:ef7eb2e8f9f7 | 1399 | /* Note: EOC flag is not cleared here by software because automatically */ |
<> | 144:ef7eb2e8f9f7 | 1400 | /* cleared by hardware when reading register DR. */ |
<> | 144:ef7eb2e8f9f7 | 1401 | |
<> | 144:ef7eb2e8f9f7 | 1402 | /* Return ADC converted value */ |
<> | 144:ef7eb2e8f9f7 | 1403 | return hadc->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 1404 | } |
<> | 144:ef7eb2e8f9f7 | 1405 | |
<> | 144:ef7eb2e8f9f7 | 1406 | /** |
Anna Bridge |
186:707f6e361f3e | 1407 | * @brief Handle ADC interrupt request. |
<> | 144:ef7eb2e8f9f7 | 1408 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1409 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1410 | */ |
<> | 144:ef7eb2e8f9f7 | 1411 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1412 | { |
<> | 144:ef7eb2e8f9f7 | 1413 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1414 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1415 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
Anna Bridge |
186:707f6e361f3e | 1416 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
<> | 144:ef7eb2e8f9f7 | 1417 | |
<> | 144:ef7eb2e8f9f7 | 1418 | /* ========== Check End of Conversion flag for regular group ========== */ |
<> | 144:ef7eb2e8f9f7 | 1419 | if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || |
Anna Bridge |
186:707f6e361f3e | 1420 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) |
<> | 144:ef7eb2e8f9f7 | 1421 | { |
<> | 144:ef7eb2e8f9f7 | 1422 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 1423 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
<> | 144:ef7eb2e8f9f7 | 1424 | { |
<> | 144:ef7eb2e8f9f7 | 1425 | /* Set ADC state */ |
Anna Bridge |
186:707f6e361f3e | 1426 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1427 | } |
Anna Bridge |
186:707f6e361f3e | 1428 | |
<> | 144:ef7eb2e8f9f7 | 1429 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1430 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 1431 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 1432 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 1433 | { |
<> | 144:ef7eb2e8f9f7 | 1434 | /* If End of Sequence is reached, disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1435 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
<> | 144:ef7eb2e8f9f7 | 1436 | { |
<> | 144:ef7eb2e8f9f7 | 1437 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
Anna Bridge |
186:707f6e361f3e | 1438 | /* ADSTART==0 (no conversion on going) */ |
<> | 144:ef7eb2e8f9f7 | 1439 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
Anna Bridge |
186:707f6e361f3e | 1440 | { |
<> | 144:ef7eb2e8f9f7 | 1441 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1442 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 1443 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 1444 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 1445 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
<> | 144:ef7eb2e8f9f7 | 1446 | |
<> | 144:ef7eb2e8f9f7 | 1447 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1448 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1449 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1450 | HAL_ADC_STATE_READY); |
Anna Bridge |
186:707f6e361f3e | 1451 | } |
Anna Bridge |
186:707f6e361f3e | 1452 | else |
Anna Bridge |
186:707f6e361f3e | 1453 | { |
Anna Bridge |
186:707f6e361f3e | 1454 | /* Change ADC state to error state */ |
<> | 144:ef7eb2e8f9f7 | 1455 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 1456 | |
Anna Bridge |
186:707f6e361f3e | 1457 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1458 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1459 | } |
<> | 144:ef7eb2e8f9f7 | 1460 | } |
Anna Bridge |
186:707f6e361f3e | 1461 | } |
Anna Bridge |
186:707f6e361f3e | 1462 | |
<> | 144:ef7eb2e8f9f7 | 1463 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1464 | /* Note: into callback, to determine if conversion has been triggered */ |
<> | 144:ef7eb2e8f9f7 | 1465 | /* from EOC or EOS, possibility to use: */ |
<> | 144:ef7eb2e8f9f7 | 1466 | /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ |
<> | 144:ef7eb2e8f9f7 | 1467 | HAL_ADC_ConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1468 | |
<> | 144:ef7eb2e8f9f7 | 1469 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 1470 | /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ |
<> | 144:ef7eb2e8f9f7 | 1471 | /* conversion flags clear induces the release of the preserved data.*/ |
<> | 144:ef7eb2e8f9f7 | 1472 | /* Therefore, if the preserved data value is needed, it must be */ |
<> | 144:ef7eb2e8f9f7 | 1473 | /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ |
Anna Bridge |
186:707f6e361f3e | 1474 | /* Note: Management of low power auto-wait enabled: flags must be cleared */ |
Anna Bridge |
186:707f6e361f3e | 1475 | /* by user when fetching ADC conversion data. */ |
Anna Bridge |
186:707f6e361f3e | 1476 | /* This case is managed in IRQ handler, but this low-power mode */ |
Anna Bridge |
186:707f6e361f3e | 1477 | /* should not be used with programming model IT or DMA. */ |
Anna Bridge |
186:707f6e361f3e | 1478 | /* Refer to comment of parameter "LowPowerAutoWait". */ |
Anna Bridge |
186:707f6e361f3e | 1479 | if (hadc->Init.LowPowerAutoWait != ENABLE) |
Anna Bridge |
186:707f6e361f3e | 1480 | { |
Anna Bridge |
186:707f6e361f3e | 1481 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); |
<> | 144:ef7eb2e8f9f7 | 1482 | } |
Anna Bridge |
186:707f6e361f3e | 1483 | } |
<> | 144:ef7eb2e8f9f7 | 1484 | |
Anna Bridge |
186:707f6e361f3e | 1485 | /* ========== Check analog watchdog 1 flag ========== */ |
<> | 144:ef7eb2e8f9f7 | 1486 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
<> | 144:ef7eb2e8f9f7 | 1487 | { |
Anna Bridge |
186:707f6e361f3e | 1488 | /* Set ADC state */ |
Anna Bridge |
186:707f6e361f3e | 1489 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 1490 | |
Anna Bridge |
186:707f6e361f3e | 1491 | /* Level out of window 1 callback */ |
<> | 144:ef7eb2e8f9f7 | 1492 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1493 | |
<> | 144:ef7eb2e8f9f7 | 1494 | /* Clear ADC Analog watchdog flag */ |
Anna Bridge |
186:707f6e361f3e | 1495 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 1496 | |
Anna Bridge |
186:707f6e361f3e | 1497 | } |
<> | 144:ef7eb2e8f9f7 | 1498 | |
<> | 144:ef7eb2e8f9f7 | 1499 | |
<> | 144:ef7eb2e8f9f7 | 1500 | /* ========== Check Overrun flag ========== */ |
<> | 144:ef7eb2e8f9f7 | 1501 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) |
<> | 144:ef7eb2e8f9f7 | 1502 | { |
<> | 144:ef7eb2e8f9f7 | 1503 | /* If overrun is set to overwrite previous data (default setting), */ |
<> | 144:ef7eb2e8f9f7 | 1504 | /* overrun event is not considered as an error. */ |
<> | 144:ef7eb2e8f9f7 | 1505 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
<> | 144:ef7eb2e8f9f7 | 1506 | /* overrun ") */ |
<> | 144:ef7eb2e8f9f7 | 1507 | /* Exception for usage with DMA overrun event always considered as an */ |
<> | 144:ef7eb2e8f9f7 | 1508 | /* error. */ |
<> | 144:ef7eb2e8f9f7 | 1509 | if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || |
<> | 144:ef7eb2e8f9f7 | 1510 | HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) |
<> | 144:ef7eb2e8f9f7 | 1511 | { |
<> | 144:ef7eb2e8f9f7 | 1512 | /* Set ADC error code to overrun */ |
<> | 144:ef7eb2e8f9f7 | 1513 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
<> | 144:ef7eb2e8f9f7 | 1514 | |
<> | 144:ef7eb2e8f9f7 | 1515 | /* Clear ADC overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1516 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1517 | |
<> | 144:ef7eb2e8f9f7 | 1518 | /* Error callback */ |
<> | 144:ef7eb2e8f9f7 | 1519 | HAL_ADC_ErrorCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1520 | } |
<> | 144:ef7eb2e8f9f7 | 1521 | |
<> | 144:ef7eb2e8f9f7 | 1522 | /* Clear the Overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1523 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1524 | } |
Anna Bridge |
186:707f6e361f3e | 1525 | |
<> | 144:ef7eb2e8f9f7 | 1526 | } |
<> | 144:ef7eb2e8f9f7 | 1527 | |
<> | 144:ef7eb2e8f9f7 | 1528 | /** |
Anna Bridge |
186:707f6e361f3e | 1529 | * @brief Conversion complete callback in non-blocking mode. |
<> | 144:ef7eb2e8f9f7 | 1530 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1531 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1532 | */ |
<> | 144:ef7eb2e8f9f7 | 1533 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1534 | { |
<> | 144:ef7eb2e8f9f7 | 1535 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1536 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1537 | |
<> | 144:ef7eb2e8f9f7 | 1538 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1539 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1540 | */ |
<> | 144:ef7eb2e8f9f7 | 1541 | } |
<> | 144:ef7eb2e8f9f7 | 1542 | |
<> | 144:ef7eb2e8f9f7 | 1543 | /** |
Anna Bridge |
186:707f6e361f3e | 1544 | * @brief Conversion DMA half-transfer callback in non-blocking mode. |
<> | 144:ef7eb2e8f9f7 | 1545 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1546 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1547 | */ |
<> | 144:ef7eb2e8f9f7 | 1548 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1549 | { |
<> | 144:ef7eb2e8f9f7 | 1550 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1551 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1552 | |
<> | 144:ef7eb2e8f9f7 | 1553 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1554 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
Anna Bridge |
186:707f6e361f3e | 1555 | */ |
<> | 144:ef7eb2e8f9f7 | 1556 | } |
<> | 144:ef7eb2e8f9f7 | 1557 | |
<> | 144:ef7eb2e8f9f7 | 1558 | /** |
Anna Bridge |
186:707f6e361f3e | 1559 | * @brief Analog watchdog 1 callback in non-blocking mode. |
<> | 144:ef7eb2e8f9f7 | 1560 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1561 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1562 | */ |
<> | 144:ef7eb2e8f9f7 | 1563 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1564 | { |
<> | 144:ef7eb2e8f9f7 | 1565 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1566 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1567 | |
<> | 144:ef7eb2e8f9f7 | 1568 | /* NOTE : This function should not be modified. When the callback is needed, |
Anna Bridge |
186:707f6e361f3e | 1569 | function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. |
Anna Bridge |
186:707f6e361f3e | 1570 | */ |
<> | 144:ef7eb2e8f9f7 | 1571 | } |
<> | 144:ef7eb2e8f9f7 | 1572 | |
<> | 144:ef7eb2e8f9f7 | 1573 | /** |
Anna Bridge |
186:707f6e361f3e | 1574 | * @brief ADC error callback in non-blocking mode |
Anna Bridge |
186:707f6e361f3e | 1575 | * (ADC conversion with interruption or transfer by DMA). |
Anna Bridge |
186:707f6e361f3e | 1576 | * @note In case of error due to overrun when using ADC with DMA transfer |
Anna Bridge |
186:707f6e361f3e | 1577 | * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): |
Anna Bridge |
186:707f6e361f3e | 1578 | * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". |
Anna Bridge |
186:707f6e361f3e | 1579 | * - If needed, restart a new ADC conversion using function |
Anna Bridge |
186:707f6e361f3e | 1580 | * "HAL_ADC_Start_DMA()" |
Anna Bridge |
186:707f6e361f3e | 1581 | * (this function is also clearing overrun flag) |
<> | 144:ef7eb2e8f9f7 | 1582 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1583 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1584 | */ |
<> | 144:ef7eb2e8f9f7 | 1585 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1586 | { |
<> | 144:ef7eb2e8f9f7 | 1587 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1588 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1589 | |
<> | 144:ef7eb2e8f9f7 | 1590 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1591 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
Anna Bridge |
186:707f6e361f3e | 1592 | */ |
<> | 144:ef7eb2e8f9f7 | 1593 | } |
<> | 144:ef7eb2e8f9f7 | 1594 | |
<> | 144:ef7eb2e8f9f7 | 1595 | /** |
<> | 144:ef7eb2e8f9f7 | 1596 | * @} |
<> | 144:ef7eb2e8f9f7 | 1597 | */ |
<> | 144:ef7eb2e8f9f7 | 1598 | |
Anna Bridge |
186:707f6e361f3e | 1599 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
Anna Bridge |
186:707f6e361f3e | 1600 | * @brief Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 1601 | * |
<> | 144:ef7eb2e8f9f7 | 1602 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1603 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1604 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 1605 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1606 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 1607 | (+) Configure channels on regular group |
<> | 144:ef7eb2e8f9f7 | 1608 | (+) Configure the analog watchdog |
<> | 144:ef7eb2e8f9f7 | 1609 | |
<> | 144:ef7eb2e8f9f7 | 1610 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1611 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1612 | */ |
<> | 144:ef7eb2e8f9f7 | 1613 | |
<> | 144:ef7eb2e8f9f7 | 1614 | /** |
Anna Bridge |
186:707f6e361f3e | 1615 | * @brief Configure a channel to be assigned to ADC group regular. |
<> | 144:ef7eb2e8f9f7 | 1616 | * @note In case of usage of internal measurement channels: |
<> | 144:ef7eb2e8f9f7 | 1617 | * VrefInt/Vlcd(STM32L0x3xx only)/TempSensor. |
<> | 144:ef7eb2e8f9f7 | 1618 | * Sampling time constraints must be respected (sampling time can be |
<> | 144:ef7eb2e8f9f7 | 1619 | * adjusted in function of ADC clock frequency and sampling time |
<> | 144:ef7eb2e8f9f7 | 1620 | * setting). |
<> | 144:ef7eb2e8f9f7 | 1621 | * Refer to device datasheet for timings values, parameters TS_vrefint, |
<> | 144:ef7eb2e8f9f7 | 1622 | * TS_vlcd (STM32L0x3xx only), TS_temp (values rough order: 5us to 17us). |
<> | 144:ef7eb2e8f9f7 | 1623 | * These internal paths can be be disabled using function |
<> | 144:ef7eb2e8f9f7 | 1624 | * HAL_ADC_DeInit(). |
<> | 144:ef7eb2e8f9f7 | 1625 | * @note Possibility to update parameters on the fly: |
Anna Bridge |
186:707f6e361f3e | 1626 | * This function initializes channel into ADC group regular, |
Anna Bridge |
186:707f6e361f3e | 1627 | * following calls to this function can be used to reconfigure |
Anna Bridge |
186:707f6e361f3e | 1628 | * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, |
Anna Bridge |
186:707f6e361f3e | 1629 | * without resetting the ADC. |
Anna Bridge |
186:707f6e361f3e | 1630 | * The setting of these parameters is conditioned to ADC state: |
Anna Bridge |
186:707f6e361f3e | 1631 | * Refer to comments of structure "ADC_ChannelConfTypeDef". |
<> | 144:ef7eb2e8f9f7 | 1632 | * @param hadc: ADC handle |
Anna Bridge |
186:707f6e361f3e | 1633 | * @param sConfig: Structure of ADC channel assigned to ADC group regular. |
<> | 144:ef7eb2e8f9f7 | 1634 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1635 | */ |
<> | 144:ef7eb2e8f9f7 | 1636 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
<> | 144:ef7eb2e8f9f7 | 1637 | { |
<> | 144:ef7eb2e8f9f7 | 1638 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1639 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1640 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1641 | assert_param(IS_ADC_RANK(sConfig->Rank)); |
<> | 144:ef7eb2e8f9f7 | 1642 | |
<> | 144:ef7eb2e8f9f7 | 1643 | /* Process locked */ |
Anna Bridge |
186:707f6e361f3e | 1644 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1645 | |
<> | 144:ef7eb2e8f9f7 | 1646 | /* Parameters update conditioned to ADC state: */ |
<> | 144:ef7eb2e8f9f7 | 1647 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
<> | 144:ef7eb2e8f9f7 | 1648 | /* conversion on going on regular group: */ |
<> | 144:ef7eb2e8f9f7 | 1649 | /* - Channel number */ |
<> | 144:ef7eb2e8f9f7 | 1650 | /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */ |
<> | 144:ef7eb2e8f9f7 | 1651 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1652 | { |
<> | 144:ef7eb2e8f9f7 | 1653 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1654 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 1655 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1656 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1657 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1658 | } |
<> | 144:ef7eb2e8f9f7 | 1659 | |
<> | 144:ef7eb2e8f9f7 | 1660 | if (sConfig->Rank != ADC_RANK_NONE) |
<> | 144:ef7eb2e8f9f7 | 1661 | { |
<> | 144:ef7eb2e8f9f7 | 1662 | /* Enable selected channels */ |
<> | 144:ef7eb2e8f9f7 | 1663 | hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK); |
<> | 144:ef7eb2e8f9f7 | 1664 | |
<> | 144:ef7eb2e8f9f7 | 1665 | /* Management of internal measurement channels: Vlcd (STM32L0x3xx only)/VrefInt/TempSensor */ |
<> | 144:ef7eb2e8f9f7 | 1666 | /* internal measurement paths enable: If internal channel selected, enable */ |
<> | 144:ef7eb2e8f9f7 | 1667 | /* dedicated internal buffers and path. */ |
<> | 144:ef7eb2e8f9f7 | 1668 | |
<> | 144:ef7eb2e8f9f7 | 1669 | /* If Temperature sensor channel is selected, then enable the internal */ |
<> | 144:ef7eb2e8f9f7 | 1670 | /* buffers and path */ |
<> | 144:ef7eb2e8f9f7 | 1671 | if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1672 | { |
<> | 144:ef7eb2e8f9f7 | 1673 | ADC->CCR |= ADC_CCR_TSEN; |
<> | 144:ef7eb2e8f9f7 | 1674 | |
<> | 144:ef7eb2e8f9f7 | 1675 | /* Delay for temperature sensor stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 1676 | ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US); |
<> | 144:ef7eb2e8f9f7 | 1677 | } |
<> | 144:ef7eb2e8f9f7 | 1678 | |
<> | 144:ef7eb2e8f9f7 | 1679 | /* If VRefInt channel is selected, then enable the internal buffers and path */ |
<> | 144:ef7eb2e8f9f7 | 1680 | if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1681 | { |
<> | 144:ef7eb2e8f9f7 | 1682 | ADC->CCR |= ADC_CCR_VREFEN; |
<> | 144:ef7eb2e8f9f7 | 1683 | } |
<> | 144:ef7eb2e8f9f7 | 1684 | |
<> | 144:ef7eb2e8f9f7 | 1685 | #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) |
<> | 144:ef7eb2e8f9f7 | 1686 | /* If Vlcd channel is selected, then enable the internal buffers and path */ |
<> | 144:ef7eb2e8f9f7 | 1687 | if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1688 | { |
<> | 144:ef7eb2e8f9f7 | 1689 | ADC->CCR |= ADC_CCR_VLCDEN; |
<> | 144:ef7eb2e8f9f7 | 1690 | } |
<> | 144:ef7eb2e8f9f7 | 1691 | #endif |
<> | 144:ef7eb2e8f9f7 | 1692 | } |
<> | 144:ef7eb2e8f9f7 | 1693 | else |
<> | 144:ef7eb2e8f9f7 | 1694 | { |
<> | 144:ef7eb2e8f9f7 | 1695 | /* Regular sequence configuration */ |
<> | 144:ef7eb2e8f9f7 | 1696 | /* Reset the channel selection register from the selected channel */ |
<> | 144:ef7eb2e8f9f7 | 1697 | hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK)); |
<> | 144:ef7eb2e8f9f7 | 1698 | |
<> | 144:ef7eb2e8f9f7 | 1699 | /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
<> | 144:ef7eb2e8f9f7 | 1700 | /* internal measurement paths disable: If internal channel selected, */ |
<> | 144:ef7eb2e8f9f7 | 1701 | /* disable dedicated internal buffers and path. */ |
<> | 144:ef7eb2e8f9f7 | 1702 | if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1703 | { |
<> | 144:ef7eb2e8f9f7 | 1704 | ADC->CCR &= ~ADC_CCR_TSEN; |
<> | 144:ef7eb2e8f9f7 | 1705 | } |
<> | 144:ef7eb2e8f9f7 | 1706 | |
<> | 144:ef7eb2e8f9f7 | 1707 | /* If VRefInt channel is selected, then enable the internal buffers and path */ |
<> | 144:ef7eb2e8f9f7 | 1708 | if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1709 | { |
<> | 144:ef7eb2e8f9f7 | 1710 | ADC->CCR &= ~ADC_CCR_VREFEN; |
<> | 144:ef7eb2e8f9f7 | 1711 | } |
<> | 144:ef7eb2e8f9f7 | 1712 | |
<> | 144:ef7eb2e8f9f7 | 1713 | #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) |
<> | 144:ef7eb2e8f9f7 | 1714 | /* If Vlcd channel is selected, then enable the internal buffers and path */ |
<> | 144:ef7eb2e8f9f7 | 1715 | if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1716 | { |
<> | 144:ef7eb2e8f9f7 | 1717 | ADC->CCR &= ~ADC_CCR_VLCDEN; |
<> | 144:ef7eb2e8f9f7 | 1718 | } |
<> | 144:ef7eb2e8f9f7 | 1719 | #endif |
<> | 144:ef7eb2e8f9f7 | 1720 | } |
Anna Bridge |
186:707f6e361f3e | 1721 | |
<> | 144:ef7eb2e8f9f7 | 1722 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1723 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1724 | |
<> | 144:ef7eb2e8f9f7 | 1725 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1726 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1727 | } |
<> | 144:ef7eb2e8f9f7 | 1728 | |
<> | 144:ef7eb2e8f9f7 | 1729 | /** |
Anna Bridge |
186:707f6e361f3e | 1730 | * @brief Configure the analog watchdog. |
<> | 144:ef7eb2e8f9f7 | 1731 | * @note Possibility to update parameters on the fly: |
Anna Bridge |
186:707f6e361f3e | 1732 | * This function initializes the selected analog watchdog, successive |
<> | 144:ef7eb2e8f9f7 | 1733 | * calls to this function can be used to reconfigure some parameters |
Anna Bridge |
186:707f6e361f3e | 1734 | * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting |
<> | 144:ef7eb2e8f9f7 | 1735 | * the ADC. |
<> | 144:ef7eb2e8f9f7 | 1736 | * The setting of these parameters is conditioned to ADC state. |
<> | 144:ef7eb2e8f9f7 | 1737 | * For parameters constraints, see comments of structure |
<> | 144:ef7eb2e8f9f7 | 1738 | * "ADC_AnalogWDGConfTypeDef". |
Anna Bridge |
186:707f6e361f3e | 1739 | * @note Analog watchdog thresholds can be modified while ADC conversion |
Anna Bridge |
186:707f6e361f3e | 1740 | * is on going. |
Anna Bridge |
186:707f6e361f3e | 1741 | * In this case, some constraints must be taken into account: |
Anna Bridge |
186:707f6e361f3e | 1742 | * the programmed threshold values are effective from the next |
Anna Bridge |
186:707f6e361f3e | 1743 | * ADC EOC (end of unitary conversion). |
Anna Bridge |
186:707f6e361f3e | 1744 | * Considering that registers write delay may happen due to |
Anna Bridge |
186:707f6e361f3e | 1745 | * bus activity, this might cause an uncertainty on the |
Anna Bridge |
186:707f6e361f3e | 1746 | * effective timing of the new programmed threshold values. |
<> | 144:ef7eb2e8f9f7 | 1747 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1748 | * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration |
<> | 151:5eaa88a5bcc7 | 1749 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1750 | */ |
<> | 144:ef7eb2e8f9f7 | 1751 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
<> | 144:ef7eb2e8f9f7 | 1752 | { |
<> | 144:ef7eb2e8f9f7 | 1753 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1754 | |
<> | 144:ef7eb2e8f9f7 | 1755 | uint32_t tmpAWDHighThresholdShifted; |
<> | 144:ef7eb2e8f9f7 | 1756 | uint32_t tmpAWDLowThresholdShifted; |
<> | 144:ef7eb2e8f9f7 | 1757 | |
<> | 144:ef7eb2e8f9f7 | 1758 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1759 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1760 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
<> | 144:ef7eb2e8f9f7 | 1761 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
<> | 144:ef7eb2e8f9f7 | 1762 | |
<> | 144:ef7eb2e8f9f7 | 1763 | if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) |
<> | 144:ef7eb2e8f9f7 | 1764 | { |
<> | 144:ef7eb2e8f9f7 | 1765 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1766 | } |
Anna Bridge |
186:707f6e361f3e | 1767 | |
Anna Bridge |
186:707f6e361f3e | 1768 | /* Verify if threshold is within the selected ADC resolution */ |
Anna Bridge |
186:707f6e361f3e | 1769 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); |
Anna Bridge |
186:707f6e361f3e | 1770 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); |
Anna Bridge |
186:707f6e361f3e | 1771 | |
<> | 144:ef7eb2e8f9f7 | 1772 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1773 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1774 | |
<> | 144:ef7eb2e8f9f7 | 1775 | /* Parameters update conditioned to ADC state: */ |
<> | 144:ef7eb2e8f9f7 | 1776 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
<> | 144:ef7eb2e8f9f7 | 1777 | /* conversion on going on regular group: */ |
<> | 144:ef7eb2e8f9f7 | 1778 | /* - Analog watchdog channels */ |
<> | 144:ef7eb2e8f9f7 | 1779 | /* - Analog watchdog thresholds */ |
<> | 144:ef7eb2e8f9f7 | 1780 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1781 | { |
<> | 144:ef7eb2e8f9f7 | 1782 | /* Configure ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1783 | if(AnalogWDGConfig->ITMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1784 | { |
<> | 144:ef7eb2e8f9f7 | 1785 | /* Enable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1786 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1787 | } |
<> | 144:ef7eb2e8f9f7 | 1788 | else |
<> | 144:ef7eb2e8f9f7 | 1789 | { |
<> | 144:ef7eb2e8f9f7 | 1790 | /* Disable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1791 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1792 | } |
Anna Bridge |
186:707f6e361f3e | 1793 | |
<> | 144:ef7eb2e8f9f7 | 1794 | /* Configuration of analog watchdog: */ |
<> | 144:ef7eb2e8f9f7 | 1795 | /* - Set the analog watchdog mode */ |
<> | 144:ef7eb2e8f9f7 | 1796 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
<> | 144:ef7eb2e8f9f7 | 1797 | /* mode "all channels": ADC_CFGR1_AWD1SGL=0) */ |
<> | 144:ef7eb2e8f9f7 | 1798 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | |
<> | 144:ef7eb2e8f9f7 | 1799 | ADC_CFGR1_AWDEN | |
<> | 144:ef7eb2e8f9f7 | 1800 | ADC_CFGR1_AWDCH); |
<> | 144:ef7eb2e8f9f7 | 1801 | |
<> | 144:ef7eb2e8f9f7 | 1802 | hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | |
<> | 144:ef7eb2e8f9f7 | 1803 | (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK)); |
<> | 144:ef7eb2e8f9f7 | 1804 | |
<> | 144:ef7eb2e8f9f7 | 1805 | |
<> | 144:ef7eb2e8f9f7 | 1806 | /* Shift the offset in function of the selected ADC resolution: Thresholds */ |
<> | 144:ef7eb2e8f9f7 | 1807 | /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ |
<> | 144:ef7eb2e8f9f7 | 1808 | tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); |
<> | 144:ef7eb2e8f9f7 | 1809 | tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); |
<> | 144:ef7eb2e8f9f7 | 1810 | |
<> | 144:ef7eb2e8f9f7 | 1811 | /* Clear High & Low high thresholds */ |
<> | 144:ef7eb2e8f9f7 | 1812 | hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT); |
<> | 144:ef7eb2e8f9f7 | 1813 | |
<> | 144:ef7eb2e8f9f7 | 1814 | /* Set the high threshold */ |
<> | 144:ef7eb2e8f9f7 | 1815 | hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted); |
<> | 144:ef7eb2e8f9f7 | 1816 | /* Set the low threshold */ |
Anna Bridge |
186:707f6e361f3e | 1817 | hadc->Instance->TR |= tmpAWDLowThresholdShifted; |
<> | 144:ef7eb2e8f9f7 | 1818 | } |
Anna Bridge |
186:707f6e361f3e | 1819 | /* If a conversion is on going on regular group, no update could be done */ |
Anna Bridge |
186:707f6e361f3e | 1820 | /* on neither of the AWD configuration structure parameters. */ |
<> | 144:ef7eb2e8f9f7 | 1821 | else |
<> | 144:ef7eb2e8f9f7 | 1822 | { |
<> | 144:ef7eb2e8f9f7 | 1823 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1824 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
Anna Bridge |
186:707f6e361f3e | 1825 | |
<> | 144:ef7eb2e8f9f7 | 1826 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1827 | } |
<> | 144:ef7eb2e8f9f7 | 1828 | |
<> | 144:ef7eb2e8f9f7 | 1829 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1830 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1831 | |
<> | 144:ef7eb2e8f9f7 | 1832 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1833 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1834 | } |
<> | 144:ef7eb2e8f9f7 | 1835 | |
Anna Bridge |
186:707f6e361f3e | 1836 | |
<> | 144:ef7eb2e8f9f7 | 1837 | /** |
<> | 144:ef7eb2e8f9f7 | 1838 | * @} |
<> | 144:ef7eb2e8f9f7 | 1839 | */ |
<> | 144:ef7eb2e8f9f7 | 1840 | |
Anna Bridge |
186:707f6e361f3e | 1841 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
Anna Bridge |
186:707f6e361f3e | 1842 | * @brief ADC Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1843 | * |
Anna Bridge |
186:707f6e361f3e | 1844 | @verbatim |
Anna Bridge |
186:707f6e361f3e | 1845 | =============================================================================== |
Anna Bridge |
186:707f6e361f3e | 1846 | ##### Peripheral state and errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1847 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1848 | [..] |
Anna Bridge |
186:707f6e361f3e | 1849 | This subsection provides functions to get in run-time the status of the |
Anna Bridge |
186:707f6e361f3e | 1850 | peripheral. |
Anna Bridge |
186:707f6e361f3e | 1851 | (+) Check the ADC state |
Anna Bridge |
186:707f6e361f3e | 1852 | (+) Check the ADC error code |
Anna Bridge |
186:707f6e361f3e | 1853 | |
<> | 144:ef7eb2e8f9f7 | 1854 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1855 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1856 | */ |
<> | 144:ef7eb2e8f9f7 | 1857 | |
<> | 144:ef7eb2e8f9f7 | 1858 | /** |
Anna Bridge |
186:707f6e361f3e | 1859 | * @brief Return the ADC handle state. |
Anna Bridge |
186:707f6e361f3e | 1860 | * @note ADC state machine is managed by bitfields, ADC status must be |
Anna Bridge |
186:707f6e361f3e | 1861 | * compared with states bits. |
Anna Bridge |
186:707f6e361f3e | 1862 | * For example: |
Anna Bridge |
186:707f6e361f3e | 1863 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " |
Anna Bridge |
186:707f6e361f3e | 1864 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " |
<> | 144:ef7eb2e8f9f7 | 1865 | * @param hadc: ADC handle |
Anna Bridge |
186:707f6e361f3e | 1866 | * @retval ADC handle state (bitfield on 32 bits) |
<> | 144:ef7eb2e8f9f7 | 1867 | */ |
<> | 144:ef7eb2e8f9f7 | 1868 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1869 | { |
<> | 144:ef7eb2e8f9f7 | 1870 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1871 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1872 | |
Anna Bridge |
186:707f6e361f3e | 1873 | /* Return ADC handle state */ |
<> | 144:ef7eb2e8f9f7 | 1874 | return hadc->State; |
<> | 144:ef7eb2e8f9f7 | 1875 | } |
<> | 144:ef7eb2e8f9f7 | 1876 | |
<> | 144:ef7eb2e8f9f7 | 1877 | /** |
Anna Bridge |
186:707f6e361f3e | 1878 | * @brief Return the ADC error code. |
<> | 144:ef7eb2e8f9f7 | 1879 | * @param hadc: ADC handle |
Anna Bridge |
186:707f6e361f3e | 1880 | * @retval ADC error code (bitfield on 32 bits) |
<> | 144:ef7eb2e8f9f7 | 1881 | */ |
<> | 144:ef7eb2e8f9f7 | 1882 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1883 | { |
Anna Bridge |
186:707f6e361f3e | 1884 | /* Check the parameters */ |
Anna Bridge |
186:707f6e361f3e | 1885 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
Anna Bridge |
186:707f6e361f3e | 1886 | |
<> | 144:ef7eb2e8f9f7 | 1887 | return hadc->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1888 | } |
<> | 144:ef7eb2e8f9f7 | 1889 | |
<> | 144:ef7eb2e8f9f7 | 1890 | /** |
<> | 144:ef7eb2e8f9f7 | 1891 | * @} |
<> | 144:ef7eb2e8f9f7 | 1892 | */ |
<> | 144:ef7eb2e8f9f7 | 1893 | |
<> | 144:ef7eb2e8f9f7 | 1894 | /** |
<> | 144:ef7eb2e8f9f7 | 1895 | * @} |
<> | 144:ef7eb2e8f9f7 | 1896 | */ |
<> | 144:ef7eb2e8f9f7 | 1897 | |
Anna Bridge |
186:707f6e361f3e | 1898 | /** @defgroup ADC_Private_Functions ADC Private Functions |
<> | 144:ef7eb2e8f9f7 | 1899 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1900 | */ |
<> | 144:ef7eb2e8f9f7 | 1901 | |
<> | 144:ef7eb2e8f9f7 | 1902 | /** |
<> | 144:ef7eb2e8f9f7 | 1903 | * @brief Enable the selected ADC. |
<> | 144:ef7eb2e8f9f7 | 1904 | * @note Prerequisite condition to use this function: ADC must be disabled |
<> | 144:ef7eb2e8f9f7 | 1905 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
Anna Bridge |
186:707f6e361f3e | 1906 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
Anna Bridge |
186:707f6e361f3e | 1907 | * performed automatically by hardware. |
Anna Bridge |
186:707f6e361f3e | 1908 | * In this mode, this function is useless and must not be called because |
Anna Bridge |
186:707f6e361f3e | 1909 | * flag ADC_FLAG_RDY is not usable. |
Anna Bridge |
186:707f6e361f3e | 1910 | * Therefore, this function must be called under condition of |
Anna Bridge |
186:707f6e361f3e | 1911 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
<> | 144:ef7eb2e8f9f7 | 1912 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1913 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1914 | */ |
<> | 144:ef7eb2e8f9f7 | 1915 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1916 | { |
<> | 151:5eaa88a5bcc7 | 1917 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1918 | |
<> | 144:ef7eb2e8f9f7 | 1919 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
<> | 144:ef7eb2e8f9f7 | 1920 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
<> | 144:ef7eb2e8f9f7 | 1921 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
<> | 144:ef7eb2e8f9f7 | 1922 | /* causes: ADC clock not running, ...). */ |
<> | 144:ef7eb2e8f9f7 | 1923 | if (ADC_IS_ENABLE(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1924 | { |
<> | 144:ef7eb2e8f9f7 | 1925 | /* Check if conditions to enable the ADC are fulfilled */ |
<> | 144:ef7eb2e8f9f7 | 1926 | if (ADC_ENABLING_CONDITIONS(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1927 | { |
<> | 144:ef7eb2e8f9f7 | 1928 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1929 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1930 | |
<> | 144:ef7eb2e8f9f7 | 1931 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1932 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1933 | |
<> | 144:ef7eb2e8f9f7 | 1934 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1935 | } |
<> | 144:ef7eb2e8f9f7 | 1936 | |
<> | 144:ef7eb2e8f9f7 | 1937 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1938 | __HAL_ADC_ENABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1939 | |
<> | 144:ef7eb2e8f9f7 | 1940 | /* Delay for ADC stabilization time. */ |
<> | 144:ef7eb2e8f9f7 | 1941 | ADC_DelayMicroSecond(ADC_STAB_DELAY_US); |
<> | 144:ef7eb2e8f9f7 | 1942 | |
<> | 144:ef7eb2e8f9f7 | 1943 | /* Get tick count */ |
Anna Bridge |
186:707f6e361f3e | 1944 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1945 | |
<> | 144:ef7eb2e8f9f7 | 1946 | /* Wait for ADC effectively enabled */ |
Anna Bridge |
186:707f6e361f3e | 1947 | while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) |
Anna Bridge |
186:707f6e361f3e | 1948 | { |
Anna Bridge |
186:707f6e361f3e | 1949 | if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 1950 | { |
Anna Bridge |
186:707f6e361f3e | 1951 | /* Update ADC state machine to error */ |
Anna Bridge |
186:707f6e361f3e | 1952 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
Anna Bridge |
186:707f6e361f3e | 1953 | |
Anna Bridge |
186:707f6e361f3e | 1954 | /* Set ADC error code to ADC IP internal error */ |
Anna Bridge |
186:707f6e361f3e | 1955 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
Anna Bridge |
186:707f6e361f3e | 1956 | |
Anna Bridge |
186:707f6e361f3e | 1957 | return HAL_ERROR; |
Anna Bridge |
186:707f6e361f3e | 1958 | } |
Anna Bridge |
186:707f6e361f3e | 1959 | } |
<> | 144:ef7eb2e8f9f7 | 1960 | } |
<> | 144:ef7eb2e8f9f7 | 1961 | |
<> | 144:ef7eb2e8f9f7 | 1962 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 1963 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1964 | } |
<> | 144:ef7eb2e8f9f7 | 1965 | |
<> | 144:ef7eb2e8f9f7 | 1966 | /** |
<> | 144:ef7eb2e8f9f7 | 1967 | * @brief Disable the selected ADC. |
<> | 144:ef7eb2e8f9f7 | 1968 | * @note Prerequisite condition to use this function: ADC conversions must be |
<> | 144:ef7eb2e8f9f7 | 1969 | * stopped. |
<> | 144:ef7eb2e8f9f7 | 1970 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1971 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1972 | */ |
<> | 144:ef7eb2e8f9f7 | 1973 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1974 | { |
<> | 151:5eaa88a5bcc7 | 1975 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1976 | |
<> | 144:ef7eb2e8f9f7 | 1977 | /* Verification if ADC is not already disabled: */ |
<> | 144:ef7eb2e8f9f7 | 1978 | /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ |
Anna Bridge |
186:707f6e361f3e | 1979 | /* disabled. */ |
Anna Bridge |
186:707f6e361f3e | 1980 | if (ADC_IS_ENABLE(hadc) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1981 | { |
<> | 144:ef7eb2e8f9f7 | 1982 | /* Check if conditions to disable the ADC are fulfilled */ |
<> | 144:ef7eb2e8f9f7 | 1983 | if (ADC_DISABLING_CONDITIONS(hadc) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1984 | { |
<> | 144:ef7eb2e8f9f7 | 1985 | /* Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1986 | __HAL_ADC_DISABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1987 | } |
<> | 144:ef7eb2e8f9f7 | 1988 | else |
<> | 144:ef7eb2e8f9f7 | 1989 | { |
<> | 144:ef7eb2e8f9f7 | 1990 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1991 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1992 | |
<> | 144:ef7eb2e8f9f7 | 1993 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1994 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1995 | |
<> | 144:ef7eb2e8f9f7 | 1996 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1997 | } |
<> | 144:ef7eb2e8f9f7 | 1998 | |
<> | 144:ef7eb2e8f9f7 | 1999 | /* Wait for ADC effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 2000 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 2001 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2002 | |
<> | 144:ef7eb2e8f9f7 | 2003 | while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) |
<> | 144:ef7eb2e8f9f7 | 2004 | { |
Anna Bridge |
186:707f6e361f3e | 2005 | if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) |
Anna Bridge |
186:707f6e361f3e | 2006 | { |
Anna Bridge |
186:707f6e361f3e | 2007 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 2008 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
Anna Bridge |
186:707f6e361f3e | 2009 | |
<> | 144:ef7eb2e8f9f7 | 2010 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 2011 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
Anna Bridge |
186:707f6e361f3e | 2012 | |
Anna Bridge |
186:707f6e361f3e | 2013 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2014 | } |
<> | 144:ef7eb2e8f9f7 | 2015 | } |
Anna Bridge |
186:707f6e361f3e | 2016 | } |
<> | 144:ef7eb2e8f9f7 | 2017 | |
<> | 144:ef7eb2e8f9f7 | 2018 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 2019 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2020 | } |
<> | 144:ef7eb2e8f9f7 | 2021 | |
Anna Bridge |
186:707f6e361f3e | 2022 | |
<> | 144:ef7eb2e8f9f7 | 2023 | /** |
<> | 144:ef7eb2e8f9f7 | 2024 | * @brief Stop ADC conversion. |
<> | 144:ef7eb2e8f9f7 | 2025 | * @note Prerequisite condition to use this function: ADC conversions must be |
<> | 144:ef7eb2e8f9f7 | 2026 | * stopped to disable the ADC. |
<> | 144:ef7eb2e8f9f7 | 2027 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 2028 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 2029 | */ |
<> | 144:ef7eb2e8f9f7 | 2030 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 2031 | { |
<> | 151:5eaa88a5bcc7 | 2032 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2033 | |
<> | 144:ef7eb2e8f9f7 | 2034 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2035 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 2036 | |
<> | 144:ef7eb2e8f9f7 | 2037 | /* Verification if ADC is not already stopped on regular group to bypass */ |
<> | 144:ef7eb2e8f9f7 | 2038 | /* this function if not needed. */ |
<> | 144:ef7eb2e8f9f7 | 2039 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) |
<> | 144:ef7eb2e8f9f7 | 2040 | { |
<> | 144:ef7eb2e8f9f7 | 2041 | |
<> | 144:ef7eb2e8f9f7 | 2042 | /* Stop potential conversion on going on regular group */ |
<> | 144:ef7eb2e8f9f7 | 2043 | /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ |
<> | 144:ef7eb2e8f9f7 | 2044 | if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && |
<> | 144:ef7eb2e8f9f7 | 2045 | HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) |
<> | 144:ef7eb2e8f9f7 | 2046 | { |
<> | 144:ef7eb2e8f9f7 | 2047 | /* Stop conversions on regular group */ |
<> | 144:ef7eb2e8f9f7 | 2048 | hadc->Instance->CR |= ADC_CR_ADSTP; |
<> | 144:ef7eb2e8f9f7 | 2049 | } |
<> | 144:ef7eb2e8f9f7 | 2050 | |
<> | 144:ef7eb2e8f9f7 | 2051 | /* Wait for conversion effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 2052 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 2053 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2054 | |
<> | 144:ef7eb2e8f9f7 | 2055 | while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2056 | { |
<> | 144:ef7eb2e8f9f7 | 2057 | if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 2058 | { |
<> | 144:ef7eb2e8f9f7 | 2059 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 2060 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
Anna Bridge |
186:707f6e361f3e | 2061 | |
<> | 144:ef7eb2e8f9f7 | 2062 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 2063 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2064 | |
<> | 144:ef7eb2e8f9f7 | 2065 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2066 | } |
<> | 144:ef7eb2e8f9f7 | 2067 | } |
<> | 144:ef7eb2e8f9f7 | 2068 | |
<> | 144:ef7eb2e8f9f7 | 2069 | } |
<> | 144:ef7eb2e8f9f7 | 2070 | |
<> | 144:ef7eb2e8f9f7 | 2071 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 2072 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2073 | } |
<> | 144:ef7eb2e8f9f7 | 2074 | |
Anna Bridge |
186:707f6e361f3e | 2075 | |
<> | 144:ef7eb2e8f9f7 | 2076 | /** |
<> | 144:ef7eb2e8f9f7 | 2077 | * @brief DMA transfer complete callback. |
<> | 144:ef7eb2e8f9f7 | 2078 | * @param hdma: pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2079 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2080 | */ |
Anna Bridge |
186:707f6e361f3e | 2081 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2082 | { |
<> | 144:ef7eb2e8f9f7 | 2083 | /* Retrieve ADC handle corresponding to current DMA handle */ |
Anna Bridge |
186:707f6e361f3e | 2084 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
Anna Bridge |
186:707f6e361f3e | 2085 | |
<> | 144:ef7eb2e8f9f7 | 2086 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 2087 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
<> | 144:ef7eb2e8f9f7 | 2088 | { |
<> | 144:ef7eb2e8f9f7 | 2089 | /* Set ADC state */ |
Anna Bridge |
186:707f6e361f3e | 2090 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 2091 | |
<> | 144:ef7eb2e8f9f7 | 2092 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 2093 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 2094 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 2095 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 2096 | { |
<> | 144:ef7eb2e8f9f7 | 2097 | /* If End of Sequence is reached, disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 2098 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
<> | 144:ef7eb2e8f9f7 | 2099 | { |
<> | 144:ef7eb2e8f9f7 | 2100 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
<> | 144:ef7eb2e8f9f7 | 2101 | /* ADSTART==0 (no conversion on going) */ |
<> | 144:ef7eb2e8f9f7 | 2102 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 2103 | { |
<> | 144:ef7eb2e8f9f7 | 2104 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 2105 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 2106 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 2107 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 2108 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
<> | 144:ef7eb2e8f9f7 | 2109 | |
<> | 144:ef7eb2e8f9f7 | 2110 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 2111 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 2112 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 2113 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 2114 | } |
<> | 144:ef7eb2e8f9f7 | 2115 | else |
<> | 144:ef7eb2e8f9f7 | 2116 | { |
<> | 144:ef7eb2e8f9f7 | 2117 | /* Change ADC state to error state */ |
<> | 144:ef7eb2e8f9f7 | 2118 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 2119 | |
<> | 144:ef7eb2e8f9f7 | 2120 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 2121 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2122 | } |
<> | 144:ef7eb2e8f9f7 | 2123 | } |
<> | 144:ef7eb2e8f9f7 | 2124 | } |
Anna Bridge |
186:707f6e361f3e | 2125 | |
<> | 144:ef7eb2e8f9f7 | 2126 | /* Conversion complete callback */ |
Anna Bridge |
186:707f6e361f3e | 2127 | HAL_ADC_ConvCpltCallback(hadc); |
Anna Bridge |
186:707f6e361f3e | 2128 | } |
<> | 144:ef7eb2e8f9f7 | 2129 | else |
<> | 144:ef7eb2e8f9f7 | 2130 | { |
<> | 144:ef7eb2e8f9f7 | 2131 | /* Call DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 2132 | hadc->DMA_Handle->XferErrorCallback(hdma); |
<> | 144:ef7eb2e8f9f7 | 2133 | } |
<> | 144:ef7eb2e8f9f7 | 2134 | } |
<> | 144:ef7eb2e8f9f7 | 2135 | |
<> | 144:ef7eb2e8f9f7 | 2136 | /** |
<> | 144:ef7eb2e8f9f7 | 2137 | * @brief DMA half transfer complete callback. |
<> | 144:ef7eb2e8f9f7 | 2138 | * @param hdma: pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2139 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2140 | */ |
Anna Bridge |
186:707f6e361f3e | 2141 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2142 | { |
<> | 144:ef7eb2e8f9f7 | 2143 | /* Retrieve ADC handle corresponding to current DMA handle */ |
Anna Bridge |
186:707f6e361f3e | 2144 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
Anna Bridge |
186:707f6e361f3e | 2145 | |
<> | 144:ef7eb2e8f9f7 | 2146 | /* Half conversion callback */ |
Anna Bridge |
186:707f6e361f3e | 2147 | HAL_ADC_ConvHalfCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2148 | } |
<> | 144:ef7eb2e8f9f7 | 2149 | |
<> | 144:ef7eb2e8f9f7 | 2150 | /** |
Anna Bridge |
186:707f6e361f3e | 2151 | * @brief DMA error callback. |
<> | 144:ef7eb2e8f9f7 | 2152 | * @param hdma: pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2153 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2154 | */ |
Anna Bridge |
186:707f6e361f3e | 2155 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2156 | { |
<> | 144:ef7eb2e8f9f7 | 2157 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 2158 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
Anna Bridge |
186:707f6e361f3e | 2159 | |
<> | 144:ef7eb2e8f9f7 | 2160 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 2161 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 2162 | |
Anna Bridge |
186:707f6e361f3e | 2163 | /* Set ADC error code to DMA error */ |
<> | 144:ef7eb2e8f9f7 | 2164 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 2165 | |
<> | 144:ef7eb2e8f9f7 | 2166 | /* Error callback */ |
<> | 144:ef7eb2e8f9f7 | 2167 | HAL_ADC_ErrorCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2168 | } |
<> | 144:ef7eb2e8f9f7 | 2169 | |
<> | 144:ef7eb2e8f9f7 | 2170 | /** |
<> | 144:ef7eb2e8f9f7 | 2171 | * @brief Delay micro seconds |
<> | 144:ef7eb2e8f9f7 | 2172 | * @param microSecond : delay |
<> | 144:ef7eb2e8f9f7 | 2173 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2174 | */ |
<> | 144:ef7eb2e8f9f7 | 2175 | static void ADC_DelayMicroSecond(uint32_t microSecond) |
<> | 144:ef7eb2e8f9f7 | 2176 | { |
<> | 144:ef7eb2e8f9f7 | 2177 | /* Compute number of CPU cycles to wait for */ |
<> | 151:5eaa88a5bcc7 | 2178 | __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000U)); |
<> | 144:ef7eb2e8f9f7 | 2179 | |
<> | 151:5eaa88a5bcc7 | 2180 | while(waitLoopIndex != 0U) |
<> | 144:ef7eb2e8f9f7 | 2181 | { |
<> | 144:ef7eb2e8f9f7 | 2182 | waitLoopIndex--; |
<> | 144:ef7eb2e8f9f7 | 2183 | } |
<> | 144:ef7eb2e8f9f7 | 2184 | } |
<> | 144:ef7eb2e8f9f7 | 2185 | |
Anna Bridge |
186:707f6e361f3e | 2186 | #endif /* HAL_ADC_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 2187 | /** |
<> | 144:ef7eb2e8f9f7 | 2188 | * @} |
<> | 144:ef7eb2e8f9f7 | 2189 | */ |
<> | 144:ef7eb2e8f9f7 | 2190 | |
<> | 144:ef7eb2e8f9f7 | 2191 | /** |
<> | 144:ef7eb2e8f9f7 | 2192 | * @} |
<> | 144:ef7eb2e8f9f7 | 2193 | */ |
<> | 144:ef7eb2e8f9f7 | 2194 | |
<> | 144:ef7eb2e8f9f7 | 2195 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |