mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
151:5eaa88a5bcc7
Child:
189:f392fc9709a3
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_adc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 6 * functionalities of the Analog to Digital Convertor (ADC)
<> 144:ef7eb2e8f9f7 7 * peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * ++ Initialization and Configuration of ADC
<> 144:ef7eb2e8f9f7 10 * + Operation functions
Anna Bridge 186:707f6e361f3e 11 * ++ Start, stop, get result of conversions of regular
Anna Bridge 186:707f6e361f3e 12 * group, using 3 possible modes: polling, interruption or DMA.
<> 144:ef7eb2e8f9f7 13 * + Control functions
<> 144:ef7eb2e8f9f7 14 * ++ Channels configuration on regular group
<> 144:ef7eb2e8f9f7 15 * ++ Analog Watchdog configuration
<> 144:ef7eb2e8f9f7 16 * + State functions
<> 144:ef7eb2e8f9f7 17 * ++ ADC state machine management
<> 144:ef7eb2e8f9f7 18 * ++ Interrupts and flags management
<> 144:ef7eb2e8f9f7 19 * Other functions (extended functions) are available in file
<> 144:ef7eb2e8f9f7 20 * "stm32l0xx_hal_adc_ex.c".
Anna Bridge 186:707f6e361f3e 21 *
<> 144:ef7eb2e8f9f7 22 @verbatim
<> 144:ef7eb2e8f9f7 23 ==============================================================================
<> 144:ef7eb2e8f9f7 24 ##### ADC peripheral features #####
<> 144:ef7eb2e8f9f7 25 ==============================================================================
Anna Bridge 186:707f6e361f3e 26 [..]
Anna Bridge 186:707f6e361f3e 27 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (+) Interrupt generation at the end of regular conversion and in case of
<> 144:ef7eb2e8f9f7 30 analog watchdog or overrun events.
Anna Bridge 186:707f6e361f3e 31
<> 144:ef7eb2e8f9f7 32 (+) Single and continuous conversion modes.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (+) Scan mode for conversion of several channels sequentially.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 (+) Data alignment with in-built data coherency.
Anna Bridge 186:707f6e361f3e 37
Anna Bridge 186:707f6e361f3e 38 (+) Programmable sampling time (common for all channels)
Anna Bridge 186:707f6e361f3e 39
Anna Bridge 186:707f6e361f3e 40 (+) External trigger (timer or EXTI) with configurable polarity
Anna Bridge 186:707f6e361f3e 41
Anna Bridge 186:707f6e361f3e 42 (+) DMA request generation for transfer of conversions data of regular group.
<> 144:ef7eb2e8f9f7 43
Anna Bridge 186:707f6e361f3e 44 (+) ADC calibration
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (+) ADC conversion of regular group.
<> 144:ef7eb2e8f9f7 47
Anna Bridge 186:707f6e361f3e 48 (+) ADC supply requirements: 1.62 V to 3.6 V.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
<> 144:ef7eb2e8f9f7 51 Vdda or to an external voltage reference).
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 55 ==============================================================================
<> 144:ef7eb2e8f9f7 56 [..]
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** Configuration of top level parameters related to ADC ***
<> 144:ef7eb2e8f9f7 59 ============================================================
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61
Anna Bridge 186:707f6e361f3e 62 (#) Enable the ADC interface
Anna Bridge 186:707f6e361f3e 63 (++) As prerequisite, ADC clock must be configured at RCC top level.
Anna Bridge 186:707f6e361f3e 64 Caution: On STM32L0, ADC clock frequency max is 16MHz (refer
Anna Bridge 186:707f6e361f3e 65 to device datasheet).
Anna Bridge 186:707f6e361f3e 66 Therefore, ADC clock prescaler must be configured in
Anna Bridge 186:707f6e361f3e 67 function of ADC clock source frequency to remain below
Anna Bridge 186:707f6e361f3e 68 this maximum frequency.
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 (++) Two clock settings are mandatory:
<> 144:ef7eb2e8f9f7 71 (+++) ADC clock (core clock, also possibly conversion clock).
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 (+++) ADC clock (conversions clock).
<> 144:ef7eb2e8f9f7 74 Two possible clock sources: synchronous clock derived from APB clock
<> 144:ef7eb2e8f9f7 75 or asynchronous clock derived from ADC dedicated HSI RC oscillator
<> 144:ef7eb2e8f9f7 76 16MHz.
<> 144:ef7eb2e8f9f7 77 If asynchronous clock is selected, parameter "HSIState" must be set either:
<> 144:ef7eb2e8f9f7 78 - to "...HSIState = RCC_HSI_ON" to maintain the HSI16 oscillator
<> 144:ef7eb2e8f9f7 79 always enabled: can be used to supply the main system clock.
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 (+++) Example:
<> 144:ef7eb2e8f9f7 82 Into HAL_ADC_MspInit() (recommended code location) or with
<> 144:ef7eb2e8f9f7 83 other device clock parameters configuration:
Anna Bridge 186:707f6e361f3e 84 (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory)
<> 144:ef7eb2e8f9f7 85
Anna Bridge 186:707f6e361f3e 86 HSI enable (optional: if asynchronous clock selected)
<> 144:ef7eb2e8f9f7 87 (+++) RCC_OscInitTypeDef RCC_OscInitStructure;
<> 144:ef7eb2e8f9f7 88 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
<> 144:ef7eb2e8f9f7 89 (+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT;
<> 144:ef7eb2e8f9f7 90 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 91 (+++) RCC_OscInitStructure.PLL... (optional if used for system clock)
<> 144:ef7eb2e8f9f7 92 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 (++) ADC clock source and clock prescaler are configured at ADC level with
<> 144:ef7eb2e8f9f7 95 parameter "ClockPrescaler" using function HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 (#) ADC pins configuration
<> 144:ef7eb2e8f9f7 98 (++) Enable the clock for the ADC GPIOs
<> 144:ef7eb2e8f9f7 99 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 100 (++) Configure these ADC pins in analog mode
<> 144:ef7eb2e8f9f7 101 using function HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 (#) Optionally, in case of usage of ADC with interruptions:
<> 144:ef7eb2e8f9f7 104 (++) Configure the NVIC for ADC
<> 144:ef7eb2e8f9f7 105 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 144:ef7eb2e8f9f7 106 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 144:ef7eb2e8f9f7 107 into the function of corresponding ADC interruption vector
<> 144:ef7eb2e8f9f7 108 ADCx_IRQHandler().
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 (#) Optionally, in case of usage of DMA:
<> 144:ef7eb2e8f9f7 111 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
<> 144:ef7eb2e8f9f7 112 using function HAL_DMA_Init().
<> 144:ef7eb2e8f9f7 113 (++) Configure the NVIC for DMA
<> 144:ef7eb2e8f9f7 114 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 144:ef7eb2e8f9f7 115 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 144:ef7eb2e8f9f7 116 into the function of corresponding DMA interruption vector
<> 144:ef7eb2e8f9f7 117 DMAx_Channelx_IRQHandler().
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 *** Configuration of ADC, group regular, channels parameters ***
<> 144:ef7eb2e8f9f7 120 ================================================================
<> 144:ef7eb2e8f9f7 121 [..]
<> 144:ef7eb2e8f9f7 122
Anna Bridge 186:707f6e361f3e 123 (#) Configure the ADC parameters (resolution, data alignment, ...)
<> 144:ef7eb2e8f9f7 124 and regular group parameters (conversion trigger, sequencer, ...)
<> 144:ef7eb2e8f9f7 125 using function HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 (#) Configure the channels for regular group parameters (channel number,
<> 144:ef7eb2e8f9f7 128 channel rank into sequencer, ..., into regular group)
<> 144:ef7eb2e8f9f7 129 using function HAL_ADC_ConfigChannel().
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 (#) Optionally, configure the analog watchdog parameters (channels
<> 144:ef7eb2e8f9f7 132 monitored, thresholds, ...)
<> 144:ef7eb2e8f9f7 133 using function HAL_ADC_AnalogWDGConfig().
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 (#) When device is in mode low-power (low-power run, low-power sleep or stop mode),
<> 144:ef7eb2e8f9f7 137 function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 138 In case of internal temperature sensor to be measured:
<> 144:ef7eb2e8f9f7 139 function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 *** Execution of ADC conversions ***
<> 144:ef7eb2e8f9f7 142 ====================================
<> 144:ef7eb2e8f9f7 143 [..]
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 (#) Optionally, perform an automatic ADC calibration to improve the
<> 144:ef7eb2e8f9f7 146 conversion accuracy
<> 144:ef7eb2e8f9f7 147 using function HAL_ADCEx_Calibration_Start().
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 (#) ADC driver can be used among three modes: polling, interruption,
<> 144:ef7eb2e8f9f7 150 transfer by DMA.
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 (++) ADC conversion by polling:
<> 144:ef7eb2e8f9f7 153 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 154 using function HAL_ADC_Start()
<> 144:ef7eb2e8f9f7 155 (+++) Wait for ADC conversion completion
<> 144:ef7eb2e8f9f7 156 using function HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 157 (+++) Retrieve conversion results
<> 144:ef7eb2e8f9f7 158 using function HAL_ADC_GetValue()
<> 144:ef7eb2e8f9f7 159 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 160 using function HAL_ADC_Stop()
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 (++) ADC conversion by interruption:
<> 144:ef7eb2e8f9f7 163 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 164 using function HAL_ADC_Start_IT()
<> 144:ef7eb2e8f9f7 165 (+++) Wait for ADC conversion completion by call of function
<> 144:ef7eb2e8f9f7 166 HAL_ADC_ConvCpltCallback()
<> 144:ef7eb2e8f9f7 167 (this function must be implemented in user program)
<> 144:ef7eb2e8f9f7 168 (+++) Retrieve conversion results
<> 144:ef7eb2e8f9f7 169 using function HAL_ADC_GetValue()
<> 144:ef7eb2e8f9f7 170 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 171 using function HAL_ADC_Stop_IT()
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 (++) ADC conversion with transfer by DMA:
<> 144:ef7eb2e8f9f7 174 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 175 using function HAL_ADC_Start_DMA()
<> 144:ef7eb2e8f9f7 176 (+++) Wait for ADC conversion completion by call of function
<> 144:ef7eb2e8f9f7 177 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
<> 144:ef7eb2e8f9f7 178 (these functions must be implemented in user program)
<> 144:ef7eb2e8f9f7 179 (+++) Conversion results are automatically transferred by DMA into
<> 144:ef7eb2e8f9f7 180 destination variable address.
<> 144:ef7eb2e8f9f7 181 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 182 using function HAL_ADC_Stop_DMA()
Anna Bridge 186:707f6e361f3e 183
Anna Bridge 186:707f6e361f3e 184 [..]
Anna Bridge 186:707f6e361f3e 185
<> 144:ef7eb2e8f9f7 186 (@) Callback functions must be implemented in user program:
<> 144:ef7eb2e8f9f7 187 (+@) HAL_ADC_ErrorCallback()
<> 144:ef7eb2e8f9f7 188 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
<> 144:ef7eb2e8f9f7 189 (+@) HAL_ADC_ConvCpltCallback()
<> 144:ef7eb2e8f9f7 190 (+@) HAL_ADC_ConvHalfCpltCallback
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 *** Deinitialization of ADC ***
<> 144:ef7eb2e8f9f7 193 ============================================================
<> 144:ef7eb2e8f9f7 194 [..]
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 (#) Disable the ADC interface
<> 144:ef7eb2e8f9f7 197 (++) ADC clock can be hard reset and disabled at RCC top level.
<> 144:ef7eb2e8f9f7 198 (++) Hard reset of ADC peripherals
<> 144:ef7eb2e8f9f7 199 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
<> 144:ef7eb2e8f9f7 200 (++) ADC clock disable
<> 144:ef7eb2e8f9f7 201 using the equivalent macro/functions as configuration step.
<> 144:ef7eb2e8f9f7 202 (+++) Example:
<> 144:ef7eb2e8f9f7 203 Into HAL_ADC_MspDeInit() (recommended code location) or with
<> 144:ef7eb2e8f9f7 204 other device clock parameters configuration:
<> 144:ef7eb2e8f9f7 205 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
<> 144:ef7eb2e8f9f7 206 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
<> 144:ef7eb2e8f9f7 207 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 (#) ADC pins configuration
<> 144:ef7eb2e8f9f7 210 (++) Disable the clock for the ADC GPIOs
<> 144:ef7eb2e8f9f7 211 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 (#) Optionally, in case of usage of ADC with interruptions:
<> 144:ef7eb2e8f9f7 214 (++) Disable the NVIC for ADC
<> 144:ef7eb2e8f9f7 215 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 (#) Optionally, in case of usage of DMA:
<> 144:ef7eb2e8f9f7 218 (++) Deinitialize the DMA
<> 144:ef7eb2e8f9f7 219 using function HAL_DMA_Init().
<> 144:ef7eb2e8f9f7 220 (++) Disable the NVIC for DMA
<> 144:ef7eb2e8f9f7 221 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 [..]
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 @endverbatim
<> 144:ef7eb2e8f9f7 226 ******************************************************************************
<> 144:ef7eb2e8f9f7 227 * @attention
<> 144:ef7eb2e8f9f7 228 *
<> 144:ef7eb2e8f9f7 229 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 230 *
<> 144:ef7eb2e8f9f7 231 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 232 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 233 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 234 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 235 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 236 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 237 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 238 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 239 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 240 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 241 *
<> 144:ef7eb2e8f9f7 242 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 243 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 244 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 245 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 246 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 247 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 248 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 249 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 250 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 251 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 252 *
<> 144:ef7eb2e8f9f7 253 ******************************************************************************
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 257 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
Anna Bridge 186:707f6e361f3e 263 /** @defgroup ADC ADC
Anna Bridge 186:707f6e361f3e 264 * @brief ADC HAL module driver
Anna Bridge 186:707f6e361f3e 265 * @{
Anna Bridge 186:707f6e361f3e 266 */
Anna Bridge 186:707f6e361f3e 267
<> 144:ef7eb2e8f9f7 268 #ifdef HAL_ADC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 269
Anna Bridge 186:707f6e361f3e 270 /* Private typedef -----------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 271 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 272
Anna Bridge 186:707f6e361f3e 273 /** @defgroup ADC_Private_Constants ADC Private Constants
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 278 /* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 279 /* Unit: us */
<> 151:5eaa88a5bcc7 280 #define ADC_STAB_DELAY_US ((uint32_t) 1U)
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Delay for temperature sensor stabilization time. */
<> 144:ef7eb2e8f9f7 283 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 284 /* Unit: us */
<> 151:5eaa88a5bcc7 285 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 291 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 292 /* Private function prototypes -----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 293 /** @defgroup ADC_Private_Functions ADC Private Functions
<> 144:ef7eb2e8f9f7 294 * @{
Anna Bridge 186:707f6e361f3e 295 */
<> 144:ef7eb2e8f9f7 296 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 297 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 298 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 299 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 300 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 301 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 302 static void ADC_DelayMicroSecond(uint32_t microSecond);
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
Anna Bridge 186:707f6e361f3e 307 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 308
Anna Bridge 186:707f6e361f3e 309 /** @defgroup ADC_Exported_Functions ADC Exported Functions
Anna Bridge 186:707f6e361f3e 310 * @{
Anna Bridge 186:707f6e361f3e 311 */
Anna Bridge 186:707f6e361f3e 312
Anna Bridge 186:707f6e361f3e 313 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
Anna Bridge 186:707f6e361f3e 314 * @brief ADC Initialization and Configuration functions
Anna Bridge 186:707f6e361f3e 315 *
<> 144:ef7eb2e8f9f7 316 @verbatim
<> 144:ef7eb2e8f9f7 317 ===============================================================================
<> 144:ef7eb2e8f9f7 318 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 319 ===============================================================================
<> 144:ef7eb2e8f9f7 320 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 321 (+) Initialize and configure the ADC.
Anna Bridge 186:707f6e361f3e 322 (+) De-initialize the ADC.
<> 144:ef7eb2e8f9f7 323 @endverbatim
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
Anna Bridge 186:707f6e361f3e 328 * @brief Initialize the ADC peripheral and regular group according to
<> 144:ef7eb2e8f9f7 329 * parameters specified in structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 330 * @note As prerequisite, ADC clock must be configured at RCC top level
Anna Bridge 186:707f6e361f3e 331 * depending on possible clock sources: APB clock of HSI clock.
Anna Bridge 186:707f6e361f3e 332 * See commented example code below that can be copied and uncommented
<> 144:ef7eb2e8f9f7 333 * into HAL_ADC_MspInit().
<> 144:ef7eb2e8f9f7 334 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 335 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<> 144:ef7eb2e8f9f7 336 * coming from ADC state reset. Following calls to this function can
<> 144:ef7eb2e8f9f7 337 * be used to reconfigure some parameters of ADC_InitTypeDef
<> 144:ef7eb2e8f9f7 338 * structure on the fly, without modifying MSP configuration. If ADC
<> 144:ef7eb2e8f9f7 339 * MSP has to be modified again, HAL_ADC_DeInit() must be called
<> 144:ef7eb2e8f9f7 340 * before HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 341 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 342 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 343 * "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 344 * @note This function configures the ADC within 2 scopes: scope of entire
<> 144:ef7eb2e8f9f7 345 * ADC and scope of regular group. For parameters details, see comments
<> 144:ef7eb2e8f9f7 346 * of structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 347 * @note When device is in mode low-power (low-power run, low-power sleep or stop mode),
<> 144:ef7eb2e8f9f7 348 * function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init()
<> 144:ef7eb2e8f9f7 349 * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first).
<> 144:ef7eb2e8f9f7 350 * In case of internal temperature sensor to be measured:
<> 144:ef7eb2e8f9f7 351 * function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly.
<> 144:ef7eb2e8f9f7 352 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 353 * @retval HAL status
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 356 {
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 359 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Check the parameters */
<> 144:ef7eb2e8f9f7 365 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 366 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
<> 144:ef7eb2e8f9f7 367 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
Anna Bridge 186:707f6e361f3e 368 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
Anna Bridge 186:707f6e361f3e 369 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<> 151:5eaa88a5bcc7 370 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 371 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 372 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
Anna Bridge 186:707f6e361f3e 373 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<> 151:5eaa88a5bcc7 374 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
Anna Bridge 186:707f6e361f3e 375 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<> 151:5eaa88a5bcc7 376 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
<> 144:ef7eb2e8f9f7 377 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
<> 144:ef7eb2e8f9f7 378 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode));
<> 144:ef7eb2e8f9f7 379 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
Anna Bridge 186:707f6e361f3e 380 assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime));
<> 144:ef7eb2e8f9f7 381 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
<> 144:ef7eb2e8f9f7 384 /* at RCC top level depending on both possible clock sources: */
<> 144:ef7eb2e8f9f7 385 /* APB clock or HSI clock. */
<> 144:ef7eb2e8f9f7 386 /* Refer to header of this file for more details on clock enabling procedure*/
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Actions performed only if ADC is coming from state reset: */
<> 144:ef7eb2e8f9f7 389 /* - Initialization of ADC MSP */
<> 144:ef7eb2e8f9f7 390 /* - ADC voltage regulator enable */
<> 144:ef7eb2e8f9f7 391 if(hadc->State == HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 /* Initialize ADC error code */
<> 144:ef7eb2e8f9f7 394 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 397 hadc->Lock = HAL_UNLOCKED;
Anna Bridge 186:707f6e361f3e 398
<> 144:ef7eb2e8f9f7 399 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 400 HAL_ADC_MspInit(hadc);
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 404 /* correctly completed. */
Anna Bridge 186:707f6e361f3e 405 /* and if there is no conversion on going on regular group (ADC can be */
<> 144:ef7eb2e8f9f7 406 /* enabled anyway, in case of call of this function to update a parameter */
<> 144:ef7eb2e8f9f7 407 /* on the fly). */
<> 144:ef7eb2e8f9f7 408 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) ||
<> 144:ef7eb2e8f9f7 409 (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) )
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 412 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Process unlocked */
<> 144:ef7eb2e8f9f7 415 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 416 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Set ADC state */
<> 144:ef7eb2e8f9f7 420 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 421 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 422 HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 425 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 426 /* - ADC clock mode */
<> 144:ef7eb2e8f9f7 427 /* - ADC clock prescaler */
<> 144:ef7eb2e8f9f7 428 /* - ADC Resolution */
<> 144:ef7eb2e8f9f7 429 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 /* Some parameters of this register are not reset, since they are set */
<> 144:ef7eb2e8f9f7 432 /* by other functions and must be kept in case of usage of this */
<> 144:ef7eb2e8f9f7 433 /* function on the fly (update of a parameter of ADC_InitTypeDef */
<> 144:ef7eb2e8f9f7 434 /* without needing to reconfigure all other ADC groups/channels */
<> 144:ef7eb2e8f9f7 435 /* parameters): */
<> 144:ef7eb2e8f9f7 436 /* - internal measurement paths: Vbat, temperature sensor, Vref */
<> 144:ef7eb2e8f9f7 437 /* (set into HAL_ADC_ConfigChannel() ) */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Configuration of ADC clock: clock source PCLK or asynchronous with
<> 144:ef7eb2e8f9f7 440 selectable prescaler */
<> 144:ef7eb2e8f9f7 441 __HAL_ADC_CLOCK_PRESCALER(hadc);
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 444 /* - Resolution */
<> 144:ef7eb2e8f9f7 445 hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES);
<> 144:ef7eb2e8f9f7 446 hadc->Instance->CFGR1 |= hadc->Init.Resolution;
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Set the Low Frequency mode */
<> 144:ef7eb2e8f9f7 450 ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN;
<> 144:ef7eb2e8f9f7 451 ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Enable voltage regulator (if disabled at this step) */
<> 144:ef7eb2e8f9f7 454 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 /* Set ADVREGEN bit */
<> 144:ef7eb2e8f9f7 457 hadc->Instance->CR |= ADC_CR_ADVREGEN;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 461 /* - Resolution */
<> 144:ef7eb2e8f9f7 462 /* - Data alignment */
<> 144:ef7eb2e8f9f7 463 /* - Scan direction */
<> 144:ef7eb2e8f9f7 464 /* - External trigger to start conversion */
<> 144:ef7eb2e8f9f7 465 /* - External trigger polarity */
<> 144:ef7eb2e8f9f7 466 /* - Continuous conversion mode */
<> 144:ef7eb2e8f9f7 467 /* - DMA continuous request */
<> 144:ef7eb2e8f9f7 468 /* - Overrun */
<> 144:ef7eb2e8f9f7 469 /* - AutoDelay feature */
<> 144:ef7eb2e8f9f7 470 /* - Discontinuous mode */
Anna Bridge 186:707f6e361f3e 471 hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN |
Anna Bridge 186:707f6e361f3e 472 ADC_CFGR1_SCANDIR |
Anna Bridge 186:707f6e361f3e 473 ADC_CFGR1_EXTSEL |
Anna Bridge 186:707f6e361f3e 474 ADC_CFGR1_EXTEN |
Anna Bridge 186:707f6e361f3e 475 ADC_CFGR1_CONT |
Anna Bridge 186:707f6e361f3e 476 ADC_CFGR1_DMACFG |
Anna Bridge 186:707f6e361f3e 477 ADC_CFGR1_OVRMOD |
Anna Bridge 186:707f6e361f3e 478 ADC_CFGR1_AUTDLY |
Anna Bridge 186:707f6e361f3e 479 ADC_CFGR1_AUTOFF |
Anna Bridge 186:707f6e361f3e 480 ADC_CFGR1_DISCEN );
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 hadc->Instance->CFGR1 |= (hadc->Init.DataAlign |
<> 144:ef7eb2e8f9f7 483 ADC_SCANDIR(hadc->Init.ScanConvMode) |
Anna Bridge 186:707f6e361f3e 484 ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) |
<> 144:ef7eb2e8f9f7 485 ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) |
<> 144:ef7eb2e8f9f7 486 hadc->Init.Overrun |
<> 144:ef7eb2e8f9f7 487 __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
<> 144:ef7eb2e8f9f7 488 __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff));
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /* Enable external trigger if trigger selection is different of software */
<> 144:ef7eb2e8f9f7 491 /* start. */
<> 144:ef7eb2e8f9f7 492 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 493 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 494 /* software start. */
<> 144:ef7eb2e8f9f7 495 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv |
<> 144:ef7eb2e8f9f7 498 hadc->Init.ExternalTrigConvEdge;
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Enable discontinuous mode only if continuous mode is disabled */
<> 144:ef7eb2e8f9f7 502 if (hadc->Init.DiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 if (hadc->Init.ContinuousConvMode == DISABLE)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Enable the selected ADC group regular discontinuous mode */
<> 144:ef7eb2e8f9f7 507 hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN);
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509 else
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 /* ADC regular group discontinuous was intended to be enabled, */
<> 144:ef7eb2e8f9f7 512 /* but ADC regular group modes continuous and sequencer discontinuous */
<> 144:ef7eb2e8f9f7 513 /* cannot be enabled simultaneously. */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 516 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 519 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 if (hadc->Init.OversamplingMode == ENABLE)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversample.Ratio));
<> 144:ef7eb2e8f9f7 526 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversample.RightBitShift));
<> 144:ef7eb2e8f9f7 527 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversample.TriggeredMode));
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Configuration of Oversampler: */
<> 144:ef7eb2e8f9f7 530 /* - Oversampling Ratio */
<> 144:ef7eb2e8f9f7 531 /* - Right bit shift */
<> 144:ef7eb2e8f9f7 532 /* - Triggered mode */
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR |
<> 144:ef7eb2e8f9f7 535 ADC_CFGR2_OVSS |
<> 144:ef7eb2e8f9f7 536 ADC_CFGR2_TOVS );
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio |
<> 144:ef7eb2e8f9f7 539 hadc->Init.Oversample.RightBitShift |
<> 144:ef7eb2e8f9f7 540 hadc->Init.Oversample.TriggeredMode );
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Enable OverSampling mode */
<> 144:ef7eb2e8f9f7 543 hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE;
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 else
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE))
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 /* Disable OverSampling mode if needed */
<> 144:ef7eb2e8f9f7 550 hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE;
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552 }
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Clear the old sampling time */
<> 144:ef7eb2e8f9f7 555 hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR);
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Set the new sample time */
<> 144:ef7eb2e8f9f7 558 hadc->Instance->SMPR |= hadc->Init.SamplingTime;
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Clear ADC error code */
<> 144:ef7eb2e8f9f7 561 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Set the ADC state */
<> 144:ef7eb2e8f9f7 564 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 565 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 566 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Return function status */
<> 144:ef7eb2e8f9f7 570 return HAL_OK;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @brief Deinitialize the ADC peripheral registers to their default reset
<> 144:ef7eb2e8f9f7 575 * values, with deinitialization of the ADC MSP.
<> 144:ef7eb2e8f9f7 576 * @note For devices with several ADCs: reset of ADC common registers is done
<> 144:ef7eb2e8f9f7 577 * only if all ADCs sharing the same common group are disabled.
<> 144:ef7eb2e8f9f7 578 * If this is not the case, reset of these common parameters reset is
<> 151:5eaa88a5bcc7 579 * bypassed without error reporting: it can be the intended behavior in
<> 144:ef7eb2e8f9f7 580 * case of reset of a single ADC while the other ADCs sharing the same
<> 144:ef7eb2e8f9f7 581 * common group is still running.
<> 144:ef7eb2e8f9f7 582 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 583 * @retval HAL status
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 590 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 591 {
Anna Bridge 186:707f6e361f3e 592 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Check the parameters */
<> 144:ef7eb2e8f9f7 596 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Set ADC state */
<> 144:ef7eb2e8f9f7 599 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Stop potential conversion on going, on regular group */
<> 144:ef7eb2e8f9f7 602 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 605 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 606 {
<> 144:ef7eb2e8f9f7 607 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 608 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 611 if (tmp_hal_status != HAL_ERROR)
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 /* Change ADC state */
<> 144:ef7eb2e8f9f7 614 hadc->State = HAL_ADC_STATE_READY;
<> 144:ef7eb2e8f9f7 615 }
Anna Bridge 186:707f6e361f3e 616 }
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 620 /* correctly completed. */
<> 144:ef7eb2e8f9f7 621 if (tmp_hal_status != HAL_ERROR)
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* ========== Reset ADC registers ========== */
<> 144:ef7eb2e8f9f7 625 /* Reset register IER */
<> 144:ef7eb2e8f9f7 626 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS | \
<> 144:ef7eb2e8f9f7 627 ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP ));
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Reset register ISR */
<> 144:ef7eb2e8f9f7 631 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS | \
<> 144:ef7eb2e8f9f7 632 ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Reset register CR */
<> 144:ef7eb2e8f9f7 636 /* Disable voltage regulator */
<> 144:ef7eb2e8f9f7 637 /* Note: Regulator disable useful for power saving */
<> 144:ef7eb2e8f9f7 638 /* Reset ADVREGEN bit */
<> 144:ef7eb2e8f9f7 639 hadc->Instance->CR &= ~ADC_CR_ADVREGEN;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable */
<> 144:ef7eb2e8f9f7 642 /* No action */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /* Reset register CFGR1 */
<> 144:ef7eb2e8f9f7 645 hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | \
<> 144:ef7eb2e8f9f7 646 ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \
<> 144:ef7eb2e8f9f7 647 ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | \
<> 144:ef7eb2e8f9f7 648 ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | \
<> 144:ef7eb2e8f9f7 649 ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Reset register CFGR2 */
<> 144:ef7eb2e8f9f7 652 hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | \
<> 144:ef7eb2e8f9f7 653 ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE );
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Reset register SMPR */
<> 144:ef7eb2e8f9f7 657 hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR);
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Reset register TR */
<> 144:ef7eb2e8f9f7 660 hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT);
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Reset register CALFACT */
<> 144:ef7eb2e8f9f7 663 hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Reset register DR */
<> 144:ef7eb2e8f9f7 670 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Reset register CALFACT */
<> 144:ef7eb2e8f9f7 673 hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* ========== Hard reset ADC peripheral ========== */
<> 144:ef7eb2e8f9f7 676 /* Performs a global reset of the entire ADC peripheral: ADC state is */
<> 144:ef7eb2e8f9f7 677 /* forced to a similar state after device power-on. */
<> 144:ef7eb2e8f9f7 678 /* If needed, copy-paste and uncomment the following reset code into */
<> 144:ef7eb2e8f9f7 679 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
<> 144:ef7eb2e8f9f7 680 /* */
<> 144:ef7eb2e8f9f7 681 /* __HAL_RCC_ADC1_FORCE_RESET() */
<> 144:ef7eb2e8f9f7 682 /* __HAL_RCC_ADC1_RELEASE_RESET() */
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 685 HAL_ADC_MspDeInit(hadc);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 688 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 689
Anna Bridge 186:707f6e361f3e 690 /* Set ADC state */
Anna Bridge 186:707f6e361f3e 691 hadc->State = HAL_ADC_STATE_RESET;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Process unlocked */
<> 144:ef7eb2e8f9f7 695 __HAL_UNLOCK(hadc);
Anna Bridge 186:707f6e361f3e 696
<> 144:ef7eb2e8f9f7 697 /* Return function status */
<> 144:ef7eb2e8f9f7 698 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /**
Anna Bridge 186:707f6e361f3e 702 * @brief Initialize the ADC MSP.
<> 144:ef7eb2e8f9f7 703 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 704 * @retval None
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 709 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 710
Anna Bridge 186:707f6e361f3e 711 /* NOTE : This function should not be modified. When the callback is needed,
Anna Bridge 186:707f6e361f3e 712 function HAL_ADC_MspInit must be implemented in the user file.
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /**
Anna Bridge 186:707f6e361f3e 717 * @brief DeInitialize the ADC MSP.
<> 144:ef7eb2e8f9f7 718 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 719 * @retval None
<> 144:ef7eb2e8f9f7 720 */
<> 144:ef7eb2e8f9f7 721 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 724 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 727 function HAL_ADC_MspDeInit must be implemented in the user file.
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /**
<> 144:ef7eb2e8f9f7 732 * @}
<> 144:ef7eb2e8f9f7 733 */
<> 144:ef7eb2e8f9f7 734
Anna Bridge 186:707f6e361f3e 735 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
Anna Bridge 186:707f6e361f3e 736 * @brief ADC IO operation functions
<> 144:ef7eb2e8f9f7 737 *
<> 144:ef7eb2e8f9f7 738 @verbatim
<> 144:ef7eb2e8f9f7 739 ===============================================================================
Anna Bridge 186:707f6e361f3e 740 ##### IO operation functions #####
Anna Bridge 186:707f6e361f3e 741 ===============================================================================
<> 144:ef7eb2e8f9f7 742 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 743 (+) Start conversion of regular group.
<> 144:ef7eb2e8f9f7 744 (+) Stop conversion of regular group.
<> 144:ef7eb2e8f9f7 745 (+) Poll for conversion complete on regular group.
Anna Bridge 186:707f6e361f3e 746 (+) Poll for conversion event.
<> 144:ef7eb2e8f9f7 747 (+) Get result of regular channel conversion.
<> 144:ef7eb2e8f9f7 748 (+) Start conversion of regular group and enable interruptions.
<> 144:ef7eb2e8f9f7 749 (+) Stop conversion of regular group and disable interruptions.
<> 144:ef7eb2e8f9f7 750 (+) Handle ADC interrupt request
<> 144:ef7eb2e8f9f7 751 (+) Start conversion of regular group and enable DMA transfer.
<> 144:ef7eb2e8f9f7 752 (+) Stop conversion of regular group and disable ADC DMA transfer.
<> 144:ef7eb2e8f9f7 753 @endverbatim
<> 144:ef7eb2e8f9f7 754 * @{
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /**
Anna Bridge 186:707f6e361f3e 758 * @brief Enable ADC, start conversion of regular group.
Anna Bridge 186:707f6e361f3e 759 * @note Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 760 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 761 * @retval HAL status
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Check the parameters */
<> 144:ef7eb2e8f9f7 768 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 771 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 /* Process locked */
<> 144:ef7eb2e8f9f7 774 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Enable the ADC peripheral */
Anna Bridge 186:707f6e361f3e 777 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
Anna Bridge 186:707f6e361f3e 778 /* performed automatically by hardware. */
<> 144:ef7eb2e8f9f7 779 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 785 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 /* Set ADC state */
<> 144:ef7eb2e8f9f7 788 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 789 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 790 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 791 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 792 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 795 ADC_CLEAR_ERRORCODE(hadc);
Anna Bridge 186:707f6e361f3e 796
Anna Bridge 186:707f6e361f3e 797 /* Process unlocked */
<> 144:ef7eb2e8f9f7 798 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 799 /* interruption, to let the process to ADC IRQ Handler. */
Anna Bridge 186:707f6e361f3e 800 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 803 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 804 /* operations) */
<> 144:ef7eb2e8f9f7 805 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 808 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 809 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 810 /* trigger event. */
<> 144:ef7eb2e8f9f7 811 hadc->Instance->CR |= ADC_CR_ADSTART;
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814 else
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /* Return function status */
<> 144:ef7eb2e8f9f7 820 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /**
Anna Bridge 186:707f6e361f3e 824 * @brief Stop ADC conversion of regular group (and injected channels in
Anna Bridge 186:707f6e361f3e 825 * case of auto_injection mode), disable ADC peripheral.
<> 144:ef7eb2e8f9f7 826 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 827 * @retval HAL status.
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /* Check the parameters */
<> 144:ef7eb2e8f9f7 834 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Process locked */
<> 144:ef7eb2e8f9f7 837 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 838
Anna Bridge 186:707f6e361f3e 839 /* 1. Stop potential conversion on going, on ADC group regular */
<> 144:ef7eb2e8f9f7 840 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 843 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 846 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 849 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 /* Set ADC state */
<> 144:ef7eb2e8f9f7 852 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 853 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 854 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 855 }
Anna Bridge 186:707f6e361f3e 856 }
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Process unlocked */
<> 144:ef7eb2e8f9f7 859 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Return function status */
<> 144:ef7eb2e8f9f7 862 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /**
<> 144:ef7eb2e8f9f7 866 * @brief Wait for regular group conversion to be completed.
<> 144:ef7eb2e8f9f7 867 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
<> 144:ef7eb2e8f9f7 868 * conversion) are cleared by this function, with an exception:
<> 144:ef7eb2e8f9f7 869 * if low power feature "LowPowerAutoWait" is enabled, flags are
<> 144:ef7eb2e8f9f7 870 * not cleared to not interfere with this feature until data register
<> 144:ef7eb2e8f9f7 871 * is read using function HAL_ADC_GetValue().
<> 144:ef7eb2e8f9f7 872 * @note This function cannot be used in a particular setup: ADC configured
<> 144:ef7eb2e8f9f7 873 * in DMA mode and polling for end of each conversion (ADC init
<> 144:ef7eb2e8f9f7 874 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
<> 144:ef7eb2e8f9f7 875 * In this case, DMA resets the flag EOC and polling cannot be
<> 144:ef7eb2e8f9f7 876 * performed on each conversion. Nevertheless, polling can still
<> 144:ef7eb2e8f9f7 877 * be performed on the complete sequence (ADC init
<> 144:ef7eb2e8f9f7 878 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
<> 144:ef7eb2e8f9f7 879 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 880 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 881 * @retval HAL status
<> 144:ef7eb2e8f9f7 882 */
<> 144:ef7eb2e8f9f7 883 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 884 {
Anna Bridge 186:707f6e361f3e 885 uint32_t tickstart = 0;
Anna Bridge 186:707f6e361f3e 886 uint32_t tmp_Flag_EOC = 0x00;
Anna Bridge 186:707f6e361f3e 887
<> 144:ef7eb2e8f9f7 888 /* Check the parameters */
<> 144:ef7eb2e8f9f7 889 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
Anna Bridge 186:707f6e361f3e 890
Anna Bridge 186:707f6e361f3e 891 /* If end of conversion selected to end of sequence conversions */
<> 144:ef7eb2e8f9f7 892 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 tmp_Flag_EOC = ADC_FLAG_EOS;
<> 144:ef7eb2e8f9f7 895 }
Anna Bridge 186:707f6e361f3e 896 /* If end of conversion selected to end of unitary conversion */
<> 144:ef7eb2e8f9f7 897 else /* ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 /* Verification that ADC configuration is compliant with polling for */
<> 144:ef7eb2e8f9f7 900 /* each conversion: */
<> 144:ef7eb2e8f9f7 901 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
<> 144:ef7eb2e8f9f7 902 /* several ranks and polling for end of each conversion. */
<> 144:ef7eb2e8f9f7 903 /* For code simplicity sake, this particular case is generalized to */
<> 144:ef7eb2e8f9f7 904 /* ADC configured in DMA mode and and polling for end of each conversion. */
<> 144:ef7eb2e8f9f7 905 if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 908 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Process unlocked */
<> 144:ef7eb2e8f9f7 911 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 else
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Get tick count */
<> 144:ef7eb2e8f9f7 922 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 923
Anna Bridge 186:707f6e361f3e 924 /* Wait until End of unitary conversion or sequence conversions flag is raised */
<> 144:ef7eb2e8f9f7 925 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 928 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 929 {
<> 151:5eaa88a5bcc7 930 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 933 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Process unlocked */
<> 144:ef7eb2e8f9f7 936 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940 }
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 944 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 947 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 948 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 949 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 950 {
<> 144:ef7eb2e8f9f7 951 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 952 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 953 {
<> 144:ef7eb2e8f9f7 954 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<> 144:ef7eb2e8f9f7 955 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 956 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 /* Disable ADC end of single conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 959 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 960 /* HAL_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 961 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 962 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* Set ADC state */
<> 144:ef7eb2e8f9f7 965 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 966 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 967 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969 else
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 /* Change ADC state to error state */
<> 144:ef7eb2e8f9f7 972 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 975 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 976 }
<> 144:ef7eb2e8f9f7 977 }
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /* Clear end of conversion flag of regular group if low power feature */
<> 144:ef7eb2e8f9f7 981 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
<> 144:ef7eb2e8f9f7 982 /* until data register is read using function HAL_ADC_GetValue(). */
<> 144:ef7eb2e8f9f7 983 if (hadc->Init.LowPowerAutoWait == DISABLE)
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 986 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
<> 144:ef7eb2e8f9f7 987 }
<> 144:ef7eb2e8f9f7 988
Anna Bridge 186:707f6e361f3e 989 /* Return function status */
<> 144:ef7eb2e8f9f7 990 return HAL_OK;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /**
Anna Bridge 186:707f6e361f3e 994 * @brief Poll for ADC event.
<> 144:ef7eb2e8f9f7 995 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 996 * @param EventType: the ADC event type.
<> 144:ef7eb2e8f9f7 997 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 998 * @arg ADC_AWD_EVENT: ADC Analog watchdog event
<> 144:ef7eb2e8f9f7 999 * @arg ADC_OVR_EVENT: ADC Overrun event
<> 144:ef7eb2e8f9f7 1000 * @param Timeout: Timeout value in millisecond.
Anna Bridge 186:707f6e361f3e 1001 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
Anna Bridge 186:707f6e361f3e 1002 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
Anna Bridge 186:707f6e361f3e 1003 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
Anna Bridge 186:707f6e361f3e 1004 * by a new converted data as soon as OVR is cleared.
Anna Bridge 186:707f6e361f3e 1005 * To reset OVR flag once the preserved data is retrieved, the user can resort
Anna Bridge 186:707f6e361f3e 1006 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1007 * @retval HAL status
<> 144:ef7eb2e8f9f7 1008 */
<> 144:ef7eb2e8f9f7 1009 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1010 {
<> 151:5eaa88a5bcc7 1011 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1014 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1015 assert_param(IS_ADC_EVENT_TYPE(EventType));
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /* Get tick count */
<> 144:ef7eb2e8f9f7 1018 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Check selected event flag */
<> 144:ef7eb2e8f9f7 1021 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1024 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1025 {
Anna Bridge 186:707f6e361f3e 1026 if((Timeout == 0U) ||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1027 {
<> 144:ef7eb2e8f9f7 1028 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1029 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1032 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 switch(EventType)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 /* Analog watchdog (level out of window) event */
<> 144:ef7eb2e8f9f7 1042 case ADC_AWD_EVENT:
<> 144:ef7eb2e8f9f7 1043 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1044 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1047 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 1048 break;
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /* Overrun event */
<> 144:ef7eb2e8f9f7 1051 default: /* Case ADC_OVR_EVENT */
<> 144:ef7eb2e8f9f7 1052 /* If overrun is set to overwrite previous data, overrun event is not */
<> 144:ef7eb2e8f9f7 1053 /* considered as an error. */
<> 144:ef7eb2e8f9f7 1054 /* (cf ref manual "Managing conversions without using the DMA and without */
<> 144:ef7eb2e8f9f7 1055 /* overrun ") */
<> 144:ef7eb2e8f9f7 1056 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1059 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /* Set ADC error code to overrun */
<> 144:ef7eb2e8f9f7 1062 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1063 }
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 /* Clear ADC Overrun flag */
<> 144:ef7eb2e8f9f7 1066 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1067 break;
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069
Anna Bridge 186:707f6e361f3e 1070 /* Return function status */
<> 144:ef7eb2e8f9f7 1071 return HAL_OK;
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /**
Anna Bridge 186:707f6e361f3e 1075 * @brief Enable ADC, start conversion of regular group with interruption.
Anna Bridge 186:707f6e361f3e 1076 * @note Interruptions enabled in this function according to initialization
Anna Bridge 186:707f6e361f3e 1077 * setting : EOC (end of conversion), EOS (end of sequence),
Anna Bridge 186:707f6e361f3e 1078 * OVR overrun.
<> 144:ef7eb2e8f9f7 1079 * Each of these interruptions has its dedicated callback function.
Anna Bridge 186:707f6e361f3e 1080 * @note To guarantee a proper reset of all interruptions once all the needed
Anna Bridge 186:707f6e361f3e 1081 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
Anna Bridge 186:707f6e361f3e 1082 * a correct stop of the IT-based conversions.
Anna Bridge 186:707f6e361f3e 1083 * @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
Anna Bridge 186:707f6e361f3e 1084 * interruption. If required (e.g. in case of oversampling with trigger
Anna Bridge 186:707f6e361f3e 1085 * mode), the user must:
Anna Bridge 186:707f6e361f3e 1086 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
Anna Bridge 186:707f6e361f3e 1087 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
Anna Bridge 186:707f6e361f3e 1088 * before calling HAL_ADC_Start_IT().
<> 144:ef7eb2e8f9f7 1089 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1090 * @retval HAL status
<> 144:ef7eb2e8f9f7 1091 */
<> 144:ef7eb2e8f9f7 1092 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
Anna Bridge 186:707f6e361f3e 1095
<> 144:ef7eb2e8f9f7 1096 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1097 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 1100 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1101 {
<> 144:ef7eb2e8f9f7 1102 /* Process locked */
<> 144:ef7eb2e8f9f7 1103 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /* Enable the ADC peripheral */
Anna Bridge 186:707f6e361f3e 1106 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
Anna Bridge 186:707f6e361f3e 1107 /* performed automatically by hardware. */
<> 144:ef7eb2e8f9f7 1108 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1114 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1115 {
<> 144:ef7eb2e8f9f7 1116 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1117 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1118 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1119 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1120 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 1121 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1124 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1127 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1128 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1129 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1132 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 1133 /* operations) */
<> 144:ef7eb2e8f9f7 1134 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /* Enable ADC end of conversion interrupt */
Anna Bridge 186:707f6e361f3e 1137 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1138 switch(hadc->Init.EOCSelection)
<> 144:ef7eb2e8f9f7 1139 {
<> 144:ef7eb2e8f9f7 1140 case ADC_EOC_SEQ_CONV:
<> 144:ef7eb2e8f9f7 1141 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 1142 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 1143 break;
<> 144:ef7eb2e8f9f7 1144 /* case ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 1145 default:
<> 144:ef7eb2e8f9f7 1146 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 1147 break;
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1151 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1152 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1153 /* trigger event. */
<> 144:ef7eb2e8f9f7 1154 hadc->Instance->CR |= ADC_CR_ADSTART;
<> 144:ef7eb2e8f9f7 1155 }
<> 144:ef7eb2e8f9f7 1156 }
<> 144:ef7eb2e8f9f7 1157 else
<> 144:ef7eb2e8f9f7 1158 {
<> 144:ef7eb2e8f9f7 1159 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1160 }
Anna Bridge 186:707f6e361f3e 1161
<> 144:ef7eb2e8f9f7 1162 /* Return function status */
<> 144:ef7eb2e8f9f7 1163 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1164 }
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /**
Anna Bridge 186:707f6e361f3e 1167 * @brief Stop ADC conversion of regular group (and injected group in
Anna Bridge 186:707f6e361f3e 1168 * case of auto_injection mode), disable interrution of
<> 144:ef7eb2e8f9f7 1169 * end-of-conversion, disable ADC peripheral.
<> 144:ef7eb2e8f9f7 1170 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1171 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1172 */
<> 144:ef7eb2e8f9f7 1173 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1178 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
Anna Bridge 186:707f6e361f3e 1179
<> 144:ef7eb2e8f9f7 1180 /* Process locked */
<> 144:ef7eb2e8f9f7 1181 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1182
Anna Bridge 186:707f6e361f3e 1183 /* 1. Stop potential conversion on going, on ADC group regular */
<> 144:ef7eb2e8f9f7 1184 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 1187 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1188 {
<> 144:ef7eb2e8f9f7 1189 /* Disable ADC end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 1190 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1191 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1194 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1197 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1198 {
<> 144:ef7eb2e8f9f7 1199 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1200 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1201 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 1202 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1203 }
<> 144:ef7eb2e8f9f7 1204 }
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1207 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Return function status */
<> 144:ef7eb2e8f9f7 1210 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1211 }
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /**
Anna Bridge 186:707f6e361f3e 1214 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
Anna Bridge 186:707f6e361f3e 1215 * @note Interruptions enabled in this function:
Anna Bridge 186:707f6e361f3e 1216 * overrun (if applicable), DMA half transfer, DMA transfer complete.
<> 144:ef7eb2e8f9f7 1217 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1218 * @param hadc: ADC handle
Anna Bridge 186:707f6e361f3e 1219 * @param pData: Destination Buffer address.
Anna Bridge 186:707f6e361f3e 1220 * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
Anna Bridge 186:707f6e361f3e 1221 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1222 */
<> 144:ef7eb2e8f9f7 1223 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 1224 {
<> 144:ef7eb2e8f9f7 1225 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1228 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 1231 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 /* Process locked */
<> 144:ef7eb2e8f9f7 1234 __HAL_LOCK(hadc);
Anna Bridge 186:707f6e361f3e 1235
Anna Bridge 186:707f6e361f3e 1236 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1237 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
<> 144:ef7eb2e8f9f7 1238 /* performed automatically by hardware. */
<> 144:ef7eb2e8f9f7 1239 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<> 144:ef7eb2e8f9f7 1240 {
<> 144:ef7eb2e8f9f7 1241 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1245 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1246 {
<> 144:ef7eb2e8f9f7 1247 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1248 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1249 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1250 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1251 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 1252 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1255 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1258 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1259 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1260 __HAL_UNLOCK(hadc);
Anna Bridge 186:707f6e361f3e 1261
<> 144:ef7eb2e8f9f7 1262 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1263 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
Anna Bridge 186:707f6e361f3e 1264
<> 144:ef7eb2e8f9f7 1265 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 1266 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1269 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 1273 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1276 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 1277 /* operations) */
<> 144:ef7eb2e8f9f7 1278 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1281 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /* Enable ADC DMA mode */
<> 144:ef7eb2e8f9f7 1284 hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* Start the DMA channel */
<> 144:ef7eb2e8f9f7 1287 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
Anna Bridge 186:707f6e361f3e 1288
<> 144:ef7eb2e8f9f7 1289 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1290 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1291 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1292 /* trigger event. */
<> 144:ef7eb2e8f9f7 1293 hadc->Instance->CR |= ADC_CR_ADSTART;
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295 }
<> 144:ef7eb2e8f9f7 1296 else
<> 144:ef7eb2e8f9f7 1297 {
<> 144:ef7eb2e8f9f7 1298 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1299 }
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /* Return function status */
<> 144:ef7eb2e8f9f7 1302 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /**
Anna Bridge 186:707f6e361f3e 1306 * @brief Stop ADC conversion of regular group (and injected group in
Anna Bridge 186:707f6e361f3e 1307 * case of auto_injection mode), disable ADC DMA transfer, disable
<> 144:ef7eb2e8f9f7 1308 * ADC peripheral.
<> 144:ef7eb2e8f9f7 1309 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1310 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1311 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1312 */
<> 144:ef7eb2e8f9f7 1313 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1314 {
<> 144:ef7eb2e8f9f7 1315 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1318 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 /* Process locked */
<> 144:ef7eb2e8f9f7 1321 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1322
Anna Bridge 186:707f6e361f3e 1323 /* 1. Stop potential ADC group regular conversion on going */
<> 144:ef7eb2e8f9f7 1324 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 1327 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1328 {
<> 144:ef7eb2e8f9f7 1329 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
Anna Bridge 186:707f6e361f3e 1330 CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
<> 144:ef7eb2e8f9f7 1331
Anna Bridge 186:707f6e361f3e 1332 /* Disable the DMA channel (in case of DMA in circular mode or stop */
<> 144:ef7eb2e8f9f7 1333 /* while DMA transfer is on going) */
Anna Bridge 186:707f6e361f3e 1334 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 1337 if (tmp_hal_status != HAL_OK)
<> 144:ef7eb2e8f9f7 1338 {
<> 144:ef7eb2e8f9f7 1339 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1340 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1344 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1347 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */
<> 144:ef7eb2e8f9f7 1348 /* in memory a potential failing status. */
<> 144:ef7eb2e8f9f7 1349 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1350 {
<> 144:ef7eb2e8f9f7 1351 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353 else
<> 144:ef7eb2e8f9f7 1354 {
<> 144:ef7eb2e8f9f7 1355 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1356 }
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1359 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1362 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1363 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 1364 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1365 }
Anna Bridge 186:707f6e361f3e 1366
Anna Bridge 186:707f6e361f3e 1367 }
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1370 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Return function status */
<> 144:ef7eb2e8f9f7 1373 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1374 }
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /**
<> 144:ef7eb2e8f9f7 1377 * @brief Get ADC regular group conversion result.
Anna Bridge 186:707f6e361f3e 1378 * @note Reading register DR automatically clears ADC flag EOC
Anna Bridge 186:707f6e361f3e 1379 * (ADC group regular end of unitary conversion).
Anna Bridge 186:707f6e361f3e 1380 * @note This function does not clear ADC flag EOS
<> 144:ef7eb2e8f9f7 1381 * (ADC group regular end of sequence conversion).
<> 144:ef7eb2e8f9f7 1382 * Occurrence of flag EOS rising:
<> 144:ef7eb2e8f9f7 1383 * - If sequencer is composed of 1 rank, flag EOS is equivalent
<> 144:ef7eb2e8f9f7 1384 * to flag EOC.
<> 144:ef7eb2e8f9f7 1385 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 1386 * sequence flag EOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 1387 * both flags EOC and EOS are raised.
<> 144:ef7eb2e8f9f7 1388 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 1389 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 1390 * model polling: @ref HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 1391 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<> 144:ef7eb2e8f9f7 1392 * @param hadc: ADC handle
Anna Bridge 186:707f6e361f3e 1393 * @retval ADC group regular conversion data
<> 144:ef7eb2e8f9f7 1394 */
<> 144:ef7eb2e8f9f7 1395 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
Anna Bridge 186:707f6e361f3e 1396 {
<> 144:ef7eb2e8f9f7 1397 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1398 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /* Note: EOC flag is not cleared here by software because automatically */
<> 144:ef7eb2e8f9f7 1401 /* cleared by hardware when reading register DR. */
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 1404 return hadc->Instance->DR;
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /**
Anna Bridge 186:707f6e361f3e 1408 * @brief Handle ADC interrupt request.
<> 144:ef7eb2e8f9f7 1409 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1410 * @retval None
<> 144:ef7eb2e8f9f7 1411 */
<> 144:ef7eb2e8f9f7 1412 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1413 {
<> 144:ef7eb2e8f9f7 1414 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1415 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1416 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
Anna Bridge 186:707f6e361f3e 1417 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 /* ========== Check End of Conversion flag for regular group ========== */
<> 144:ef7eb2e8f9f7 1420 if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
Anna Bridge 186:707f6e361f3e 1421 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
<> 144:ef7eb2e8f9f7 1422 {
<> 144:ef7eb2e8f9f7 1423 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 1424 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 1425 {
<> 144:ef7eb2e8f9f7 1426 /* Set ADC state */
Anna Bridge 186:707f6e361f3e 1427 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 1428 }
Anna Bridge 186:707f6e361f3e 1429
<> 144:ef7eb2e8f9f7 1430 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 1431 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 1432 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1433 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 1434 {
<> 144:ef7eb2e8f9f7 1435 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 1436 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 1437 {
<> 144:ef7eb2e8f9f7 1438 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
Anna Bridge 186:707f6e361f3e 1439 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 1440 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
Anna Bridge 186:707f6e361f3e 1441 {
<> 144:ef7eb2e8f9f7 1442 /* Disable ADC end of single conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 1443 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 1444 /* HAL_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 1445 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 1446 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1449 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1450 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 1451 HAL_ADC_STATE_READY);
Anna Bridge 186:707f6e361f3e 1452 }
Anna Bridge 186:707f6e361f3e 1453 else
Anna Bridge 186:707f6e361f3e 1454 {
Anna Bridge 186:707f6e361f3e 1455 /* Change ADC state to error state */
<> 144:ef7eb2e8f9f7 1456 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1457
Anna Bridge 186:707f6e361f3e 1458 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1459 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1460 }
<> 144:ef7eb2e8f9f7 1461 }
Anna Bridge 186:707f6e361f3e 1462 }
Anna Bridge 186:707f6e361f3e 1463
<> 144:ef7eb2e8f9f7 1464 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1465 /* Note: into callback, to determine if conversion has been triggered */
<> 144:ef7eb2e8f9f7 1466 /* from EOC or EOS, possibility to use: */
<> 144:ef7eb2e8f9f7 1467 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
<> 144:ef7eb2e8f9f7 1468 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 1471 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
<> 144:ef7eb2e8f9f7 1472 /* conversion flags clear induces the release of the preserved data.*/
<> 144:ef7eb2e8f9f7 1473 /* Therefore, if the preserved data value is needed, it must be */
<> 144:ef7eb2e8f9f7 1474 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
Anna Bridge 186:707f6e361f3e 1475 /* Note: Management of low power auto-wait enabled: flags must be cleared */
Anna Bridge 186:707f6e361f3e 1476 /* by user when fetching ADC conversion data. */
Anna Bridge 186:707f6e361f3e 1477 /* This case is managed in IRQ handler, but this low-power mode */
Anna Bridge 186:707f6e361f3e 1478 /* should not be used with programming model IT or DMA. */
Anna Bridge 186:707f6e361f3e 1479 /* Refer to comment of parameter "LowPowerAutoWait". */
Anna Bridge 186:707f6e361f3e 1480 if (hadc->Init.LowPowerAutoWait != ENABLE)
Anna Bridge 186:707f6e361f3e 1481 {
Anna Bridge 186:707f6e361f3e 1482 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
<> 144:ef7eb2e8f9f7 1483 }
Anna Bridge 186:707f6e361f3e 1484 }
<> 144:ef7eb2e8f9f7 1485
Anna Bridge 186:707f6e361f3e 1486 /* ========== Check analog watchdog 1 flag ========== */
<> 144:ef7eb2e8f9f7 1487 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
<> 144:ef7eb2e8f9f7 1488 {
Anna Bridge 186:707f6e361f3e 1489 /* Set ADC state */
Anna Bridge 186:707f6e361f3e 1490 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1491
Anna Bridge 186:707f6e361f3e 1492 /* Level out of window 1 callback */
<> 144:ef7eb2e8f9f7 1493 HAL_ADC_LevelOutOfWindowCallback(hadc);
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* Clear ADC Analog watchdog flag */
Anna Bridge 186:707f6e361f3e 1496 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 1497
Anna Bridge 186:707f6e361f3e 1498 }
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /* ========== Check Overrun flag ========== */
<> 144:ef7eb2e8f9f7 1502 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
<> 144:ef7eb2e8f9f7 1503 {
<> 144:ef7eb2e8f9f7 1504 /* If overrun is set to overwrite previous data (default setting), */
<> 144:ef7eb2e8f9f7 1505 /* overrun event is not considered as an error. */
<> 144:ef7eb2e8f9f7 1506 /* (cf ref manual "Managing conversions without using the DMA and without */
<> 144:ef7eb2e8f9f7 1507 /* overrun ") */
<> 144:ef7eb2e8f9f7 1508 /* Exception for usage with DMA overrun event always considered as an */
<> 144:ef7eb2e8f9f7 1509 /* error. */
<> 144:ef7eb2e8f9f7 1510 if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) ||
<> 144:ef7eb2e8f9f7 1511 HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) )
<> 144:ef7eb2e8f9f7 1512 {
<> 144:ef7eb2e8f9f7 1513 /* Set ADC error code to overrun */
<> 144:ef7eb2e8f9f7 1514 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Clear ADC overrun flag */
<> 144:ef7eb2e8f9f7 1517 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 /* Error callback */
<> 144:ef7eb2e8f9f7 1520 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 1521 }
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /* Clear the Overrun flag */
<> 144:ef7eb2e8f9f7 1524 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1525 }
Anna Bridge 186:707f6e361f3e 1526
<> 144:ef7eb2e8f9f7 1527 }
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /**
Anna Bridge 186:707f6e361f3e 1530 * @brief Conversion complete callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1531 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1532 * @retval None
<> 144:ef7eb2e8f9f7 1533 */
<> 144:ef7eb2e8f9f7 1534 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1535 {
<> 144:ef7eb2e8f9f7 1536 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1537 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1540 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1541 */
<> 144:ef7eb2e8f9f7 1542 }
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /**
Anna Bridge 186:707f6e361f3e 1545 * @brief Conversion DMA half-transfer callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1546 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1547 * @retval None
<> 144:ef7eb2e8f9f7 1548 */
<> 144:ef7eb2e8f9f7 1549 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1550 {
<> 144:ef7eb2e8f9f7 1551 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1552 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1555 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
Anna Bridge 186:707f6e361f3e 1556 */
<> 144:ef7eb2e8f9f7 1557 }
<> 144:ef7eb2e8f9f7 1558
<> 144:ef7eb2e8f9f7 1559 /**
Anna Bridge 186:707f6e361f3e 1560 * @brief Analog watchdog 1 callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1561 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1562 * @retval None
<> 144:ef7eb2e8f9f7 1563 */
<> 144:ef7eb2e8f9f7 1564 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1565 {
<> 144:ef7eb2e8f9f7 1566 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1567 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 /* NOTE : This function should not be modified. When the callback is needed,
Anna Bridge 186:707f6e361f3e 1570 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
Anna Bridge 186:707f6e361f3e 1571 */
<> 144:ef7eb2e8f9f7 1572 }
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574 /**
Anna Bridge 186:707f6e361f3e 1575 * @brief ADC error callback in non-blocking mode
Anna Bridge 186:707f6e361f3e 1576 * (ADC conversion with interruption or transfer by DMA).
Anna Bridge 186:707f6e361f3e 1577 * @note In case of error due to overrun when using ADC with DMA transfer
Anna Bridge 186:707f6e361f3e 1578 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
Anna Bridge 186:707f6e361f3e 1579 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
Anna Bridge 186:707f6e361f3e 1580 * - If needed, restart a new ADC conversion using function
Anna Bridge 186:707f6e361f3e 1581 * "HAL_ADC_Start_DMA()"
Anna Bridge 186:707f6e361f3e 1582 * (this function is also clearing overrun flag)
<> 144:ef7eb2e8f9f7 1583 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1584 * @retval None
<> 144:ef7eb2e8f9f7 1585 */
<> 144:ef7eb2e8f9f7 1586 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
<> 144:ef7eb2e8f9f7 1587 {
<> 144:ef7eb2e8f9f7 1588 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1589 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1592 function HAL_ADC_ErrorCallback must be implemented in the user file.
Anna Bridge 186:707f6e361f3e 1593 */
<> 144:ef7eb2e8f9f7 1594 }
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /**
<> 144:ef7eb2e8f9f7 1597 * @}
<> 144:ef7eb2e8f9f7 1598 */
<> 144:ef7eb2e8f9f7 1599
Anna Bridge 186:707f6e361f3e 1600 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
Anna Bridge 186:707f6e361f3e 1601 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1602 *
<> 144:ef7eb2e8f9f7 1603 @verbatim
<> 144:ef7eb2e8f9f7 1604 ===============================================================================
<> 144:ef7eb2e8f9f7 1605 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1606 ===============================================================================
<> 144:ef7eb2e8f9f7 1607 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1608 (+) Configure channels on regular group
<> 144:ef7eb2e8f9f7 1609 (+) Configure the analog watchdog
<> 144:ef7eb2e8f9f7 1610
<> 144:ef7eb2e8f9f7 1611 @endverbatim
<> 144:ef7eb2e8f9f7 1612 * @{
<> 144:ef7eb2e8f9f7 1613 */
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 /**
Anna Bridge 186:707f6e361f3e 1616 * @brief Configure a channel to be assigned to ADC group regular.
<> 144:ef7eb2e8f9f7 1617 * @note In case of usage of internal measurement channels:
<> 144:ef7eb2e8f9f7 1618 * VrefInt/Vlcd(STM32L0x3xx only)/TempSensor.
<> 144:ef7eb2e8f9f7 1619 * Sampling time constraints must be respected (sampling time can be
<> 144:ef7eb2e8f9f7 1620 * adjusted in function of ADC clock frequency and sampling time
<> 144:ef7eb2e8f9f7 1621 * setting).
<> 144:ef7eb2e8f9f7 1622 * Refer to device datasheet for timings values, parameters TS_vrefint,
<> 144:ef7eb2e8f9f7 1623 * TS_vlcd (STM32L0x3xx only), TS_temp (values rough order: 5us to 17us).
<> 144:ef7eb2e8f9f7 1624 * These internal paths can be be disabled using function
<> 144:ef7eb2e8f9f7 1625 * HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 1626 * @note Possibility to update parameters on the fly:
Anna Bridge 186:707f6e361f3e 1627 * This function initializes channel into ADC group regular,
Anna Bridge 186:707f6e361f3e 1628 * following calls to this function can be used to reconfigure
Anna Bridge 186:707f6e361f3e 1629 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
Anna Bridge 186:707f6e361f3e 1630 * without resetting the ADC.
Anna Bridge 186:707f6e361f3e 1631 * The setting of these parameters is conditioned to ADC state:
Anna Bridge 186:707f6e361f3e 1632 * Refer to comments of structure "ADC_ChannelConfTypeDef".
<> 144:ef7eb2e8f9f7 1633 * @param hadc: ADC handle
Anna Bridge 186:707f6e361f3e 1634 * @param sConfig: Structure of ADC channel assigned to ADC group regular.
<> 144:ef7eb2e8f9f7 1635 * @retval HAL status
<> 144:ef7eb2e8f9f7 1636 */
<> 144:ef7eb2e8f9f7 1637 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 1638 {
<> 144:ef7eb2e8f9f7 1639 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1640 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1641 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 1642 assert_param(IS_ADC_RANK(sConfig->Rank));
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 /* Process locked */
Anna Bridge 186:707f6e361f3e 1645 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 1648 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 1649 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 1650 /* - Channel number */
<> 144:ef7eb2e8f9f7 1651 /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 1652 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)
<> 144:ef7eb2e8f9f7 1653 {
<> 144:ef7eb2e8f9f7 1654 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1655 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1656 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1657 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1658 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1659 }
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 if (sConfig->Rank != ADC_RANK_NONE)
<> 144:ef7eb2e8f9f7 1662 {
<> 144:ef7eb2e8f9f7 1663 /* Enable selected channels */
<> 144:ef7eb2e8f9f7 1664 hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK);
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 /* Management of internal measurement channels: Vlcd (STM32L0x3xx only)/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 1667 /* internal measurement paths enable: If internal channel selected, enable */
<> 144:ef7eb2e8f9f7 1668 /* dedicated internal buffers and path. */
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 /* If Temperature sensor channel is selected, then enable the internal */
<> 144:ef7eb2e8f9f7 1671 /* buffers and path */
<> 144:ef7eb2e8f9f7 1672 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1673 {
<> 144:ef7eb2e8f9f7 1674 ADC->CCR |= ADC_CCR_TSEN;
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 1677 ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US);
<> 144:ef7eb2e8f9f7 1678 }
<> 144:ef7eb2e8f9f7 1679
<> 144:ef7eb2e8f9f7 1680 /* If VRefInt channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1681 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1682 {
<> 144:ef7eb2e8f9f7 1683 ADC->CCR |= ADC_CCR_VREFEN;
<> 144:ef7eb2e8f9f7 1684 }
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 1687 /* If Vlcd channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1688 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1689 {
<> 144:ef7eb2e8f9f7 1690 ADC->CCR |= ADC_CCR_VLCDEN;
<> 144:ef7eb2e8f9f7 1691 }
<> 144:ef7eb2e8f9f7 1692 #endif
<> 144:ef7eb2e8f9f7 1693 }
<> 144:ef7eb2e8f9f7 1694 else
<> 144:ef7eb2e8f9f7 1695 {
<> 144:ef7eb2e8f9f7 1696 /* Regular sequence configuration */
<> 144:ef7eb2e8f9f7 1697 /* Reset the channel selection register from the selected channel */
<> 144:ef7eb2e8f9f7 1698 hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK));
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
<> 144:ef7eb2e8f9f7 1701 /* internal measurement paths disable: If internal channel selected, */
<> 144:ef7eb2e8f9f7 1702 /* disable dedicated internal buffers and path. */
<> 144:ef7eb2e8f9f7 1703 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1704 {
<> 144:ef7eb2e8f9f7 1705 ADC->CCR &= ~ADC_CCR_TSEN;
<> 144:ef7eb2e8f9f7 1706 }
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 /* If VRefInt channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1709 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1710 {
<> 144:ef7eb2e8f9f7 1711 ADC->CCR &= ~ADC_CCR_VREFEN;
<> 144:ef7eb2e8f9f7 1712 }
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 1715 /* If Vlcd channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1716 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1717 {
<> 144:ef7eb2e8f9f7 1718 ADC->CCR &= ~ADC_CCR_VLCDEN;
<> 144:ef7eb2e8f9f7 1719 }
<> 144:ef7eb2e8f9f7 1720 #endif
<> 144:ef7eb2e8f9f7 1721 }
Anna Bridge 186:707f6e361f3e 1722
<> 144:ef7eb2e8f9f7 1723 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1724 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1725
<> 144:ef7eb2e8f9f7 1726 /* Return function status */
<> 144:ef7eb2e8f9f7 1727 return HAL_OK;
<> 144:ef7eb2e8f9f7 1728 }
<> 144:ef7eb2e8f9f7 1729
<> 144:ef7eb2e8f9f7 1730 /**
Anna Bridge 186:707f6e361f3e 1731 * @brief Configure the analog watchdog.
<> 144:ef7eb2e8f9f7 1732 * @note Possibility to update parameters on the fly:
Anna Bridge 186:707f6e361f3e 1733 * This function initializes the selected analog watchdog, successive
<> 144:ef7eb2e8f9f7 1734 * calls to this function can be used to reconfigure some parameters
Anna Bridge 186:707f6e361f3e 1735 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
<> 144:ef7eb2e8f9f7 1736 * the ADC.
<> 144:ef7eb2e8f9f7 1737 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 1738 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 1739 * "ADC_AnalogWDGConfTypeDef".
Anna Bridge 186:707f6e361f3e 1740 * @note Analog watchdog thresholds can be modified while ADC conversion
Anna Bridge 186:707f6e361f3e 1741 * is on going.
Anna Bridge 186:707f6e361f3e 1742 * In this case, some constraints must be taken into account:
Anna Bridge 186:707f6e361f3e 1743 * the programmed threshold values are effective from the next
Anna Bridge 186:707f6e361f3e 1744 * ADC EOC (end of unitary conversion).
Anna Bridge 186:707f6e361f3e 1745 * Considering that registers write delay may happen due to
Anna Bridge 186:707f6e361f3e 1746 * bus activity, this might cause an uncertainty on the
Anna Bridge 186:707f6e361f3e 1747 * effective timing of the new programmed threshold values.
<> 144:ef7eb2e8f9f7 1748 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1749 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<> 151:5eaa88a5bcc7 1750 * @retval HAL status
<> 144:ef7eb2e8f9f7 1751 */
<> 144:ef7eb2e8f9f7 1752 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<> 144:ef7eb2e8f9f7 1753 {
<> 144:ef7eb2e8f9f7 1754 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1755
<> 144:ef7eb2e8f9f7 1756 uint32_t tmpAWDHighThresholdShifted;
<> 144:ef7eb2e8f9f7 1757 uint32_t tmpAWDLowThresholdShifted;
<> 144:ef7eb2e8f9f7 1758
<> 144:ef7eb2e8f9f7 1759 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1760 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1761 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<> 144:ef7eb2e8f9f7 1762 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
<> 144:ef7eb2e8f9f7 1765 {
<> 144:ef7eb2e8f9f7 1766 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 1767 }
Anna Bridge 186:707f6e361f3e 1768
Anna Bridge 186:707f6e361f3e 1769 /* Verify if threshold is within the selected ADC resolution */
Anna Bridge 186:707f6e361f3e 1770 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
Anna Bridge 186:707f6e361f3e 1771 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
Anna Bridge 186:707f6e361f3e 1772
<> 144:ef7eb2e8f9f7 1773 /* Process locked */
<> 144:ef7eb2e8f9f7 1774 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1775
<> 144:ef7eb2e8f9f7 1776 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 1777 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 1778 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 1779 /* - Analog watchdog channels */
<> 144:ef7eb2e8f9f7 1780 /* - Analog watchdog thresholds */
<> 144:ef7eb2e8f9f7 1781 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1782 {
<> 144:ef7eb2e8f9f7 1783 /* Configure ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1784 if(AnalogWDGConfig->ITMode == ENABLE)
<> 144:ef7eb2e8f9f7 1785 {
<> 144:ef7eb2e8f9f7 1786 /* Enable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1787 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 1788 }
<> 144:ef7eb2e8f9f7 1789 else
<> 144:ef7eb2e8f9f7 1790 {
<> 144:ef7eb2e8f9f7 1791 /* Disable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1792 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 1793 }
Anna Bridge 186:707f6e361f3e 1794
<> 144:ef7eb2e8f9f7 1795 /* Configuration of analog watchdog: */
<> 144:ef7eb2e8f9f7 1796 /* - Set the analog watchdog mode */
<> 144:ef7eb2e8f9f7 1797 /* - Set the Analog watchdog channel (is not used if watchdog */
<> 144:ef7eb2e8f9f7 1798 /* mode "all channels": ADC_CFGR1_AWD1SGL=0) */
<> 144:ef7eb2e8f9f7 1799 hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
<> 144:ef7eb2e8f9f7 1800 ADC_CFGR1_AWDEN |
<> 144:ef7eb2e8f9f7 1801 ADC_CFGR1_AWDCH);
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
<> 144:ef7eb2e8f9f7 1804 (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK));
<> 144:ef7eb2e8f9f7 1805
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 /* Shift the offset in function of the selected ADC resolution: Thresholds */
<> 144:ef7eb2e8f9f7 1808 /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
<> 144:ef7eb2e8f9f7 1809 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<> 144:ef7eb2e8f9f7 1810 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 /* Clear High & Low high thresholds */
<> 144:ef7eb2e8f9f7 1813 hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT);
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /* Set the high threshold */
<> 144:ef7eb2e8f9f7 1816 hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted);
<> 144:ef7eb2e8f9f7 1817 /* Set the low threshold */
Anna Bridge 186:707f6e361f3e 1818 hadc->Instance->TR |= tmpAWDLowThresholdShifted;
<> 144:ef7eb2e8f9f7 1819 }
Anna Bridge 186:707f6e361f3e 1820 /* If a conversion is on going on regular group, no update could be done */
Anna Bridge 186:707f6e361f3e 1821 /* on neither of the AWD configuration structure parameters. */
<> 144:ef7eb2e8f9f7 1822 else
<> 144:ef7eb2e8f9f7 1823 {
<> 144:ef7eb2e8f9f7 1824 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1825 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
Anna Bridge 186:707f6e361f3e 1826
<> 144:ef7eb2e8f9f7 1827 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1828 }
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1831 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1832
<> 144:ef7eb2e8f9f7 1833 /* Return function status */
<> 144:ef7eb2e8f9f7 1834 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1835 }
<> 144:ef7eb2e8f9f7 1836
Anna Bridge 186:707f6e361f3e 1837
<> 144:ef7eb2e8f9f7 1838 /**
<> 144:ef7eb2e8f9f7 1839 * @}
<> 144:ef7eb2e8f9f7 1840 */
<> 144:ef7eb2e8f9f7 1841
Anna Bridge 186:707f6e361f3e 1842 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
Anna Bridge 186:707f6e361f3e 1843 * @brief ADC Peripheral State functions
<> 144:ef7eb2e8f9f7 1844 *
Anna Bridge 186:707f6e361f3e 1845 @verbatim
Anna Bridge 186:707f6e361f3e 1846 ===============================================================================
Anna Bridge 186:707f6e361f3e 1847 ##### Peripheral state and errors functions #####
<> 144:ef7eb2e8f9f7 1848 ===============================================================================
<> 144:ef7eb2e8f9f7 1849 [..]
Anna Bridge 186:707f6e361f3e 1850 This subsection provides functions to get in run-time the status of the
Anna Bridge 186:707f6e361f3e 1851 peripheral.
Anna Bridge 186:707f6e361f3e 1852 (+) Check the ADC state
Anna Bridge 186:707f6e361f3e 1853 (+) Check the ADC error code
Anna Bridge 186:707f6e361f3e 1854
<> 144:ef7eb2e8f9f7 1855 @endverbatim
<> 144:ef7eb2e8f9f7 1856 * @{
<> 144:ef7eb2e8f9f7 1857 */
<> 144:ef7eb2e8f9f7 1858
<> 144:ef7eb2e8f9f7 1859 /**
Anna Bridge 186:707f6e361f3e 1860 * @brief Return the ADC handle state.
Anna Bridge 186:707f6e361f3e 1861 * @note ADC state machine is managed by bitfields, ADC status must be
Anna Bridge 186:707f6e361f3e 1862 * compared with states bits.
Anna Bridge 186:707f6e361f3e 1863 * For example:
Anna Bridge 186:707f6e361f3e 1864 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
Anna Bridge 186:707f6e361f3e 1865 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
<> 144:ef7eb2e8f9f7 1866 * @param hadc: ADC handle
Anna Bridge 186:707f6e361f3e 1867 * @retval ADC handle state (bitfield on 32 bits)
<> 144:ef7eb2e8f9f7 1868 */
<> 144:ef7eb2e8f9f7 1869 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1870 {
<> 144:ef7eb2e8f9f7 1871 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1872 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1873
Anna Bridge 186:707f6e361f3e 1874 /* Return ADC handle state */
<> 144:ef7eb2e8f9f7 1875 return hadc->State;
<> 144:ef7eb2e8f9f7 1876 }
<> 144:ef7eb2e8f9f7 1877
<> 144:ef7eb2e8f9f7 1878 /**
Anna Bridge 186:707f6e361f3e 1879 * @brief Return the ADC error code.
<> 144:ef7eb2e8f9f7 1880 * @param hadc: ADC handle
Anna Bridge 186:707f6e361f3e 1881 * @retval ADC error code (bitfield on 32 bits)
<> 144:ef7eb2e8f9f7 1882 */
<> 144:ef7eb2e8f9f7 1883 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
<> 144:ef7eb2e8f9f7 1884 {
Anna Bridge 186:707f6e361f3e 1885 /* Check the parameters */
Anna Bridge 186:707f6e361f3e 1886 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
Anna Bridge 186:707f6e361f3e 1887
<> 144:ef7eb2e8f9f7 1888 return hadc->ErrorCode;
<> 144:ef7eb2e8f9f7 1889 }
<> 144:ef7eb2e8f9f7 1890
<> 144:ef7eb2e8f9f7 1891 /**
<> 144:ef7eb2e8f9f7 1892 * @}
<> 144:ef7eb2e8f9f7 1893 */
<> 144:ef7eb2e8f9f7 1894
<> 144:ef7eb2e8f9f7 1895 /**
<> 144:ef7eb2e8f9f7 1896 * @}
<> 144:ef7eb2e8f9f7 1897 */
<> 144:ef7eb2e8f9f7 1898
Anna Bridge 186:707f6e361f3e 1899 /** @defgroup ADC_Private_Functions ADC Private Functions
<> 144:ef7eb2e8f9f7 1900 * @{
<> 144:ef7eb2e8f9f7 1901 */
<> 144:ef7eb2e8f9f7 1902
<> 144:ef7eb2e8f9f7 1903 /**
<> 144:ef7eb2e8f9f7 1904 * @brief Enable the selected ADC.
<> 144:ef7eb2e8f9f7 1905 * @note Prerequisite condition to use this function: ADC must be disabled
<> 144:ef7eb2e8f9f7 1906 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
Anna Bridge 186:707f6e361f3e 1907 * @note If low power mode AutoPowerOff is enabled, power-on/off phases are
Anna Bridge 186:707f6e361f3e 1908 * performed automatically by hardware.
Anna Bridge 186:707f6e361f3e 1909 * In this mode, this function is useless and must not be called because
Anna Bridge 186:707f6e361f3e 1910 * flag ADC_FLAG_RDY is not usable.
Anna Bridge 186:707f6e361f3e 1911 * Therefore, this function must be called under condition of
Anna Bridge 186:707f6e361f3e 1912 * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
<> 144:ef7eb2e8f9f7 1913 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1914 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1915 */
<> 144:ef7eb2e8f9f7 1916 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1917 {
<> 151:5eaa88a5bcc7 1918 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1919
<> 144:ef7eb2e8f9f7 1920 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<> 144:ef7eb2e8f9f7 1921 /* enabling phase not yet completed: flag ADC ready not yet set). */
<> 144:ef7eb2e8f9f7 1922 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<> 144:ef7eb2e8f9f7 1923 /* causes: ADC clock not running, ...). */
<> 144:ef7eb2e8f9f7 1924 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1925 {
<> 144:ef7eb2e8f9f7 1926 /* Check if conditions to enable the ADC are fulfilled */
<> 144:ef7eb2e8f9f7 1927 if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1928 {
<> 144:ef7eb2e8f9f7 1929 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1930 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1931
<> 144:ef7eb2e8f9f7 1932 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1933 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1936 }
<> 144:ef7eb2e8f9f7 1937
<> 144:ef7eb2e8f9f7 1938 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1939 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 1940
<> 144:ef7eb2e8f9f7 1941 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 1942 ADC_DelayMicroSecond(ADC_STAB_DELAY_US);
<> 144:ef7eb2e8f9f7 1943
<> 144:ef7eb2e8f9f7 1944 /* Get tick count */
Anna Bridge 186:707f6e361f3e 1945 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1946
<> 144:ef7eb2e8f9f7 1947 /* Wait for ADC effectively enabled */
Anna Bridge 186:707f6e361f3e 1948 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
Anna Bridge 186:707f6e361f3e 1949 {
Anna Bridge 186:707f6e361f3e 1950 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 1951 {
Anna Bridge 186:707f6e361f3e 1952 /* Update ADC state machine to error */
Anna Bridge 186:707f6e361f3e 1953 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
Anna Bridge 186:707f6e361f3e 1954
Anna Bridge 186:707f6e361f3e 1955 /* Set ADC error code to ADC IP internal error */
Anna Bridge 186:707f6e361f3e 1956 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
Anna Bridge 186:707f6e361f3e 1957
Anna Bridge 186:707f6e361f3e 1958 return HAL_ERROR;
Anna Bridge 186:707f6e361f3e 1959 }
Anna Bridge 186:707f6e361f3e 1960 }
<> 144:ef7eb2e8f9f7 1961 }
<> 144:ef7eb2e8f9f7 1962
<> 144:ef7eb2e8f9f7 1963 /* Return HAL status */
<> 144:ef7eb2e8f9f7 1964 return HAL_OK;
<> 144:ef7eb2e8f9f7 1965 }
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 /**
<> 144:ef7eb2e8f9f7 1968 * @brief Disable the selected ADC.
<> 144:ef7eb2e8f9f7 1969 * @note Prerequisite condition to use this function: ADC conversions must be
<> 144:ef7eb2e8f9f7 1970 * stopped.
<> 144:ef7eb2e8f9f7 1971 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1972 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1973 */
<> 144:ef7eb2e8f9f7 1974 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1975 {
<> 151:5eaa88a5bcc7 1976 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1977
<> 144:ef7eb2e8f9f7 1978 /* Verification if ADC is not already disabled: */
<> 144:ef7eb2e8f9f7 1979 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
Anna Bridge 186:707f6e361f3e 1980 /* disabled. */
Anna Bridge 186:707f6e361f3e 1981 if (ADC_IS_ENABLE(hadc) != RESET)
<> 144:ef7eb2e8f9f7 1982 {
<> 144:ef7eb2e8f9f7 1983 /* Check if conditions to disable the ADC are fulfilled */
<> 144:ef7eb2e8f9f7 1984 if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
<> 144:ef7eb2e8f9f7 1985 {
<> 144:ef7eb2e8f9f7 1986 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1987 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 1988 }
<> 144:ef7eb2e8f9f7 1989 else
<> 144:ef7eb2e8f9f7 1990 {
<> 144:ef7eb2e8f9f7 1991 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1992 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1993
<> 144:ef7eb2e8f9f7 1994 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1995 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1996
<> 144:ef7eb2e8f9f7 1997 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1998 }
<> 144:ef7eb2e8f9f7 1999
<> 144:ef7eb2e8f9f7 2000 /* Wait for ADC effectively disabled */
<> 144:ef7eb2e8f9f7 2001 /* Get tick count */
<> 144:ef7eb2e8f9f7 2002 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2003
<> 144:ef7eb2e8f9f7 2004 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
<> 144:ef7eb2e8f9f7 2005 {
Anna Bridge 186:707f6e361f3e 2006 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
Anna Bridge 186:707f6e361f3e 2007 {
Anna Bridge 186:707f6e361f3e 2008 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2009 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
Anna Bridge 186:707f6e361f3e 2010
<> 144:ef7eb2e8f9f7 2011 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2012 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
Anna Bridge 186:707f6e361f3e 2013
Anna Bridge 186:707f6e361f3e 2014 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2015 }
<> 144:ef7eb2e8f9f7 2016 }
Anna Bridge 186:707f6e361f3e 2017 }
<> 144:ef7eb2e8f9f7 2018
<> 144:ef7eb2e8f9f7 2019 /* Return HAL status */
<> 144:ef7eb2e8f9f7 2020 return HAL_OK;
<> 144:ef7eb2e8f9f7 2021 }
<> 144:ef7eb2e8f9f7 2022
Anna Bridge 186:707f6e361f3e 2023
<> 144:ef7eb2e8f9f7 2024 /**
<> 144:ef7eb2e8f9f7 2025 * @brief Stop ADC conversion.
<> 144:ef7eb2e8f9f7 2026 * @note Prerequisite condition to use this function: ADC conversions must be
<> 144:ef7eb2e8f9f7 2027 * stopped to disable the ADC.
<> 144:ef7eb2e8f9f7 2028 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2029 * @retval HAL status.
<> 144:ef7eb2e8f9f7 2030 */
<> 144:ef7eb2e8f9f7 2031 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2032 {
<> 151:5eaa88a5bcc7 2033 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 2034
<> 144:ef7eb2e8f9f7 2035 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2036 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2037
<> 144:ef7eb2e8f9f7 2038 /* Verification if ADC is not already stopped on regular group to bypass */
<> 144:ef7eb2e8f9f7 2039 /* this function if not needed. */
<> 144:ef7eb2e8f9f7 2040 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
<> 144:ef7eb2e8f9f7 2041 {
<> 144:ef7eb2e8f9f7 2042
<> 144:ef7eb2e8f9f7 2043 /* Stop potential conversion on going on regular group */
<> 144:ef7eb2e8f9f7 2044 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
<> 144:ef7eb2e8f9f7 2045 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
<> 144:ef7eb2e8f9f7 2046 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<> 144:ef7eb2e8f9f7 2047 {
<> 144:ef7eb2e8f9f7 2048 /* Stop conversions on regular group */
<> 144:ef7eb2e8f9f7 2049 hadc->Instance->CR |= ADC_CR_ADSTP;
<> 144:ef7eb2e8f9f7 2050 }
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 /* Wait for conversion effectively stopped */
<> 144:ef7eb2e8f9f7 2053 /* Get tick count */
<> 144:ef7eb2e8f9f7 2054 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2055
<> 144:ef7eb2e8f9f7 2056 while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
<> 144:ef7eb2e8f9f7 2057 {
<> 144:ef7eb2e8f9f7 2058 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<> 144:ef7eb2e8f9f7 2059 {
<> 144:ef7eb2e8f9f7 2060 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2061 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
Anna Bridge 186:707f6e361f3e 2062
<> 144:ef7eb2e8f9f7 2063 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2064 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2065
<> 144:ef7eb2e8f9f7 2066 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2067 }
<> 144:ef7eb2e8f9f7 2068 }
<> 144:ef7eb2e8f9f7 2069
<> 144:ef7eb2e8f9f7 2070 }
<> 144:ef7eb2e8f9f7 2071
<> 144:ef7eb2e8f9f7 2072 /* Return HAL status */
<> 144:ef7eb2e8f9f7 2073 return HAL_OK;
<> 144:ef7eb2e8f9f7 2074 }
<> 144:ef7eb2e8f9f7 2075
Anna Bridge 186:707f6e361f3e 2076
<> 144:ef7eb2e8f9f7 2077 /**
<> 144:ef7eb2e8f9f7 2078 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 2079 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2080 * @retval None
<> 144:ef7eb2e8f9f7 2081 */
Anna Bridge 186:707f6e361f3e 2082 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2083 {
<> 144:ef7eb2e8f9f7 2084 /* Retrieve ADC handle corresponding to current DMA handle */
Anna Bridge 186:707f6e361f3e 2085 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
Anna Bridge 186:707f6e361f3e 2086
<> 144:ef7eb2e8f9f7 2087 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 2088 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
<> 144:ef7eb2e8f9f7 2089 {
<> 144:ef7eb2e8f9f7 2090 /* Set ADC state */
Anna Bridge 186:707f6e361f3e 2091 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 2094 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 2095 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 2096 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 2097 {
<> 144:ef7eb2e8f9f7 2098 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 2099 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 2100 {
<> 144:ef7eb2e8f9f7 2101 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<> 144:ef7eb2e8f9f7 2102 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 2103 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2104 {
<> 144:ef7eb2e8f9f7 2105 /* Disable ADC end of single conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 2106 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 2107 /* HAL_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 2108 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 2109 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
<> 144:ef7eb2e8f9f7 2110
<> 144:ef7eb2e8f9f7 2111 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2112 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2113 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 2114 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2115 }
<> 144:ef7eb2e8f9f7 2116 else
<> 144:ef7eb2e8f9f7 2117 {
<> 144:ef7eb2e8f9f7 2118 /* Change ADC state to error state */
<> 144:ef7eb2e8f9f7 2119 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 2120
<> 144:ef7eb2e8f9f7 2121 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2122 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2123 }
<> 144:ef7eb2e8f9f7 2124 }
<> 144:ef7eb2e8f9f7 2125 }
Anna Bridge 186:707f6e361f3e 2126
<> 144:ef7eb2e8f9f7 2127 /* Conversion complete callback */
Anna Bridge 186:707f6e361f3e 2128 HAL_ADC_ConvCpltCallback(hadc);
Anna Bridge 186:707f6e361f3e 2129 }
<> 144:ef7eb2e8f9f7 2130 else
<> 144:ef7eb2e8f9f7 2131 {
<> 144:ef7eb2e8f9f7 2132 /* Call DMA error callback */
<> 144:ef7eb2e8f9f7 2133 hadc->DMA_Handle->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 2134 }
<> 144:ef7eb2e8f9f7 2135 }
<> 144:ef7eb2e8f9f7 2136
<> 144:ef7eb2e8f9f7 2137 /**
<> 144:ef7eb2e8f9f7 2138 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 2139 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2140 * @retval None
<> 144:ef7eb2e8f9f7 2141 */
Anna Bridge 186:707f6e361f3e 2142 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2143 {
<> 144:ef7eb2e8f9f7 2144 /* Retrieve ADC handle corresponding to current DMA handle */
Anna Bridge 186:707f6e361f3e 2145 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
Anna Bridge 186:707f6e361f3e 2146
<> 144:ef7eb2e8f9f7 2147 /* Half conversion callback */
Anna Bridge 186:707f6e361f3e 2148 HAL_ADC_ConvHalfCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 2149 }
<> 144:ef7eb2e8f9f7 2150
<> 144:ef7eb2e8f9f7 2151 /**
Anna Bridge 186:707f6e361f3e 2152 * @brief DMA error callback.
<> 144:ef7eb2e8f9f7 2153 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2154 * @retval None
<> 144:ef7eb2e8f9f7 2155 */
Anna Bridge 186:707f6e361f3e 2156 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2157 {
<> 144:ef7eb2e8f9f7 2158 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 2159 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
Anna Bridge 186:707f6e361f3e 2160
<> 144:ef7eb2e8f9f7 2161 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2162 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2163
Anna Bridge 186:707f6e361f3e 2164 /* Set ADC error code to DMA error */
<> 144:ef7eb2e8f9f7 2165 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 /* Error callback */
<> 144:ef7eb2e8f9f7 2168 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 2169 }
<> 144:ef7eb2e8f9f7 2170
<> 144:ef7eb2e8f9f7 2171 /**
<> 144:ef7eb2e8f9f7 2172 * @brief Delay micro seconds
<> 144:ef7eb2e8f9f7 2173 * @param microSecond : delay
<> 144:ef7eb2e8f9f7 2174 * @retval None
<> 144:ef7eb2e8f9f7 2175 */
<> 144:ef7eb2e8f9f7 2176 static void ADC_DelayMicroSecond(uint32_t microSecond)
<> 144:ef7eb2e8f9f7 2177 {
<> 144:ef7eb2e8f9f7 2178 /* Compute number of CPU cycles to wait for */
<> 151:5eaa88a5bcc7 2179 __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000U));
<> 144:ef7eb2e8f9f7 2180
<> 151:5eaa88a5bcc7 2181 while(waitLoopIndex != 0U)
<> 144:ef7eb2e8f9f7 2182 {
<> 144:ef7eb2e8f9f7 2183 waitLoopIndex--;
<> 144:ef7eb2e8f9f7 2184 }
<> 144:ef7eb2e8f9f7 2185 }
<> 144:ef7eb2e8f9f7 2186
Anna Bridge 186:707f6e361f3e 2187 #endif /* HAL_ADC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2188 /**
<> 144:ef7eb2e8f9f7 2189 * @}
<> 144:ef7eb2e8f9f7 2190 */
<> 144:ef7eb2e8f9f7 2191
<> 144:ef7eb2e8f9f7 2192 /**
<> 144:ef7eb2e8f9f7 2193 * @}
<> 144:ef7eb2e8f9f7 2194 */
<> 144:ef7eb2e8f9f7 2195
<> 144:ef7eb2e8f9f7 2196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/