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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
182:a56a73fd2a6f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_gpio.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief GPIO HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the General Purpose Input/Output (GPIO) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### GPIO Peripheral features #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
<> 144:ef7eb2e8f9f7 17 port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
<> 144:ef7eb2e8f9f7 18 in several modes:
<> 144:ef7eb2e8f9f7 19 (+) Input mode
<> 144:ef7eb2e8f9f7 20 (+) Analog mode
<> 144:ef7eb2e8f9f7 21 (+) Output mode
<> 144:ef7eb2e8f9f7 22 (+) Alternate function mode
<> 144:ef7eb2e8f9f7 23 (+) External interrupt/event lines
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 [..]
<> 144:ef7eb2e8f9f7 26 During and just after reset, the alternate functions and external interrupt
<> 144:ef7eb2e8f9f7 27 lines are not active and the I/O ports are configured in input floating mode.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 [..]
<> 144:ef7eb2e8f9f7 30 All GPIO pins have weak internal pull-up and pull-down resistors, which can be
<> 144:ef7eb2e8f9f7 31 activated or not.
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 [..]
<> 144:ef7eb2e8f9f7 34 In Output or Alternate mode, each IO can be configured on open-drain or push-pull
<> 144:ef7eb2e8f9f7 35 type and the IO speed can be selected depending on the VDD value.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 All ports have external interrupt/event capability. To use external interrupt
<> 144:ef7eb2e8f9f7 39 lines, the port must be configured in input mode. All available GPIO pins are
<> 144:ef7eb2e8f9f7 40 connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 The external interrupt/event controller consists of up to 23 edge detectors
<> 144:ef7eb2e8f9f7 44 (16 lines are connected to GPIO) for generating event/interrupt requests (each
<> 144:ef7eb2e8f9f7 45 input line can be independently configured to select the type (interrupt or event)
<> 144:ef7eb2e8f9f7 46 and the corresponding trigger event (rising or falling or both). Each line can
<> 144:ef7eb2e8f9f7 47 also be masked independently.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 50 ==============================================================================
<> 144:ef7eb2e8f9f7 51 [..]
<> 144:ef7eb2e8f9f7 52 (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
<> 144:ef7eb2e8f9f7 55 (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
<> 144:ef7eb2e8f9f7 56 (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
<> 144:ef7eb2e8f9f7 57 structure.
<> 144:ef7eb2e8f9f7 58 (++) In case of Output or alternate function mode selection: the speed is
<> 144:ef7eb2e8f9f7 59 configured through "Speed" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 60 (++) In alternate mode is selection, the alternate function connected to the IO
<> 144:ef7eb2e8f9f7 61 is configured through "Alternate" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 62 (++) Analog mode is required when a pin is to be used as ADC channel
<> 144:ef7eb2e8f9f7 63 or DAC output.
<> 144:ef7eb2e8f9f7 64 (++) In case of external interrupt/event selection the "Mode" member from
<> 144:ef7eb2e8f9f7 65 GPIO_InitTypeDef structure select the type (interrupt or event) and
<> 144:ef7eb2e8f9f7 66 the corresponding trigger event (rising or falling or both).
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
<> 144:ef7eb2e8f9f7 69 mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
<> 144:ef7eb2e8f9f7 70 HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 (#) To set/reset the level of a pin configured in output mode use
<> 144:ef7eb2e8f9f7 75 HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 (#) During and just after reset, the alternate functions are not
<> 144:ef7eb2e8f9f7 81 active and the GPIO pins are configured in input floating mode (except JTAG
<> 144:ef7eb2e8f9f7 82 pins).
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
<> 144:ef7eb2e8f9f7 85 (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
<> 144:ef7eb2e8f9f7 86 priority over the GPIO function.
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
<> 144:ef7eb2e8f9f7 89 general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
<> 144:ef7eb2e8f9f7 90 The HSE has priority over the GPIO function.
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 @endverbatim
<> 144:ef7eb2e8f9f7 93 ******************************************************************************
<> 144:ef7eb2e8f9f7 94 * @attention
<> 144:ef7eb2e8f9f7 95 *
AnnaBridge 168:9672193075cf 96 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 99 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 100 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 101 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 102 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 103 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 104 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 105 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 106 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 107 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 110 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 111 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 112 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 113 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 114 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 115 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 116 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 117 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 118 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 119 *
<> 144:ef7eb2e8f9f7 120 ******************************************************************************
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 124 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 127 * @{
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup GPIO GPIO
<> 144:ef7eb2e8f9f7 131 * @brief GPIO HAL module driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 #ifdef HAL_GPIO_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 #define GPIO_MODE ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 143 #define EXTI_MODE ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 144 #define GPIO_MODE_IT ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 145 #define GPIO_MODE_EVT ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 146 #define RISING_EDGE ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 147 #define FALLING_EDGE ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 148 #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #define GPIO_NUMBER ((uint32_t)16U)
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @}
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 155 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 156 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 164 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 165 *
<> 144:ef7eb2e8f9f7 166 @verbatim
<> 144:ef7eb2e8f9f7 167 ===============================================================================
<> 144:ef7eb2e8f9f7 168 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 169 ===============================================================================
<> 144:ef7eb2e8f9f7 170 [..]
<> 144:ef7eb2e8f9f7 171 This section provides functions allowing to initialize and de-initialize the GPIOs
<> 144:ef7eb2e8f9f7 172 to be ready for use.
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 @endverbatim
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
AnnaBridge 182:a56a73fd2a6f 180 * @param GPIOx where x can be (A..K) to select the GPIO peripheral.
AnnaBridge 182:a56a73fd2a6f 181 * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 182 * the configuration information for the specified GPIO peripheral.
<> 144:ef7eb2e8f9f7 183 * @retval None
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 uint32_t position = 0x00;
<> 144:ef7eb2e8f9f7 188 uint32_t ioposition = 0x00;
<> 144:ef7eb2e8f9f7 189 uint32_t iocurrent = 0x00;
<> 144:ef7eb2e8f9f7 190 uint32_t temp = 0x00;
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Check the parameters */
<> 144:ef7eb2e8f9f7 193 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 194 assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
<> 144:ef7eb2e8f9f7 195 assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
<> 144:ef7eb2e8f9f7 196 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 199 for(position = 0; position < GPIO_NUMBER; position++)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 /* Get the IO position */
<> 144:ef7eb2e8f9f7 202 ioposition = ((uint32_t)0x01) << position;
<> 144:ef7eb2e8f9f7 203 /* Get the current IO position */
<> 144:ef7eb2e8f9f7 204 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 if(iocurrent == ioposition)
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 /*--------------------- GPIO Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 209 /* In case of Alternate function mode selection */
<> 144:ef7eb2e8f9f7 210 if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 /* Check the Alternate function parameter */
<> 144:ef7eb2e8f9f7 213 assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Configure Alternate function mapped with the current IO */
<> 144:ef7eb2e8f9f7 216 temp = GPIOx->AFR[position >> 3];
<> 144:ef7eb2e8f9f7 217 temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
<> 144:ef7eb2e8f9f7 218 temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
<> 144:ef7eb2e8f9f7 219 GPIOx->AFR[position >> 3] = temp;
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
<> 144:ef7eb2e8f9f7 223 temp = GPIOx->MODER;
<> 144:ef7eb2e8f9f7 224 temp &= ~(GPIO_MODER_MODER0 << (position * 2));
<> 144:ef7eb2e8f9f7 225 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
<> 144:ef7eb2e8f9f7 226 GPIOx->MODER = temp;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* In case of Output or Alternate function mode selection */
<> 144:ef7eb2e8f9f7 229 if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
<> 144:ef7eb2e8f9f7 230 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Check the Speed parameter */
<> 144:ef7eb2e8f9f7 233 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 234 /* Configure the IO Speed */
<> 144:ef7eb2e8f9f7 235 temp = GPIOx->OSPEEDR;
<> 144:ef7eb2e8f9f7 236 temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
<> 144:ef7eb2e8f9f7 237 temp |= (GPIO_Init->Speed << (position * 2));
<> 144:ef7eb2e8f9f7 238 GPIOx->OSPEEDR = temp;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Configure the IO Output Type */
<> 144:ef7eb2e8f9f7 241 temp = GPIOx->OTYPER;
<> 144:ef7eb2e8f9f7 242 temp &= ~(GPIO_OTYPER_OT_0 << position) ;
<> 144:ef7eb2e8f9f7 243 temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
<> 144:ef7eb2e8f9f7 244 GPIOx->OTYPER = temp;
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Activate the Pull-up or Pull down resistor for the current IO */
<> 144:ef7eb2e8f9f7 248 temp = GPIOx->PUPDR;
<> 144:ef7eb2e8f9f7 249 temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
<> 144:ef7eb2e8f9f7 250 temp |= ((GPIO_Init->Pull) << (position * 2));
<> 144:ef7eb2e8f9f7 251 GPIOx->PUPDR = temp;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /*--------------------- EXTI Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 254 /* Configure the External Interrupt or event for the current IO */
<> 144:ef7eb2e8f9f7 255 if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 /* Enable SYSCFG Clock */
<> 144:ef7eb2e8f9f7 258 __HAL_RCC_SYSCFG_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 temp = SYSCFG->EXTICR[position >> 2];
<> 144:ef7eb2e8f9f7 261 temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 262 temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 263 SYSCFG->EXTICR[position >> 2] = temp;
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 266 temp = EXTI->IMR;
<> 144:ef7eb2e8f9f7 267 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 268 if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 EXTI->IMR = temp;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 temp = EXTI->EMR;
<> 144:ef7eb2e8f9f7 275 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 276 if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280 EXTI->EMR = temp;
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 283 temp = EXTI->RTSR;
<> 144:ef7eb2e8f9f7 284 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 285 if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289 EXTI->RTSR = temp;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 temp = EXTI->FTSR;
<> 144:ef7eb2e8f9f7 292 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 293 if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297 EXTI->FTSR = temp;
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @brief De-initializes the GPIOx peripheral registers to their default reset values.
AnnaBridge 182:a56a73fd2a6f 305 * @param GPIOx where x can be (A..K) to select the GPIO peripheral.
AnnaBridge 182:a56a73fd2a6f 306 * @param GPIO_Pin specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 307 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 308 * @retval None
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 uint32_t position;
<> 144:ef7eb2e8f9f7 313 uint32_t ioposition = 0x00;
<> 144:ef7eb2e8f9f7 314 uint32_t iocurrent = 0x00;
<> 144:ef7eb2e8f9f7 315 uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Check the parameters */
<> 144:ef7eb2e8f9f7 318 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 321 for(position = 0; position < GPIO_NUMBER; position++)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Get the IO position */
<> 144:ef7eb2e8f9f7 324 ioposition = ((uint32_t)0x01) << position;
<> 144:ef7eb2e8f9f7 325 /* Get the current IO position */
<> 144:ef7eb2e8f9f7 326 iocurrent = (GPIO_Pin) & ioposition;
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 if(iocurrent == ioposition)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 /*------------------------- GPIO Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 331 /* Configure IO Direction in Input Floating Mode */
<> 144:ef7eb2e8f9f7 332 GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Configure the default Alternate Function in current IO */
<> 144:ef7eb2e8f9f7 335 GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Configure the default value for IO Speed */
<> 144:ef7eb2e8f9f7 338 GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Configure the default value IO Output Type */
<> 144:ef7eb2e8f9f7 341 GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Deactivate the Pull-up and Pull-down resistor for the current IO */
<> 144:ef7eb2e8f9f7 344 GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /*------------------------- EXTI Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 347 tmp = SYSCFG->EXTICR[position >> 2];
<> 144:ef7eb2e8f9f7 348 tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 349 if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 /* Configure the External Interrupt or event for the current IO */
<> 144:ef7eb2e8f9f7 352 tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
<> 144:ef7eb2e8f9f7 353 SYSCFG->EXTICR[position >> 2] &= ~tmp;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 356 EXTI->IMR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 357 EXTI->EMR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 360 EXTI->RTSR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 361 EXTI->FTSR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @}
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 372 * @brief GPIO Read and Write
<> 144:ef7eb2e8f9f7 373 *
<> 144:ef7eb2e8f9f7 374 @verbatim
<> 144:ef7eb2e8f9f7 375 ===============================================================================
<> 144:ef7eb2e8f9f7 376 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 377 ===============================================================================
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 @endverbatim
<> 144:ef7eb2e8f9f7 380 * @{
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief Reads the specified input port pin.
AnnaBridge 182:a56a73fd2a6f 385 * @param GPIOx where x can be (A..K) to select the GPIO peripheral.
AnnaBridge 182:a56a73fd2a6f 386 * @param GPIO_Pin specifies the port bit to read.
<> 144:ef7eb2e8f9f7 387 * This parameter can be GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 388 * @retval The input port pin value.
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 GPIO_PinState bitstatus;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Check the parameters */
<> 144:ef7eb2e8f9f7 395 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 bitstatus = GPIO_PIN_SET;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 else
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 bitstatus = GPIO_PIN_RESET;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 return bitstatus;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @brief Sets or clears the selected data port bit.
<> 144:ef7eb2e8f9f7 410 *
<> 144:ef7eb2e8f9f7 411 * @note This function uses GPIOx_BSRR register to allow atomic read/modify
<> 144:ef7eb2e8f9f7 412 * accesses. In this way, there is no risk of an IRQ occurring between
<> 144:ef7eb2e8f9f7 413 * the read and the modify access.
<> 144:ef7eb2e8f9f7 414 *
AnnaBridge 182:a56a73fd2a6f 415 * @param GPIOx where x can be (A..K) to select the GPIO peripheral.
AnnaBridge 182:a56a73fd2a6f 416 * @param GPIO_Pin specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 417 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
AnnaBridge 182:a56a73fd2a6f 418 * @param PinState specifies the value to be written to the selected bit.
<> 144:ef7eb2e8f9f7 419 * This parameter can be one of the GPIO_PinState enum values:
<> 144:ef7eb2e8f9f7 420 * @arg GPIO_PIN_RESET: to clear the port pin
<> 144:ef7eb2e8f9f7 421 * @arg GPIO_PIN_SET: to set the port pin
<> 144:ef7eb2e8f9f7 422 * @retval None
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 /* Check the parameters */
<> 144:ef7eb2e8f9f7 427 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 428 assert_param(IS_GPIO_PIN_ACTION(PinState));
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 if(PinState != GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 GPIOx->BSRR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434 else
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @brief Toggles the specified GPIO pins.
AnnaBridge 182:a56a73fd2a6f 442 * @param GPIOx Where x can be (A..I) to select the GPIO peripheral.
AnnaBridge 182:a56a73fd2a6f 443 * @param GPIO_Pin Specifies the pins to be toggled.
<> 144:ef7eb2e8f9f7 444 * @retval None
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 /* Check the parameters */
<> 144:ef7eb2e8f9f7 449 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 GPIOx->ODR ^= GPIO_Pin;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @brief Locks GPIO Pins configuration registers.
<> 144:ef7eb2e8f9f7 456 * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
<> 144:ef7eb2e8f9f7 457 * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
<> 144:ef7eb2e8f9f7 458 * @note The configuration of the locked GPIO pins can no longer be modified
<> 144:ef7eb2e8f9f7 459 * until the next reset.
AnnaBridge 182:a56a73fd2a6f 460 * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family
AnnaBridge 182:a56a73fd2a6f 461 * @param GPIO_Pin specifies the port bit to be locked.
<> 144:ef7eb2e8f9f7 462 * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 463 * @retval None
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 __IO uint32_t tmp = GPIO_LCKR_LCKK;
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Check the parameters */
<> 144:ef7eb2e8f9f7 470 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Apply lock key write sequence */
<> 144:ef7eb2e8f9f7 473 tmp |= GPIO_Pin;
<> 144:ef7eb2e8f9f7 474 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 475 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 476 /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 477 GPIOx->LCKR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 478 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 479 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 480 /* Read LCKK bit*/
<> 144:ef7eb2e8f9f7 481 tmp = GPIOx->LCKR;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 return HAL_OK;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 else
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @brief This function handles EXTI interrupt request.
AnnaBridge 182:a56a73fd2a6f 495 * @param GPIO_Pin Specifies the pins connected EXTI line
<> 144:ef7eb2e8f9f7 496 * @retval None
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 /* EXTI line interrupt detected */
<> 144:ef7eb2e8f9f7 501 if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
<> 144:ef7eb2e8f9f7 504 HAL_GPIO_EXTI_Callback(GPIO_Pin);
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief EXTI line detection callbacks.
AnnaBridge 182:a56a73fd2a6f 510 * @param GPIO_Pin Specifies the pins connected EXTI line
<> 144:ef7eb2e8f9f7 511 * @retval None
<> 144:ef7eb2e8f9f7 512 */
<> 144:ef7eb2e8f9f7 513 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 516 UNUSED(GPIO_Pin);
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 519 the HAL_GPIO_EXTI_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /**
<> 144:ef7eb2e8f9f7 524 * @}
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /**
<> 144:ef7eb2e8f9f7 529 * @}
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 #endif /* HAL_GPIO_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @}
<> 144:ef7eb2e8f9f7 535 */
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /**
<> 144:ef7eb2e8f9f7 538 * @}
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/