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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_utils.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:e84263d55307 1 /**
AnnaBridge 167:e84263d55307 2 ******************************************************************************
AnnaBridge 167:e84263d55307 3 * @file stm32f2xx_ll_utils.c
AnnaBridge 167:e84263d55307 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
AnnaBridge 167:e84263d55307 7 * @brief UTILS LL module driver.
AnnaBridge 167:e84263d55307 8 ******************************************************************************
AnnaBridge 167:e84263d55307 9 * @attention
AnnaBridge 167:e84263d55307 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 167:e84263d55307 12 *
AnnaBridge 167:e84263d55307 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 167:e84263d55307 14 * are permitted provided that the following conditions are met:
AnnaBridge 167:e84263d55307 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 167:e84263d55307 16 * this list of conditions and the following disclaimer.
AnnaBridge 167:e84263d55307 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 167:e84263d55307 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 167:e84263d55307 19 * and/or other materials provided with the distribution.
AnnaBridge 167:e84263d55307 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 167:e84263d55307 21 * may be used to endorse or promote products derived from this software
AnnaBridge 167:e84263d55307 22 * without specific prior written permission.
AnnaBridge 167:e84263d55307 23 *
AnnaBridge 167:e84263d55307 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 167:e84263d55307 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 167:e84263d55307 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 167:e84263d55307 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 167:e84263d55307 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 167:e84263d55307 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 167:e84263d55307 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 167:e84263d55307 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 167:e84263d55307 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 167:e84263d55307 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 167:e84263d55307 34 *
AnnaBridge 167:e84263d55307 35 ******************************************************************************
AnnaBridge 167:e84263d55307 36 */
AnnaBridge 167:e84263d55307 37 /* Includes ------------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 38 #include "stm32f2xx_ll_utils.h"
AnnaBridge 167:e84263d55307 39 #include "stm32f2xx_ll_rcc.h"
AnnaBridge 167:e84263d55307 40 #include "stm32f2xx_ll_system.h"
AnnaBridge 167:e84263d55307 41 #ifdef USE_FULL_ASSERT
AnnaBridge 167:e84263d55307 42 #include "stm32_assert.h"
AnnaBridge 167:e84263d55307 43 #else
AnnaBridge 167:e84263d55307 44 #define assert_param(expr) ((void)0U)
AnnaBridge 167:e84263d55307 45 #endif /* USE_FULL_ASSERT */
AnnaBridge 167:e84263d55307 46
AnnaBridge 167:e84263d55307 47 /** @addtogroup STM32F2xx_LL_Driver
AnnaBridge 167:e84263d55307 48 * @{
AnnaBridge 167:e84263d55307 49 */
AnnaBridge 167:e84263d55307 50
AnnaBridge 167:e84263d55307 51 /** @addtogroup UTILS_LL
AnnaBridge 167:e84263d55307 52 * @{
AnnaBridge 167:e84263d55307 53 */
AnnaBridge 167:e84263d55307 54
AnnaBridge 167:e84263d55307 55 /* Private types -------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 56 /* Private variables ---------------------------------------------------------*/
AnnaBridge 167:e84263d55307 57 /* Private constants ---------------------------------------------------------*/
AnnaBridge 167:e84263d55307 58 /** @addtogroup UTILS_LL_Private_Constants
AnnaBridge 167:e84263d55307 59 * @{
AnnaBridge 167:e84263d55307 60 */
AnnaBridge 167:e84263d55307 61 #define UTILS_MAX_FREQUENCY 120000000U /*!< Maximum frequency for system clock, in Hz */
AnnaBridge 167:e84263d55307 62
AnnaBridge 167:e84263d55307 63 /* Defines used for PLL range */
AnnaBridge 167:e84263d55307 64 #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 167:e84263d55307 65 #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 167:e84263d55307 66 #define UTILS_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 167:e84263d55307 67 #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 167:e84263d55307 68
AnnaBridge 167:e84263d55307 69 /* Defines used for HSE range */
AnnaBridge 167:e84263d55307 70 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
AnnaBridge 167:e84263d55307 71 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
AnnaBridge 167:e84263d55307 72
AnnaBridge 167:e84263d55307 73 /* Defines used for FLASH latency according to HCLK Frequency */
AnnaBridge 167:e84263d55307 74 #define UTILS_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
AnnaBridge 167:e84263d55307 75 #define UTILS_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
AnnaBridge 167:e84263d55307 76 #define UTILS_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
AnnaBridge 167:e84263d55307 77 /**
AnnaBridge 167:e84263d55307 78 * @}
AnnaBridge 167:e84263d55307 79 */
AnnaBridge 167:e84263d55307 80
AnnaBridge 167:e84263d55307 81 /* Private macros ------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 82 /** @addtogroup UTILS_LL_Private_Macros
AnnaBridge 167:e84263d55307 83 * @{
AnnaBridge 167:e84263d55307 84 */
AnnaBridge 167:e84263d55307 85 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
AnnaBridge 167:e84263d55307 86 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
AnnaBridge 167:e84263d55307 87 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
AnnaBridge 167:e84263d55307 88 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
AnnaBridge 167:e84263d55307 89 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
AnnaBridge 167:e84263d55307 90 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
AnnaBridge 167:e84263d55307 91 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
AnnaBridge 167:e84263d55307 92 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
AnnaBridge 167:e84263d55307 93 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
AnnaBridge 167:e84263d55307 94
AnnaBridge 167:e84263d55307 95 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
AnnaBridge 167:e84263d55307 96 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
AnnaBridge 167:e84263d55307 97 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
AnnaBridge 167:e84263d55307 98 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
AnnaBridge 167:e84263d55307 99 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
AnnaBridge 167:e84263d55307 100
AnnaBridge 167:e84263d55307 101 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
AnnaBridge 167:e84263d55307 102 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
AnnaBridge 167:e84263d55307 103 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
AnnaBridge 167:e84263d55307 104 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
AnnaBridge 167:e84263d55307 105 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
AnnaBridge 167:e84263d55307 106
AnnaBridge 167:e84263d55307 107 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
AnnaBridge 167:e84263d55307 108 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
AnnaBridge 167:e84263d55307 109 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
AnnaBridge 167:e84263d55307 110 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
AnnaBridge 167:e84263d55307 111 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
AnnaBridge 167:e84263d55307 112 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
AnnaBridge 167:e84263d55307 113 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
AnnaBridge 167:e84263d55307 114 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
AnnaBridge 167:e84263d55307 115 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
AnnaBridge 167:e84263d55307 116 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
AnnaBridge 167:e84263d55307 117 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
AnnaBridge 167:e84263d55307 118 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
AnnaBridge 167:e84263d55307 119 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
AnnaBridge 167:e84263d55307 120 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
AnnaBridge 167:e84263d55307 121 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
AnnaBridge 167:e84263d55307 122 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
AnnaBridge 167:e84263d55307 123 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
AnnaBridge 167:e84263d55307 124 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
AnnaBridge 167:e84263d55307 125 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
AnnaBridge 167:e84263d55307 126 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
AnnaBridge 167:e84263d55307 127 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
AnnaBridge 167:e84263d55307 128 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
AnnaBridge 167:e84263d55307 129 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
AnnaBridge 167:e84263d55307 130 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
AnnaBridge 167:e84263d55307 131 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
AnnaBridge 167:e84263d55307 132 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
AnnaBridge 167:e84263d55307 133 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
AnnaBridge 167:e84263d55307 134 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
AnnaBridge 167:e84263d55307 135 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
AnnaBridge 167:e84263d55307 136 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
AnnaBridge 167:e84263d55307 137 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
AnnaBridge 167:e84263d55307 138 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
AnnaBridge 167:e84263d55307 139 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
AnnaBridge 167:e84263d55307 140 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
AnnaBridge 167:e84263d55307 141 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
AnnaBridge 167:e84263d55307 142 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
AnnaBridge 167:e84263d55307 143 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
AnnaBridge 167:e84263d55307 144 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
AnnaBridge 167:e84263d55307 145 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
AnnaBridge 167:e84263d55307 146 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
AnnaBridge 167:e84263d55307 147 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
AnnaBridge 167:e84263d55307 148 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
AnnaBridge 167:e84263d55307 149 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
AnnaBridge 167:e84263d55307 150 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
AnnaBridge 167:e84263d55307 151 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
AnnaBridge 167:e84263d55307 152 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
AnnaBridge 167:e84263d55307 153 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
AnnaBridge 167:e84263d55307 154 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
AnnaBridge 167:e84263d55307 155 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
AnnaBridge 167:e84263d55307 156 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
AnnaBridge 167:e84263d55307 157 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
AnnaBridge 167:e84263d55307 158 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
AnnaBridge 167:e84263d55307 159 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
AnnaBridge 167:e84263d55307 160 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
AnnaBridge 167:e84263d55307 161 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
AnnaBridge 167:e84263d55307 162 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
AnnaBridge 167:e84263d55307 163 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
AnnaBridge 167:e84263d55307 164 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
AnnaBridge 167:e84263d55307 165 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
AnnaBridge 167:e84263d55307 166 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
AnnaBridge 167:e84263d55307 167 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
AnnaBridge 167:e84263d55307 168 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
AnnaBridge 167:e84263d55307 169
AnnaBridge 167:e84263d55307 170 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((192 <= (__VALUE__)) && ((__VALUE__) <= 432))
AnnaBridge 167:e84263d55307 171
AnnaBridge 167:e84263d55307 172 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
AnnaBridge 167:e84263d55307 173 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
AnnaBridge 167:e84263d55307 174 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
AnnaBridge 167:e84263d55307 175 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
AnnaBridge 167:e84263d55307 176
AnnaBridge 167:e84263d55307 177 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
AnnaBridge 167:e84263d55307 178
AnnaBridge 167:e84263d55307 179 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
AnnaBridge 167:e84263d55307 180
AnnaBridge 167:e84263d55307 181 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
AnnaBridge 167:e84263d55307 182
AnnaBridge 167:e84263d55307 183 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
AnnaBridge 167:e84263d55307 184 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
AnnaBridge 167:e84263d55307 185
AnnaBridge 167:e84263d55307 186 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
AnnaBridge 167:e84263d55307 187 /**
AnnaBridge 167:e84263d55307 188 * @}
AnnaBridge 167:e84263d55307 189 */
AnnaBridge 167:e84263d55307 190 /* Private function prototypes -----------------------------------------------*/
AnnaBridge 167:e84263d55307 191 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
AnnaBridge 167:e84263d55307 192 * @{
AnnaBridge 167:e84263d55307 193 */
AnnaBridge 167:e84263d55307 194 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
AnnaBridge 167:e84263d55307 195 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
AnnaBridge 167:e84263d55307 196 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
AnnaBridge 167:e84263d55307 197 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
AnnaBridge 167:e84263d55307 198 static ErrorStatus UTILS_PLL_IsBusy(void);
AnnaBridge 167:e84263d55307 199 /**
AnnaBridge 167:e84263d55307 200 * @}
AnnaBridge 167:e84263d55307 201 */
AnnaBridge 167:e84263d55307 202
AnnaBridge 167:e84263d55307 203 /* Exported functions --------------------------------------------------------*/
AnnaBridge 167:e84263d55307 204 /** @addtogroup UTILS_LL_Exported_Functions
AnnaBridge 167:e84263d55307 205 * @{
AnnaBridge 167:e84263d55307 206 */
AnnaBridge 167:e84263d55307 207
AnnaBridge 167:e84263d55307 208 /** @addtogroup UTILS_LL_EF_DELAY
AnnaBridge 167:e84263d55307 209 * @{
AnnaBridge 167:e84263d55307 210 */
AnnaBridge 167:e84263d55307 211
AnnaBridge 167:e84263d55307 212 /**
AnnaBridge 167:e84263d55307 213 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
AnnaBridge 167:e84263d55307 214 * @note When a RTOS is used, it is recommended to avoid changing the Systick
AnnaBridge 167:e84263d55307 215 * configuration by calling this function, for a delay use rather osDelay RTOS service.
AnnaBridge 167:e84263d55307 216 * @param HCLKFrequency HCLK frequency in Hz
AnnaBridge 167:e84263d55307 217 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
AnnaBridge 167:e84263d55307 218 * @retval None
AnnaBridge 167:e84263d55307 219 */
AnnaBridge 167:e84263d55307 220 void LL_Init1msTick(uint32_t HCLKFrequency)
AnnaBridge 167:e84263d55307 221 {
AnnaBridge 167:e84263d55307 222 /* Use frequency provided in argument */
AnnaBridge 167:e84263d55307 223 LL_InitTick(HCLKFrequency, 1000U);
AnnaBridge 167:e84263d55307 224 }
AnnaBridge 167:e84263d55307 225
AnnaBridge 167:e84263d55307 226 /**
AnnaBridge 167:e84263d55307 227 * @brief This function provides accurate delay (in milliseconds) based
AnnaBridge 167:e84263d55307 228 * on SysTick counter flag
AnnaBridge 167:e84263d55307 229 * @note When a RTOS is used, it is recommended to avoid using blocking delay
AnnaBridge 167:e84263d55307 230 * and use rather osDelay service.
AnnaBridge 167:e84263d55307 231 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
AnnaBridge 167:e84263d55307 232 * will configure Systick to 1ms
AnnaBridge 167:e84263d55307 233 * @param Delay specifies the delay time length, in milliseconds.
AnnaBridge 167:e84263d55307 234 * @retval None
AnnaBridge 167:e84263d55307 235 */
AnnaBridge 167:e84263d55307 236 void LL_mDelay(uint32_t Delay)
AnnaBridge 167:e84263d55307 237 {
AnnaBridge 167:e84263d55307 238 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
AnnaBridge 167:e84263d55307 239 /* Add this code to indicate that local variable is not used */
AnnaBridge 167:e84263d55307 240 ((void)tmp);
AnnaBridge 167:e84263d55307 241
AnnaBridge 167:e84263d55307 242 /* Add a period to guaranty minimum wait */
AnnaBridge 167:e84263d55307 243 if(Delay < LL_MAX_DELAY)
AnnaBridge 167:e84263d55307 244 {
AnnaBridge 167:e84263d55307 245 Delay++;
AnnaBridge 167:e84263d55307 246 }
AnnaBridge 167:e84263d55307 247
AnnaBridge 167:e84263d55307 248 while (Delay)
AnnaBridge 167:e84263d55307 249 {
AnnaBridge 167:e84263d55307 250 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
AnnaBridge 167:e84263d55307 251 {
AnnaBridge 167:e84263d55307 252 Delay--;
AnnaBridge 167:e84263d55307 253 }
AnnaBridge 167:e84263d55307 254 }
AnnaBridge 167:e84263d55307 255 }
AnnaBridge 167:e84263d55307 256
AnnaBridge 167:e84263d55307 257 /**
AnnaBridge 167:e84263d55307 258 * @}
AnnaBridge 167:e84263d55307 259 */
AnnaBridge 167:e84263d55307 260
AnnaBridge 167:e84263d55307 261 /** @addtogroup UTILS_EF_SYSTEM
AnnaBridge 167:e84263d55307 262 * @brief System Configuration functions
AnnaBridge 167:e84263d55307 263 *
AnnaBridge 167:e84263d55307 264 @verbatim
AnnaBridge 167:e84263d55307 265 ===============================================================================
AnnaBridge 167:e84263d55307 266 ##### System Configuration functions #####
AnnaBridge 167:e84263d55307 267 ===============================================================================
AnnaBridge 167:e84263d55307 268 [..]
AnnaBridge 167:e84263d55307 269 System, AHB and APB buses clocks configuration
AnnaBridge 167:e84263d55307 270
AnnaBridge 167:e84263d55307 271 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 120000000 Hz.
AnnaBridge 167:e84263d55307 272 @endverbatim
AnnaBridge 167:e84263d55307 273 @internal
AnnaBridge 167:e84263d55307 274 Depending on the device voltage range, the maximum frequency should be
AnnaBridge 167:e84263d55307 275 adapted accordingly:
AnnaBridge 167:e84263d55307 276
AnnaBridge 167:e84263d55307 277 (++) Table 1. HCLK clock frequency.
AnnaBridge 167:e84263d55307 278 (++) +------------------------------------------------------------------------------------------------+
AnnaBridge 167:e84263d55307 279 (++) | Wait states | HCLK clock frequency (MHz) |
AnnaBridge 167:e84263d55307 280 (++) | |-------------------------------------------------------------------------------|
AnnaBridge 167:e84263d55307 281 (++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
AnnaBridge 167:e84263d55307 282 (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V |
AnnaBridge 167:e84263d55307 283 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 284 (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 18 | 0 < HCLK <= 16 |
AnnaBridge 167:e84263d55307 285 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 286 (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 18 < HCLK <= 36 | 16 < HCLK <= 32 |
AnnaBridge 167:e84263d55307 287 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 288 (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 36 < HCLK <= 54 | 32 < HCLK <= 48 |
AnnaBridge 167:e84263d55307 289 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 290 (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 54 < HCLK <= 72 | 48 < HCLK <= 64 |
AnnaBridge 167:e84263d55307 291 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 292 (++) |4WS(5CPU cycle) | | 96 < HCLK <= 120 | 72 < HCLK <= 90 | 64 < HCLK <= 80 |
AnnaBridge 167:e84263d55307 293 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 294 (++) |5WS(6CPU cycle) | | | 90 < HCLK <= 108 | 80 < HCLK <= 96 |
AnnaBridge 167:e84263d55307 295 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 296 (++) |6WS(7CPU cycle) | | | 108 < HCLK <= 120 | 96 < HCLK <= 112 |
AnnaBridge 167:e84263d55307 297 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
AnnaBridge 167:e84263d55307 298 (++) |7WS(8CPU cycle) | | | | 112 < HCLK <= 120 |
AnnaBridge 167:e84263d55307 299 (++) +------------------------------------------------------------------------------------------------+
AnnaBridge 167:e84263d55307 300 @endinternal
AnnaBridge 167:e84263d55307 301 * @{
AnnaBridge 167:e84263d55307 302 */
AnnaBridge 167:e84263d55307 303
AnnaBridge 167:e84263d55307 304 /**
AnnaBridge 167:e84263d55307 305 * @brief This function sets directly SystemCoreClock CMSIS variable.
AnnaBridge 167:e84263d55307 306 * @note Variable can be calculated also through SystemCoreClockUpdate function.
AnnaBridge 167:e84263d55307 307 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
AnnaBridge 167:e84263d55307 308 * @retval None
AnnaBridge 167:e84263d55307 309 */
AnnaBridge 167:e84263d55307 310 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
AnnaBridge 167:e84263d55307 311 {
AnnaBridge 167:e84263d55307 312 /* HCLK clock frequency */
AnnaBridge 167:e84263d55307 313 SystemCoreClock = HCLKFrequency;
AnnaBridge 167:e84263d55307 314 }
AnnaBridge 167:e84263d55307 315
AnnaBridge 167:e84263d55307 316 /**
AnnaBridge 167:e84263d55307 317 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
AnnaBridge 167:e84263d55307 318 * @note The application need to ensure that PLL is disabled.
AnnaBridge 167:e84263d55307 319 * @note Function is based on the following formula:
AnnaBridge 167:e84263d55307 320 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
AnnaBridge 167:e84263d55307 321 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSI frequency / PLLM)
AnnaBridge 167:e84263d55307 322 * - PLLN: ensure that the VCO output frequency is between 192 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
AnnaBridge 167:e84263d55307 323 * - PLLP: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLP)
AnnaBridge 167:e84263d55307 324 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
AnnaBridge 167:e84263d55307 325 * the configuration information for the PLL.
AnnaBridge 167:e84263d55307 326 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
AnnaBridge 167:e84263d55307 327 * the configuration information for the BUS prescalers.
AnnaBridge 167:e84263d55307 328 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 329 * - SUCCESS: Max frequency configuration done
AnnaBridge 167:e84263d55307 330 * - ERROR: Max frequency configuration not done
AnnaBridge 167:e84263d55307 331 */
AnnaBridge 167:e84263d55307 332 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
AnnaBridge 167:e84263d55307 333 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
AnnaBridge 167:e84263d55307 334 {
AnnaBridge 167:e84263d55307 335 ErrorStatus status = SUCCESS;
AnnaBridge 167:e84263d55307 336 uint32_t pllfreq = 0U;
AnnaBridge 167:e84263d55307 337
AnnaBridge 167:e84263d55307 338 /* Check if one of the PLL is enabled */
AnnaBridge 167:e84263d55307 339 if(UTILS_PLL_IsBusy() == SUCCESS)
AnnaBridge 167:e84263d55307 340 {
AnnaBridge 167:e84263d55307 341 /* Calculate the new PLL output frequency */
AnnaBridge 167:e84263d55307 342 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
AnnaBridge 167:e84263d55307 343
AnnaBridge 167:e84263d55307 344 /* Enable HSI if not enabled */
AnnaBridge 167:e84263d55307 345 if(LL_RCC_HSI_IsReady() != 1U)
AnnaBridge 167:e84263d55307 346 {
AnnaBridge 167:e84263d55307 347 LL_RCC_HSI_Enable();
AnnaBridge 167:e84263d55307 348 while (LL_RCC_HSI_IsReady() != 1U)
AnnaBridge 167:e84263d55307 349 {
AnnaBridge 167:e84263d55307 350 /* Wait for HSI ready */
AnnaBridge 167:e84263d55307 351 }
AnnaBridge 167:e84263d55307 352 }
AnnaBridge 167:e84263d55307 353
AnnaBridge 167:e84263d55307 354 /* Configure PLL */
AnnaBridge 167:e84263d55307 355 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
AnnaBridge 167:e84263d55307 356 UTILS_PLLInitStruct->PLLP);
AnnaBridge 167:e84263d55307 357
AnnaBridge 167:e84263d55307 358 /* Enable PLL and switch system clock to PLL */
AnnaBridge 167:e84263d55307 359 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
AnnaBridge 167:e84263d55307 360 }
AnnaBridge 167:e84263d55307 361 else
AnnaBridge 167:e84263d55307 362 {
AnnaBridge 167:e84263d55307 363 /* Current PLL configuration cannot be modified */
AnnaBridge 167:e84263d55307 364 status = ERROR;
AnnaBridge 167:e84263d55307 365 }
AnnaBridge 167:e84263d55307 366
AnnaBridge 167:e84263d55307 367 return status;
AnnaBridge 167:e84263d55307 368 }
AnnaBridge 167:e84263d55307 369
AnnaBridge 167:e84263d55307 370 /**
AnnaBridge 167:e84263d55307 371 * @brief This function configures system clock with HSE as clock source of the PLL
AnnaBridge 167:e84263d55307 372 * @note The application need to ensure that PLL is disabled.
AnnaBridge 167:e84263d55307 373 * @note Function is based on the following formula:
AnnaBridge 167:e84263d55307 374 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
AnnaBridge 167:e84263d55307 375 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
AnnaBridge 167:e84263d55307 376 * - PLLN: ensure that the VCO output frequency is between 192 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
AnnaBridge 167:e84263d55307 377 * - PLLP: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLP)
AnnaBridge 167:e84263d55307 378 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
AnnaBridge 167:e84263d55307 379 * @param HSEBypass This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 380 * @arg @ref LL_UTILS_HSEBYPASS_ON
AnnaBridge 167:e84263d55307 381 * @arg @ref LL_UTILS_HSEBYPASS_OFF
AnnaBridge 167:e84263d55307 382 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
AnnaBridge 167:e84263d55307 383 * the configuration information for the PLL.
AnnaBridge 167:e84263d55307 384 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
AnnaBridge 167:e84263d55307 385 * the configuration information for the BUS prescalers.
AnnaBridge 167:e84263d55307 386 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 387 * - SUCCESS: Max frequency configuration done
AnnaBridge 167:e84263d55307 388 * - ERROR: Max frequency configuration not done
AnnaBridge 167:e84263d55307 389 */
AnnaBridge 167:e84263d55307 390 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
AnnaBridge 167:e84263d55307 391 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
AnnaBridge 167:e84263d55307 392 {
AnnaBridge 167:e84263d55307 393 ErrorStatus status = SUCCESS;
AnnaBridge 167:e84263d55307 394 uint32_t pllfreq = 0U;
AnnaBridge 167:e84263d55307 395
AnnaBridge 167:e84263d55307 396 /* Check the parameters */
AnnaBridge 167:e84263d55307 397 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
AnnaBridge 167:e84263d55307 398 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
AnnaBridge 167:e84263d55307 399
AnnaBridge 167:e84263d55307 400 /* Check if one of the PLL is enabled */
AnnaBridge 167:e84263d55307 401 if(UTILS_PLL_IsBusy() == SUCCESS)
AnnaBridge 167:e84263d55307 402 {
AnnaBridge 167:e84263d55307 403 /* Calculate the new PLL output frequency */
AnnaBridge 167:e84263d55307 404 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
AnnaBridge 167:e84263d55307 405
AnnaBridge 167:e84263d55307 406 /* Enable HSE if not enabled */
AnnaBridge 167:e84263d55307 407 if(LL_RCC_HSE_IsReady() != 1U)
AnnaBridge 167:e84263d55307 408 {
AnnaBridge 167:e84263d55307 409 /* Check if need to enable HSE bypass feature or not */
AnnaBridge 167:e84263d55307 410 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
AnnaBridge 167:e84263d55307 411 {
AnnaBridge 167:e84263d55307 412 LL_RCC_HSE_EnableBypass();
AnnaBridge 167:e84263d55307 413 }
AnnaBridge 167:e84263d55307 414 else
AnnaBridge 167:e84263d55307 415 {
AnnaBridge 167:e84263d55307 416 LL_RCC_HSE_DisableBypass();
AnnaBridge 167:e84263d55307 417 }
AnnaBridge 167:e84263d55307 418
AnnaBridge 167:e84263d55307 419 /* Enable HSE */
AnnaBridge 167:e84263d55307 420 LL_RCC_HSE_Enable();
AnnaBridge 167:e84263d55307 421 while (LL_RCC_HSE_IsReady() != 1U)
AnnaBridge 167:e84263d55307 422 {
AnnaBridge 167:e84263d55307 423 /* Wait for HSE ready */
AnnaBridge 167:e84263d55307 424 }
AnnaBridge 167:e84263d55307 425 }
AnnaBridge 167:e84263d55307 426
AnnaBridge 167:e84263d55307 427 /* Configure PLL */
AnnaBridge 167:e84263d55307 428 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
AnnaBridge 167:e84263d55307 429 UTILS_PLLInitStruct->PLLP);
AnnaBridge 167:e84263d55307 430
AnnaBridge 167:e84263d55307 431 /* Enable PLL and switch system clock to PLL */
AnnaBridge 167:e84263d55307 432 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
AnnaBridge 167:e84263d55307 433 }
AnnaBridge 167:e84263d55307 434 else
AnnaBridge 167:e84263d55307 435 {
AnnaBridge 167:e84263d55307 436 /* Current PLL configuration cannot be modified */
AnnaBridge 167:e84263d55307 437 status = ERROR;
AnnaBridge 167:e84263d55307 438 }
AnnaBridge 167:e84263d55307 439
AnnaBridge 167:e84263d55307 440 return status;
AnnaBridge 167:e84263d55307 441 }
AnnaBridge 167:e84263d55307 442
AnnaBridge 167:e84263d55307 443 /**
AnnaBridge 167:e84263d55307 444 * @}
AnnaBridge 167:e84263d55307 445 */
AnnaBridge 167:e84263d55307 446
AnnaBridge 167:e84263d55307 447 /**
AnnaBridge 167:e84263d55307 448 * @}
AnnaBridge 167:e84263d55307 449 */
AnnaBridge 167:e84263d55307 450
AnnaBridge 167:e84263d55307 451 /** @addtogroup UTILS_LL_Private_Functions
AnnaBridge 167:e84263d55307 452 * @{
AnnaBridge 167:e84263d55307 453 */
AnnaBridge 167:e84263d55307 454 /**
AnnaBridge 167:e84263d55307 455 * @brief Update number of Flash wait states in line with new frequency and current
AnnaBridge 167:e84263d55307 456 voltage range.
AnnaBridge 167:e84263d55307 457 * @param HCLK_Frequency HCLK frequency
AnnaBridge 167:e84263d55307 458 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 459 * - SUCCESS: Latency has been modified
AnnaBridge 167:e84263d55307 460 * - ERROR: Latency cannot be modified
AnnaBridge 167:e84263d55307 461 */
AnnaBridge 167:e84263d55307 462 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
AnnaBridge 167:e84263d55307 463 {
AnnaBridge 167:e84263d55307 464 ErrorStatus status = SUCCESS;
AnnaBridge 167:e84263d55307 465
AnnaBridge 167:e84263d55307 466 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
AnnaBridge 167:e84263d55307 467
AnnaBridge 167:e84263d55307 468 /* Frequency cannot be equal to 0 */
AnnaBridge 167:e84263d55307 469 if(HCLK_Frequency == 0U)
AnnaBridge 167:e84263d55307 470 {
AnnaBridge 167:e84263d55307 471 status = ERROR;
AnnaBridge 167:e84263d55307 472 }
AnnaBridge 167:e84263d55307 473 else
AnnaBridge 167:e84263d55307 474 {
AnnaBridge 167:e84263d55307 475 if(HCLK_Frequency > UTILS_LATENCY3_FREQ)
AnnaBridge 167:e84263d55307 476 {
AnnaBridge 167:e84263d55307 477 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
AnnaBridge 167:e84263d55307 478 latency = LL_FLASH_LATENCY_3;
AnnaBridge 167:e84263d55307 479 }
AnnaBridge 167:e84263d55307 480 else if(HCLK_Frequency > UTILS_LATENCY2_FREQ)
AnnaBridge 167:e84263d55307 481 {
AnnaBridge 167:e84263d55307 482 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
AnnaBridge 167:e84263d55307 483 latency = LL_FLASH_LATENCY_2;
AnnaBridge 167:e84263d55307 484 }
AnnaBridge 167:e84263d55307 485 else
AnnaBridge 167:e84263d55307 486 {
AnnaBridge 167:e84263d55307 487 if(HCLK_Frequency > UTILS_LATENCY1_FREQ)
AnnaBridge 167:e84263d55307 488 {
AnnaBridge 167:e84263d55307 489 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
AnnaBridge 167:e84263d55307 490 latency = LL_FLASH_LATENCY_1;
AnnaBridge 167:e84263d55307 491 }
AnnaBridge 167:e84263d55307 492 /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
AnnaBridge 167:e84263d55307 493 }
AnnaBridge 167:e84263d55307 494
AnnaBridge 167:e84263d55307 495 LL_FLASH_SetLatency(latency);
AnnaBridge 167:e84263d55307 496
AnnaBridge 167:e84263d55307 497 /* Check that the new number of wait states is taken into account to access the Flash
AnnaBridge 167:e84263d55307 498 memory by reading the FLASH_ACR register */
AnnaBridge 167:e84263d55307 499 if(LL_FLASH_GetLatency() != latency)
AnnaBridge 167:e84263d55307 500 {
AnnaBridge 167:e84263d55307 501 status = ERROR;
AnnaBridge 167:e84263d55307 502 }
AnnaBridge 167:e84263d55307 503 }
AnnaBridge 167:e84263d55307 504 return status;
AnnaBridge 167:e84263d55307 505 }
AnnaBridge 167:e84263d55307 506
AnnaBridge 167:e84263d55307 507 /**
AnnaBridge 167:e84263d55307 508 * @brief Function to check that PLL can be modified
AnnaBridge 167:e84263d55307 509 * @param PLL_InputFrequency PLL input frequency (in Hz)
AnnaBridge 167:e84263d55307 510 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
AnnaBridge 167:e84263d55307 511 * the configuration information for the PLL.
AnnaBridge 167:e84263d55307 512 * @retval PLL output frequency (in Hz)
AnnaBridge 167:e84263d55307 513 */
AnnaBridge 167:e84263d55307 514 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
AnnaBridge 167:e84263d55307 515 {
AnnaBridge 167:e84263d55307 516 uint32_t pllfreq = 0U;
AnnaBridge 167:e84263d55307 517
AnnaBridge 167:e84263d55307 518 /* Check the parameters */
AnnaBridge 167:e84263d55307 519 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
AnnaBridge 167:e84263d55307 520 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
AnnaBridge 167:e84263d55307 521 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
AnnaBridge 167:e84263d55307 522
AnnaBridge 167:e84263d55307 523 /* Check different PLL parameters according to RM */
AnnaBridge 167:e84263d55307 524 /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
AnnaBridge 167:e84263d55307 525 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
AnnaBridge 167:e84263d55307 526 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
AnnaBridge 167:e84263d55307 527
AnnaBridge 167:e84263d55307 528 /* - PLLN: ensure that the VCO output frequency is between 192 and 432 MHz.*/
AnnaBridge 167:e84263d55307 529 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
AnnaBridge 167:e84263d55307 530 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
AnnaBridge 167:e84263d55307 531
AnnaBridge 167:e84263d55307 532 /* - PLLP: ensure that max frequency at 120000000 Hz is reached */
AnnaBridge 167:e84263d55307 533 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
AnnaBridge 167:e84263d55307 534 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
AnnaBridge 167:e84263d55307 535
AnnaBridge 167:e84263d55307 536 return pllfreq;
AnnaBridge 167:e84263d55307 537 }
AnnaBridge 167:e84263d55307 538
AnnaBridge 167:e84263d55307 539 /**
AnnaBridge 167:e84263d55307 540 * @brief Function to check that PLL can be modified
AnnaBridge 167:e84263d55307 541 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 542 * - SUCCESS: PLL modification can be done
AnnaBridge 167:e84263d55307 543 * - ERROR: PLL is busy
AnnaBridge 167:e84263d55307 544 */
AnnaBridge 167:e84263d55307 545 static ErrorStatus UTILS_PLL_IsBusy(void)
AnnaBridge 167:e84263d55307 546 {
AnnaBridge 167:e84263d55307 547 ErrorStatus status = SUCCESS;
AnnaBridge 167:e84263d55307 548
AnnaBridge 167:e84263d55307 549 /* Check if PLL is busy*/
AnnaBridge 167:e84263d55307 550 if(LL_RCC_PLL_IsReady() != 0U)
AnnaBridge 167:e84263d55307 551 {
AnnaBridge 167:e84263d55307 552 /* PLL configuration cannot be modified */
AnnaBridge 167:e84263d55307 553 status = ERROR;
AnnaBridge 167:e84263d55307 554 }
AnnaBridge 167:e84263d55307 555
AnnaBridge 167:e84263d55307 556 /* Check if PLLI2S is busy*/
AnnaBridge 167:e84263d55307 557 if(LL_RCC_PLLI2S_IsReady() != 0U)
AnnaBridge 167:e84263d55307 558 {
AnnaBridge 167:e84263d55307 559 /* PLLI2S configuration cannot be modified */
AnnaBridge 167:e84263d55307 560 status = ERROR;
AnnaBridge 167:e84263d55307 561 }
AnnaBridge 167:e84263d55307 562 return status;
AnnaBridge 167:e84263d55307 563 }
AnnaBridge 167:e84263d55307 564
AnnaBridge 167:e84263d55307 565 /**
AnnaBridge 167:e84263d55307 566 * @brief Function to enable PLL and switch system clock to PLL
AnnaBridge 167:e84263d55307 567 * @param SYSCLK_Frequency SYSCLK frequency
AnnaBridge 167:e84263d55307 568 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
AnnaBridge 167:e84263d55307 569 * the configuration information for the BUS prescalers.
AnnaBridge 167:e84263d55307 570 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 571 * - SUCCESS: No problem to switch system to PLL
AnnaBridge 167:e84263d55307 572 * - ERROR: Problem to switch system to PLL
AnnaBridge 167:e84263d55307 573 */
AnnaBridge 167:e84263d55307 574 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
AnnaBridge 167:e84263d55307 575 {
AnnaBridge 167:e84263d55307 576 ErrorStatus status = SUCCESS;
AnnaBridge 167:e84263d55307 577 uint32_t hclk_frequency = 0U;
AnnaBridge 167:e84263d55307 578
AnnaBridge 167:e84263d55307 579 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
AnnaBridge 167:e84263d55307 580 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
AnnaBridge 167:e84263d55307 581 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
AnnaBridge 167:e84263d55307 582
AnnaBridge 167:e84263d55307 583 /* Calculate HCLK frequency */
AnnaBridge 167:e84263d55307 584 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
AnnaBridge 167:e84263d55307 585
AnnaBridge 167:e84263d55307 586 /* Increasing the number of wait states because of higher CPU frequency */
AnnaBridge 167:e84263d55307 587 if(SystemCoreClock < hclk_frequency)
AnnaBridge 167:e84263d55307 588 {
AnnaBridge 167:e84263d55307 589 /* Set FLASH latency to highest latency */
AnnaBridge 167:e84263d55307 590 status = UTILS_SetFlashLatency(hclk_frequency);
AnnaBridge 167:e84263d55307 591 }
AnnaBridge 167:e84263d55307 592
AnnaBridge 167:e84263d55307 593 /* Update system clock configuration */
AnnaBridge 167:e84263d55307 594 if(status == SUCCESS)
AnnaBridge 167:e84263d55307 595 {
AnnaBridge 167:e84263d55307 596 /* Enable PLL */
AnnaBridge 167:e84263d55307 597 LL_RCC_PLL_Enable();
AnnaBridge 167:e84263d55307 598 while (LL_RCC_PLL_IsReady() != 1U)
AnnaBridge 167:e84263d55307 599 {
AnnaBridge 167:e84263d55307 600 /* Wait for PLL ready */
AnnaBridge 167:e84263d55307 601 }
AnnaBridge 167:e84263d55307 602
AnnaBridge 167:e84263d55307 603 /* Sysclk activation on the main PLL */
AnnaBridge 167:e84263d55307 604 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
AnnaBridge 167:e84263d55307 605 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
AnnaBridge 167:e84263d55307 606 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
AnnaBridge 167:e84263d55307 607 {
AnnaBridge 167:e84263d55307 608 /* Wait for system clock switch to PLL */
AnnaBridge 167:e84263d55307 609 }
AnnaBridge 167:e84263d55307 610
AnnaBridge 167:e84263d55307 611 /* Set APB1 & APB2 prescaler*/
AnnaBridge 167:e84263d55307 612 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
AnnaBridge 167:e84263d55307 613 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
AnnaBridge 167:e84263d55307 614 }
AnnaBridge 167:e84263d55307 615
AnnaBridge 167:e84263d55307 616 /* Decreasing the number of wait states because of lower CPU frequency */
AnnaBridge 167:e84263d55307 617 if(SystemCoreClock > hclk_frequency)
AnnaBridge 167:e84263d55307 618 {
AnnaBridge 167:e84263d55307 619 /* Set FLASH latency to lowest latency */
AnnaBridge 167:e84263d55307 620 status = UTILS_SetFlashLatency(hclk_frequency);
AnnaBridge 167:e84263d55307 621 }
AnnaBridge 167:e84263d55307 622
AnnaBridge 167:e84263d55307 623 /* Update SystemCoreClock variable */
AnnaBridge 167:e84263d55307 624 if(status == SUCCESS)
AnnaBridge 167:e84263d55307 625 {
AnnaBridge 167:e84263d55307 626 LL_SetSystemCoreClock(hclk_frequency);
AnnaBridge 167:e84263d55307 627 }
AnnaBridge 167:e84263d55307 628
AnnaBridge 167:e84263d55307 629 return status;
AnnaBridge 167:e84263d55307 630 }
AnnaBridge 167:e84263d55307 631
AnnaBridge 167:e84263d55307 632 /**
AnnaBridge 167:e84263d55307 633 * @}
AnnaBridge 167:e84263d55307 634 */
AnnaBridge 167:e84263d55307 635
AnnaBridge 167:e84263d55307 636 /**
AnnaBridge 167:e84263d55307 637 * @}
AnnaBridge 167:e84263d55307 638 */
AnnaBridge 167:e84263d55307 639
AnnaBridge 167:e84263d55307 640 /**
AnnaBridge 167:e84263d55307 641 * @}
AnnaBridge 167:e84263d55307 642 */
AnnaBridge 167:e84263d55307 643
AnnaBridge 167:e84263d55307 644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/