mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_sdmmc.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 167:e84263d55307
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f2xx_ll_sdmmc.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
AnnaBridge | 167:e84263d55307 | 5 | * @version V1.2.1 |
AnnaBridge | 167:e84263d55307 | 6 | * @date 14-April-2017 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief SDMMC Low Layer HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * |
<> | 144:ef7eb2e8f9f7 | 9 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 10 | * functionalities of the SDMMC peripheral: |
<> | 144:ef7eb2e8f9f7 | 11 | * + Initialization/de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 12 | * + I/O operation functions |
<> | 144:ef7eb2e8f9f7 | 13 | * + Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 14 | * + Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 15 | * |
<> | 144:ef7eb2e8f9f7 | 16 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 17 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 18 | ##### SDMMC peripheral features ##### |
<> | 144:ef7eb2e8f9f7 | 19 | ============================================================================== |
AnnaBridge | 167:e84263d55307 | 20 | [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2 |
AnnaBridge | 167:e84263d55307 | 21 | peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA |
<> | 144:ef7eb2e8f9f7 | 22 | devices. |
AnnaBridge | 167:e84263d55307 | 23 | |
AnnaBridge | 167:e84263d55307 | 24 | [..] The SDMMC features include the following: |
<> | 144:ef7eb2e8f9f7 | 25 | (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support |
<> | 144:ef7eb2e8f9f7 | 26 | for three different databus modes: 1-bit (default), 4-bit and 8-bit |
<> | 144:ef7eb2e8f9f7 | 27 | (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) |
<> | 144:ef7eb2e8f9f7 | 28 | (+) Full compliance with SD Memory Card Specifications Version 2.0 |
<> | 144:ef7eb2e8f9f7 | 29 | (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two |
<> | 144:ef7eb2e8f9f7 | 30 | different data bus modes: 1-bit (default) and 4-bit |
<> | 144:ef7eb2e8f9f7 | 31 | (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol |
<> | 144:ef7eb2e8f9f7 | 32 | Rev1.1) |
<> | 144:ef7eb2e8f9f7 | 33 | (+) Data transfer up to 48 MHz for the 8 bit mode |
<> | 144:ef7eb2e8f9f7 | 34 | (+) Data and command output enable signals to control external bidirectional drivers. |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 38 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 39 | [..] |
<> | 144:ef7eb2e8f9f7 | 40 | This driver is a considered as a driver of service for external devices drivers |
AnnaBridge | 167:e84263d55307 | 41 | that interfaces with the SDMMC peripheral. |
AnnaBridge | 167:e84263d55307 | 42 | According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs |
AnnaBridge | 167:e84263d55307 | 43 | is used in the device's driver to perform SDMMC operations and functionalities. |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | This driver is almost transparent for the final user, it is only used to implement other |
<> | 144:ef7eb2e8f9f7 | 46 | functionalities of the external device. |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | [..] |
AnnaBridge | 167:e84263d55307 | 49 | (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL |
AnnaBridge | 167:e84263d55307 | 50 | (PLL48CLK). Before start working with SDMMC peripheral make sure that the |
<> | 144:ef7eb2e8f9f7 | 51 | PLL is well configured. |
AnnaBridge | 167:e84263d55307 | 52 | The SDMMC peripheral uses two clock signals: |
AnnaBridge | 167:e84263d55307 | 53 | (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) |
<> | 144:ef7eb2e8f9f7 | 54 | (++) APB2 bus clock (PCLK2) |
<> | 144:ef7eb2e8f9f7 | 55 | |
AnnaBridge | 167:e84263d55307 | 56 | -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: |
AnnaBridge | 167:e84263d55307 | 57 | Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) |
<> | 144:ef7eb2e8f9f7 | 58 | |
AnnaBridge | 167:e84263d55307 | 59 | (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC |
<> | 144:ef7eb2e8f9f7 | 60 | peripheral. |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx) |
AnnaBridge | 167:e84263d55307 | 63 | function and disable it using the function SDIO_PowerState_ON(SDIOx). |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. |
<> | 144:ef7eb2e8f9f7 | 66 | |
AnnaBridge | 167:e84263d55307 | 67 | (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hSDIO, IT) |
AnnaBridge | 167:e84263d55307 | 68 | and __SDIO_DISABLE_IT(hSDIO, IT) if you need to use interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | (+) When using the DMA mode |
<> | 144:ef7eb2e8f9f7 | 71 | (++) Configure the DMA in the MSP layer of the external device |
<> | 144:ef7eb2e8f9f7 | 72 | (++) Active the needed channel Request |
<> | 144:ef7eb2e8f9f7 | 73 | (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro |
<> | 144:ef7eb2e8f9f7 | 74 | __SDIO_DMA_DISABLE(). |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | (+) To control the CPSM (Command Path State Machine) and send |
AnnaBridge | 167:e84263d55307 | 77 | commands to the card use the SDIO_SendCommand(), |
<> | 144:ef7eb2e8f9f7 | 78 | SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has |
<> | 144:ef7eb2e8f9f7 | 79 | to fill the command structure (pointer to SDIO_CmdInitTypeDef) according |
<> | 144:ef7eb2e8f9f7 | 80 | to the selected command to be sent. |
<> | 144:ef7eb2e8f9f7 | 81 | The parameters that should be filled are: |
<> | 144:ef7eb2e8f9f7 | 82 | (++) Command Argument |
<> | 144:ef7eb2e8f9f7 | 83 | (++) Command Index |
<> | 144:ef7eb2e8f9f7 | 84 | (++) Command Response type |
<> | 144:ef7eb2e8f9f7 | 85 | (++) Command Wait |
<> | 144:ef7eb2e8f9f7 | 86 | (++) CPSM Status (Enable or Disable). |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | -@@- To check if the command is well received, read the SDIO_CMDRESP |
<> | 144:ef7eb2e8f9f7 | 89 | register using the SDIO_GetCommandResponse(). |
AnnaBridge | 167:e84263d55307 | 90 | The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the |
<> | 144:ef7eb2e8f9f7 | 91 | SDIO_GetResponse() function. |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | (+) To control the DPSM (Data Path State Machine) and send/receive |
AnnaBridge | 167:e84263d55307 | 94 | data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(), |
AnnaBridge | 167:e84263d55307 | 95 | SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | *** Read Operations *** |
<> | 144:ef7eb2e8f9f7 | 98 | ======================= |
<> | 144:ef7eb2e8f9f7 | 99 | [..] |
<> | 144:ef7eb2e8f9f7 | 100 | (#) First, user has to fill the data structure (pointer to |
<> | 144:ef7eb2e8f9f7 | 101 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
<> | 144:ef7eb2e8f9f7 | 102 | The parameters that should be filled are: |
AnnaBridge | 167:e84263d55307 | 103 | (++) Data TimeOut |
<> | 144:ef7eb2e8f9f7 | 104 | (++) Data Length |
<> | 144:ef7eb2e8f9f7 | 105 | (++) Data Block size |
AnnaBridge | 167:e84263d55307 | 106 | (++) Data Transfer direction: should be from card (To SDMMC) |
<> | 144:ef7eb2e8f9f7 | 107 | (++) Data Transfer mode |
<> | 144:ef7eb2e8f9f7 | 108 | (++) DPSM Status (Enable or Disable) |
<> | 144:ef7eb2e8f9f7 | 109 | |
AnnaBridge | 167:e84263d55307 | 110 | (#) Configure the SDMMC resources to receive the data from the card |
<> | 144:ef7eb2e8f9f7 | 111 | according to selected transfer mode (Refer to Step 8, 9 and 10). |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | (#) Send the selected Read command (refer to step 11). |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | (#) Use the SDIO flags/interrupts to check the transfer status. |
<> | 144:ef7eb2e8f9f7 | 116 | |
<> | 144:ef7eb2e8f9f7 | 117 | *** Write Operations *** |
<> | 144:ef7eb2e8f9f7 | 118 | ======================== |
<> | 144:ef7eb2e8f9f7 | 119 | [..] |
<> | 144:ef7eb2e8f9f7 | 120 | (#) First, user has to fill the data structure (pointer to |
<> | 144:ef7eb2e8f9f7 | 121 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
<> | 144:ef7eb2e8f9f7 | 122 | The parameters that should be filled are: |
AnnaBridge | 167:e84263d55307 | 123 | (++) Data TimeOut |
<> | 144:ef7eb2e8f9f7 | 124 | (++) Data Length |
<> | 144:ef7eb2e8f9f7 | 125 | (++) Data Block size |
<> | 144:ef7eb2e8f9f7 | 126 | (++) Data Transfer direction: should be to card (To CARD) |
<> | 144:ef7eb2e8f9f7 | 127 | (++) Data Transfer mode |
<> | 144:ef7eb2e8f9f7 | 128 | (++) DPSM Status (Enable or Disable) |
<> | 144:ef7eb2e8f9f7 | 129 | |
AnnaBridge | 167:e84263d55307 | 130 | (#) Configure the SDMMC resources to send the data to the card according to |
<> | 144:ef7eb2e8f9f7 | 131 | selected transfer mode. |
<> | 144:ef7eb2e8f9f7 | 132 | |
<> | 144:ef7eb2e8f9f7 | 133 | (#) Send the selected Write command. |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | (#) Use the SDIO flags/interrupts to check the transfer status. |
AnnaBridge | 167:e84263d55307 | 136 | |
AnnaBridge | 167:e84263d55307 | 137 | *** Command management operations *** |
AnnaBridge | 167:e84263d55307 | 138 | ===================================== |
AnnaBridge | 167:e84263d55307 | 139 | [..] |
AnnaBridge | 167:e84263d55307 | 140 | (#) The commands used for Read/Write//Erase operations are managed in |
AnnaBridge | 167:e84263d55307 | 141 | separate functions. |
AnnaBridge | 167:e84263d55307 | 142 | Each function allows to send the needed command with the related argument, |
AnnaBridge | 167:e84263d55307 | 143 | then check the response. |
AnnaBridge | 167:e84263d55307 | 144 | By the same approach, you could implement a command and check the response. |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 147 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 148 | * @attention |
<> | 144:ef7eb2e8f9f7 | 149 | * |
AnnaBridge | 167:e84263d55307 | 150 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 151 | * |
<> | 144:ef7eb2e8f9f7 | 152 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 153 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 154 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 155 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 156 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 157 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 158 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 159 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 160 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 161 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 162 | * |
<> | 144:ef7eb2e8f9f7 | 163 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 164 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 165 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 166 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 167 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 168 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 169 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 170 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 171 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 172 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 173 | * |
<> | 144:ef7eb2e8f9f7 | 174 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 175 | */ |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 178 | #include "stm32f2xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | /** @addtogroup STM32F2xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 181 | * @{ |
<> | 144:ef7eb2e8f9f7 | 182 | */ |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | /** @defgroup SDMMC_LL SDMMC Low Layer |
AnnaBridge | 167:e84263d55307 | 185 | * @brief Low layer module for SD |
<> | 144:ef7eb2e8f9f7 | 186 | * @{ |
<> | 144:ef7eb2e8f9f7 | 187 | */ |
<> | 144:ef7eb2e8f9f7 | 188 | |
AnnaBridge | 167:e84263d55307 | 189 | #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 192 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 193 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 194 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 195 | /* Private function prototypes -----------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 196 | static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 197 | static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); |
AnnaBridge | 167:e84263d55307 | 198 | static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 199 | static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 200 | static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 201 | static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); |
<> | 144:ef7eb2e8f9f7 | 202 | |
AnnaBridge | 167:e84263d55307 | 203 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 204 | |
AnnaBridge | 167:e84263d55307 | 205 | /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions |
<> | 144:ef7eb2e8f9f7 | 206 | * @{ |
<> | 144:ef7eb2e8f9f7 | 207 | */ |
<> | 144:ef7eb2e8f9f7 | 208 | |
AnnaBridge | 167:e84263d55307 | 209 | /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 210 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 211 | * |
<> | 144:ef7eb2e8f9f7 | 212 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 213 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 214 | ##### Initialization/de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 215 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 216 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 217 | |
<> | 144:ef7eb2e8f9f7 | 218 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 219 | * @{ |
<> | 144:ef7eb2e8f9f7 | 220 | */ |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | /** |
AnnaBridge | 167:e84263d55307 | 223 | * @brief Initializes the SDMMC according to the specified |
AnnaBridge | 167:e84263d55307 | 224 | * parameters in the SDMMC_InitTypeDef and create the associated handle. |
AnnaBridge | 167:e84263d55307 | 225 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 226 | * @param Init: SDMMC initialization structure |
<> | 144:ef7eb2e8f9f7 | 227 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 228 | */ |
<> | 144:ef7eb2e8f9f7 | 229 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) |
<> | 144:ef7eb2e8f9f7 | 230 | { |
AnnaBridge | 167:e84263d55307 | 231 | uint32_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 234 | assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); |
<> | 144:ef7eb2e8f9f7 | 235 | assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); |
<> | 144:ef7eb2e8f9f7 | 236 | assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); |
<> | 144:ef7eb2e8f9f7 | 237 | assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); |
<> | 144:ef7eb2e8f9f7 | 238 | assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); |
<> | 144:ef7eb2e8f9f7 | 239 | assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); |
<> | 144:ef7eb2e8f9f7 | 240 | assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); |
<> | 144:ef7eb2e8f9f7 | 241 | |
AnnaBridge | 167:e84263d55307 | 242 | /* Set SDMMC configuration parameters */ |
<> | 144:ef7eb2e8f9f7 | 243 | tmpreg |= (Init.ClockEdge |\ |
<> | 144:ef7eb2e8f9f7 | 244 | Init.ClockBypass |\ |
<> | 144:ef7eb2e8f9f7 | 245 | Init.ClockPowerSave |\ |
<> | 144:ef7eb2e8f9f7 | 246 | Init.BusWide |\ |
<> | 144:ef7eb2e8f9f7 | 247 | Init.HardwareFlowControl |\ |
<> | 144:ef7eb2e8f9f7 | 248 | Init.ClockDiv |
<> | 144:ef7eb2e8f9f7 | 249 | ); |
<> | 144:ef7eb2e8f9f7 | 250 | |
AnnaBridge | 167:e84263d55307 | 251 | /* Write to SDMMC CLKCR */ |
<> | 144:ef7eb2e8f9f7 | 252 | MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 255 | } |
<> | 144:ef7eb2e8f9f7 | 256 | |
AnnaBridge | 167:e84263d55307 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /** |
<> | 144:ef7eb2e8f9f7 | 259 | * @} |
<> | 144:ef7eb2e8f9f7 | 260 | */ |
<> | 144:ef7eb2e8f9f7 | 261 | |
AnnaBridge | 167:e84263d55307 | 262 | /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 263 | * @brief Data transfers functions |
<> | 144:ef7eb2e8f9f7 | 264 | * |
<> | 144:ef7eb2e8f9f7 | 265 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 266 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 267 | ##### I/O operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 268 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 269 | [..] |
AnnaBridge | 167:e84263d55307 | 270 | This subsection provides a set of functions allowing to manage the SDMMC data |
<> | 144:ef7eb2e8f9f7 | 271 | transfers. |
<> | 144:ef7eb2e8f9f7 | 272 | |
<> | 144:ef7eb2e8f9f7 | 273 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 274 | * @{ |
<> | 144:ef7eb2e8f9f7 | 275 | */ |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | /** |
<> | 144:ef7eb2e8f9f7 | 278 | * @brief Read data (word) from Rx FIFO in blocking mode (polling) |
AnnaBridge | 167:e84263d55307 | 279 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 280 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 281 | */ |
<> | 144:ef7eb2e8f9f7 | 282 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) |
<> | 144:ef7eb2e8f9f7 | 283 | { |
<> | 144:ef7eb2e8f9f7 | 284 | /* Read data from Rx FIFO */ |
<> | 144:ef7eb2e8f9f7 | 285 | return (SDIOx->FIFO); |
<> | 144:ef7eb2e8f9f7 | 286 | } |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | /** |
<> | 144:ef7eb2e8f9f7 | 289 | * @brief Write data (word) to Tx FIFO in blocking mode (polling) |
AnnaBridge | 167:e84263d55307 | 290 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 291 | * @param pWriteData: pointer to data to write |
<> | 144:ef7eb2e8f9f7 | 292 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 293 | */ |
<> | 144:ef7eb2e8f9f7 | 294 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) |
<> | 144:ef7eb2e8f9f7 | 295 | { |
<> | 144:ef7eb2e8f9f7 | 296 | /* Write data to FIFO */ |
<> | 144:ef7eb2e8f9f7 | 297 | SDIOx->FIFO = *pWriteData; |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 300 | } |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | /** |
<> | 144:ef7eb2e8f9f7 | 303 | * @} |
<> | 144:ef7eb2e8f9f7 | 304 | */ |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 307 | * @brief management functions |
<> | 144:ef7eb2e8f9f7 | 308 | * |
<> | 144:ef7eb2e8f9f7 | 309 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 310 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 311 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 312 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 313 | [..] |
AnnaBridge | 167:e84263d55307 | 314 | This subsection provides a set of functions allowing to control the SDMMC data |
<> | 144:ef7eb2e8f9f7 | 315 | transfers. |
<> | 144:ef7eb2e8f9f7 | 316 | |
<> | 144:ef7eb2e8f9f7 | 317 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 318 | * @{ |
<> | 144:ef7eb2e8f9f7 | 319 | */ |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | /** |
AnnaBridge | 167:e84263d55307 | 322 | * @brief Set SDMMC Power state to ON. |
AnnaBridge | 167:e84263d55307 | 323 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 324 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 325 | */ |
<> | 144:ef7eb2e8f9f7 | 326 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) |
<> | 144:ef7eb2e8f9f7 | 327 | { |
<> | 144:ef7eb2e8f9f7 | 328 | /* Set power state to ON */ |
<> | 144:ef7eb2e8f9f7 | 329 | SDIOx->POWER = SDIO_POWER_PWRCTRL; |
AnnaBridge | 167:e84263d55307 | 330 | |
AnnaBridge | 167:e84263d55307 | 331 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 332 | } |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /** |
AnnaBridge | 167:e84263d55307 | 335 | * @brief Set SDMMC Power state to OFF. |
AnnaBridge | 167:e84263d55307 | 336 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 337 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 338 | */ |
<> | 144:ef7eb2e8f9f7 | 339 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) |
<> | 144:ef7eb2e8f9f7 | 340 | { |
<> | 144:ef7eb2e8f9f7 | 341 | /* Set power state to OFF */ |
AnnaBridge | 167:e84263d55307 | 342 | SDIOx->POWER = 0x00000000U; |
<> | 144:ef7eb2e8f9f7 | 343 | |
<> | 144:ef7eb2e8f9f7 | 344 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 345 | } |
<> | 144:ef7eb2e8f9f7 | 346 | |
<> | 144:ef7eb2e8f9f7 | 347 | /** |
AnnaBridge | 167:e84263d55307 | 348 | * @brief Get SDMMC Power state. |
AnnaBridge | 167:e84263d55307 | 349 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 350 | * @retval Power status of the controller. The returned value can be one of the |
<> | 144:ef7eb2e8f9f7 | 351 | * following values: |
<> | 144:ef7eb2e8f9f7 | 352 | * - 0x00: Power OFF |
<> | 144:ef7eb2e8f9f7 | 353 | * - 0x02: Power UP |
<> | 144:ef7eb2e8f9f7 | 354 | * - 0x03: Power ON |
<> | 144:ef7eb2e8f9f7 | 355 | */ |
<> | 144:ef7eb2e8f9f7 | 356 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) |
<> | 144:ef7eb2e8f9f7 | 357 | { |
<> | 144:ef7eb2e8f9f7 | 358 | return (SDIOx->POWER & SDIO_POWER_PWRCTRL); |
<> | 144:ef7eb2e8f9f7 | 359 | } |
<> | 144:ef7eb2e8f9f7 | 360 | |
<> | 144:ef7eb2e8f9f7 | 361 | /** |
AnnaBridge | 167:e84263d55307 | 362 | * @brief Configure the SDMMC command path according to the specified parameters in |
<> | 144:ef7eb2e8f9f7 | 363 | * SDIO_CmdInitTypeDef structure and send the command |
AnnaBridge | 167:e84263d55307 | 364 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 365 | * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains |
AnnaBridge | 167:e84263d55307 | 366 | * the configuration information for the SDMMC command |
<> | 144:ef7eb2e8f9f7 | 367 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 368 | */ |
AnnaBridge | 167:e84263d55307 | 369 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) |
<> | 144:ef7eb2e8f9f7 | 370 | { |
AnnaBridge | 167:e84263d55307 | 371 | uint32_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 372 | |
<> | 144:ef7eb2e8f9f7 | 373 | /* Check the parameters */ |
AnnaBridge | 167:e84263d55307 | 374 | assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex)); |
AnnaBridge | 167:e84263d55307 | 375 | assert_param(IS_SDIO_RESPONSE(Command->Response)); |
AnnaBridge | 167:e84263d55307 | 376 | assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); |
AnnaBridge | 167:e84263d55307 | 377 | assert_param(IS_SDIO_CPSM(Command->CPSM)); |
<> | 144:ef7eb2e8f9f7 | 378 | |
AnnaBridge | 167:e84263d55307 | 379 | /* Set the SDMMC Argument value */ |
AnnaBridge | 167:e84263d55307 | 380 | SDIOx->ARG = Command->Argument; |
<> | 144:ef7eb2e8f9f7 | 381 | |
AnnaBridge | 167:e84263d55307 | 382 | /* Set SDMMC command parameters */ |
AnnaBridge | 167:e84263d55307 | 383 | tmpreg |= (uint32_t)(Command->CmdIndex |\ |
AnnaBridge | 167:e84263d55307 | 384 | Command->Response |\ |
AnnaBridge | 167:e84263d55307 | 385 | Command->WaitForInterrupt |\ |
AnnaBridge | 167:e84263d55307 | 386 | Command->CPSM); |
<> | 144:ef7eb2e8f9f7 | 387 | |
AnnaBridge | 167:e84263d55307 | 388 | /* Write to SDMMC CMD register */ |
<> | 144:ef7eb2e8f9f7 | 389 | MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); |
<> | 144:ef7eb2e8f9f7 | 390 | |
<> | 144:ef7eb2e8f9f7 | 391 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 392 | } |
<> | 144:ef7eb2e8f9f7 | 393 | |
<> | 144:ef7eb2e8f9f7 | 394 | /** |
<> | 144:ef7eb2e8f9f7 | 395 | * @brief Return the command index of last command for which response received |
AnnaBridge | 167:e84263d55307 | 396 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 397 | * @retval Command index of the last command response received |
<> | 144:ef7eb2e8f9f7 | 398 | */ |
<> | 144:ef7eb2e8f9f7 | 399 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) |
<> | 144:ef7eb2e8f9f7 | 400 | { |
<> | 144:ef7eb2e8f9f7 | 401 | return (uint8_t)(SDIOx->RESPCMD); |
<> | 144:ef7eb2e8f9f7 | 402 | } |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | |
<> | 144:ef7eb2e8f9f7 | 405 | /** |
<> | 144:ef7eb2e8f9f7 | 406 | * @brief Return the response received from the card for the last command |
AnnaBridge | 167:e84263d55307 | 407 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 408 | * @param Response: Specifies the SDMMC response register. |
<> | 144:ef7eb2e8f9f7 | 409 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 410 | * @arg SDIO_RESP1: Response Register 1 |
AnnaBridge | 167:e84263d55307 | 411 | * @arg SDIO_RESP1: Response Register 2 |
AnnaBridge | 167:e84263d55307 | 412 | * @arg SDIO_RESP1: Response Register 3 |
AnnaBridge | 167:e84263d55307 | 413 | * @arg SDIO_RESP1: Response Register 4 |
<> | 144:ef7eb2e8f9f7 | 414 | * @retval The Corresponding response register value |
<> | 144:ef7eb2e8f9f7 | 415 | */ |
AnnaBridge | 167:e84263d55307 | 416 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) |
<> | 144:ef7eb2e8f9f7 | 417 | { |
AnnaBridge | 167:e84263d55307 | 418 | __IO uint32_t tmp = 0U; |
<> | 144:ef7eb2e8f9f7 | 419 | |
<> | 144:ef7eb2e8f9f7 | 420 | /* Check the parameters */ |
AnnaBridge | 167:e84263d55307 | 421 | assert_param(IS_SDIO_RESP(Response)); |
AnnaBridge | 167:e84263d55307 | 422 | |
<> | 144:ef7eb2e8f9f7 | 423 | /* Get the response */ |
AnnaBridge | 167:e84263d55307 | 424 | tmp = (uint32_t)&(SDIOx->RESP1) + Response; |
<> | 144:ef7eb2e8f9f7 | 425 | |
<> | 144:ef7eb2e8f9f7 | 426 | return (*(__IO uint32_t *) tmp); |
<> | 144:ef7eb2e8f9f7 | 427 | } |
<> | 144:ef7eb2e8f9f7 | 428 | |
<> | 144:ef7eb2e8f9f7 | 429 | /** |
AnnaBridge | 167:e84263d55307 | 430 | * @brief Configure the SDMMC data path according to the specified |
<> | 144:ef7eb2e8f9f7 | 431 | * parameters in the SDIO_DataInitTypeDef. |
AnnaBridge | 167:e84263d55307 | 432 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 433 | * @param Data : pointer to a SDIO_DataInitTypeDef structure |
AnnaBridge | 167:e84263d55307 | 434 | * that contains the configuration information for the SDMMC data. |
<> | 144:ef7eb2e8f9f7 | 435 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 436 | */ |
AnnaBridge | 167:e84263d55307 | 437 | HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) |
<> | 144:ef7eb2e8f9f7 | 438 | { |
AnnaBridge | 167:e84263d55307 | 439 | uint32_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 440 | |
<> | 144:ef7eb2e8f9f7 | 441 | /* Check the parameters */ |
AnnaBridge | 167:e84263d55307 | 442 | assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength)); |
AnnaBridge | 167:e84263d55307 | 443 | assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize)); |
AnnaBridge | 167:e84263d55307 | 444 | assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir)); |
AnnaBridge | 167:e84263d55307 | 445 | assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); |
AnnaBridge | 167:e84263d55307 | 446 | assert_param(IS_SDIO_DPSM(Data->DPSM)); |
<> | 144:ef7eb2e8f9f7 | 447 | |
AnnaBridge | 167:e84263d55307 | 448 | /* Set the SDMMC Data TimeOut value */ |
AnnaBridge | 167:e84263d55307 | 449 | SDIOx->DTIMER = Data->DataTimeOut; |
<> | 144:ef7eb2e8f9f7 | 450 | |
AnnaBridge | 167:e84263d55307 | 451 | /* Set the SDMMC DataLength value */ |
AnnaBridge | 167:e84263d55307 | 452 | SDIOx->DLEN = Data->DataLength; |
<> | 144:ef7eb2e8f9f7 | 453 | |
AnnaBridge | 167:e84263d55307 | 454 | /* Set the SDMMC data configuration parameters */ |
AnnaBridge | 167:e84263d55307 | 455 | tmpreg |= (uint32_t)(Data->DataBlockSize |\ |
AnnaBridge | 167:e84263d55307 | 456 | Data->TransferDir |\ |
AnnaBridge | 167:e84263d55307 | 457 | Data->TransferMode |\ |
AnnaBridge | 167:e84263d55307 | 458 | Data->DPSM); |
<> | 144:ef7eb2e8f9f7 | 459 | |
AnnaBridge | 167:e84263d55307 | 460 | /* Write to SDMMC DCTRL */ |
<> | 144:ef7eb2e8f9f7 | 461 | MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); |
<> | 144:ef7eb2e8f9f7 | 462 | |
<> | 144:ef7eb2e8f9f7 | 463 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 464 | |
<> | 144:ef7eb2e8f9f7 | 465 | } |
<> | 144:ef7eb2e8f9f7 | 466 | |
<> | 144:ef7eb2e8f9f7 | 467 | /** |
<> | 144:ef7eb2e8f9f7 | 468 | * @brief Returns number of remaining data bytes to be transferred. |
AnnaBridge | 167:e84263d55307 | 469 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 470 | * @retval Number of remaining data bytes to be transferred |
<> | 144:ef7eb2e8f9f7 | 471 | */ |
<> | 144:ef7eb2e8f9f7 | 472 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) |
<> | 144:ef7eb2e8f9f7 | 473 | { |
<> | 144:ef7eb2e8f9f7 | 474 | return (SDIOx->DCOUNT); |
<> | 144:ef7eb2e8f9f7 | 475 | } |
<> | 144:ef7eb2e8f9f7 | 476 | |
<> | 144:ef7eb2e8f9f7 | 477 | /** |
<> | 144:ef7eb2e8f9f7 | 478 | * @brief Get the FIFO data |
AnnaBridge | 167:e84263d55307 | 479 | * @param SDIOx: Pointer to SDMMC register base |
<> | 144:ef7eb2e8f9f7 | 480 | * @retval Data received |
<> | 144:ef7eb2e8f9f7 | 481 | */ |
<> | 144:ef7eb2e8f9f7 | 482 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) |
<> | 144:ef7eb2e8f9f7 | 483 | { |
<> | 144:ef7eb2e8f9f7 | 484 | return (SDIOx->FIFO); |
<> | 144:ef7eb2e8f9f7 | 485 | } |
<> | 144:ef7eb2e8f9f7 | 486 | |
<> | 144:ef7eb2e8f9f7 | 487 | /** |
<> | 144:ef7eb2e8f9f7 | 488 | * @brief Sets one of the two options of inserting read wait interval. |
AnnaBridge | 167:e84263d55307 | 489 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 490 | * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode. |
<> | 144:ef7eb2e8f9f7 | 491 | * This parameter can be: |
AnnaBridge | 167:e84263d55307 | 492 | * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK |
AnnaBridge | 167:e84263d55307 | 493 | * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 |
<> | 144:ef7eb2e8f9f7 | 494 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 495 | */ |
AnnaBridge | 167:e84263d55307 | 496 | HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode) |
<> | 144:ef7eb2e8f9f7 | 497 | { |
<> | 144:ef7eb2e8f9f7 | 498 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 499 | assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); |
AnnaBridge | 167:e84263d55307 | 500 | |
AnnaBridge | 167:e84263d55307 | 501 | /* Set SDMMC read wait mode */ |
AnnaBridge | 167:e84263d55307 | 502 | MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode); |
<> | 144:ef7eb2e8f9f7 | 503 | |
<> | 144:ef7eb2e8f9f7 | 504 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 505 | } |
<> | 144:ef7eb2e8f9f7 | 506 | |
<> | 144:ef7eb2e8f9f7 | 507 | /** |
<> | 144:ef7eb2e8f9f7 | 508 | * @} |
<> | 144:ef7eb2e8f9f7 | 509 | */ |
<> | 144:ef7eb2e8f9f7 | 510 | |
AnnaBridge | 167:e84263d55307 | 511 | |
AnnaBridge | 167:e84263d55307 | 512 | /** @defgroup HAL_SDMMC_LL_Group4 Command management functions |
AnnaBridge | 167:e84263d55307 | 513 | * @brief Data transfers functions |
AnnaBridge | 167:e84263d55307 | 514 | * |
AnnaBridge | 167:e84263d55307 | 515 | @verbatim |
AnnaBridge | 167:e84263d55307 | 516 | =============================================================================== |
AnnaBridge | 167:e84263d55307 | 517 | ##### Commands management functions ##### |
AnnaBridge | 167:e84263d55307 | 518 | =============================================================================== |
AnnaBridge | 167:e84263d55307 | 519 | [..] |
AnnaBridge | 167:e84263d55307 | 520 | This subsection provides a set of functions allowing to manage the needed commands. |
AnnaBridge | 167:e84263d55307 | 521 | |
AnnaBridge | 167:e84263d55307 | 522 | @endverbatim |
AnnaBridge | 167:e84263d55307 | 523 | * @{ |
AnnaBridge | 167:e84263d55307 | 524 | */ |
AnnaBridge | 167:e84263d55307 | 525 | |
AnnaBridge | 167:e84263d55307 | 526 | /** |
AnnaBridge | 167:e84263d55307 | 527 | * @brief Send the Data Block Lenght command and check the response |
AnnaBridge | 167:e84263d55307 | 528 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 529 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 530 | */ |
AnnaBridge | 167:e84263d55307 | 531 | uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) |
AnnaBridge | 167:e84263d55307 | 532 | { |
AnnaBridge | 167:e84263d55307 | 533 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 534 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 535 | |
AnnaBridge | 167:e84263d55307 | 536 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 537 | sdmmc_cmdinit.Argument = (uint32_t)BlockSize; |
AnnaBridge | 167:e84263d55307 | 538 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; |
AnnaBridge | 167:e84263d55307 | 539 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 540 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 541 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 542 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 543 | |
AnnaBridge | 167:e84263d55307 | 544 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 545 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 546 | |
AnnaBridge | 167:e84263d55307 | 547 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 548 | } |
AnnaBridge | 167:e84263d55307 | 549 | |
AnnaBridge | 167:e84263d55307 | 550 | /** |
AnnaBridge | 167:e84263d55307 | 551 | * @brief Send the Read Single Block command and check the response |
AnnaBridge | 167:e84263d55307 | 552 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 553 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 554 | */ |
AnnaBridge | 167:e84263d55307 | 555 | uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) |
AnnaBridge | 167:e84263d55307 | 556 | { |
AnnaBridge | 167:e84263d55307 | 557 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 558 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 559 | |
AnnaBridge | 167:e84263d55307 | 560 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 561 | sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; |
AnnaBridge | 167:e84263d55307 | 562 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; |
AnnaBridge | 167:e84263d55307 | 563 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 564 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 565 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 566 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 567 | |
AnnaBridge | 167:e84263d55307 | 568 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 569 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 570 | |
AnnaBridge | 167:e84263d55307 | 571 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 572 | } |
AnnaBridge | 167:e84263d55307 | 573 | |
AnnaBridge | 167:e84263d55307 | 574 | /** |
AnnaBridge | 167:e84263d55307 | 575 | * @brief Send the Read Multi Block command and check the response |
AnnaBridge | 167:e84263d55307 | 576 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 577 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 578 | */ |
AnnaBridge | 167:e84263d55307 | 579 | uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) |
AnnaBridge | 167:e84263d55307 | 580 | { |
AnnaBridge | 167:e84263d55307 | 581 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 582 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 583 | |
AnnaBridge | 167:e84263d55307 | 584 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 585 | sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; |
AnnaBridge | 167:e84263d55307 | 586 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; |
AnnaBridge | 167:e84263d55307 | 587 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 588 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 589 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 590 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 591 | |
AnnaBridge | 167:e84263d55307 | 592 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 593 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 594 | |
AnnaBridge | 167:e84263d55307 | 595 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 596 | } |
AnnaBridge | 167:e84263d55307 | 597 | |
AnnaBridge | 167:e84263d55307 | 598 | /** |
AnnaBridge | 167:e84263d55307 | 599 | * @brief Send the Write Single Block command and check the response |
AnnaBridge | 167:e84263d55307 | 600 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 601 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 602 | */ |
AnnaBridge | 167:e84263d55307 | 603 | uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) |
AnnaBridge | 167:e84263d55307 | 604 | { |
AnnaBridge | 167:e84263d55307 | 605 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 606 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 607 | |
AnnaBridge | 167:e84263d55307 | 608 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 609 | sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; |
AnnaBridge | 167:e84263d55307 | 610 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; |
AnnaBridge | 167:e84263d55307 | 611 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 612 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 613 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 614 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 615 | |
AnnaBridge | 167:e84263d55307 | 616 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 617 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 618 | |
AnnaBridge | 167:e84263d55307 | 619 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 620 | } |
AnnaBridge | 167:e84263d55307 | 621 | |
AnnaBridge | 167:e84263d55307 | 622 | /** |
AnnaBridge | 167:e84263d55307 | 623 | * @brief Send the Write Multi Block command and check the response |
AnnaBridge | 167:e84263d55307 | 624 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 625 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 626 | */ |
AnnaBridge | 167:e84263d55307 | 627 | uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) |
AnnaBridge | 167:e84263d55307 | 628 | { |
AnnaBridge | 167:e84263d55307 | 629 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 630 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 631 | |
AnnaBridge | 167:e84263d55307 | 632 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 633 | sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; |
AnnaBridge | 167:e84263d55307 | 634 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; |
AnnaBridge | 167:e84263d55307 | 635 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 636 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 637 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 638 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 639 | |
AnnaBridge | 167:e84263d55307 | 640 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 641 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 642 | |
AnnaBridge | 167:e84263d55307 | 643 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 644 | } |
AnnaBridge | 167:e84263d55307 | 645 | |
AnnaBridge | 167:e84263d55307 | 646 | /** |
AnnaBridge | 167:e84263d55307 | 647 | * @brief Send the Start Address Erase command for SD and check the response |
AnnaBridge | 167:e84263d55307 | 648 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 649 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 650 | */ |
AnnaBridge | 167:e84263d55307 | 651 | uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) |
AnnaBridge | 167:e84263d55307 | 652 | { |
AnnaBridge | 167:e84263d55307 | 653 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 654 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 655 | |
AnnaBridge | 167:e84263d55307 | 656 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 657 | sdmmc_cmdinit.Argument = (uint32_t)StartAdd; |
AnnaBridge | 167:e84263d55307 | 658 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; |
AnnaBridge | 167:e84263d55307 | 659 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 660 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 661 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 662 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 663 | |
AnnaBridge | 167:e84263d55307 | 664 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 665 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 666 | |
AnnaBridge | 167:e84263d55307 | 667 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 668 | } |
AnnaBridge | 167:e84263d55307 | 669 | |
AnnaBridge | 167:e84263d55307 | 670 | /** |
AnnaBridge | 167:e84263d55307 | 671 | * @brief Send the End Address Erase command for SD and check the response |
AnnaBridge | 167:e84263d55307 | 672 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 673 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 674 | */ |
AnnaBridge | 167:e84263d55307 | 675 | uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) |
AnnaBridge | 167:e84263d55307 | 676 | { |
AnnaBridge | 167:e84263d55307 | 677 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 678 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 679 | |
AnnaBridge | 167:e84263d55307 | 680 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 681 | sdmmc_cmdinit.Argument = (uint32_t)EndAdd; |
AnnaBridge | 167:e84263d55307 | 682 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; |
AnnaBridge | 167:e84263d55307 | 683 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 684 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 685 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 686 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 687 | |
AnnaBridge | 167:e84263d55307 | 688 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 689 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 690 | |
AnnaBridge | 167:e84263d55307 | 691 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 692 | } |
AnnaBridge | 167:e84263d55307 | 693 | |
AnnaBridge | 167:e84263d55307 | 694 | /** |
AnnaBridge | 167:e84263d55307 | 695 | * @brief Send the Start Address Erase command and check the response |
AnnaBridge | 167:e84263d55307 | 696 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 697 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 698 | */ |
AnnaBridge | 167:e84263d55307 | 699 | uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) |
AnnaBridge | 167:e84263d55307 | 700 | { |
AnnaBridge | 167:e84263d55307 | 701 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 702 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 703 | |
AnnaBridge | 167:e84263d55307 | 704 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 705 | sdmmc_cmdinit.Argument = (uint32_t)StartAdd; |
AnnaBridge | 167:e84263d55307 | 706 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; |
AnnaBridge | 167:e84263d55307 | 707 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 708 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 709 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 710 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 711 | |
AnnaBridge | 167:e84263d55307 | 712 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 713 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 714 | |
AnnaBridge | 167:e84263d55307 | 715 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 716 | } |
AnnaBridge | 167:e84263d55307 | 717 | |
AnnaBridge | 167:e84263d55307 | 718 | /** |
AnnaBridge | 167:e84263d55307 | 719 | * @brief Send the End Address Erase command and check the response |
AnnaBridge | 167:e84263d55307 | 720 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 721 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 722 | */ |
AnnaBridge | 167:e84263d55307 | 723 | uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) |
AnnaBridge | 167:e84263d55307 | 724 | { |
AnnaBridge | 167:e84263d55307 | 725 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 726 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 727 | |
AnnaBridge | 167:e84263d55307 | 728 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 729 | sdmmc_cmdinit.Argument = (uint32_t)EndAdd; |
AnnaBridge | 167:e84263d55307 | 730 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; |
AnnaBridge | 167:e84263d55307 | 731 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 732 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 733 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 734 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 735 | |
AnnaBridge | 167:e84263d55307 | 736 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 737 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 738 | |
AnnaBridge | 167:e84263d55307 | 739 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 740 | } |
AnnaBridge | 167:e84263d55307 | 741 | |
AnnaBridge | 167:e84263d55307 | 742 | /** |
AnnaBridge | 167:e84263d55307 | 743 | * @brief Send the Erase command and check the response |
AnnaBridge | 167:e84263d55307 | 744 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 745 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 746 | */ |
AnnaBridge | 167:e84263d55307 | 747 | uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 748 | { |
AnnaBridge | 167:e84263d55307 | 749 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 750 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 751 | |
AnnaBridge | 167:e84263d55307 | 752 | /* Set Block Size for Card */ |
AnnaBridge | 167:e84263d55307 | 753 | sdmmc_cmdinit.Argument = 0U; |
AnnaBridge | 167:e84263d55307 | 754 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; |
AnnaBridge | 167:e84263d55307 | 755 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 756 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 757 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 758 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 759 | |
AnnaBridge | 167:e84263d55307 | 760 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 761 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT); |
AnnaBridge | 167:e84263d55307 | 762 | |
AnnaBridge | 167:e84263d55307 | 763 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 764 | } |
AnnaBridge | 167:e84263d55307 | 765 | |
AnnaBridge | 167:e84263d55307 | 766 | /** |
AnnaBridge | 167:e84263d55307 | 767 | * @brief Send the Stop Transfer command and check the response. |
AnnaBridge | 167:e84263d55307 | 768 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 769 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 770 | */ |
AnnaBridge | 167:e84263d55307 | 771 | uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 772 | { |
AnnaBridge | 167:e84263d55307 | 773 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 774 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 775 | |
AnnaBridge | 167:e84263d55307 | 776 | /* Send CMD12 STOP_TRANSMISSION */ |
AnnaBridge | 167:e84263d55307 | 777 | sdmmc_cmdinit.Argument = 0U; |
AnnaBridge | 167:e84263d55307 | 778 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; |
AnnaBridge | 167:e84263d55307 | 779 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 780 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 781 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 782 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 783 | |
AnnaBridge | 167:e84263d55307 | 784 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 785 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, 100000000U); |
AnnaBridge | 167:e84263d55307 | 786 | |
AnnaBridge | 167:e84263d55307 | 787 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 788 | } |
AnnaBridge | 167:e84263d55307 | 789 | |
AnnaBridge | 167:e84263d55307 | 790 | /** |
AnnaBridge | 167:e84263d55307 | 791 | * @brief Send the Select Deselect command and check the response. |
AnnaBridge | 167:e84263d55307 | 792 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 793 | * @param addr: Address of the card to be selected |
AnnaBridge | 167:e84263d55307 | 794 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 795 | */ |
AnnaBridge | 167:e84263d55307 | 796 | uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) |
AnnaBridge | 167:e84263d55307 | 797 | { |
AnnaBridge | 167:e84263d55307 | 798 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 799 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 800 | |
AnnaBridge | 167:e84263d55307 | 801 | /* Send CMD7 SDMMC_SEL_DESEL_CARD */ |
AnnaBridge | 167:e84263d55307 | 802 | sdmmc_cmdinit.Argument = (uint32_t)Addr; |
AnnaBridge | 167:e84263d55307 | 803 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; |
AnnaBridge | 167:e84263d55307 | 804 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 805 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 806 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 807 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 808 | |
AnnaBridge | 167:e84263d55307 | 809 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 810 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 811 | |
AnnaBridge | 167:e84263d55307 | 812 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 813 | } |
AnnaBridge | 167:e84263d55307 | 814 | |
AnnaBridge | 167:e84263d55307 | 815 | /** |
AnnaBridge | 167:e84263d55307 | 816 | * @brief Send the Go Idle State command and check the response. |
AnnaBridge | 167:e84263d55307 | 817 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 818 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 819 | */ |
AnnaBridge | 167:e84263d55307 | 820 | uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 821 | { |
AnnaBridge | 167:e84263d55307 | 822 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 823 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 824 | |
AnnaBridge | 167:e84263d55307 | 825 | sdmmc_cmdinit.Argument = 0U; |
AnnaBridge | 167:e84263d55307 | 826 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; |
AnnaBridge | 167:e84263d55307 | 827 | sdmmc_cmdinit.Response = SDIO_RESPONSE_NO; |
AnnaBridge | 167:e84263d55307 | 828 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 829 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 830 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 831 | |
AnnaBridge | 167:e84263d55307 | 832 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 833 | errorstate = SDMMC_GetCmdError(SDIOx); |
AnnaBridge | 167:e84263d55307 | 834 | |
AnnaBridge | 167:e84263d55307 | 835 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 836 | } |
AnnaBridge | 167:e84263d55307 | 837 | |
AnnaBridge | 167:e84263d55307 | 838 | /** |
AnnaBridge | 167:e84263d55307 | 839 | * @brief Send the Operating Condition command and check the response. |
AnnaBridge | 167:e84263d55307 | 840 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 841 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 842 | */ |
AnnaBridge | 167:e84263d55307 | 843 | uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 844 | { |
AnnaBridge | 167:e84263d55307 | 845 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 846 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 847 | |
AnnaBridge | 167:e84263d55307 | 848 | /* Send CMD8 to verify SD card interface operating condition */ |
AnnaBridge | 167:e84263d55307 | 849 | /* Argument: - [31:12]: Reserved (shall be set to '0') |
AnnaBridge | 167:e84263d55307 | 850 | - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) |
AnnaBridge | 167:e84263d55307 | 851 | - [7:0]: Check Pattern (recommended 0xAA) */ |
AnnaBridge | 167:e84263d55307 | 852 | /* CMD Response: R7 */ |
AnnaBridge | 167:e84263d55307 | 853 | sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; |
AnnaBridge | 167:e84263d55307 | 854 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; |
AnnaBridge | 167:e84263d55307 | 855 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 856 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 857 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 858 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 859 | |
AnnaBridge | 167:e84263d55307 | 860 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 861 | errorstate = SDMMC_GetCmdResp7(SDIOx); |
AnnaBridge | 167:e84263d55307 | 862 | |
AnnaBridge | 167:e84263d55307 | 863 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 864 | } |
AnnaBridge | 167:e84263d55307 | 865 | |
AnnaBridge | 167:e84263d55307 | 866 | /** |
AnnaBridge | 167:e84263d55307 | 867 | * @brief Send the Application command to verify that that the next command |
AnnaBridge | 167:e84263d55307 | 868 | * is an application specific com-mand rather than a standard command |
AnnaBridge | 167:e84263d55307 | 869 | * and check the response. |
AnnaBridge | 167:e84263d55307 | 870 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 871 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 872 | */ |
AnnaBridge | 167:e84263d55307 | 873 | uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) |
AnnaBridge | 167:e84263d55307 | 874 | { |
AnnaBridge | 167:e84263d55307 | 875 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 876 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 877 | |
AnnaBridge | 167:e84263d55307 | 878 | sdmmc_cmdinit.Argument = (uint32_t)Argument; |
AnnaBridge | 167:e84263d55307 | 879 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; |
AnnaBridge | 167:e84263d55307 | 880 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 881 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 882 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 883 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 884 | |
AnnaBridge | 167:e84263d55307 | 885 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 886 | /* If there is a HAL_ERROR, it is a MMC card, else |
AnnaBridge | 167:e84263d55307 | 887 | it is a SD card: SD card 2.0 (voltage range mismatch) |
AnnaBridge | 167:e84263d55307 | 888 | or SD card 1.x */ |
AnnaBridge | 167:e84263d55307 | 889 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 890 | |
AnnaBridge | 167:e84263d55307 | 891 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 892 | } |
AnnaBridge | 167:e84263d55307 | 893 | |
AnnaBridge | 167:e84263d55307 | 894 | /** |
AnnaBridge | 167:e84263d55307 | 895 | * @brief Send the command asking the accessed card to send its operating |
AnnaBridge | 167:e84263d55307 | 896 | * condition register (OCR) |
AnnaBridge | 167:e84263d55307 | 897 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 898 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 899 | */ |
AnnaBridge | 167:e84263d55307 | 900 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType) |
AnnaBridge | 167:e84263d55307 | 901 | { |
AnnaBridge | 167:e84263d55307 | 902 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 903 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 904 | |
AnnaBridge | 167:e84263d55307 | 905 | sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType; |
AnnaBridge | 167:e84263d55307 | 906 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; |
AnnaBridge | 167:e84263d55307 | 907 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 908 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 909 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 910 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 911 | |
AnnaBridge | 167:e84263d55307 | 912 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 913 | errorstate = SDMMC_GetCmdResp3(SDIOx); |
AnnaBridge | 167:e84263d55307 | 914 | |
AnnaBridge | 167:e84263d55307 | 915 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 916 | } |
AnnaBridge | 167:e84263d55307 | 917 | |
AnnaBridge | 167:e84263d55307 | 918 | /** |
AnnaBridge | 167:e84263d55307 | 919 | * @brief Send the Bus Width command and check the response. |
AnnaBridge | 167:e84263d55307 | 920 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 921 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 922 | */ |
AnnaBridge | 167:e84263d55307 | 923 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) |
AnnaBridge | 167:e84263d55307 | 924 | { |
AnnaBridge | 167:e84263d55307 | 925 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 926 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 927 | |
AnnaBridge | 167:e84263d55307 | 928 | sdmmc_cmdinit.Argument = (uint32_t)BusWidth; |
AnnaBridge | 167:e84263d55307 | 929 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; |
AnnaBridge | 167:e84263d55307 | 930 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 931 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 932 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 933 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 934 | |
AnnaBridge | 167:e84263d55307 | 935 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 936 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 937 | |
AnnaBridge | 167:e84263d55307 | 938 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 939 | } |
AnnaBridge | 167:e84263d55307 | 940 | |
AnnaBridge | 167:e84263d55307 | 941 | /** |
AnnaBridge | 167:e84263d55307 | 942 | * @brief Send the Send SCR command and check the response. |
AnnaBridge | 167:e84263d55307 | 943 | * @param SDIOx: Pointer to SDMMC register base |
AnnaBridge | 167:e84263d55307 | 944 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 945 | */ |
AnnaBridge | 167:e84263d55307 | 946 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 947 | { |
AnnaBridge | 167:e84263d55307 | 948 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 949 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 950 | |
AnnaBridge | 167:e84263d55307 | 951 | /* Send CMD51 SD_APP_SEND_SCR */ |
AnnaBridge | 167:e84263d55307 | 952 | sdmmc_cmdinit.Argument = 0U; |
AnnaBridge | 167:e84263d55307 | 953 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; |
AnnaBridge | 167:e84263d55307 | 954 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 955 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 956 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 957 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 958 | |
AnnaBridge | 167:e84263d55307 | 959 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 960 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 961 | |
AnnaBridge | 167:e84263d55307 | 962 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 963 | } |
AnnaBridge | 167:e84263d55307 | 964 | |
AnnaBridge | 167:e84263d55307 | 965 | /** |
AnnaBridge | 167:e84263d55307 | 966 | * @brief Send the Send CID command and check the response. |
AnnaBridge | 167:e84263d55307 | 967 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 968 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 969 | */ |
AnnaBridge | 167:e84263d55307 | 970 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 971 | { |
AnnaBridge | 167:e84263d55307 | 972 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 973 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 974 | |
AnnaBridge | 167:e84263d55307 | 975 | /* Send CMD2 ALL_SEND_CID */ |
AnnaBridge | 167:e84263d55307 | 976 | sdmmc_cmdinit.Argument = 0U; |
AnnaBridge | 167:e84263d55307 | 977 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; |
AnnaBridge | 167:e84263d55307 | 978 | sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; |
AnnaBridge | 167:e84263d55307 | 979 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 980 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 981 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 982 | |
AnnaBridge | 167:e84263d55307 | 983 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 984 | errorstate = SDMMC_GetCmdResp2(SDIOx); |
AnnaBridge | 167:e84263d55307 | 985 | |
AnnaBridge | 167:e84263d55307 | 986 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 987 | } |
AnnaBridge | 167:e84263d55307 | 988 | |
AnnaBridge | 167:e84263d55307 | 989 | /** |
AnnaBridge | 167:e84263d55307 | 990 | * @brief Send the Send CSD command and check the response. |
AnnaBridge | 167:e84263d55307 | 991 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 992 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 993 | */ |
AnnaBridge | 167:e84263d55307 | 994 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) |
AnnaBridge | 167:e84263d55307 | 995 | { |
AnnaBridge | 167:e84263d55307 | 996 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 997 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 998 | |
AnnaBridge | 167:e84263d55307 | 999 | /* Send CMD9 SEND_CSD */ |
AnnaBridge | 167:e84263d55307 | 1000 | sdmmc_cmdinit.Argument = (uint32_t)Argument; |
AnnaBridge | 167:e84263d55307 | 1001 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; |
AnnaBridge | 167:e84263d55307 | 1002 | sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; |
AnnaBridge | 167:e84263d55307 | 1003 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 1004 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 1005 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 1006 | |
AnnaBridge | 167:e84263d55307 | 1007 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 1008 | errorstate = SDMMC_GetCmdResp2(SDIOx); |
AnnaBridge | 167:e84263d55307 | 1009 | |
AnnaBridge | 167:e84263d55307 | 1010 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 1011 | } |
AnnaBridge | 167:e84263d55307 | 1012 | |
AnnaBridge | 167:e84263d55307 | 1013 | /** |
AnnaBridge | 167:e84263d55307 | 1014 | * @brief Send the Send CSD command and check the response. |
AnnaBridge | 167:e84263d55307 | 1015 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 1016 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 1017 | */ |
AnnaBridge | 167:e84263d55307 | 1018 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) |
AnnaBridge | 167:e84263d55307 | 1019 | { |
AnnaBridge | 167:e84263d55307 | 1020 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 1021 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1022 | |
AnnaBridge | 167:e84263d55307 | 1023 | /* Send CMD3 SD_CMD_SET_REL_ADDR */ |
AnnaBridge | 167:e84263d55307 | 1024 | sdmmc_cmdinit.Argument = 0U; |
AnnaBridge | 167:e84263d55307 | 1025 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; |
AnnaBridge | 167:e84263d55307 | 1026 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 1027 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 1028 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 1029 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 1030 | |
AnnaBridge | 167:e84263d55307 | 1031 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 1032 | errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA); |
AnnaBridge | 167:e84263d55307 | 1033 | |
AnnaBridge | 167:e84263d55307 | 1034 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 1035 | } |
AnnaBridge | 167:e84263d55307 | 1036 | |
AnnaBridge | 167:e84263d55307 | 1037 | /** |
AnnaBridge | 167:e84263d55307 | 1038 | * @brief Send the Status command and check the response. |
AnnaBridge | 167:e84263d55307 | 1039 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 1040 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 1041 | */ |
AnnaBridge | 167:e84263d55307 | 1042 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) |
AnnaBridge | 167:e84263d55307 | 1043 | { |
AnnaBridge | 167:e84263d55307 | 1044 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 1045 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1046 | |
AnnaBridge | 167:e84263d55307 | 1047 | sdmmc_cmdinit.Argument = (uint32_t)Argument; |
AnnaBridge | 167:e84263d55307 | 1048 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; |
AnnaBridge | 167:e84263d55307 | 1049 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 1050 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 1051 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 1052 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 1053 | |
AnnaBridge | 167:e84263d55307 | 1054 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 1055 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 1056 | |
AnnaBridge | 167:e84263d55307 | 1057 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 1058 | } |
AnnaBridge | 167:e84263d55307 | 1059 | |
AnnaBridge | 167:e84263d55307 | 1060 | /** |
AnnaBridge | 167:e84263d55307 | 1061 | * @brief Send the Status register command and check the response. |
AnnaBridge | 167:e84263d55307 | 1062 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 1063 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 1064 | */ |
AnnaBridge | 167:e84263d55307 | 1065 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 1066 | { |
AnnaBridge | 167:e84263d55307 | 1067 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 1068 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1069 | |
AnnaBridge | 167:e84263d55307 | 1070 | sdmmc_cmdinit.Argument = 0U; |
AnnaBridge | 167:e84263d55307 | 1071 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; |
AnnaBridge | 167:e84263d55307 | 1072 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 1073 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 1074 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 1075 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 1076 | |
AnnaBridge | 167:e84263d55307 | 1077 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 1078 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 1079 | |
AnnaBridge | 167:e84263d55307 | 1080 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 1081 | } |
AnnaBridge | 167:e84263d55307 | 1082 | |
AnnaBridge | 167:e84263d55307 | 1083 | /** |
AnnaBridge | 167:e84263d55307 | 1084 | * @brief Sends host capacity support information and activates the card's |
AnnaBridge | 167:e84263d55307 | 1085 | * initialization process. Send SDMMC_CMD_SEND_OP_COND command |
AnnaBridge | 167:e84263d55307 | 1086 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 1087 | * @parame Argument: Argument used for the command |
AnnaBridge | 167:e84263d55307 | 1088 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 1089 | */ |
AnnaBridge | 167:e84263d55307 | 1090 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument) |
AnnaBridge | 167:e84263d55307 | 1091 | { |
AnnaBridge | 167:e84263d55307 | 1092 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 1093 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1094 | |
AnnaBridge | 167:e84263d55307 | 1095 | sdmmc_cmdinit.Argument = Argument; |
AnnaBridge | 167:e84263d55307 | 1096 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; |
AnnaBridge | 167:e84263d55307 | 1097 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 1098 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 1099 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 1100 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 1101 | |
AnnaBridge | 167:e84263d55307 | 1102 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 1103 | errorstate = SDMMC_GetCmdResp3(SDIOx); |
AnnaBridge | 167:e84263d55307 | 1104 | |
AnnaBridge | 167:e84263d55307 | 1105 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 1106 | } |
AnnaBridge | 167:e84263d55307 | 1107 | |
AnnaBridge | 167:e84263d55307 | 1108 | /** |
AnnaBridge | 167:e84263d55307 | 1109 | * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand |
AnnaBridge | 167:e84263d55307 | 1110 | * @param SDIOx: Pointer to SDIO register base |
AnnaBridge | 167:e84263d55307 | 1111 | * @parame Argument: Argument used for the command |
AnnaBridge | 167:e84263d55307 | 1112 | * @retval HAL status |
AnnaBridge | 167:e84263d55307 | 1113 | */ |
AnnaBridge | 167:e84263d55307 | 1114 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) |
AnnaBridge | 167:e84263d55307 | 1115 | { |
AnnaBridge | 167:e84263d55307 | 1116 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
AnnaBridge | 167:e84263d55307 | 1117 | uint32_t errorstate = SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1118 | |
AnnaBridge | 167:e84263d55307 | 1119 | sdmmc_cmdinit.Argument = Argument; |
AnnaBridge | 167:e84263d55307 | 1120 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; |
AnnaBridge | 167:e84263d55307 | 1121 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
AnnaBridge | 167:e84263d55307 | 1122 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
AnnaBridge | 167:e84263d55307 | 1123 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
AnnaBridge | 167:e84263d55307 | 1124 | SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
AnnaBridge | 167:e84263d55307 | 1125 | |
AnnaBridge | 167:e84263d55307 | 1126 | /* Check for error conditions */ |
AnnaBridge | 167:e84263d55307 | 1127 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 1128 | |
AnnaBridge | 167:e84263d55307 | 1129 | return errorstate; |
AnnaBridge | 167:e84263d55307 | 1130 | } |
AnnaBridge | 167:e84263d55307 | 1131 | |
AnnaBridge | 167:e84263d55307 | 1132 | /** |
AnnaBridge | 167:e84263d55307 | 1133 | * @} |
AnnaBridge | 167:e84263d55307 | 1134 | */ |
AnnaBridge | 167:e84263d55307 | 1135 | |
AnnaBridge | 167:e84263d55307 | 1136 | /* Private function ----------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 1137 | /** @addtogroup SD_Private_Functions |
AnnaBridge | 167:e84263d55307 | 1138 | * @{ |
AnnaBridge | 167:e84263d55307 | 1139 | */ |
AnnaBridge | 167:e84263d55307 | 1140 | |
AnnaBridge | 167:e84263d55307 | 1141 | /** |
AnnaBridge | 167:e84263d55307 | 1142 | * @brief Checks for error conditions for CMD0. |
AnnaBridge | 167:e84263d55307 | 1143 | * @param hsd: SD handle |
AnnaBridge | 167:e84263d55307 | 1144 | * @retval SD Card error state |
AnnaBridge | 167:e84263d55307 | 1145 | */ |
AnnaBridge | 167:e84263d55307 | 1146 | static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 1147 | { |
AnnaBridge | 167:e84263d55307 | 1148 | /* 8 is the number of required instructions cycles for the below loop statement. |
AnnaBridge | 167:e84263d55307 | 1149 | The SDMMC_CMDTIMEOUT is expressed in ms */ |
AnnaBridge | 167:e84263d55307 | 1150 | register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
AnnaBridge | 167:e84263d55307 | 1151 | |
AnnaBridge | 167:e84263d55307 | 1152 | do |
AnnaBridge | 167:e84263d55307 | 1153 | { |
AnnaBridge | 167:e84263d55307 | 1154 | if (count-- == 0U) |
AnnaBridge | 167:e84263d55307 | 1155 | { |
AnnaBridge | 167:e84263d55307 | 1156 | return SDMMC_ERROR_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1157 | } |
AnnaBridge | 167:e84263d55307 | 1158 | |
AnnaBridge | 167:e84263d55307 | 1159 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); |
AnnaBridge | 167:e84263d55307 | 1160 | |
AnnaBridge | 167:e84263d55307 | 1161 | /* Clear all the static flags */ |
AnnaBridge | 167:e84263d55307 | 1162 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); |
AnnaBridge | 167:e84263d55307 | 1163 | |
AnnaBridge | 167:e84263d55307 | 1164 | return SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1165 | } |
AnnaBridge | 167:e84263d55307 | 1166 | |
AnnaBridge | 167:e84263d55307 | 1167 | /** |
AnnaBridge | 167:e84263d55307 | 1168 | * @brief Checks for error conditions for R1 response. |
AnnaBridge | 167:e84263d55307 | 1169 | * @param hsd: SD handle |
AnnaBridge | 167:e84263d55307 | 1170 | * @param SD_CMD: The sent command index |
AnnaBridge | 167:e84263d55307 | 1171 | * @retval SD Card error state |
AnnaBridge | 167:e84263d55307 | 1172 | */ |
AnnaBridge | 167:e84263d55307 | 1173 | static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) |
AnnaBridge | 167:e84263d55307 | 1174 | { |
AnnaBridge | 167:e84263d55307 | 1175 | uint32_t response_r1; |
AnnaBridge | 167:e84263d55307 | 1176 | |
AnnaBridge | 167:e84263d55307 | 1177 | /* 8 is the number of required instructions cycles for the below loop statement. |
AnnaBridge | 167:e84263d55307 | 1178 | The Timeout is expressed in ms */ |
AnnaBridge | 167:e84263d55307 | 1179 | register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); |
AnnaBridge | 167:e84263d55307 | 1180 | |
AnnaBridge | 167:e84263d55307 | 1181 | do |
AnnaBridge | 167:e84263d55307 | 1182 | { |
AnnaBridge | 167:e84263d55307 | 1183 | if (count-- == 0U) |
AnnaBridge | 167:e84263d55307 | 1184 | { |
AnnaBridge | 167:e84263d55307 | 1185 | return SDMMC_ERROR_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1186 | } |
AnnaBridge | 167:e84263d55307 | 1187 | |
AnnaBridge | 167:e84263d55307 | 1188 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); |
AnnaBridge | 167:e84263d55307 | 1189 | |
AnnaBridge | 167:e84263d55307 | 1190 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
AnnaBridge | 167:e84263d55307 | 1191 | { |
AnnaBridge | 167:e84263d55307 | 1192 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 1193 | |
AnnaBridge | 167:e84263d55307 | 1194 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1195 | } |
AnnaBridge | 167:e84263d55307 | 1196 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
AnnaBridge | 167:e84263d55307 | 1197 | { |
AnnaBridge | 167:e84263d55307 | 1198 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
AnnaBridge | 167:e84263d55307 | 1199 | |
AnnaBridge | 167:e84263d55307 | 1200 | return SDMMC_ERROR_CMD_CRC_FAIL; |
AnnaBridge | 167:e84263d55307 | 1201 | } |
AnnaBridge | 167:e84263d55307 | 1202 | |
AnnaBridge | 167:e84263d55307 | 1203 | /* Check response received is of desired command */ |
AnnaBridge | 167:e84263d55307 | 1204 | if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) |
AnnaBridge | 167:e84263d55307 | 1205 | { |
AnnaBridge | 167:e84263d55307 | 1206 | return SDMMC_ERROR_CMD_CRC_FAIL; |
AnnaBridge | 167:e84263d55307 | 1207 | } |
AnnaBridge | 167:e84263d55307 | 1208 | |
AnnaBridge | 167:e84263d55307 | 1209 | /* Clear all the static flags */ |
AnnaBridge | 167:e84263d55307 | 1210 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); |
AnnaBridge | 167:e84263d55307 | 1211 | |
AnnaBridge | 167:e84263d55307 | 1212 | /* We have received response, retrieve it for analysis */ |
AnnaBridge | 167:e84263d55307 | 1213 | response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); |
AnnaBridge | 167:e84263d55307 | 1214 | |
AnnaBridge | 167:e84263d55307 | 1215 | if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) |
AnnaBridge | 167:e84263d55307 | 1216 | { |
AnnaBridge | 167:e84263d55307 | 1217 | return SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1218 | } |
AnnaBridge | 167:e84263d55307 | 1219 | else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) |
AnnaBridge | 167:e84263d55307 | 1220 | { |
AnnaBridge | 167:e84263d55307 | 1221 | return SDMMC_ERROR_ADDR_OUT_OF_RANGE; |
AnnaBridge | 167:e84263d55307 | 1222 | } |
AnnaBridge | 167:e84263d55307 | 1223 | else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) |
AnnaBridge | 167:e84263d55307 | 1224 | { |
AnnaBridge | 167:e84263d55307 | 1225 | return SDMMC_ERROR_ADDR_MISALIGNED; |
AnnaBridge | 167:e84263d55307 | 1226 | } |
AnnaBridge | 167:e84263d55307 | 1227 | else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) |
AnnaBridge | 167:e84263d55307 | 1228 | { |
AnnaBridge | 167:e84263d55307 | 1229 | return SDMMC_ERROR_BLOCK_LEN_ERR; |
AnnaBridge | 167:e84263d55307 | 1230 | } |
AnnaBridge | 167:e84263d55307 | 1231 | else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) |
AnnaBridge | 167:e84263d55307 | 1232 | { |
AnnaBridge | 167:e84263d55307 | 1233 | return SDMMC_ERROR_ERASE_SEQ_ERR; |
AnnaBridge | 167:e84263d55307 | 1234 | } |
AnnaBridge | 167:e84263d55307 | 1235 | else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) |
AnnaBridge | 167:e84263d55307 | 1236 | { |
AnnaBridge | 167:e84263d55307 | 1237 | return SDMMC_ERROR_BAD_ERASE_PARAM; |
AnnaBridge | 167:e84263d55307 | 1238 | } |
AnnaBridge | 167:e84263d55307 | 1239 | else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) |
AnnaBridge | 167:e84263d55307 | 1240 | { |
AnnaBridge | 167:e84263d55307 | 1241 | return SDMMC_ERROR_WRITE_PROT_VIOLATION; |
AnnaBridge | 167:e84263d55307 | 1242 | } |
AnnaBridge | 167:e84263d55307 | 1243 | else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) |
AnnaBridge | 167:e84263d55307 | 1244 | { |
AnnaBridge | 167:e84263d55307 | 1245 | return SDMMC_ERROR_LOCK_UNLOCK_FAILED; |
AnnaBridge | 167:e84263d55307 | 1246 | } |
AnnaBridge | 167:e84263d55307 | 1247 | else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) |
AnnaBridge | 167:e84263d55307 | 1248 | { |
AnnaBridge | 167:e84263d55307 | 1249 | return SDMMC_ERROR_COM_CRC_FAILED; |
AnnaBridge | 167:e84263d55307 | 1250 | } |
AnnaBridge | 167:e84263d55307 | 1251 | else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) |
AnnaBridge | 167:e84263d55307 | 1252 | { |
AnnaBridge | 167:e84263d55307 | 1253 | return SDMMC_ERROR_ILLEGAL_CMD; |
AnnaBridge | 167:e84263d55307 | 1254 | } |
AnnaBridge | 167:e84263d55307 | 1255 | else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) |
AnnaBridge | 167:e84263d55307 | 1256 | { |
AnnaBridge | 167:e84263d55307 | 1257 | return SDMMC_ERROR_CARD_ECC_FAILED; |
AnnaBridge | 167:e84263d55307 | 1258 | } |
AnnaBridge | 167:e84263d55307 | 1259 | else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) |
AnnaBridge | 167:e84263d55307 | 1260 | { |
AnnaBridge | 167:e84263d55307 | 1261 | return SDMMC_ERROR_CC_ERR; |
AnnaBridge | 167:e84263d55307 | 1262 | } |
AnnaBridge | 167:e84263d55307 | 1263 | else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) |
AnnaBridge | 167:e84263d55307 | 1264 | { |
AnnaBridge | 167:e84263d55307 | 1265 | return SDMMC_ERROR_STREAM_READ_UNDERRUN; |
AnnaBridge | 167:e84263d55307 | 1266 | } |
AnnaBridge | 167:e84263d55307 | 1267 | else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) |
AnnaBridge | 167:e84263d55307 | 1268 | { |
AnnaBridge | 167:e84263d55307 | 1269 | return SDMMC_ERROR_STREAM_WRITE_OVERRUN; |
AnnaBridge | 167:e84263d55307 | 1270 | } |
AnnaBridge | 167:e84263d55307 | 1271 | else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) |
AnnaBridge | 167:e84263d55307 | 1272 | { |
AnnaBridge | 167:e84263d55307 | 1273 | return SDMMC_ERROR_CID_CSD_OVERWRITE; |
AnnaBridge | 167:e84263d55307 | 1274 | } |
AnnaBridge | 167:e84263d55307 | 1275 | else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) |
AnnaBridge | 167:e84263d55307 | 1276 | { |
AnnaBridge | 167:e84263d55307 | 1277 | return SDMMC_ERROR_WP_ERASE_SKIP; |
AnnaBridge | 167:e84263d55307 | 1278 | } |
AnnaBridge | 167:e84263d55307 | 1279 | else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) |
AnnaBridge | 167:e84263d55307 | 1280 | { |
AnnaBridge | 167:e84263d55307 | 1281 | return SDMMC_ERROR_CARD_ECC_DISABLED; |
AnnaBridge | 167:e84263d55307 | 1282 | } |
AnnaBridge | 167:e84263d55307 | 1283 | else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) |
AnnaBridge | 167:e84263d55307 | 1284 | { |
AnnaBridge | 167:e84263d55307 | 1285 | return SDMMC_ERROR_ERASE_RESET; |
AnnaBridge | 167:e84263d55307 | 1286 | } |
AnnaBridge | 167:e84263d55307 | 1287 | else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) |
AnnaBridge | 167:e84263d55307 | 1288 | { |
AnnaBridge | 167:e84263d55307 | 1289 | return SDMMC_ERROR_AKE_SEQ_ERR; |
AnnaBridge | 167:e84263d55307 | 1290 | } |
AnnaBridge | 167:e84263d55307 | 1291 | else |
AnnaBridge | 167:e84263d55307 | 1292 | { |
AnnaBridge | 167:e84263d55307 | 1293 | return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; |
AnnaBridge | 167:e84263d55307 | 1294 | } |
AnnaBridge | 167:e84263d55307 | 1295 | } |
AnnaBridge | 167:e84263d55307 | 1296 | |
AnnaBridge | 167:e84263d55307 | 1297 | /** |
AnnaBridge | 167:e84263d55307 | 1298 | * @brief Checks for error conditions for R2 (CID or CSD) response. |
AnnaBridge | 167:e84263d55307 | 1299 | * @param hsd: SD handle |
AnnaBridge | 167:e84263d55307 | 1300 | * @retval SD Card error state |
AnnaBridge | 167:e84263d55307 | 1301 | */ |
AnnaBridge | 167:e84263d55307 | 1302 | static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 1303 | { |
AnnaBridge | 167:e84263d55307 | 1304 | /* 8 is the number of required instructions cycles for the below loop statement. |
AnnaBridge | 167:e84263d55307 | 1305 | The SDMMC_CMDTIMEOUT is expressed in ms */ |
AnnaBridge | 167:e84263d55307 | 1306 | register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
AnnaBridge | 167:e84263d55307 | 1307 | |
AnnaBridge | 167:e84263d55307 | 1308 | do |
AnnaBridge | 167:e84263d55307 | 1309 | { |
AnnaBridge | 167:e84263d55307 | 1310 | if (count-- == 0U) |
AnnaBridge | 167:e84263d55307 | 1311 | { |
AnnaBridge | 167:e84263d55307 | 1312 | return SDMMC_ERROR_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1313 | } |
AnnaBridge | 167:e84263d55307 | 1314 | |
AnnaBridge | 167:e84263d55307 | 1315 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); |
AnnaBridge | 167:e84263d55307 | 1316 | |
AnnaBridge | 167:e84263d55307 | 1317 | if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
AnnaBridge | 167:e84263d55307 | 1318 | { |
AnnaBridge | 167:e84263d55307 | 1319 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 1320 | |
AnnaBridge | 167:e84263d55307 | 1321 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1322 | } |
AnnaBridge | 167:e84263d55307 | 1323 | else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
AnnaBridge | 167:e84263d55307 | 1324 | { |
AnnaBridge | 167:e84263d55307 | 1325 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
AnnaBridge | 167:e84263d55307 | 1326 | |
AnnaBridge | 167:e84263d55307 | 1327 | return SDMMC_ERROR_CMD_CRC_FAIL; |
AnnaBridge | 167:e84263d55307 | 1328 | } |
AnnaBridge | 167:e84263d55307 | 1329 | else |
AnnaBridge | 167:e84263d55307 | 1330 | { |
AnnaBridge | 167:e84263d55307 | 1331 | /* No error flag set */ |
AnnaBridge | 167:e84263d55307 | 1332 | /* Clear all the static flags */ |
AnnaBridge | 167:e84263d55307 | 1333 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); |
AnnaBridge | 167:e84263d55307 | 1334 | } |
AnnaBridge | 167:e84263d55307 | 1335 | |
AnnaBridge | 167:e84263d55307 | 1336 | return SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1337 | } |
AnnaBridge | 167:e84263d55307 | 1338 | |
AnnaBridge | 167:e84263d55307 | 1339 | /** |
AnnaBridge | 167:e84263d55307 | 1340 | * @brief Checks for error conditions for R3 (OCR) response. |
AnnaBridge | 167:e84263d55307 | 1341 | * @param hsd: SD handle |
AnnaBridge | 167:e84263d55307 | 1342 | * @retval SD Card error state |
AnnaBridge | 167:e84263d55307 | 1343 | */ |
AnnaBridge | 167:e84263d55307 | 1344 | static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 1345 | { |
AnnaBridge | 167:e84263d55307 | 1346 | /* 8 is the number of required instructions cycles for the below loop statement. |
AnnaBridge | 167:e84263d55307 | 1347 | The SDMMC_CMDTIMEOUT is expressed in ms */ |
AnnaBridge | 167:e84263d55307 | 1348 | register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
AnnaBridge | 167:e84263d55307 | 1349 | |
AnnaBridge | 167:e84263d55307 | 1350 | do |
AnnaBridge | 167:e84263d55307 | 1351 | { |
AnnaBridge | 167:e84263d55307 | 1352 | if (count-- == 0U) |
AnnaBridge | 167:e84263d55307 | 1353 | { |
AnnaBridge | 167:e84263d55307 | 1354 | return SDMMC_ERROR_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1355 | } |
AnnaBridge | 167:e84263d55307 | 1356 | |
AnnaBridge | 167:e84263d55307 | 1357 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); |
AnnaBridge | 167:e84263d55307 | 1358 | |
AnnaBridge | 167:e84263d55307 | 1359 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
AnnaBridge | 167:e84263d55307 | 1360 | { |
AnnaBridge | 167:e84263d55307 | 1361 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 1362 | |
AnnaBridge | 167:e84263d55307 | 1363 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1364 | } |
AnnaBridge | 167:e84263d55307 | 1365 | else |
AnnaBridge | 167:e84263d55307 | 1366 | |
AnnaBridge | 167:e84263d55307 | 1367 | { |
AnnaBridge | 167:e84263d55307 | 1368 | /* Clear all the static flags */ |
AnnaBridge | 167:e84263d55307 | 1369 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); |
AnnaBridge | 167:e84263d55307 | 1370 | } |
AnnaBridge | 167:e84263d55307 | 1371 | |
AnnaBridge | 167:e84263d55307 | 1372 | return SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1373 | } |
AnnaBridge | 167:e84263d55307 | 1374 | |
AnnaBridge | 167:e84263d55307 | 1375 | /** |
AnnaBridge | 167:e84263d55307 | 1376 | * @brief Checks for error conditions for R6 (RCA) response. |
AnnaBridge | 167:e84263d55307 | 1377 | * @param hsd: SD handle |
AnnaBridge | 167:e84263d55307 | 1378 | * @param SD_CMD: The sent command index |
AnnaBridge | 167:e84263d55307 | 1379 | * @param pRCA: Pointer to the variable that will contain the SD card relative |
AnnaBridge | 167:e84263d55307 | 1380 | * address RCA |
AnnaBridge | 167:e84263d55307 | 1381 | * @retval SD Card error state |
AnnaBridge | 167:e84263d55307 | 1382 | */ |
AnnaBridge | 167:e84263d55307 | 1383 | static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) |
AnnaBridge | 167:e84263d55307 | 1384 | { |
AnnaBridge | 167:e84263d55307 | 1385 | uint32_t response_r1; |
AnnaBridge | 167:e84263d55307 | 1386 | |
AnnaBridge | 167:e84263d55307 | 1387 | /* 8 is the number of required instructions cycles for the below loop statement. |
AnnaBridge | 167:e84263d55307 | 1388 | The SDMMC_CMDTIMEOUT is expressed in ms */ |
AnnaBridge | 167:e84263d55307 | 1389 | register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
AnnaBridge | 167:e84263d55307 | 1390 | |
AnnaBridge | 167:e84263d55307 | 1391 | do |
AnnaBridge | 167:e84263d55307 | 1392 | { |
AnnaBridge | 167:e84263d55307 | 1393 | if (count-- == 0U) |
AnnaBridge | 167:e84263d55307 | 1394 | { |
AnnaBridge | 167:e84263d55307 | 1395 | return SDMMC_ERROR_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1396 | } |
AnnaBridge | 167:e84263d55307 | 1397 | |
AnnaBridge | 167:e84263d55307 | 1398 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); |
AnnaBridge | 167:e84263d55307 | 1399 | |
AnnaBridge | 167:e84263d55307 | 1400 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
AnnaBridge | 167:e84263d55307 | 1401 | { |
AnnaBridge | 167:e84263d55307 | 1402 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
AnnaBridge | 167:e84263d55307 | 1403 | |
AnnaBridge | 167:e84263d55307 | 1404 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1405 | } |
AnnaBridge | 167:e84263d55307 | 1406 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
AnnaBridge | 167:e84263d55307 | 1407 | { |
AnnaBridge | 167:e84263d55307 | 1408 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
AnnaBridge | 167:e84263d55307 | 1409 | |
AnnaBridge | 167:e84263d55307 | 1410 | return SDMMC_ERROR_CMD_CRC_FAIL; |
AnnaBridge | 167:e84263d55307 | 1411 | } |
AnnaBridge | 167:e84263d55307 | 1412 | |
AnnaBridge | 167:e84263d55307 | 1413 | /* Check response received is of desired command */ |
AnnaBridge | 167:e84263d55307 | 1414 | if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) |
AnnaBridge | 167:e84263d55307 | 1415 | { |
AnnaBridge | 167:e84263d55307 | 1416 | return SDMMC_ERROR_CMD_CRC_FAIL; |
AnnaBridge | 167:e84263d55307 | 1417 | } |
AnnaBridge | 167:e84263d55307 | 1418 | |
AnnaBridge | 167:e84263d55307 | 1419 | /* Clear all the static flags */ |
AnnaBridge | 167:e84263d55307 | 1420 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); |
AnnaBridge | 167:e84263d55307 | 1421 | |
AnnaBridge | 167:e84263d55307 | 1422 | /* We have received response, retrieve it. */ |
AnnaBridge | 167:e84263d55307 | 1423 | response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); |
AnnaBridge | 167:e84263d55307 | 1424 | |
AnnaBridge | 167:e84263d55307 | 1425 | if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) |
AnnaBridge | 167:e84263d55307 | 1426 | { |
AnnaBridge | 167:e84263d55307 | 1427 | *pRCA = (uint16_t) (response_r1 >> 16); |
AnnaBridge | 167:e84263d55307 | 1428 | |
AnnaBridge | 167:e84263d55307 | 1429 | return SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1430 | } |
AnnaBridge | 167:e84263d55307 | 1431 | else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) |
AnnaBridge | 167:e84263d55307 | 1432 | { |
AnnaBridge | 167:e84263d55307 | 1433 | return SDMMC_ERROR_ILLEGAL_CMD; |
AnnaBridge | 167:e84263d55307 | 1434 | } |
AnnaBridge | 167:e84263d55307 | 1435 | else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) |
AnnaBridge | 167:e84263d55307 | 1436 | { |
AnnaBridge | 167:e84263d55307 | 1437 | return SDMMC_ERROR_COM_CRC_FAILED; |
AnnaBridge | 167:e84263d55307 | 1438 | } |
AnnaBridge | 167:e84263d55307 | 1439 | else |
AnnaBridge | 167:e84263d55307 | 1440 | { |
AnnaBridge | 167:e84263d55307 | 1441 | return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; |
AnnaBridge | 167:e84263d55307 | 1442 | } |
AnnaBridge | 167:e84263d55307 | 1443 | } |
AnnaBridge | 167:e84263d55307 | 1444 | |
AnnaBridge | 167:e84263d55307 | 1445 | /** |
AnnaBridge | 167:e84263d55307 | 1446 | * @brief Checks for error conditions for R7 response. |
AnnaBridge | 167:e84263d55307 | 1447 | * @param hsd: SD handle |
AnnaBridge | 167:e84263d55307 | 1448 | * @retval SD Card error state |
AnnaBridge | 167:e84263d55307 | 1449 | */ |
AnnaBridge | 167:e84263d55307 | 1450 | static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) |
AnnaBridge | 167:e84263d55307 | 1451 | { |
AnnaBridge | 167:e84263d55307 | 1452 | /* 8 is the number of required instructions cycles for the below loop statement. |
AnnaBridge | 167:e84263d55307 | 1453 | The SDIO_CMDTIMEOUT is expressed in ms */ |
AnnaBridge | 167:e84263d55307 | 1454 | register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
AnnaBridge | 167:e84263d55307 | 1455 | |
AnnaBridge | 167:e84263d55307 | 1456 | do |
AnnaBridge | 167:e84263d55307 | 1457 | { |
AnnaBridge | 167:e84263d55307 | 1458 | if (count-- == 0U) |
AnnaBridge | 167:e84263d55307 | 1459 | { |
AnnaBridge | 167:e84263d55307 | 1460 | return SDMMC_ERROR_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1461 | } |
AnnaBridge | 167:e84263d55307 | 1462 | |
AnnaBridge | 167:e84263d55307 | 1463 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); |
AnnaBridge | 167:e84263d55307 | 1464 | |
AnnaBridge | 167:e84263d55307 | 1465 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
AnnaBridge | 167:e84263d55307 | 1466 | { |
AnnaBridge | 167:e84263d55307 | 1467 | /* Card is SD V2.0 compliant */ |
AnnaBridge | 167:e84263d55307 | 1468 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); |
AnnaBridge | 167:e84263d55307 | 1469 | |
AnnaBridge | 167:e84263d55307 | 1470 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
AnnaBridge | 167:e84263d55307 | 1471 | } |
AnnaBridge | 167:e84263d55307 | 1472 | |
AnnaBridge | 167:e84263d55307 | 1473 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND)) |
AnnaBridge | 167:e84263d55307 | 1474 | { |
AnnaBridge | 167:e84263d55307 | 1475 | /* Card is SD V2.0 compliant */ |
AnnaBridge | 167:e84263d55307 | 1476 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); |
AnnaBridge | 167:e84263d55307 | 1477 | } |
AnnaBridge | 167:e84263d55307 | 1478 | |
AnnaBridge | 167:e84263d55307 | 1479 | return SDMMC_ERROR_NONE; |
AnnaBridge | 167:e84263d55307 | 1480 | |
AnnaBridge | 167:e84263d55307 | 1481 | } |
AnnaBridge | 167:e84263d55307 | 1482 | |
AnnaBridge | 167:e84263d55307 | 1483 | /** |
AnnaBridge | 167:e84263d55307 | 1484 | * @} |
AnnaBridge | 167:e84263d55307 | 1485 | */ |
AnnaBridge | 167:e84263d55307 | 1486 | |
<> | 144:ef7eb2e8f9f7 | 1487 | /** |
<> | 144:ef7eb2e8f9f7 | 1488 | * @} |
<> | 144:ef7eb2e8f9f7 | 1489 | */ |
<> | 144:ef7eb2e8f9f7 | 1490 | #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ |
<> | 144:ef7eb2e8f9f7 | 1491 | /** |
<> | 144:ef7eb2e8f9f7 | 1492 | * @} |
<> | 144:ef7eb2e8f9f7 | 1493 | */ |
<> | 144:ef7eb2e8f9f7 | 1494 | |
<> | 144:ef7eb2e8f9f7 | 1495 | /** |
<> | 144:ef7eb2e8f9f7 | 1496 | * @} |
<> | 144:ef7eb2e8f9f7 | 1497 | */ |
<> | 144:ef7eb2e8f9f7 | 1498 | |
<> | 144:ef7eb2e8f9f7 | 1499 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |