mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 167:e84263d55307
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 167:e84263d55307 | 1 | /** |
AnnaBridge | 167:e84263d55307 | 2 | ****************************************************************************** |
AnnaBridge | 167:e84263d55307 | 3 | * @file stm32f2xx_ll_cortex.h |
AnnaBridge | 167:e84263d55307 | 4 | * @author MCD Application Team |
AnnaBridge | 167:e84263d55307 | 5 | * @version V1.2.1 |
AnnaBridge | 167:e84263d55307 | 6 | * @date 14-April-2017 |
AnnaBridge | 167:e84263d55307 | 7 | * @brief Header file of CORTEX LL module. |
AnnaBridge | 167:e84263d55307 | 8 | @verbatim |
AnnaBridge | 167:e84263d55307 | 9 | ============================================================================== |
AnnaBridge | 167:e84263d55307 | 10 | ##### How to use this driver ##### |
AnnaBridge | 167:e84263d55307 | 11 | ============================================================================== |
AnnaBridge | 167:e84263d55307 | 12 | [..] |
AnnaBridge | 167:e84263d55307 | 13 | The LL CORTEX driver contains a set of generic APIs that can be |
AnnaBridge | 167:e84263d55307 | 14 | used by user: |
AnnaBridge | 167:e84263d55307 | 15 | (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick |
AnnaBridge | 167:e84263d55307 | 16 | functions |
AnnaBridge | 167:e84263d55307 | 17 | (+) Low power mode configuration (SCB register of Cortex-MCU) |
AnnaBridge | 167:e84263d55307 | 18 | (+) MPU API to configure and enable regions |
AnnaBridge | 167:e84263d55307 | 19 | (MPU services provided only on some devices) |
AnnaBridge | 167:e84263d55307 | 20 | (+) API to access to MCU info (CPUID register) |
AnnaBridge | 167:e84263d55307 | 21 | (+) API to enable fault handler (SHCSR accesses) |
AnnaBridge | 167:e84263d55307 | 22 | |
AnnaBridge | 167:e84263d55307 | 23 | @endverbatim |
AnnaBridge | 167:e84263d55307 | 24 | ****************************************************************************** |
AnnaBridge | 167:e84263d55307 | 25 | * @attention |
AnnaBridge | 167:e84263d55307 | 26 | * |
AnnaBridge | 167:e84263d55307 | 27 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 167:e84263d55307 | 28 | * |
AnnaBridge | 167:e84263d55307 | 29 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 167:e84263d55307 | 30 | * are permitted provided that the following conditions are met: |
AnnaBridge | 167:e84263d55307 | 31 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 167:e84263d55307 | 32 | * this list of conditions and the following disclaimer. |
AnnaBridge | 167:e84263d55307 | 33 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 167:e84263d55307 | 34 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 167:e84263d55307 | 35 | * and/or other materials provided with the distribution. |
AnnaBridge | 167:e84263d55307 | 36 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 167:e84263d55307 | 37 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 167:e84263d55307 | 38 | * without specific prior written permission. |
AnnaBridge | 167:e84263d55307 | 39 | * |
AnnaBridge | 167:e84263d55307 | 40 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 167:e84263d55307 | 41 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 167:e84263d55307 | 42 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 167:e84263d55307 | 43 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 167:e84263d55307 | 44 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 167:e84263d55307 | 45 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 167:e84263d55307 | 46 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 167:e84263d55307 | 47 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 167:e84263d55307 | 48 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 167:e84263d55307 | 49 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 167:e84263d55307 | 50 | * |
AnnaBridge | 167:e84263d55307 | 51 | ****************************************************************************** |
AnnaBridge | 167:e84263d55307 | 52 | */ |
AnnaBridge | 167:e84263d55307 | 53 | |
AnnaBridge | 167:e84263d55307 | 54 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 55 | #ifndef __STM32F2xx_LL_CORTEX_H |
AnnaBridge | 167:e84263d55307 | 56 | #define __STM32F2xx_LL_CORTEX_H |
AnnaBridge | 167:e84263d55307 | 57 | |
AnnaBridge | 167:e84263d55307 | 58 | #ifdef __cplusplus |
AnnaBridge | 167:e84263d55307 | 59 | extern "C" { |
AnnaBridge | 167:e84263d55307 | 60 | #endif |
AnnaBridge | 167:e84263d55307 | 61 | |
AnnaBridge | 167:e84263d55307 | 62 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 63 | #include "stm32f2xx.h" |
AnnaBridge | 167:e84263d55307 | 64 | |
AnnaBridge | 167:e84263d55307 | 65 | /** @addtogroup STM32F2xx_LL_Driver |
AnnaBridge | 167:e84263d55307 | 66 | * @{ |
AnnaBridge | 167:e84263d55307 | 67 | */ |
AnnaBridge | 167:e84263d55307 | 68 | |
AnnaBridge | 167:e84263d55307 | 69 | /** @defgroup CORTEX_LL CORTEX |
AnnaBridge | 167:e84263d55307 | 70 | * @{ |
AnnaBridge | 167:e84263d55307 | 71 | */ |
AnnaBridge | 167:e84263d55307 | 72 | |
AnnaBridge | 167:e84263d55307 | 73 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 74 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 75 | |
AnnaBridge | 167:e84263d55307 | 76 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 77 | |
AnnaBridge | 167:e84263d55307 | 78 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 79 | |
AnnaBridge | 167:e84263d55307 | 80 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 81 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 82 | /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants |
AnnaBridge | 167:e84263d55307 | 83 | * @{ |
AnnaBridge | 167:e84263d55307 | 84 | */ |
AnnaBridge | 167:e84263d55307 | 85 | |
AnnaBridge | 167:e84263d55307 | 86 | /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source |
AnnaBridge | 167:e84263d55307 | 87 | * @{ |
AnnaBridge | 167:e84263d55307 | 88 | */ |
AnnaBridge | 167:e84263d55307 | 89 | #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ |
AnnaBridge | 167:e84263d55307 | 90 | #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ |
AnnaBridge | 167:e84263d55307 | 91 | /** |
AnnaBridge | 167:e84263d55307 | 92 | * @} |
AnnaBridge | 167:e84263d55307 | 93 | */ |
AnnaBridge | 167:e84263d55307 | 94 | |
AnnaBridge | 167:e84263d55307 | 95 | /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type |
AnnaBridge | 167:e84263d55307 | 96 | * @{ |
AnnaBridge | 167:e84263d55307 | 97 | */ |
AnnaBridge | 167:e84263d55307 | 98 | #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ |
AnnaBridge | 167:e84263d55307 | 99 | #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ |
AnnaBridge | 167:e84263d55307 | 100 | #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ |
AnnaBridge | 167:e84263d55307 | 101 | /** |
AnnaBridge | 167:e84263d55307 | 102 | * @} |
AnnaBridge | 167:e84263d55307 | 103 | */ |
AnnaBridge | 167:e84263d55307 | 104 | |
AnnaBridge | 167:e84263d55307 | 105 | #if __MPU_PRESENT |
AnnaBridge | 167:e84263d55307 | 106 | |
AnnaBridge | 167:e84263d55307 | 107 | /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control |
AnnaBridge | 167:e84263d55307 | 108 | * @{ |
AnnaBridge | 167:e84263d55307 | 109 | */ |
AnnaBridge | 167:e84263d55307 | 110 | #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ |
AnnaBridge | 167:e84263d55307 | 111 | #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ |
AnnaBridge | 167:e84263d55307 | 112 | #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ |
AnnaBridge | 167:e84263d55307 | 113 | #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ |
AnnaBridge | 167:e84263d55307 | 114 | /** |
AnnaBridge | 167:e84263d55307 | 115 | * @} |
AnnaBridge | 167:e84263d55307 | 116 | */ |
AnnaBridge | 167:e84263d55307 | 117 | |
AnnaBridge | 167:e84263d55307 | 118 | /** @defgroup CORTEX_LL_EC_REGION MPU Region Number |
AnnaBridge | 167:e84263d55307 | 119 | * @{ |
AnnaBridge | 167:e84263d55307 | 120 | */ |
AnnaBridge | 167:e84263d55307 | 121 | #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ |
AnnaBridge | 167:e84263d55307 | 122 | #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ |
AnnaBridge | 167:e84263d55307 | 123 | #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ |
AnnaBridge | 167:e84263d55307 | 124 | #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ |
AnnaBridge | 167:e84263d55307 | 125 | #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ |
AnnaBridge | 167:e84263d55307 | 126 | #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ |
AnnaBridge | 167:e84263d55307 | 127 | #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ |
AnnaBridge | 167:e84263d55307 | 128 | #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ |
AnnaBridge | 167:e84263d55307 | 129 | /** |
AnnaBridge | 167:e84263d55307 | 130 | * @} |
AnnaBridge | 167:e84263d55307 | 131 | */ |
AnnaBridge | 167:e84263d55307 | 132 | |
AnnaBridge | 167:e84263d55307 | 133 | /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size |
AnnaBridge | 167:e84263d55307 | 134 | * @{ |
AnnaBridge | 167:e84263d55307 | 135 | */ |
AnnaBridge | 167:e84263d55307 | 136 | #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 137 | #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 138 | #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 139 | #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 140 | #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 141 | #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 142 | #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 143 | #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 144 | #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 145 | #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 146 | #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 147 | #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 148 | #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 149 | #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 150 | #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 151 | #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 152 | #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 153 | #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 154 | #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 155 | #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 156 | #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 157 | #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 158 | #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 159 | #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 160 | #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 161 | #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 162 | #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 163 | #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ |
AnnaBridge | 167:e84263d55307 | 164 | /** |
AnnaBridge | 167:e84263d55307 | 165 | * @} |
AnnaBridge | 167:e84263d55307 | 166 | */ |
AnnaBridge | 167:e84263d55307 | 167 | |
AnnaBridge | 167:e84263d55307 | 168 | /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges |
AnnaBridge | 167:e84263d55307 | 169 | * @{ |
AnnaBridge | 167:e84263d55307 | 170 | */ |
AnnaBridge | 167:e84263d55307 | 171 | #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ |
AnnaBridge | 167:e84263d55307 | 172 | #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ |
AnnaBridge | 167:e84263d55307 | 173 | #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ |
AnnaBridge | 167:e84263d55307 | 174 | #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ |
AnnaBridge | 167:e84263d55307 | 175 | #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ |
AnnaBridge | 167:e84263d55307 | 176 | #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ |
AnnaBridge | 167:e84263d55307 | 177 | /** |
AnnaBridge | 167:e84263d55307 | 178 | * @} |
AnnaBridge | 167:e84263d55307 | 179 | */ |
AnnaBridge | 167:e84263d55307 | 180 | |
AnnaBridge | 167:e84263d55307 | 181 | /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level |
AnnaBridge | 167:e84263d55307 | 182 | * @{ |
AnnaBridge | 167:e84263d55307 | 183 | */ |
AnnaBridge | 167:e84263d55307 | 184 | #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ |
AnnaBridge | 167:e84263d55307 | 185 | #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ |
AnnaBridge | 167:e84263d55307 | 186 | #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ |
AnnaBridge | 167:e84263d55307 | 187 | #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ |
AnnaBridge | 167:e84263d55307 | 188 | /** |
AnnaBridge | 167:e84263d55307 | 189 | * @} |
AnnaBridge | 167:e84263d55307 | 190 | */ |
AnnaBridge | 167:e84263d55307 | 191 | |
AnnaBridge | 167:e84263d55307 | 192 | /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access |
AnnaBridge | 167:e84263d55307 | 193 | * @{ |
AnnaBridge | 167:e84263d55307 | 194 | */ |
AnnaBridge | 167:e84263d55307 | 195 | #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ |
AnnaBridge | 167:e84263d55307 | 196 | #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ |
AnnaBridge | 167:e84263d55307 | 197 | /** |
AnnaBridge | 167:e84263d55307 | 198 | * @} |
AnnaBridge | 167:e84263d55307 | 199 | */ |
AnnaBridge | 167:e84263d55307 | 200 | |
AnnaBridge | 167:e84263d55307 | 201 | /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access |
AnnaBridge | 167:e84263d55307 | 202 | * @{ |
AnnaBridge | 167:e84263d55307 | 203 | */ |
AnnaBridge | 167:e84263d55307 | 204 | #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ |
AnnaBridge | 167:e84263d55307 | 205 | #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ |
AnnaBridge | 167:e84263d55307 | 206 | /** |
AnnaBridge | 167:e84263d55307 | 207 | * @} |
AnnaBridge | 167:e84263d55307 | 208 | */ |
AnnaBridge | 167:e84263d55307 | 209 | |
AnnaBridge | 167:e84263d55307 | 210 | /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access |
AnnaBridge | 167:e84263d55307 | 211 | * @{ |
AnnaBridge | 167:e84263d55307 | 212 | */ |
AnnaBridge | 167:e84263d55307 | 213 | #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ |
AnnaBridge | 167:e84263d55307 | 214 | #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ |
AnnaBridge | 167:e84263d55307 | 215 | /** |
AnnaBridge | 167:e84263d55307 | 216 | * @} |
AnnaBridge | 167:e84263d55307 | 217 | */ |
AnnaBridge | 167:e84263d55307 | 218 | |
AnnaBridge | 167:e84263d55307 | 219 | /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access |
AnnaBridge | 167:e84263d55307 | 220 | * @{ |
AnnaBridge | 167:e84263d55307 | 221 | */ |
AnnaBridge | 167:e84263d55307 | 222 | #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ |
AnnaBridge | 167:e84263d55307 | 223 | #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ |
AnnaBridge | 167:e84263d55307 | 224 | /** |
AnnaBridge | 167:e84263d55307 | 225 | * @} |
AnnaBridge | 167:e84263d55307 | 226 | */ |
AnnaBridge | 167:e84263d55307 | 227 | #endif /* __MPU_PRESENT */ |
AnnaBridge | 167:e84263d55307 | 228 | /** |
AnnaBridge | 167:e84263d55307 | 229 | * @} |
AnnaBridge | 167:e84263d55307 | 230 | */ |
AnnaBridge | 167:e84263d55307 | 231 | |
AnnaBridge | 167:e84263d55307 | 232 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 233 | |
AnnaBridge | 167:e84263d55307 | 234 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 235 | /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions |
AnnaBridge | 167:e84263d55307 | 236 | * @{ |
AnnaBridge | 167:e84263d55307 | 237 | */ |
AnnaBridge | 167:e84263d55307 | 238 | |
AnnaBridge | 167:e84263d55307 | 239 | /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK |
AnnaBridge | 167:e84263d55307 | 240 | * @{ |
AnnaBridge | 167:e84263d55307 | 241 | */ |
AnnaBridge | 167:e84263d55307 | 242 | |
AnnaBridge | 167:e84263d55307 | 243 | /** |
AnnaBridge | 167:e84263d55307 | 244 | * @brief This function checks if the Systick counter flag is active or not. |
AnnaBridge | 167:e84263d55307 | 245 | * @note It can be used in timeout function on application side. |
AnnaBridge | 167:e84263d55307 | 246 | * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag |
AnnaBridge | 167:e84263d55307 | 247 | * @retval State of bit (1 or 0). |
AnnaBridge | 167:e84263d55307 | 248 | */ |
AnnaBridge | 167:e84263d55307 | 249 | __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) |
AnnaBridge | 167:e84263d55307 | 250 | { |
AnnaBridge | 167:e84263d55307 | 251 | return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); |
AnnaBridge | 167:e84263d55307 | 252 | } |
AnnaBridge | 167:e84263d55307 | 253 | |
AnnaBridge | 167:e84263d55307 | 254 | /** |
AnnaBridge | 167:e84263d55307 | 255 | * @brief Configures the SysTick clock source |
AnnaBridge | 167:e84263d55307 | 256 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource |
AnnaBridge | 167:e84263d55307 | 257 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 167:e84263d55307 | 258 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
AnnaBridge | 167:e84263d55307 | 259 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
AnnaBridge | 167:e84263d55307 | 260 | * @retval None |
AnnaBridge | 167:e84263d55307 | 261 | */ |
AnnaBridge | 167:e84263d55307 | 262 | __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) |
AnnaBridge | 167:e84263d55307 | 263 | { |
AnnaBridge | 167:e84263d55307 | 264 | if (Source == LL_SYSTICK_CLKSOURCE_HCLK) |
AnnaBridge | 167:e84263d55307 | 265 | { |
AnnaBridge | 167:e84263d55307 | 266 | SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
AnnaBridge | 167:e84263d55307 | 267 | } |
AnnaBridge | 167:e84263d55307 | 268 | else |
AnnaBridge | 167:e84263d55307 | 269 | { |
AnnaBridge | 167:e84263d55307 | 270 | CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
AnnaBridge | 167:e84263d55307 | 271 | } |
AnnaBridge | 167:e84263d55307 | 272 | } |
AnnaBridge | 167:e84263d55307 | 273 | |
AnnaBridge | 167:e84263d55307 | 274 | /** |
AnnaBridge | 167:e84263d55307 | 275 | * @brief Get the SysTick clock source |
AnnaBridge | 167:e84263d55307 | 276 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource |
AnnaBridge | 167:e84263d55307 | 277 | * @retval Returned value can be one of the following values: |
AnnaBridge | 167:e84263d55307 | 278 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
AnnaBridge | 167:e84263d55307 | 279 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
AnnaBridge | 167:e84263d55307 | 280 | */ |
AnnaBridge | 167:e84263d55307 | 281 | __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) |
AnnaBridge | 167:e84263d55307 | 282 | { |
AnnaBridge | 167:e84263d55307 | 283 | return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
AnnaBridge | 167:e84263d55307 | 284 | } |
AnnaBridge | 167:e84263d55307 | 285 | |
AnnaBridge | 167:e84263d55307 | 286 | /** |
AnnaBridge | 167:e84263d55307 | 287 | * @brief Enable SysTick exception request |
AnnaBridge | 167:e84263d55307 | 288 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT |
AnnaBridge | 167:e84263d55307 | 289 | * @retval None |
AnnaBridge | 167:e84263d55307 | 290 | */ |
AnnaBridge | 167:e84263d55307 | 291 | __STATIC_INLINE void LL_SYSTICK_EnableIT(void) |
AnnaBridge | 167:e84263d55307 | 292 | { |
AnnaBridge | 167:e84263d55307 | 293 | SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
AnnaBridge | 167:e84263d55307 | 294 | } |
AnnaBridge | 167:e84263d55307 | 295 | |
AnnaBridge | 167:e84263d55307 | 296 | /** |
AnnaBridge | 167:e84263d55307 | 297 | * @brief Disable SysTick exception request |
AnnaBridge | 167:e84263d55307 | 298 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT |
AnnaBridge | 167:e84263d55307 | 299 | * @retval None |
AnnaBridge | 167:e84263d55307 | 300 | */ |
AnnaBridge | 167:e84263d55307 | 301 | __STATIC_INLINE void LL_SYSTICK_DisableIT(void) |
AnnaBridge | 167:e84263d55307 | 302 | { |
AnnaBridge | 167:e84263d55307 | 303 | CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
AnnaBridge | 167:e84263d55307 | 304 | } |
AnnaBridge | 167:e84263d55307 | 305 | |
AnnaBridge | 167:e84263d55307 | 306 | /** |
AnnaBridge | 167:e84263d55307 | 307 | * @brief Checks if the SYSTICK interrupt is enabled or disabled. |
AnnaBridge | 167:e84263d55307 | 308 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT |
AnnaBridge | 167:e84263d55307 | 309 | * @retval State of bit (1 or 0). |
AnnaBridge | 167:e84263d55307 | 310 | */ |
AnnaBridge | 167:e84263d55307 | 311 | __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) |
AnnaBridge | 167:e84263d55307 | 312 | { |
AnnaBridge | 167:e84263d55307 | 313 | return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); |
AnnaBridge | 167:e84263d55307 | 314 | } |
AnnaBridge | 167:e84263d55307 | 315 | |
AnnaBridge | 167:e84263d55307 | 316 | /** |
AnnaBridge | 167:e84263d55307 | 317 | * @} |
AnnaBridge | 167:e84263d55307 | 318 | */ |
AnnaBridge | 167:e84263d55307 | 319 | |
AnnaBridge | 167:e84263d55307 | 320 | /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE |
AnnaBridge | 167:e84263d55307 | 321 | * @{ |
AnnaBridge | 167:e84263d55307 | 322 | */ |
AnnaBridge | 167:e84263d55307 | 323 | |
AnnaBridge | 167:e84263d55307 | 324 | /** |
AnnaBridge | 167:e84263d55307 | 325 | * @brief Processor uses sleep as its low power mode |
AnnaBridge | 167:e84263d55307 | 326 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep |
AnnaBridge | 167:e84263d55307 | 327 | * @retval None |
AnnaBridge | 167:e84263d55307 | 328 | */ |
AnnaBridge | 167:e84263d55307 | 329 | __STATIC_INLINE void LL_LPM_EnableSleep(void) |
AnnaBridge | 167:e84263d55307 | 330 | { |
AnnaBridge | 167:e84263d55307 | 331 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
AnnaBridge | 167:e84263d55307 | 332 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
AnnaBridge | 167:e84263d55307 | 333 | } |
AnnaBridge | 167:e84263d55307 | 334 | |
AnnaBridge | 167:e84263d55307 | 335 | /** |
AnnaBridge | 167:e84263d55307 | 336 | * @brief Processor uses deep sleep as its low power mode |
AnnaBridge | 167:e84263d55307 | 337 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep |
AnnaBridge | 167:e84263d55307 | 338 | * @retval None |
AnnaBridge | 167:e84263d55307 | 339 | */ |
AnnaBridge | 167:e84263d55307 | 340 | __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) |
AnnaBridge | 167:e84263d55307 | 341 | { |
AnnaBridge | 167:e84263d55307 | 342 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
AnnaBridge | 167:e84263d55307 | 343 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
AnnaBridge | 167:e84263d55307 | 344 | } |
AnnaBridge | 167:e84263d55307 | 345 | |
AnnaBridge | 167:e84263d55307 | 346 | /** |
AnnaBridge | 167:e84263d55307 | 347 | * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. |
AnnaBridge | 167:e84263d55307 | 348 | * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an |
AnnaBridge | 167:e84263d55307 | 349 | * empty main application. |
AnnaBridge | 167:e84263d55307 | 350 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit |
AnnaBridge | 167:e84263d55307 | 351 | * @retval None |
AnnaBridge | 167:e84263d55307 | 352 | */ |
AnnaBridge | 167:e84263d55307 | 353 | __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) |
AnnaBridge | 167:e84263d55307 | 354 | { |
AnnaBridge | 167:e84263d55307 | 355 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
AnnaBridge | 167:e84263d55307 | 356 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
AnnaBridge | 167:e84263d55307 | 357 | } |
AnnaBridge | 167:e84263d55307 | 358 | |
AnnaBridge | 167:e84263d55307 | 359 | /** |
AnnaBridge | 167:e84263d55307 | 360 | * @brief Do not sleep when returning to Thread mode. |
AnnaBridge | 167:e84263d55307 | 361 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit |
AnnaBridge | 167:e84263d55307 | 362 | * @retval None |
AnnaBridge | 167:e84263d55307 | 363 | */ |
AnnaBridge | 167:e84263d55307 | 364 | __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) |
AnnaBridge | 167:e84263d55307 | 365 | { |
AnnaBridge | 167:e84263d55307 | 366 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
AnnaBridge | 167:e84263d55307 | 367 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
AnnaBridge | 167:e84263d55307 | 368 | } |
AnnaBridge | 167:e84263d55307 | 369 | |
AnnaBridge | 167:e84263d55307 | 370 | /** |
AnnaBridge | 167:e84263d55307 | 371 | * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the |
AnnaBridge | 167:e84263d55307 | 372 | * processor. |
AnnaBridge | 167:e84263d55307 | 373 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend |
AnnaBridge | 167:e84263d55307 | 374 | * @retval None |
AnnaBridge | 167:e84263d55307 | 375 | */ |
AnnaBridge | 167:e84263d55307 | 376 | __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) |
AnnaBridge | 167:e84263d55307 | 377 | { |
AnnaBridge | 167:e84263d55307 | 378 | /* Set SEVEONPEND bit of Cortex System Control Register */ |
AnnaBridge | 167:e84263d55307 | 379 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
AnnaBridge | 167:e84263d55307 | 380 | } |
AnnaBridge | 167:e84263d55307 | 381 | |
AnnaBridge | 167:e84263d55307 | 382 | /** |
AnnaBridge | 167:e84263d55307 | 383 | * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are |
AnnaBridge | 167:e84263d55307 | 384 | * excluded |
AnnaBridge | 167:e84263d55307 | 385 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend |
AnnaBridge | 167:e84263d55307 | 386 | * @retval None |
AnnaBridge | 167:e84263d55307 | 387 | */ |
AnnaBridge | 167:e84263d55307 | 388 | __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) |
AnnaBridge | 167:e84263d55307 | 389 | { |
AnnaBridge | 167:e84263d55307 | 390 | /* Clear SEVEONPEND bit of Cortex System Control Register */ |
AnnaBridge | 167:e84263d55307 | 391 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
AnnaBridge | 167:e84263d55307 | 392 | } |
AnnaBridge | 167:e84263d55307 | 393 | |
AnnaBridge | 167:e84263d55307 | 394 | /** |
AnnaBridge | 167:e84263d55307 | 395 | * @} |
AnnaBridge | 167:e84263d55307 | 396 | */ |
AnnaBridge | 167:e84263d55307 | 397 | |
AnnaBridge | 167:e84263d55307 | 398 | /** @defgroup CORTEX_LL_EF_HANDLER HANDLER |
AnnaBridge | 167:e84263d55307 | 399 | * @{ |
AnnaBridge | 167:e84263d55307 | 400 | */ |
AnnaBridge | 167:e84263d55307 | 401 | |
AnnaBridge | 167:e84263d55307 | 402 | /** |
AnnaBridge | 167:e84263d55307 | 403 | * @brief Enable a fault in System handler control register (SHCSR) |
AnnaBridge | 167:e84263d55307 | 404 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault |
AnnaBridge | 167:e84263d55307 | 405 | * @param Fault This parameter can be a combination of the following values: |
AnnaBridge | 167:e84263d55307 | 406 | * @arg @ref LL_HANDLER_FAULT_USG |
AnnaBridge | 167:e84263d55307 | 407 | * @arg @ref LL_HANDLER_FAULT_BUS |
AnnaBridge | 167:e84263d55307 | 408 | * @arg @ref LL_HANDLER_FAULT_MEM |
AnnaBridge | 167:e84263d55307 | 409 | * @retval None |
AnnaBridge | 167:e84263d55307 | 410 | */ |
AnnaBridge | 167:e84263d55307 | 411 | __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) |
AnnaBridge | 167:e84263d55307 | 412 | { |
AnnaBridge | 167:e84263d55307 | 413 | /* Enable the system handler fault */ |
AnnaBridge | 167:e84263d55307 | 414 | SET_BIT(SCB->SHCSR, Fault); |
AnnaBridge | 167:e84263d55307 | 415 | } |
AnnaBridge | 167:e84263d55307 | 416 | |
AnnaBridge | 167:e84263d55307 | 417 | /** |
AnnaBridge | 167:e84263d55307 | 418 | * @brief Disable a fault in System handler control register (SHCSR) |
AnnaBridge | 167:e84263d55307 | 419 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault |
AnnaBridge | 167:e84263d55307 | 420 | * @param Fault This parameter can be a combination of the following values: |
AnnaBridge | 167:e84263d55307 | 421 | * @arg @ref LL_HANDLER_FAULT_USG |
AnnaBridge | 167:e84263d55307 | 422 | * @arg @ref LL_HANDLER_FAULT_BUS |
AnnaBridge | 167:e84263d55307 | 423 | * @arg @ref LL_HANDLER_FAULT_MEM |
AnnaBridge | 167:e84263d55307 | 424 | * @retval None |
AnnaBridge | 167:e84263d55307 | 425 | */ |
AnnaBridge | 167:e84263d55307 | 426 | __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) |
AnnaBridge | 167:e84263d55307 | 427 | { |
AnnaBridge | 167:e84263d55307 | 428 | /* Disable the system handler fault */ |
AnnaBridge | 167:e84263d55307 | 429 | CLEAR_BIT(SCB->SHCSR, Fault); |
AnnaBridge | 167:e84263d55307 | 430 | } |
AnnaBridge | 167:e84263d55307 | 431 | |
AnnaBridge | 167:e84263d55307 | 432 | /** |
AnnaBridge | 167:e84263d55307 | 433 | * @} |
AnnaBridge | 167:e84263d55307 | 434 | */ |
AnnaBridge | 167:e84263d55307 | 435 | |
AnnaBridge | 167:e84263d55307 | 436 | /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO |
AnnaBridge | 167:e84263d55307 | 437 | * @{ |
AnnaBridge | 167:e84263d55307 | 438 | */ |
AnnaBridge | 167:e84263d55307 | 439 | |
AnnaBridge | 167:e84263d55307 | 440 | /** |
AnnaBridge | 167:e84263d55307 | 441 | * @brief Get Implementer code |
AnnaBridge | 167:e84263d55307 | 442 | * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer |
AnnaBridge | 167:e84263d55307 | 443 | * @retval Value should be equal to 0x41 for ARM |
AnnaBridge | 167:e84263d55307 | 444 | */ |
AnnaBridge | 167:e84263d55307 | 445 | __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) |
AnnaBridge | 167:e84263d55307 | 446 | { |
AnnaBridge | 167:e84263d55307 | 447 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); |
AnnaBridge | 167:e84263d55307 | 448 | } |
AnnaBridge | 167:e84263d55307 | 449 | |
AnnaBridge | 167:e84263d55307 | 450 | /** |
AnnaBridge | 167:e84263d55307 | 451 | * @brief Get Variant number (The r value in the rnpn product revision identifier) |
AnnaBridge | 167:e84263d55307 | 452 | * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant |
AnnaBridge | 167:e84263d55307 | 453 | * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2) |
AnnaBridge | 167:e84263d55307 | 454 | */ |
AnnaBridge | 167:e84263d55307 | 455 | __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) |
AnnaBridge | 167:e84263d55307 | 456 | { |
AnnaBridge | 167:e84263d55307 | 457 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); |
AnnaBridge | 167:e84263d55307 | 458 | } |
AnnaBridge | 167:e84263d55307 | 459 | |
AnnaBridge | 167:e84263d55307 | 460 | /** |
AnnaBridge | 167:e84263d55307 | 461 | * @brief Get Constant number |
AnnaBridge | 167:e84263d55307 | 462 | * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant |
AnnaBridge | 167:e84263d55307 | 463 | * @retval Value should be equal to 0xF for Cortex-M3 devices |
AnnaBridge | 167:e84263d55307 | 464 | */ |
AnnaBridge | 167:e84263d55307 | 465 | __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) |
AnnaBridge | 167:e84263d55307 | 466 | { |
AnnaBridge | 167:e84263d55307 | 467 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); |
AnnaBridge | 167:e84263d55307 | 468 | } |
AnnaBridge | 167:e84263d55307 | 469 | |
AnnaBridge | 167:e84263d55307 | 470 | /** |
AnnaBridge | 167:e84263d55307 | 471 | * @brief Get Part number |
AnnaBridge | 167:e84263d55307 | 472 | * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo |
AnnaBridge | 167:e84263d55307 | 473 | * @retval Value should be equal to 0xC23 for Cortex-M3 |
AnnaBridge | 167:e84263d55307 | 474 | */ |
AnnaBridge | 167:e84263d55307 | 475 | __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) |
AnnaBridge | 167:e84263d55307 | 476 | { |
AnnaBridge | 167:e84263d55307 | 477 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); |
AnnaBridge | 167:e84263d55307 | 478 | } |
AnnaBridge | 167:e84263d55307 | 479 | |
AnnaBridge | 167:e84263d55307 | 480 | /** |
AnnaBridge | 167:e84263d55307 | 481 | * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) |
AnnaBridge | 167:e84263d55307 | 482 | * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision |
AnnaBridge | 167:e84263d55307 | 483 | * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1) |
AnnaBridge | 167:e84263d55307 | 484 | */ |
AnnaBridge | 167:e84263d55307 | 485 | __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) |
AnnaBridge | 167:e84263d55307 | 486 | { |
AnnaBridge | 167:e84263d55307 | 487 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); |
AnnaBridge | 167:e84263d55307 | 488 | } |
AnnaBridge | 167:e84263d55307 | 489 | |
AnnaBridge | 167:e84263d55307 | 490 | /** |
AnnaBridge | 167:e84263d55307 | 491 | * @} |
AnnaBridge | 167:e84263d55307 | 492 | */ |
AnnaBridge | 167:e84263d55307 | 493 | |
AnnaBridge | 167:e84263d55307 | 494 | #if __MPU_PRESENT |
AnnaBridge | 167:e84263d55307 | 495 | /** @defgroup CORTEX_LL_EF_MPU MPU |
AnnaBridge | 167:e84263d55307 | 496 | * @{ |
AnnaBridge | 167:e84263d55307 | 497 | */ |
AnnaBridge | 167:e84263d55307 | 498 | |
AnnaBridge | 167:e84263d55307 | 499 | /** |
AnnaBridge | 167:e84263d55307 | 500 | * @brief Enable MPU with input options |
AnnaBridge | 167:e84263d55307 | 501 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable |
AnnaBridge | 167:e84263d55307 | 502 | * @param Options This parameter can be one of the following values: |
AnnaBridge | 167:e84263d55307 | 503 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE |
AnnaBridge | 167:e84263d55307 | 504 | * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI |
AnnaBridge | 167:e84263d55307 | 505 | * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT |
AnnaBridge | 167:e84263d55307 | 506 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF |
AnnaBridge | 167:e84263d55307 | 507 | * @retval None |
AnnaBridge | 167:e84263d55307 | 508 | */ |
AnnaBridge | 167:e84263d55307 | 509 | __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) |
AnnaBridge | 167:e84263d55307 | 510 | { |
AnnaBridge | 167:e84263d55307 | 511 | /* Enable the MPU*/ |
AnnaBridge | 167:e84263d55307 | 512 | WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); |
AnnaBridge | 167:e84263d55307 | 513 | /* Ensure MPU settings take effects */ |
AnnaBridge | 167:e84263d55307 | 514 | __DSB(); |
AnnaBridge | 167:e84263d55307 | 515 | /* Sequence instruction fetches using update settings */ |
AnnaBridge | 167:e84263d55307 | 516 | __ISB(); |
AnnaBridge | 167:e84263d55307 | 517 | } |
AnnaBridge | 167:e84263d55307 | 518 | |
AnnaBridge | 167:e84263d55307 | 519 | /** |
AnnaBridge | 167:e84263d55307 | 520 | * @brief Disable MPU |
AnnaBridge | 167:e84263d55307 | 521 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable |
AnnaBridge | 167:e84263d55307 | 522 | * @retval None |
AnnaBridge | 167:e84263d55307 | 523 | */ |
AnnaBridge | 167:e84263d55307 | 524 | __STATIC_INLINE void LL_MPU_Disable(void) |
AnnaBridge | 167:e84263d55307 | 525 | { |
AnnaBridge | 167:e84263d55307 | 526 | /* Make sure outstanding transfers are done */ |
AnnaBridge | 167:e84263d55307 | 527 | __DMB(); |
AnnaBridge | 167:e84263d55307 | 528 | /* Disable MPU*/ |
AnnaBridge | 167:e84263d55307 | 529 | WRITE_REG(MPU->CTRL, 0U); |
AnnaBridge | 167:e84263d55307 | 530 | } |
AnnaBridge | 167:e84263d55307 | 531 | |
AnnaBridge | 167:e84263d55307 | 532 | /** |
AnnaBridge | 167:e84263d55307 | 533 | * @brief Check if MPU is enabled or not |
AnnaBridge | 167:e84263d55307 | 534 | * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled |
AnnaBridge | 167:e84263d55307 | 535 | * @retval State of bit (1 or 0). |
AnnaBridge | 167:e84263d55307 | 536 | */ |
AnnaBridge | 167:e84263d55307 | 537 | __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) |
AnnaBridge | 167:e84263d55307 | 538 | { |
AnnaBridge | 167:e84263d55307 | 539 | return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); |
AnnaBridge | 167:e84263d55307 | 540 | } |
AnnaBridge | 167:e84263d55307 | 541 | |
AnnaBridge | 167:e84263d55307 | 542 | /** |
AnnaBridge | 167:e84263d55307 | 543 | * @brief Enable a MPU region |
AnnaBridge | 167:e84263d55307 | 544 | * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion |
AnnaBridge | 167:e84263d55307 | 545 | * @param Region This parameter can be one of the following values: |
AnnaBridge | 167:e84263d55307 | 546 | * @arg @ref LL_MPU_REGION_NUMBER0 |
AnnaBridge | 167:e84263d55307 | 547 | * @arg @ref LL_MPU_REGION_NUMBER1 |
AnnaBridge | 167:e84263d55307 | 548 | * @arg @ref LL_MPU_REGION_NUMBER2 |
AnnaBridge | 167:e84263d55307 | 549 | * @arg @ref LL_MPU_REGION_NUMBER3 |
AnnaBridge | 167:e84263d55307 | 550 | * @arg @ref LL_MPU_REGION_NUMBER4 |
AnnaBridge | 167:e84263d55307 | 551 | * @arg @ref LL_MPU_REGION_NUMBER5 |
AnnaBridge | 167:e84263d55307 | 552 | * @arg @ref LL_MPU_REGION_NUMBER6 |
AnnaBridge | 167:e84263d55307 | 553 | * @arg @ref LL_MPU_REGION_NUMBER7 |
AnnaBridge | 167:e84263d55307 | 554 | * @retval None |
AnnaBridge | 167:e84263d55307 | 555 | */ |
AnnaBridge | 167:e84263d55307 | 556 | __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) |
AnnaBridge | 167:e84263d55307 | 557 | { |
AnnaBridge | 167:e84263d55307 | 558 | /* Set Region number */ |
AnnaBridge | 167:e84263d55307 | 559 | WRITE_REG(MPU->RNR, Region); |
AnnaBridge | 167:e84263d55307 | 560 | /* Enable the MPU region */ |
AnnaBridge | 167:e84263d55307 | 561 | SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
AnnaBridge | 167:e84263d55307 | 562 | } |
AnnaBridge | 167:e84263d55307 | 563 | |
AnnaBridge | 167:e84263d55307 | 564 | /** |
AnnaBridge | 167:e84263d55307 | 565 | * @brief Configure and enable a region |
AnnaBridge | 167:e84263d55307 | 566 | * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 567 | * MPU_RBAR REGION LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 568 | * MPU_RBAR ADDR LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 569 | * MPU_RASR XN LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 570 | * MPU_RASR AP LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 571 | * MPU_RASR S LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 572 | * MPU_RASR C LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 573 | * MPU_RASR B LL_MPU_ConfigRegion\n |
AnnaBridge | 167:e84263d55307 | 574 | * MPU_RASR SIZE LL_MPU_ConfigRegion |
AnnaBridge | 167:e84263d55307 | 575 | * @param Region This parameter can be one of the following values: |
AnnaBridge | 167:e84263d55307 | 576 | * @arg @ref LL_MPU_REGION_NUMBER0 |
AnnaBridge | 167:e84263d55307 | 577 | * @arg @ref LL_MPU_REGION_NUMBER1 |
AnnaBridge | 167:e84263d55307 | 578 | * @arg @ref LL_MPU_REGION_NUMBER2 |
AnnaBridge | 167:e84263d55307 | 579 | * @arg @ref LL_MPU_REGION_NUMBER3 |
AnnaBridge | 167:e84263d55307 | 580 | * @arg @ref LL_MPU_REGION_NUMBER4 |
AnnaBridge | 167:e84263d55307 | 581 | * @arg @ref LL_MPU_REGION_NUMBER5 |
AnnaBridge | 167:e84263d55307 | 582 | * @arg @ref LL_MPU_REGION_NUMBER6 |
AnnaBridge | 167:e84263d55307 | 583 | * @arg @ref LL_MPU_REGION_NUMBER7 |
AnnaBridge | 167:e84263d55307 | 584 | * @param Address Value of region base address |
AnnaBridge | 167:e84263d55307 | 585 | * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 167:e84263d55307 | 586 | * @param Attributes This parameter can be a combination of the following values: |
AnnaBridge | 167:e84263d55307 | 587 | * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B |
AnnaBridge | 167:e84263d55307 | 588 | * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB |
AnnaBridge | 167:e84263d55307 | 589 | * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB |
AnnaBridge | 167:e84263d55307 | 590 | * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB |
AnnaBridge | 167:e84263d55307 | 591 | * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB |
AnnaBridge | 167:e84263d55307 | 592 | * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB |
AnnaBridge | 167:e84263d55307 | 593 | * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS |
AnnaBridge | 167:e84263d55307 | 594 | * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO |
AnnaBridge | 167:e84263d55307 | 595 | * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 |
AnnaBridge | 167:e84263d55307 | 596 | * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE |
AnnaBridge | 167:e84263d55307 | 597 | * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE |
AnnaBridge | 167:e84263d55307 | 598 | * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE |
AnnaBridge | 167:e84263d55307 | 599 | * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE |
AnnaBridge | 167:e84263d55307 | 600 | * @retval None |
AnnaBridge | 167:e84263d55307 | 601 | */ |
AnnaBridge | 167:e84263d55307 | 602 | __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) |
AnnaBridge | 167:e84263d55307 | 603 | { |
AnnaBridge | 167:e84263d55307 | 604 | /* Set Region number */ |
AnnaBridge | 167:e84263d55307 | 605 | WRITE_REG(MPU->RNR, Region); |
AnnaBridge | 167:e84263d55307 | 606 | /* Set base address */ |
AnnaBridge | 167:e84263d55307 | 607 | WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); |
AnnaBridge | 167:e84263d55307 | 608 | /* Configure MPU */ |
AnnaBridge | 167:e84263d55307 | 609 | WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); |
AnnaBridge | 167:e84263d55307 | 610 | } |
AnnaBridge | 167:e84263d55307 | 611 | |
AnnaBridge | 167:e84263d55307 | 612 | /** |
AnnaBridge | 167:e84263d55307 | 613 | * @brief Disable a region |
AnnaBridge | 167:e84263d55307 | 614 | * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n |
AnnaBridge | 167:e84263d55307 | 615 | * MPU_RASR ENABLE LL_MPU_DisableRegion |
AnnaBridge | 167:e84263d55307 | 616 | * @param Region This parameter can be one of the following values: |
AnnaBridge | 167:e84263d55307 | 617 | * @arg @ref LL_MPU_REGION_NUMBER0 |
AnnaBridge | 167:e84263d55307 | 618 | * @arg @ref LL_MPU_REGION_NUMBER1 |
AnnaBridge | 167:e84263d55307 | 619 | * @arg @ref LL_MPU_REGION_NUMBER2 |
AnnaBridge | 167:e84263d55307 | 620 | * @arg @ref LL_MPU_REGION_NUMBER3 |
AnnaBridge | 167:e84263d55307 | 621 | * @arg @ref LL_MPU_REGION_NUMBER4 |
AnnaBridge | 167:e84263d55307 | 622 | * @arg @ref LL_MPU_REGION_NUMBER5 |
AnnaBridge | 167:e84263d55307 | 623 | * @arg @ref LL_MPU_REGION_NUMBER6 |
AnnaBridge | 167:e84263d55307 | 624 | * @arg @ref LL_MPU_REGION_NUMBER7 |
AnnaBridge | 167:e84263d55307 | 625 | * @retval None |
AnnaBridge | 167:e84263d55307 | 626 | */ |
AnnaBridge | 167:e84263d55307 | 627 | __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) |
AnnaBridge | 167:e84263d55307 | 628 | { |
AnnaBridge | 167:e84263d55307 | 629 | /* Set Region number */ |
AnnaBridge | 167:e84263d55307 | 630 | WRITE_REG(MPU->RNR, Region); |
AnnaBridge | 167:e84263d55307 | 631 | /* Disable the MPU region */ |
AnnaBridge | 167:e84263d55307 | 632 | CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
AnnaBridge | 167:e84263d55307 | 633 | } |
AnnaBridge | 167:e84263d55307 | 634 | |
AnnaBridge | 167:e84263d55307 | 635 | /** |
AnnaBridge | 167:e84263d55307 | 636 | * @} |
AnnaBridge | 167:e84263d55307 | 637 | */ |
AnnaBridge | 167:e84263d55307 | 638 | |
AnnaBridge | 167:e84263d55307 | 639 | #endif /* __MPU_PRESENT */ |
AnnaBridge | 167:e84263d55307 | 640 | /** |
AnnaBridge | 167:e84263d55307 | 641 | * @} |
AnnaBridge | 167:e84263d55307 | 642 | */ |
AnnaBridge | 167:e84263d55307 | 643 | |
AnnaBridge | 167:e84263d55307 | 644 | /** |
AnnaBridge | 167:e84263d55307 | 645 | * @} |
AnnaBridge | 167:e84263d55307 | 646 | */ |
AnnaBridge | 167:e84263d55307 | 647 | |
AnnaBridge | 167:e84263d55307 | 648 | /** |
AnnaBridge | 167:e84263d55307 | 649 | * @} |
AnnaBridge | 167:e84263d55307 | 650 | */ |
AnnaBridge | 167:e84263d55307 | 651 | |
AnnaBridge | 167:e84263d55307 | 652 | #ifdef __cplusplus |
AnnaBridge | 167:e84263d55307 | 653 | } |
AnnaBridge | 167:e84263d55307 | 654 | #endif |
AnnaBridge | 167:e84263d55307 | 655 | |
AnnaBridge | 167:e84263d55307 | 656 | #endif /* __STM32F2xx_LL_CORTEX_H */ |
AnnaBridge | 167:e84263d55307 | 657 | |
AnnaBridge | 167:e84263d55307 | 658 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |