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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	154:37f96f9d4de2	1	/**
<>	154:37f96f9d4de2	2	******************************************************************************
<>	154:37f96f9d4de2	3	* @file stm32f1xx_ll_utils.c
<>	154:37f96f9d4de2	4	* @author MCD Application Team
<>	154:37f96f9d4de2	5	* @brief UTILS LL module driver.
<>	154:37f96f9d4de2	6	******************************************************************************
<>	154:37f96f9d4de2	7	* @attention
<>	154:37f96f9d4de2	8	*
<>	154:37f96f9d4de2	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	154:37f96f9d4de2	10	*
<>	154:37f96f9d4de2	11	* Redistribution and use in source and binary forms, with or without modification,
<>	154:37f96f9d4de2	12	* are permitted provided that the following conditions are met:
<>	154:37f96f9d4de2	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	154:37f96f9d4de2	14	* this list of conditions and the following disclaimer.
<>	154:37f96f9d4de2	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	154:37f96f9d4de2	16	* this list of conditions and the following disclaimer in the documentation
<>	154:37f96f9d4de2	17	* and/or other materials provided with the distribution.
<>	154:37f96f9d4de2	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	154:37f96f9d4de2	19	* may be used to endorse or promote products derived from this software
<>	154:37f96f9d4de2	20	* without specific prior written permission.
<>	154:37f96f9d4de2	21	*
<>	154:37f96f9d4de2	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	154:37f96f9d4de2	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	154:37f96f9d4de2	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	154:37f96f9d4de2	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	154:37f96f9d4de2	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	154:37f96f9d4de2	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	154:37f96f9d4de2	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	154:37f96f9d4de2	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	154:37f96f9d4de2	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	154:37f96f9d4de2	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	154:37f96f9d4de2	32	*
<>	154:37f96f9d4de2	33	******************************************************************************
<>	154:37f96f9d4de2	34	*/
<>	154:37f96f9d4de2	35	/* Includes ------------------------------------------------------------------*/
<>	154:37f96f9d4de2	36	#include "stm32f1xx_ll_rcc.h"
<>	154:37f96f9d4de2	37	#include "stm32f1xx_ll_utils.h"
<>	154:37f96f9d4de2	38	#include "stm32f1xx_ll_system.h"
<>	154:37f96f9d4de2	39	#ifdef USE_FULL_ASSERT
<>	154:37f96f9d4de2	40	#include "stm32_assert.h"
<>	154:37f96f9d4de2	41	#else
<>	154:37f96f9d4de2	42	#define assert_param(expr) ((void)0U)
<>	154:37f96f9d4de2	43	#endif
<>	154:37f96f9d4de2	44
<>	154:37f96f9d4de2	45	/** @addtogroup STM32F1xx_LL_Driver
<>	154:37f96f9d4de2	46	* @{
<>	154:37f96f9d4de2	47	*/
<>	154:37f96f9d4de2	48
<>	154:37f96f9d4de2	49	/** @addtogroup UTILS_LL
<>	154:37f96f9d4de2	50	* @{
<>	154:37f96f9d4de2	51	*/
<>	154:37f96f9d4de2	52
<>	154:37f96f9d4de2	53	/* Private types -------------------------------------------------------------*/
<>	154:37f96f9d4de2	54	/* Private variables ---------------------------------------------------------*/
<>	154:37f96f9d4de2	55	/* Private constants ---------------------------------------------------------*/
<>	154:37f96f9d4de2	56	/** @addtogroup UTILS_LL_Private_Constants
<>	154:37f96f9d4de2	57	* @{
<>	154:37f96f9d4de2	58	*/
<>	154:37f96f9d4de2	59
<>	154:37f96f9d4de2	60	/* Defines used for PLL range */
<>	154:37f96f9d4de2	61	#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /!< Frequency max for PLL output, in Hz /
<>	154:37f96f9d4de2	62
<>	154:37f96f9d4de2	63	/* Defines used for HSE range */
<>	154:37f96f9d4de2	64	#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /!< Frequency min for HSE frequency, in Hz /
<>	154:37f96f9d4de2	65	#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /!< Frequency max for HSE frequency, in Hz /
<>	154:37f96f9d4de2	66
<>	154:37f96f9d4de2	67	/* Defines used for FLASH latency according to HCLK Frequency */
<>	154:37f96f9d4de2	68	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	69	#define UTILS_LATENCY1_FREQ 24000000U /!< SYSCLK frequency to set FLASH latency 1 /
<>	154:37f96f9d4de2	70	#define UTILS_LATENCY2_FREQ 48000000U /!< SYSCLK frequency to set FLASH latency 2 /
<>	154:37f96f9d4de2	71	#else
<>	154:37f96f9d4de2	72	/!< No Latency Configuration in this device /
<>	154:37f96f9d4de2	73	#endif
<>	154:37f96f9d4de2	74	/**
<>	154:37f96f9d4de2	75	* @}
<>	154:37f96f9d4de2	76	*/
<>	154:37f96f9d4de2	77	/* Private macros ------------------------------------------------------------*/
<>	154:37f96f9d4de2	78	/** @addtogroup UTILS_LL_Private_Macros
<>	154:37f96f9d4de2	79	* @{
<>	154:37f96f9d4de2	80	*/
<>	154:37f96f9d4de2	81	#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
<>	154:37f96f9d4de2	82	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
<>	154:37f96f9d4de2	83	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
<>	154:37f96f9d4de2	84	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
<>	154:37f96f9d4de2	85	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
<>	154:37f96f9d4de2	86	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
<>	154:37f96f9d4de2	87	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
<>	154:37f96f9d4de2	88	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
<>	154:37f96f9d4de2	89	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
<>	154:37f96f9d4de2	90
<>	154:37f96f9d4de2	91	#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
<>	154:37f96f9d4de2	92	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
<>	154:37f96f9d4de2	93	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
<>	154:37f96f9d4de2	94	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
<>	154:37f96f9d4de2	95	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_16))
<>	154:37f96f9d4de2	96
<>	154:37f96f9d4de2	97	#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
<>	154:37f96f9d4de2	98	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
<>	154:37f96f9d4de2	99	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
<>	154:37f96f9d4de2	100	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
<>	154:37f96f9d4de2	101	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_16))
<>	154:37f96f9d4de2	102
<>	154:37f96f9d4de2	103	#if defined(RCC_CFGR_PLLMULL6_5)
<>	154:37f96f9d4de2	104	#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
<>	154:37f96f9d4de2	105	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
<>	154:37f96f9d4de2	106	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
<>	154:37f96f9d4de2	107	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
<>	154:37f96f9d4de2	108	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
<>	154:37f96f9d4de2	109	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
<>	154:37f96f9d4de2	110	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
<>	154:37f96f9d4de2	111	#else
<>	154:37f96f9d4de2	112	#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
<>	154:37f96f9d4de2	113	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_3) \
<>	154:37f96f9d4de2	114	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_4) \
<>	154:37f96f9d4de2	115	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
<>	154:37f96f9d4de2	116	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
<>	154:37f96f9d4de2	117	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
<>	154:37f96f9d4de2	118	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
<>	154:37f96f9d4de2	119	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
<>	154:37f96f9d4de2	120	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_10) \
<>	154:37f96f9d4de2	121	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_11) \
<>	154:37f96f9d4de2	122	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_12) \
<>	154:37f96f9d4de2	123	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_13) \
<>	154:37f96f9d4de2	124	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_14) \
<>	154:37f96f9d4de2	125	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_15) \
<>	154:37f96f9d4de2	126	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_16))
<>	154:37f96f9d4de2	127	#endif /* RCC_CFGR_PLLMULL6_5 */
<>	154:37f96f9d4de2	128
AnnaBridge	165:e614a9f1c9e2	129	#if defined(RCC_CFGR2_PREDIV1)
<>	154:37f96f9d4de2	130	#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_2) \|\| \
<>	154:37f96f9d4de2	131	((__VALUE__) == LL_RCC_PREDIV_DIV_3) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_4) \|\| \
<>	154:37f96f9d4de2	132	((__VALUE__) == LL_RCC_PREDIV_DIV_5) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_6) \|\| \
<>	154:37f96f9d4de2	133	((__VALUE__) == LL_RCC_PREDIV_DIV_7) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_8) \|\| \
<>	154:37f96f9d4de2	134	((__VALUE__) == LL_RCC_PREDIV_DIV_9) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_10) \|\| \
<>	154:37f96f9d4de2	135	((__VALUE__) == LL_RCC_PREDIV_DIV_11) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_12) \|\| \
<>	154:37f96f9d4de2	136	((__VALUE__) == LL_RCC_PREDIV_DIV_13) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_14) \|\| \
<>	154:37f96f9d4de2	137	((__VALUE__) == LL_RCC_PREDIV_DIV_15) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
<>	154:37f96f9d4de2	138	#else
<>	154:37f96f9d4de2	139	#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
<>	154:37f96f9d4de2	140	#endif /RCC_PREDIV1_DIV_2_16_SUPPORT/
<>	154:37f96f9d4de2	141
<>	154:37f96f9d4de2	142	#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
<>	154:37f96f9d4de2	143
<>	154:37f96f9d4de2	144
<>	154:37f96f9d4de2	145	#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
<>	154:37f96f9d4de2	146	\|\| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
<>	154:37f96f9d4de2	147
<>	154:37f96f9d4de2	148	#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
<>	154:37f96f9d4de2	149	/**
<>	154:37f96f9d4de2	150	* @}
<>	154:37f96f9d4de2	151	*/
<>	154:37f96f9d4de2	152	/* Private function prototypes -----------------------------------------------*/
<>	154:37f96f9d4de2	153	/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
<>	154:37f96f9d4de2	154	* @{
<>	154:37f96f9d4de2	155	*/
<>	154:37f96f9d4de2	156	static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
<>	154:37f96f9d4de2	157	LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
<>	154:37f96f9d4de2	158	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	159	static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
<>	154:37f96f9d4de2	160	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	161	static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<>	154:37f96f9d4de2	162	static ErrorStatus UTILS_PLL_IsBusy(void);
<>	154:37f96f9d4de2	163	/**
<>	154:37f96f9d4de2	164	* @}
<>	154:37f96f9d4de2	165	*/
<>	154:37f96f9d4de2	166
<>	154:37f96f9d4de2	167	/* Exported functions --------------------------------------------------------*/
<>	154:37f96f9d4de2	168	/** @addtogroup UTILS_LL_Exported_Functions
<>	154:37f96f9d4de2	169	* @{
<>	154:37f96f9d4de2	170	*/
<>	154:37f96f9d4de2	171
<>	154:37f96f9d4de2	172	/** @addtogroup UTILS_LL_EF_DELAY
<>	154:37f96f9d4de2	173	* @{
<>	154:37f96f9d4de2	174	*/
<>	154:37f96f9d4de2	175
<>	154:37f96f9d4de2	176	/**
<>	154:37f96f9d4de2	177	* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
<>	154:37f96f9d4de2	178	* @note When a RTOS is used, it is recommended to avoid changing the Systick
<>	154:37f96f9d4de2	179	* configuration by calling this function, for a delay use rather osDelay RTOS service.
<>	154:37f96f9d4de2	180	* @param HCLKFrequency HCLK frequency in Hz
<>	154:37f96f9d4de2	181	* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
<>	154:37f96f9d4de2	182	* @retval None
<>	154:37f96f9d4de2	183	*/
<>	154:37f96f9d4de2	184	void LL_Init1msTick(uint32_t HCLKFrequency)
<>	154:37f96f9d4de2	185	{
<>	154:37f96f9d4de2	186	/* Use frequency provided in argument */
<>	154:37f96f9d4de2	187	LL_InitTick(HCLKFrequency, 1000U);
<>	154:37f96f9d4de2	188	}
<>	154:37f96f9d4de2	189
<>	154:37f96f9d4de2	190	/**
<>	154:37f96f9d4de2	191	* @brief This function provides accurate delay (in milliseconds) based
<>	154:37f96f9d4de2	192	* on SysTick counter flag
<>	154:37f96f9d4de2	193	* @note When a RTOS is used, it is recommended to avoid using blocking delay
<>	154:37f96f9d4de2	194	* and use rather osDelay service.
<>	154:37f96f9d4de2	195	* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
<>	154:37f96f9d4de2	196	* will configure Systick to 1ms
<>	154:37f96f9d4de2	197	* @param Delay specifies the delay time length, in milliseconds.
<>	154:37f96f9d4de2	198	* @retval None
<>	154:37f96f9d4de2	199	*/
<>	154:37f96f9d4de2	200	void LL_mDelay(uint32_t Delay)
<>	154:37f96f9d4de2	201	{
<>	154:37f96f9d4de2	202	__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
<>	154:37f96f9d4de2	203	/* Add this code to indicate that local variable is not used */
<>	154:37f96f9d4de2	204	((void)tmp);
<>	154:37f96f9d4de2	205
<>	154:37f96f9d4de2	206	/* Add a period to guaranty minimum wait */
<>	154:37f96f9d4de2	207	if (Delay < LL_MAX_DELAY)
<>	154:37f96f9d4de2	208	{
<>	154:37f96f9d4de2	209	Delay++;
<>	154:37f96f9d4de2	210	}
<>	154:37f96f9d4de2	211
<>	154:37f96f9d4de2	212	while (Delay)
<>	154:37f96f9d4de2	213	{
<>	154:37f96f9d4de2	214	if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
<>	154:37f96f9d4de2	215	{
<>	154:37f96f9d4de2	216	Delay--;
<>	154:37f96f9d4de2	217	}
<>	154:37f96f9d4de2	218	}
<>	154:37f96f9d4de2	219	}
<>	154:37f96f9d4de2	220
<>	154:37f96f9d4de2	221	/**
<>	154:37f96f9d4de2	222	* @}
<>	154:37f96f9d4de2	223	*/
<>	154:37f96f9d4de2	224
<>	154:37f96f9d4de2	225	/** @addtogroup UTILS_EF_SYSTEM
<>	154:37f96f9d4de2	226	* @brief System Configuration functions
<>	154:37f96f9d4de2	227	*
<>	154:37f96f9d4de2	228	@verbatim
<>	154:37f96f9d4de2	229	===============================================================================
<>	154:37f96f9d4de2	230	##### System Configuration functions #####
<>	154:37f96f9d4de2	231	===============================================================================
<>	154:37f96f9d4de2	232	[..]
<>	154:37f96f9d4de2	233	System, AHB and APB buses clocks configuration
<>	154:37f96f9d4de2	234
<>	154:37f96f9d4de2	235	(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
<>	154:37f96f9d4de2	236	@endverbatim
<>	154:37f96f9d4de2	237	@internal
<>	154:37f96f9d4de2	238	Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
<>	154:37f96f9d4de2	239	(++) +-----------------------------------------------+
<>	154:37f96f9d4de2	240	(++) \| Latency \| SYSCLK clock frequency (MHz) \|
<>	154:37f96f9d4de2	241	(++) \|---------------\|-------------------------------\|
<>	154:37f96f9d4de2	242	(++) \|0WS(1CPU cycle)\| 0 < SYSCLK <= 24 \|
<>	154:37f96f9d4de2	243	(++) \|---------------\|-------------------------------\|
<>	154:37f96f9d4de2	244	(++) \|1WS(2CPU cycle)\| 24 < SYSCLK <= 48 \|
<>	154:37f96f9d4de2	245	(++) \|---------------\|-------------------------------\|
<>	154:37f96f9d4de2	246	(++) \|2WS(3CPU cycle)\| 48 < SYSCLK <= 72 \|
<>	154:37f96f9d4de2	247	(++) +-----------------------------------------------+
<>	154:37f96f9d4de2	248	@endinternal
<>	154:37f96f9d4de2	249	* @{
<>	154:37f96f9d4de2	250	*/
<>	154:37f96f9d4de2	251
<>	154:37f96f9d4de2	252	/**
<>	154:37f96f9d4de2	253	* @brief This function sets directly SystemCoreClock CMSIS variable.
<>	154:37f96f9d4de2	254	* @note Variable can be calculated also through SystemCoreClockUpdate function.
<>	154:37f96f9d4de2	255	* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<>	154:37f96f9d4de2	256	* @retval None
<>	154:37f96f9d4de2	257	*/
<>	154:37f96f9d4de2	258	void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
<>	154:37f96f9d4de2	259	{
<>	154:37f96f9d4de2	260	/* HCLK clock frequency */
<>	154:37f96f9d4de2	261	SystemCoreClock = HCLKFrequency;
<>	154:37f96f9d4de2	262	}
<>	154:37f96f9d4de2	263
<>	154:37f96f9d4de2	264	/**
<>	154:37f96f9d4de2	265	* @brief This function configures system clock with HSI as clock source of the PLL
<>	154:37f96f9d4de2	266	* @note The application need to ensure that PLL is disabled.
<>	154:37f96f9d4de2	267	* @note Function is based on the following formula:
<>	154:37f96f9d4de2	268	* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
<>	154:37f96f9d4de2	269	* - PREDIV: Set to 2 for few devices
<>	154:37f96f9d4de2	270	* - PLLMUL: The application software must set correctly the PLL multiplication factor to
<>	154:37f96f9d4de2	271	* not exceed 72MHz
<>	154:37f96f9d4de2	272	* @note FLASH latency can be modified through this function.
<>	154:37f96f9d4de2	273	* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<>	154:37f96f9d4de2	274	* the configuration information for the PLL.
<>	154:37f96f9d4de2	275	* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<>	154:37f96f9d4de2	276	* the configuration information for the BUS prescalers.
<>	154:37f96f9d4de2	277	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	278	* - SUCCESS: Max frequency configuration done
<>	154:37f96f9d4de2	279	* - ERROR: Max frequency configuration not done
<>	154:37f96f9d4de2	280	*/
<>	154:37f96f9d4de2	281	ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<>	154:37f96f9d4de2	282	LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<>	154:37f96f9d4de2	283	{
<>	154:37f96f9d4de2	284	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	285	uint32_t pllfreq = 0U;
<>	154:37f96f9d4de2	286
<>	154:37f96f9d4de2	287	/* Check if one of the PLL is enabled */
<>	154:37f96f9d4de2	288	if (UTILS_PLL_IsBusy() == SUCCESS)
<>	154:37f96f9d4de2	289	{
<>	154:37f96f9d4de2	290	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	154:37f96f9d4de2	291	/* Check PREDIV value */
<>	154:37f96f9d4de2	292	assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
<>	154:37f96f9d4de2	293	#else
<>	154:37f96f9d4de2	294	/* Force PREDIV value to 2 */
<>	154:37f96f9d4de2	295	UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
<>	154:37f96f9d4de2	296	#endif /RCC_PLLSRC_PREDIV1_SUPPORT/
<>	154:37f96f9d4de2	297	/* Calculate the new PLL output frequency */
<>	154:37f96f9d4de2	298	pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
<>	154:37f96f9d4de2	299
<>	154:37f96f9d4de2	300	/* Enable HSI if not enabled */
<>	154:37f96f9d4de2	301	if (LL_RCC_HSI_IsReady() != 1U)
<>	154:37f96f9d4de2	302	{
<>	154:37f96f9d4de2	303	LL_RCC_HSI_Enable();
<>	154:37f96f9d4de2	304	while (LL_RCC_HSI_IsReady() != 1U)
<>	154:37f96f9d4de2	305	{
<>	154:37f96f9d4de2	306	/* Wait for HSI ready */
<>	154:37f96f9d4de2	307	}
<>	154:37f96f9d4de2	308	}
<>	154:37f96f9d4de2	309
<>	154:37f96f9d4de2	310	/* Configure PLL */
<>	154:37f96f9d4de2	311	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
<>	154:37f96f9d4de2	312
<>	154:37f96f9d4de2	313	/* Enable PLL and switch system clock to PLL */
<>	154:37f96f9d4de2	314	status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<>	154:37f96f9d4de2	315	}
<>	154:37f96f9d4de2	316	else
<>	154:37f96f9d4de2	317	{
<>	154:37f96f9d4de2	318	/* Current PLL configuration cannot be modified */
<>	154:37f96f9d4de2	319	status = ERROR;
<>	154:37f96f9d4de2	320	}
<>	154:37f96f9d4de2	321
<>	154:37f96f9d4de2	322	return status;
<>	154:37f96f9d4de2	323	}
<>	154:37f96f9d4de2	324
<>	154:37f96f9d4de2	325	/**
<>	154:37f96f9d4de2	326	* @brief This function configures system clock with HSE as clock source of the PLL
<>	154:37f96f9d4de2	327	* @note The application need to ensure that PLL is disabled.
<>	154:37f96f9d4de2	328	* @note Function is based on the following formula:
<>	154:37f96f9d4de2	329	* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
<>	154:37f96f9d4de2	330	* - PREDIV: Set to 2 for few devices
<>	154:37f96f9d4de2	331	* - PLLMUL: The application software must set correctly the PLL multiplication factor to
<>	154:37f96f9d4de2	332	* not exceed @ref UTILS_PLL_OUTPUT_MAX
<>	154:37f96f9d4de2	333	* @note FLASH latency can be modified through this function.
<>	154:37f96f9d4de2	334	* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
<>	154:37f96f9d4de2	335	* @param HSEBypass This parameter can be one of the following values:
<>	154:37f96f9d4de2	336	* @arg @ref LL_UTILS_HSEBYPASS_ON
<>	154:37f96f9d4de2	337	* @arg @ref LL_UTILS_HSEBYPASS_OFF
<>	154:37f96f9d4de2	338	* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<>	154:37f96f9d4de2	339	* the configuration information for the PLL.
<>	154:37f96f9d4de2	340	* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<>	154:37f96f9d4de2	341	* the configuration information for the BUS prescalers.
<>	154:37f96f9d4de2	342	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	343	* - SUCCESS: Max frequency configuration done
<>	154:37f96f9d4de2	344	* - ERROR: Max frequency configuration not done
<>	154:37f96f9d4de2	345	*/
<>	154:37f96f9d4de2	346	ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<>	154:37f96f9d4de2	347	LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
<>	154:37f96f9d4de2	348	{
<>	154:37f96f9d4de2	349	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	350	uint32_t pllfreq = 0U;
<>	154:37f96f9d4de2	351
<>	154:37f96f9d4de2	352	/* Check the parameters */
<>	154:37f96f9d4de2	353	assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
<>	154:37f96f9d4de2	354	assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
<>	154:37f96f9d4de2	355
<>	154:37f96f9d4de2	356	/* Check if one of the PLL is enabled */
<>	154:37f96f9d4de2	357	if (UTILS_PLL_IsBusy() == SUCCESS)
<>	154:37f96f9d4de2	358	{
<>	154:37f96f9d4de2	359	assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
<>	154:37f96f9d4de2	360
<>	154:37f96f9d4de2	361	/* Calculate the new PLL output frequency */
<>	154:37f96f9d4de2	362	pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
<>	154:37f96f9d4de2	363
<>	154:37f96f9d4de2	364	/* Enable HSE if not enabled */
<>	154:37f96f9d4de2	365	if (LL_RCC_HSE_IsReady() != 1U)
<>	154:37f96f9d4de2	366	{
<>	154:37f96f9d4de2	367	/* Check if need to enable HSE bypass feature or not */
<>	154:37f96f9d4de2	368	if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
<>	154:37f96f9d4de2	369	{
<>	154:37f96f9d4de2	370	LL_RCC_HSE_EnableBypass();
<>	154:37f96f9d4de2	371	}
<>	154:37f96f9d4de2	372	else
<>	154:37f96f9d4de2	373	{
<>	154:37f96f9d4de2	374	LL_RCC_HSE_DisableBypass();
<>	154:37f96f9d4de2	375	}
<>	154:37f96f9d4de2	376
<>	154:37f96f9d4de2	377	/* Enable HSE */
<>	154:37f96f9d4de2	378	LL_RCC_HSE_Enable();
<>	154:37f96f9d4de2	379	while (LL_RCC_HSE_IsReady() != 1U)
<>	154:37f96f9d4de2	380	{
<>	154:37f96f9d4de2	381	/* Wait for HSE ready */
<>	154:37f96f9d4de2	382	}
<>	154:37f96f9d4de2	383	}
<>	154:37f96f9d4de2	384
<>	154:37f96f9d4de2	385	/* Configure PLL */
<>	154:37f96f9d4de2	386	LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC \| UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
<>	154:37f96f9d4de2	387
<>	154:37f96f9d4de2	388	/* Enable PLL and switch system clock to PLL */
<>	154:37f96f9d4de2	389	status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<>	154:37f96f9d4de2	390	}
<>	154:37f96f9d4de2	391	else
<>	154:37f96f9d4de2	392	{
<>	154:37f96f9d4de2	393	/* Current PLL configuration cannot be modified */
<>	154:37f96f9d4de2	394	status = ERROR;
<>	154:37f96f9d4de2	395	}
<>	154:37f96f9d4de2	396
<>	154:37f96f9d4de2	397	return status;
<>	154:37f96f9d4de2	398	}
<>	154:37f96f9d4de2	399
<>	154:37f96f9d4de2	400	/**
<>	154:37f96f9d4de2	401	* @}
<>	154:37f96f9d4de2	402	*/
<>	154:37f96f9d4de2	403
<>	154:37f96f9d4de2	404	/**
<>	154:37f96f9d4de2	405	* @}
<>	154:37f96f9d4de2	406	*/
<>	154:37f96f9d4de2	407
<>	154:37f96f9d4de2	408	/** @addtogroup UTILS_LL_Private_Functions
<>	154:37f96f9d4de2	409	* @{
<>	154:37f96f9d4de2	410	*/
<>	154:37f96f9d4de2	411	/**
<>	154:37f96f9d4de2	412	* @brief Update number of Flash wait states in line with new frequency and current
<>	154:37f96f9d4de2	413	voltage range.
<>	154:37f96f9d4de2	414	* @param Frequency SYSCLK frequency
<>	154:37f96f9d4de2	415	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	416	* - SUCCESS: Latency has been modified
<>	154:37f96f9d4de2	417	* - ERROR: Latency cannot be modified
<>	154:37f96f9d4de2	418	*/
<>	154:37f96f9d4de2	419	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	420	static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
<>	154:37f96f9d4de2	421	{
<>	154:37f96f9d4de2	422	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	423
<>	154:37f96f9d4de2	424	uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
<>	154:37f96f9d4de2	425
<>	154:37f96f9d4de2	426	/* Frequency cannot be equal to 0 */
<>	154:37f96f9d4de2	427	if (Frequency == 0U)
<>	154:37f96f9d4de2	428	{
<>	154:37f96f9d4de2	429	status = ERROR;
<>	154:37f96f9d4de2	430	}
<>	154:37f96f9d4de2	431	else
<>	154:37f96f9d4de2	432	{
<>	154:37f96f9d4de2	433	if (Frequency > UTILS_LATENCY2_FREQ)
<>	154:37f96f9d4de2	434	{
<>	154:37f96f9d4de2	435	/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
<>	154:37f96f9d4de2	436	latency = LL_FLASH_LATENCY_2;
<>	154:37f96f9d4de2	437	}
<>	154:37f96f9d4de2	438	else
<>	154:37f96f9d4de2	439	{
<>	154:37f96f9d4de2	440	if (Frequency > UTILS_LATENCY1_FREQ)
<>	154:37f96f9d4de2	441	{
<>	154:37f96f9d4de2	442	/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
<>	154:37f96f9d4de2	443	latency = LL_FLASH_LATENCY_1;
<>	154:37f96f9d4de2	444	}
<>	154:37f96f9d4de2	445	/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
<>	154:37f96f9d4de2	446	}
<>	154:37f96f9d4de2	447
<>	154:37f96f9d4de2	448	LL_FLASH_SetLatency(latency);
<>	154:37f96f9d4de2	449
<>	154:37f96f9d4de2	450	/* Check that the new number of wait states is taken into account to access the Flash
<>	154:37f96f9d4de2	451	memory by reading the FLASH_ACR register */
<>	154:37f96f9d4de2	452	if (LL_FLASH_GetLatency() != latency)
<>	154:37f96f9d4de2	453	{
<>	154:37f96f9d4de2	454	status = ERROR;
<>	154:37f96f9d4de2	455	}
<>	154:37f96f9d4de2	456	}
<>	154:37f96f9d4de2	457	return status;
<>	154:37f96f9d4de2	458	}
<>	154:37f96f9d4de2	459	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	460
<>	154:37f96f9d4de2	461	/**
<>	154:37f96f9d4de2	462	* @brief Function to check that PLL can be modified
<>	154:37f96f9d4de2	463	* @param PLL_InputFrequency PLL input frequency (in Hz)
<>	154:37f96f9d4de2	464	* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<>	154:37f96f9d4de2	465	* the configuration information for the PLL.
<>	154:37f96f9d4de2	466	* @retval PLL output frequency (in Hz)
<>	154:37f96f9d4de2	467	*/
<>	154:37f96f9d4de2	468	static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
<>	154:37f96f9d4de2	469	{
<>	154:37f96f9d4de2	470	uint32_t pllfreq = 0U;
<>	154:37f96f9d4de2	471
<>	154:37f96f9d4de2	472	/* Check the parameters */
<>	154:37f96f9d4de2	473	assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
<>	154:37f96f9d4de2	474
<>	154:37f96f9d4de2	475	/* Check different PLL parameters according to RM */
AnnaBridge	165:e614a9f1c9e2	476	#if defined (RCC_CFGR2_PREDIV1)
AnnaBridge	165:e614a9f1c9e2	477	pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
AnnaBridge	165:e614a9f1c9e2	478	#elif defined(RCC_CFGR2_PREDIV1SRC)
<>	154:37f96f9d4de2	479	pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
<>	154:37f96f9d4de2	480	#else
<>	154:37f96f9d4de2	481	pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
AnnaBridge	165:e614a9f1c9e2	482	#endif /RCC_CFGR2_PREDIV1SRC/
<>	154:37f96f9d4de2	483	assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
<>	154:37f96f9d4de2	484
<>	154:37f96f9d4de2	485	return pllfreq;
<>	154:37f96f9d4de2	486	}
<>	154:37f96f9d4de2	487
<>	154:37f96f9d4de2	488	/**
<>	154:37f96f9d4de2	489	* @brief Function to check that PLL can be modified
<>	154:37f96f9d4de2	490	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	491	* - SUCCESS: PLL modification can be done
<>	154:37f96f9d4de2	492	* - ERROR: PLL is busy
<>	154:37f96f9d4de2	493	*/
<>	154:37f96f9d4de2	494	static ErrorStatus UTILS_PLL_IsBusy(void)
<>	154:37f96f9d4de2	495	{
<>	154:37f96f9d4de2	496	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	497
<>	154:37f96f9d4de2	498	/* Check if PLL is busy*/
<>	154:37f96f9d4de2	499	if (LL_RCC_PLL_IsReady() != 0U)
<>	154:37f96f9d4de2	500	{
<>	154:37f96f9d4de2	501	/* PLL configuration cannot be modified */
<>	154:37f96f9d4de2	502	status = ERROR;
<>	154:37f96f9d4de2	503	}
<>	154:37f96f9d4de2	504	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	505	/* Check if PLL2 is busy*/
<>	154:37f96f9d4de2	506	if (LL_RCC_PLL2_IsReady() != 0U)
<>	154:37f96f9d4de2	507	{
<>	154:37f96f9d4de2	508	/* PLL2 configuration cannot be modified */
<>	154:37f96f9d4de2	509	status = ERROR;
<>	154:37f96f9d4de2	510	}
<>	154:37f96f9d4de2	511	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	512
AnnaBridge	165:e614a9f1c9e2	513	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	165:e614a9f1c9e2	514	/* Check if PLLI2S is busy*/
AnnaBridge	165:e614a9f1c9e2	515	if (LL_RCC_PLLI2S_IsReady() != 0U)
<>	154:37f96f9d4de2	516	{
AnnaBridge	165:e614a9f1c9e2	517	/* PLLI2S configuration cannot be modified */
<>	154:37f96f9d4de2	518	status = ERROR;
<>	154:37f96f9d4de2	519	}
AnnaBridge	165:e614a9f1c9e2	520	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	521
<>	154:37f96f9d4de2	522	return status;
<>	154:37f96f9d4de2	523	}
<>	154:37f96f9d4de2	524
<>	154:37f96f9d4de2	525	/**
<>	154:37f96f9d4de2	526	* @brief Function to enable PLL and switch system clock to PLL
<>	154:37f96f9d4de2	527	* @param SYSCLK_Frequency SYSCLK frequency
<>	154:37f96f9d4de2	528	* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<>	154:37f96f9d4de2	529	* the configuration information for the BUS prescalers.
<>	154:37f96f9d4de2	530	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	531	* - SUCCESS: No problem to switch system to PLL
<>	154:37f96f9d4de2	532	* - ERROR: Problem to switch system to PLL
<>	154:37f96f9d4de2	533	*/
<>	154:37f96f9d4de2	534	static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<>	154:37f96f9d4de2	535	{
<>	154:37f96f9d4de2	536	ErrorStatus status = SUCCESS;
AnnaBridge	165:e614a9f1c9e2	537	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	538	uint32_t sysclk_frequency_current = 0U;
AnnaBridge	165:e614a9f1c9e2	539	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	540
<>	154:37f96f9d4de2	541	assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
<>	154:37f96f9d4de2	542	assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
<>	154:37f96f9d4de2	543	assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
<>	154:37f96f9d4de2	544
AnnaBridge	165:e614a9f1c9e2	545	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	546	/* Calculate current SYSCLK frequency */
AnnaBridge	165:e614a9f1c9e2	547	sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
AnnaBridge	165:e614a9f1c9e2	548	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	549
<>	154:37f96f9d4de2	550	/* Increasing the number of wait states because of higher CPU frequency */
<>	154:37f96f9d4de2	551	#if defined (FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	552	if (sysclk_frequency_current < SYSCLK_Frequency)
<>	154:37f96f9d4de2	553	{
<>	154:37f96f9d4de2	554	/* Set FLASH latency to highest latency */
<>	154:37f96f9d4de2	555	status = UTILS_SetFlashLatency(SYSCLK_Frequency);
<>	154:37f96f9d4de2	556	}
<>	154:37f96f9d4de2	557	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	558
<>	154:37f96f9d4de2	559	/* Update system clock configuration */
<>	154:37f96f9d4de2	560	if (status == SUCCESS)
<>	154:37f96f9d4de2	561	{
<>	154:37f96f9d4de2	562	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	563	/* Enable PLL2 */
<>	154:37f96f9d4de2	564	LL_RCC_PLL2_Enable();
<>	154:37f96f9d4de2	565	while (LL_RCC_PLL2_IsReady() != 1U)
<>	154:37f96f9d4de2	566	{
<>	154:37f96f9d4de2	567	/* Wait for PLL2 ready */
<>	154:37f96f9d4de2	568	}
<>	154:37f96f9d4de2	569
<>	154:37f96f9d4de2	570	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	571	/* Enable PLL */
<>	154:37f96f9d4de2	572	LL_RCC_PLL_Enable();
<>	154:37f96f9d4de2	573	while (LL_RCC_PLL_IsReady() != 1U)
<>	154:37f96f9d4de2	574	{
<>	154:37f96f9d4de2	575	/* Wait for PLL ready */
<>	154:37f96f9d4de2	576	}
<>	154:37f96f9d4de2	577
<>	154:37f96f9d4de2	578	/* Sysclk activation on the main PLL */
<>	154:37f96f9d4de2	579	LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
<>	154:37f96f9d4de2	580	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
<>	154:37f96f9d4de2	581	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
<>	154:37f96f9d4de2	582	{
<>	154:37f96f9d4de2	583	/* Wait for system clock switch to PLL */
<>	154:37f96f9d4de2	584	}
<>	154:37f96f9d4de2	585
<>	154:37f96f9d4de2	586	/* Set APB1 & APB2 prescaler*/
<>	154:37f96f9d4de2	587	LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
<>	154:37f96f9d4de2	588	LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
<>	154:37f96f9d4de2	589	}
<>	154:37f96f9d4de2	590
<>	154:37f96f9d4de2	591	/* Decreasing the number of wait states because of lower CPU frequency */
<>	154:37f96f9d4de2	592	#if defined (FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	593	if (sysclk_frequency_current > SYSCLK_Frequency)
<>	154:37f96f9d4de2	594	{
<>	154:37f96f9d4de2	595	/* Set FLASH latency to lowest latency */
<>	154:37f96f9d4de2	596	status = UTILS_SetFlashLatency(SYSCLK_Frequency);
<>	154:37f96f9d4de2	597	}
<>	154:37f96f9d4de2	598	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	599
<>	154:37f96f9d4de2	600	/* Update SystemCoreClock variable */
<>	154:37f96f9d4de2	601	if (status == SUCCESS)
<>	154:37f96f9d4de2	602	{
<>	154:37f96f9d4de2	603	LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
<>	154:37f96f9d4de2	604	}
<>	154:37f96f9d4de2	605
<>	154:37f96f9d4de2	606	return status;
<>	154:37f96f9d4de2	607	}
<>	154:37f96f9d4de2	608
<>	154:37f96f9d4de2	609	/**
<>	154:37f96f9d4de2	610	* @}
<>	154:37f96f9d4de2	611	*/
<>	154:37f96f9d4de2	612
<>	154:37f96f9d4de2	613	/**
<>	154:37f96f9d4de2	614	* @}
<>	154:37f96f9d4de2	615	*/
<>	154:37f96f9d4de2	616
<>	154:37f96f9d4de2	617	/**
<>	154:37f96f9d4de2	618	* @}
<>	154:37f96f9d4de2	619	*/
<>	154:37f96f9d4de2	620
<>	154:37f96f9d4de2	621	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/