mbed-dev - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:: <>
Date:: Wed Jan 04 16:58:05 2017 +0000
Revision:: 154:37f96f9d4de2
Child:: 165:e614a9f1c9e2

This updates the lib to the mbed lib v133

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	154:37f96f9d4de2	1	/**
<>	154:37f96f9d4de2	2	******************************************************************************
<>	154:37f96f9d4de2	3	* @file stm32f1xx_ll_utils.c
<>	154:37f96f9d4de2	4	* @author MCD Application Team
<>	154:37f96f9d4de2	5	* @version $VERSION$
<>	154:37f96f9d4de2	6	* @date $DATE$
<>	154:37f96f9d4de2	7	* @brief UTILS LL module driver.
<>	154:37f96f9d4de2	8	******************************************************************************
<>	154:37f96f9d4de2	9	* @attention
<>	154:37f96f9d4de2	10	*
<>	154:37f96f9d4de2	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	154:37f96f9d4de2	12	*
<>	154:37f96f9d4de2	13	* Redistribution and use in source and binary forms, with or without modification,
<>	154:37f96f9d4de2	14	* are permitted provided that the following conditions are met:
<>	154:37f96f9d4de2	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	154:37f96f9d4de2	16	* this list of conditions and the following disclaimer.
<>	154:37f96f9d4de2	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	154:37f96f9d4de2	18	* this list of conditions and the following disclaimer in the documentation
<>	154:37f96f9d4de2	19	* and/or other materials provided with the distribution.
<>	154:37f96f9d4de2	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	154:37f96f9d4de2	21	* may be used to endorse or promote products derived from this software
<>	154:37f96f9d4de2	22	* without specific prior written permission.
<>	154:37f96f9d4de2	23	*
<>	154:37f96f9d4de2	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	154:37f96f9d4de2	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	154:37f96f9d4de2	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	154:37f96f9d4de2	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	154:37f96f9d4de2	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	154:37f96f9d4de2	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	154:37f96f9d4de2	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	154:37f96f9d4de2	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	154:37f96f9d4de2	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	154:37f96f9d4de2	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	154:37f96f9d4de2	34	*
<>	154:37f96f9d4de2	35	******************************************************************************
<>	154:37f96f9d4de2	36	*/
<>	154:37f96f9d4de2	37	/* Includes ------------------------------------------------------------------*/
<>	154:37f96f9d4de2	38	#include "stm32f1xx_ll_rcc.h"
<>	154:37f96f9d4de2	39	#include "stm32f1xx_ll_utils.h"
<>	154:37f96f9d4de2	40	#include "stm32f1xx_ll_system.h"
<>	154:37f96f9d4de2	41	#ifdef USE_FULL_ASSERT
<>	154:37f96f9d4de2	42	#include "stm32_assert.h"
<>	154:37f96f9d4de2	43	#else
<>	154:37f96f9d4de2	44	#define assert_param(expr) ((void)0U)
<>	154:37f96f9d4de2	45	#endif
<>	154:37f96f9d4de2	46
<>	154:37f96f9d4de2	47	/** @addtogroup STM32F1xx_LL_Driver
<>	154:37f96f9d4de2	48	* @{
<>	154:37f96f9d4de2	49	*/
<>	154:37f96f9d4de2	50
<>	154:37f96f9d4de2	51	/** @addtogroup UTILS_LL
<>	154:37f96f9d4de2	52	* @{
<>	154:37f96f9d4de2	53	*/
<>	154:37f96f9d4de2	54
<>	154:37f96f9d4de2	55	/* Private types -------------------------------------------------------------*/
<>	154:37f96f9d4de2	56	/* Private variables ---------------------------------------------------------*/
<>	154:37f96f9d4de2	57	/* Private constants ---------------------------------------------------------*/
<>	154:37f96f9d4de2	58	/** @addtogroup UTILS_LL_Private_Constants
<>	154:37f96f9d4de2	59	* @{
<>	154:37f96f9d4de2	60	*/
<>	154:37f96f9d4de2	61
<>	154:37f96f9d4de2	62	/* Defines used for PLL range */
<>	154:37f96f9d4de2	63	#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /!< Frequency max for PLL output, in Hz /
<>	154:37f96f9d4de2	64
<>	154:37f96f9d4de2	65	/* Defines used for HSE range */
<>	154:37f96f9d4de2	66	#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /!< Frequency min for HSE frequency, in Hz /
<>	154:37f96f9d4de2	67	#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /!< Frequency max for HSE frequency, in Hz /
<>	154:37f96f9d4de2	68
<>	154:37f96f9d4de2	69	/* Defines used for FLASH latency according to HCLK Frequency */
<>	154:37f96f9d4de2	70	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	71	#define UTILS_LATENCY1_FREQ 24000000U /!< SYSCLK frequency to set FLASH latency 1 /
<>	154:37f96f9d4de2	72	#define UTILS_LATENCY2_FREQ 48000000U /!< SYSCLK frequency to set FLASH latency 2 /
<>	154:37f96f9d4de2	73	#else
<>	154:37f96f9d4de2	74	/!< No Latency Configuration in this device /
<>	154:37f96f9d4de2	75	#endif
<>	154:37f96f9d4de2	76	/**
<>	154:37f96f9d4de2	77	* @}
<>	154:37f96f9d4de2	78	*/
<>	154:37f96f9d4de2	79	/* Private macros ------------------------------------------------------------*/
<>	154:37f96f9d4de2	80	/** @addtogroup UTILS_LL_Private_Macros
<>	154:37f96f9d4de2	81	* @{
<>	154:37f96f9d4de2	82	*/
<>	154:37f96f9d4de2	83	#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
<>	154:37f96f9d4de2	84	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
<>	154:37f96f9d4de2	85	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
<>	154:37f96f9d4de2	86	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
<>	154:37f96f9d4de2	87	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
<>	154:37f96f9d4de2	88	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
<>	154:37f96f9d4de2	89	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
<>	154:37f96f9d4de2	90	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
<>	154:37f96f9d4de2	91	\|\| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
<>	154:37f96f9d4de2	92
<>	154:37f96f9d4de2	93	#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
<>	154:37f96f9d4de2	94	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
<>	154:37f96f9d4de2	95	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
<>	154:37f96f9d4de2	96	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
<>	154:37f96f9d4de2	97	\|\| ((__VALUE__) == LL_RCC_APB1_DIV_16))
<>	154:37f96f9d4de2	98
<>	154:37f96f9d4de2	99	#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
<>	154:37f96f9d4de2	100	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
<>	154:37f96f9d4de2	101	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
<>	154:37f96f9d4de2	102	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
<>	154:37f96f9d4de2	103	\|\| ((__VALUE__) == LL_RCC_APB2_DIV_16))
<>	154:37f96f9d4de2	104
<>	154:37f96f9d4de2	105	#if defined(RCC_CFGR_PLLMULL6_5)
<>	154:37f96f9d4de2	106	#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
<>	154:37f96f9d4de2	107	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
<>	154:37f96f9d4de2	108	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
<>	154:37f96f9d4de2	109	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
<>	154:37f96f9d4de2	110	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
<>	154:37f96f9d4de2	111	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
<>	154:37f96f9d4de2	112	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
<>	154:37f96f9d4de2	113	#else
<>	154:37f96f9d4de2	114	#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
<>	154:37f96f9d4de2	115	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_3) \
<>	154:37f96f9d4de2	116	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_4) \
<>	154:37f96f9d4de2	117	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
<>	154:37f96f9d4de2	118	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
<>	154:37f96f9d4de2	119	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
<>	154:37f96f9d4de2	120	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
<>	154:37f96f9d4de2	121	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
<>	154:37f96f9d4de2	122	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_10) \
<>	154:37f96f9d4de2	123	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_11) \
<>	154:37f96f9d4de2	124	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_12) \
<>	154:37f96f9d4de2	125	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_13) \
<>	154:37f96f9d4de2	126	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_14) \
<>	154:37f96f9d4de2	127	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_15) \
<>	154:37f96f9d4de2	128	\|\| ((__VALUE__) == LL_RCC_PLL_MUL_16))
<>	154:37f96f9d4de2	129	#endif /* RCC_CFGR_PLLMULL6_5 */
<>	154:37f96f9d4de2	130
<>	154:37f96f9d4de2	131	#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT)
<>	154:37f96f9d4de2	132	#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_2) \|\| \
<>	154:37f96f9d4de2	133	((__VALUE__) == LL_RCC_PREDIV_DIV_3) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_4) \|\| \
<>	154:37f96f9d4de2	134	((__VALUE__) == LL_RCC_PREDIV_DIV_5) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_6) \|\| \
<>	154:37f96f9d4de2	135	((__VALUE__) == LL_RCC_PREDIV_DIV_7) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_8) \|\| \
<>	154:37f96f9d4de2	136	((__VALUE__) == LL_RCC_PREDIV_DIV_9) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_10) \|\| \
<>	154:37f96f9d4de2	137	((__VALUE__) == LL_RCC_PREDIV_DIV_11) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_12) \|\| \
<>	154:37f96f9d4de2	138	((__VALUE__) == LL_RCC_PREDIV_DIV_13) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_14) \|\| \
<>	154:37f96f9d4de2	139	((__VALUE__) == LL_RCC_PREDIV_DIV_15) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
<>	154:37f96f9d4de2	140	#else
<>	154:37f96f9d4de2	141	#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) \|\| ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
<>	154:37f96f9d4de2	142	#endif /RCC_PREDIV1_DIV_2_16_SUPPORT/
<>	154:37f96f9d4de2	143
<>	154:37f96f9d4de2	144	#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
<>	154:37f96f9d4de2	145
<>	154:37f96f9d4de2	146
<>	154:37f96f9d4de2	147	#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
<>	154:37f96f9d4de2	148	\|\| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
<>	154:37f96f9d4de2	149
<>	154:37f96f9d4de2	150	#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
<>	154:37f96f9d4de2	151	/**
<>	154:37f96f9d4de2	152	* @}
<>	154:37f96f9d4de2	153	*/
<>	154:37f96f9d4de2	154	/* Private function prototypes -----------------------------------------------*/
<>	154:37f96f9d4de2	155	/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
<>	154:37f96f9d4de2	156	* @{
<>	154:37f96f9d4de2	157	*/
<>	154:37f96f9d4de2	158	static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
<>	154:37f96f9d4de2	159	LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
<>	154:37f96f9d4de2	160	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	161	static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
<>	154:37f96f9d4de2	162	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	163	static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<>	154:37f96f9d4de2	164	static ErrorStatus UTILS_PLL_IsBusy(void);
<>	154:37f96f9d4de2	165	/**
<>	154:37f96f9d4de2	166	* @}
<>	154:37f96f9d4de2	167	*/
<>	154:37f96f9d4de2	168
<>	154:37f96f9d4de2	169	/* Exported functions --------------------------------------------------------*/
<>	154:37f96f9d4de2	170	/** @addtogroup UTILS_LL_Exported_Functions
<>	154:37f96f9d4de2	171	* @{
<>	154:37f96f9d4de2	172	*/
<>	154:37f96f9d4de2	173
<>	154:37f96f9d4de2	174	/** @addtogroup UTILS_LL_EF_DELAY
<>	154:37f96f9d4de2	175	* @{
<>	154:37f96f9d4de2	176	*/
<>	154:37f96f9d4de2	177
<>	154:37f96f9d4de2	178	/**
<>	154:37f96f9d4de2	179	* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
<>	154:37f96f9d4de2	180	* @note When a RTOS is used, it is recommended to avoid changing the Systick
<>	154:37f96f9d4de2	181	* configuration by calling this function, for a delay use rather osDelay RTOS service.
<>	154:37f96f9d4de2	182	* @param HCLKFrequency HCLK frequency in Hz
<>	154:37f96f9d4de2	183	* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
<>	154:37f96f9d4de2	184	* @retval None
<>	154:37f96f9d4de2	185	*/
<>	154:37f96f9d4de2	186	void LL_Init1msTick(uint32_t HCLKFrequency)
<>	154:37f96f9d4de2	187	{
<>	154:37f96f9d4de2	188	/* Use frequency provided in argument */
<>	154:37f96f9d4de2	189	LL_InitTick(HCLKFrequency, 1000U);
<>	154:37f96f9d4de2	190	}
<>	154:37f96f9d4de2	191
<>	154:37f96f9d4de2	192	/**
<>	154:37f96f9d4de2	193	* @brief This function provides accurate delay (in milliseconds) based
<>	154:37f96f9d4de2	194	* on SysTick counter flag
<>	154:37f96f9d4de2	195	* @note When a RTOS is used, it is recommended to avoid using blocking delay
<>	154:37f96f9d4de2	196	* and use rather osDelay service.
<>	154:37f96f9d4de2	197	* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
<>	154:37f96f9d4de2	198	* will configure Systick to 1ms
<>	154:37f96f9d4de2	199	* @param Delay specifies the delay time length, in milliseconds.
<>	154:37f96f9d4de2	200	* @retval None
<>	154:37f96f9d4de2	201	*/
<>	154:37f96f9d4de2	202	void LL_mDelay(uint32_t Delay)
<>	154:37f96f9d4de2	203	{
<>	154:37f96f9d4de2	204	__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
<>	154:37f96f9d4de2	205	/* Add this code to indicate that local variable is not used */
<>	154:37f96f9d4de2	206	((void)tmp);
<>	154:37f96f9d4de2	207
<>	154:37f96f9d4de2	208	/* Add a period to guaranty minimum wait */
<>	154:37f96f9d4de2	209	if (Delay < LL_MAX_DELAY)
<>	154:37f96f9d4de2	210	{
<>	154:37f96f9d4de2	211	Delay++;
<>	154:37f96f9d4de2	212	}
<>	154:37f96f9d4de2	213
<>	154:37f96f9d4de2	214	while (Delay)
<>	154:37f96f9d4de2	215	{
<>	154:37f96f9d4de2	216	if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
<>	154:37f96f9d4de2	217	{
<>	154:37f96f9d4de2	218	Delay--;
<>	154:37f96f9d4de2	219	}
<>	154:37f96f9d4de2	220	}
<>	154:37f96f9d4de2	221	}
<>	154:37f96f9d4de2	222
<>	154:37f96f9d4de2	223	/**
<>	154:37f96f9d4de2	224	* @}
<>	154:37f96f9d4de2	225	*/
<>	154:37f96f9d4de2	226
<>	154:37f96f9d4de2	227	/** @addtogroup UTILS_EF_SYSTEM
<>	154:37f96f9d4de2	228	* @brief System Configuration functions
<>	154:37f96f9d4de2	229	*
<>	154:37f96f9d4de2	230	@verbatim
<>	154:37f96f9d4de2	231	===============================================================================
<>	154:37f96f9d4de2	232	##### System Configuration functions #####
<>	154:37f96f9d4de2	233	===============================================================================
<>	154:37f96f9d4de2	234	[..]
<>	154:37f96f9d4de2	235	System, AHB and APB buses clocks configuration
<>	154:37f96f9d4de2	236
<>	154:37f96f9d4de2	237	(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
<>	154:37f96f9d4de2	238	@endverbatim
<>	154:37f96f9d4de2	239	@internal
<>	154:37f96f9d4de2	240	Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
<>	154:37f96f9d4de2	241	(++) +-----------------------------------------------+
<>	154:37f96f9d4de2	242	(++) \| Latency \| SYSCLK clock frequency (MHz) \|
<>	154:37f96f9d4de2	243	(++) \|---------------\|-------------------------------\|
<>	154:37f96f9d4de2	244	(++) \|0WS(1CPU cycle)\| 0 < SYSCLK <= 24 \|
<>	154:37f96f9d4de2	245	(++) \|---------------\|-------------------------------\|
<>	154:37f96f9d4de2	246	(++) \|1WS(2CPU cycle)\| 24 < SYSCLK <= 48 \|
<>	154:37f96f9d4de2	247	(++) \|---------------\|-------------------------------\|
<>	154:37f96f9d4de2	248	(++) \|2WS(3CPU cycle)\| 48 < SYSCLK <= 72 \|
<>	154:37f96f9d4de2	249	(++) +-----------------------------------------------+
<>	154:37f96f9d4de2	250	@endinternal
<>	154:37f96f9d4de2	251	* @{
<>	154:37f96f9d4de2	252	*/
<>	154:37f96f9d4de2	253
<>	154:37f96f9d4de2	254	/**
<>	154:37f96f9d4de2	255	* @brief This function sets directly SystemCoreClock CMSIS variable.
<>	154:37f96f9d4de2	256	* @note Variable can be calculated also through SystemCoreClockUpdate function.
<>	154:37f96f9d4de2	257	* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<>	154:37f96f9d4de2	258	* @retval None
<>	154:37f96f9d4de2	259	*/
<>	154:37f96f9d4de2	260	void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
<>	154:37f96f9d4de2	261	{
<>	154:37f96f9d4de2	262	/* HCLK clock frequency */
<>	154:37f96f9d4de2	263	SystemCoreClock = HCLKFrequency;
<>	154:37f96f9d4de2	264	}
<>	154:37f96f9d4de2	265
<>	154:37f96f9d4de2	266	/**
<>	154:37f96f9d4de2	267	* @brief This function configures system clock with HSI as clock source of the PLL
<>	154:37f96f9d4de2	268	* @note The application need to ensure that PLL is disabled.
<>	154:37f96f9d4de2	269	* @note Function is based on the following formula:
<>	154:37f96f9d4de2	270	* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
<>	154:37f96f9d4de2	271	* - PREDIV: Set to 2 for few devices
<>	154:37f96f9d4de2	272	* - PLLMUL: The application software must set correctly the PLL multiplication factor to
<>	154:37f96f9d4de2	273	* not exceed 72MHz
<>	154:37f96f9d4de2	274	* @note FLASH latency can be modified through this function.
<>	154:37f96f9d4de2	275	* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<>	154:37f96f9d4de2	276	* the configuration information for the PLL.
<>	154:37f96f9d4de2	277	* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<>	154:37f96f9d4de2	278	* the configuration information for the BUS prescalers.
<>	154:37f96f9d4de2	279	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	280	* - SUCCESS: Max frequency configuration done
<>	154:37f96f9d4de2	281	* - ERROR: Max frequency configuration not done
<>	154:37f96f9d4de2	282	*/
<>	154:37f96f9d4de2	283	ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<>	154:37f96f9d4de2	284	LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<>	154:37f96f9d4de2	285	{
<>	154:37f96f9d4de2	286	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	287	uint32_t pllfreq = 0U;
<>	154:37f96f9d4de2	288
<>	154:37f96f9d4de2	289	/* Check if one of the PLL is enabled */
<>	154:37f96f9d4de2	290	if (UTILS_PLL_IsBusy() == SUCCESS)
<>	154:37f96f9d4de2	291	{
<>	154:37f96f9d4de2	292	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	154:37f96f9d4de2	293	/* Check PREDIV value */
<>	154:37f96f9d4de2	294	assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
<>	154:37f96f9d4de2	295	#else
<>	154:37f96f9d4de2	296	/* Force PREDIV value to 2 */
<>	154:37f96f9d4de2	297	UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
<>	154:37f96f9d4de2	298	#endif /RCC_PLLSRC_PREDIV1_SUPPORT/
<>	154:37f96f9d4de2	299	/* Calculate the new PLL output frequency */
<>	154:37f96f9d4de2	300	pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
<>	154:37f96f9d4de2	301
<>	154:37f96f9d4de2	302	/* Enable HSI if not enabled */
<>	154:37f96f9d4de2	303	if (LL_RCC_HSI_IsReady() != 1U)
<>	154:37f96f9d4de2	304	{
<>	154:37f96f9d4de2	305	LL_RCC_HSI_Enable();
<>	154:37f96f9d4de2	306	while (LL_RCC_HSI_IsReady() != 1U)
<>	154:37f96f9d4de2	307	{
<>	154:37f96f9d4de2	308	/* Wait for HSI ready */
<>	154:37f96f9d4de2	309	}
<>	154:37f96f9d4de2	310	}
<>	154:37f96f9d4de2	311
<>	154:37f96f9d4de2	312	/* Configure PLL */
<>	154:37f96f9d4de2	313	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
<>	154:37f96f9d4de2	314
<>	154:37f96f9d4de2	315	/* Enable PLL and switch system clock to PLL */
<>	154:37f96f9d4de2	316	status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<>	154:37f96f9d4de2	317	}
<>	154:37f96f9d4de2	318	else
<>	154:37f96f9d4de2	319	{
<>	154:37f96f9d4de2	320	/* Current PLL configuration cannot be modified */
<>	154:37f96f9d4de2	321	status = ERROR;
<>	154:37f96f9d4de2	322	}
<>	154:37f96f9d4de2	323
<>	154:37f96f9d4de2	324	return status;
<>	154:37f96f9d4de2	325	}
<>	154:37f96f9d4de2	326
<>	154:37f96f9d4de2	327	/**
<>	154:37f96f9d4de2	328	* @brief This function configures system clock with HSE as clock source of the PLL
<>	154:37f96f9d4de2	329	* @note The application need to ensure that PLL is disabled.
<>	154:37f96f9d4de2	330	* @note Function is based on the following formula:
<>	154:37f96f9d4de2	331	* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
<>	154:37f96f9d4de2	332	* - PREDIV: Set to 2 for few devices
<>	154:37f96f9d4de2	333	* - PLLMUL: The application software must set correctly the PLL multiplication factor to
<>	154:37f96f9d4de2	334	* not exceed @ref UTILS_PLL_OUTPUT_MAX
<>	154:37f96f9d4de2	335	* @note FLASH latency can be modified through this function.
<>	154:37f96f9d4de2	336	* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
<>	154:37f96f9d4de2	337	* @param HSEBypass This parameter can be one of the following values:
<>	154:37f96f9d4de2	338	* @arg @ref LL_UTILS_HSEBYPASS_ON
<>	154:37f96f9d4de2	339	* @arg @ref LL_UTILS_HSEBYPASS_OFF
<>	154:37f96f9d4de2	340	* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<>	154:37f96f9d4de2	341	* the configuration information for the PLL.
<>	154:37f96f9d4de2	342	* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<>	154:37f96f9d4de2	343	* the configuration information for the BUS prescalers.
<>	154:37f96f9d4de2	344	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	345	* - SUCCESS: Max frequency configuration done
<>	154:37f96f9d4de2	346	* - ERROR: Max frequency configuration not done
<>	154:37f96f9d4de2	347	*/
<>	154:37f96f9d4de2	348	ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<>	154:37f96f9d4de2	349	LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
<>	154:37f96f9d4de2	350	{
<>	154:37f96f9d4de2	351	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	352	uint32_t pllfreq = 0U;
<>	154:37f96f9d4de2	353
<>	154:37f96f9d4de2	354	/* Check the parameters */
<>	154:37f96f9d4de2	355	assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
<>	154:37f96f9d4de2	356	assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
<>	154:37f96f9d4de2	357
<>	154:37f96f9d4de2	358	/* Check if one of the PLL is enabled */
<>	154:37f96f9d4de2	359	if (UTILS_PLL_IsBusy() == SUCCESS)
<>	154:37f96f9d4de2	360	{
<>	154:37f96f9d4de2	361	assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
<>	154:37f96f9d4de2	362
<>	154:37f96f9d4de2	363	/* Calculate the new PLL output frequency */
<>	154:37f96f9d4de2	364	pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
<>	154:37f96f9d4de2	365
<>	154:37f96f9d4de2	366	/* Enable HSE if not enabled */
<>	154:37f96f9d4de2	367	if (LL_RCC_HSE_IsReady() != 1U)
<>	154:37f96f9d4de2	368	{
<>	154:37f96f9d4de2	369	/* Check if need to enable HSE bypass feature or not */
<>	154:37f96f9d4de2	370	if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
<>	154:37f96f9d4de2	371	{
<>	154:37f96f9d4de2	372	LL_RCC_HSE_EnableBypass();
<>	154:37f96f9d4de2	373	}
<>	154:37f96f9d4de2	374	else
<>	154:37f96f9d4de2	375	{
<>	154:37f96f9d4de2	376	LL_RCC_HSE_DisableBypass();
<>	154:37f96f9d4de2	377	}
<>	154:37f96f9d4de2	378
<>	154:37f96f9d4de2	379	/* Enable HSE */
<>	154:37f96f9d4de2	380	LL_RCC_HSE_Enable();
<>	154:37f96f9d4de2	381	while (LL_RCC_HSE_IsReady() != 1U)
<>	154:37f96f9d4de2	382	{
<>	154:37f96f9d4de2	383	/* Wait for HSE ready */
<>	154:37f96f9d4de2	384	}
<>	154:37f96f9d4de2	385	}
<>	154:37f96f9d4de2	386
<>	154:37f96f9d4de2	387	/* Configure PLL */
<>	154:37f96f9d4de2	388	LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC \| UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
<>	154:37f96f9d4de2	389
<>	154:37f96f9d4de2	390	/* Enable PLL and switch system clock to PLL */
<>	154:37f96f9d4de2	391	status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<>	154:37f96f9d4de2	392	}
<>	154:37f96f9d4de2	393	else
<>	154:37f96f9d4de2	394	{
<>	154:37f96f9d4de2	395	/* Current PLL configuration cannot be modified */
<>	154:37f96f9d4de2	396	status = ERROR;
<>	154:37f96f9d4de2	397	}
<>	154:37f96f9d4de2	398
<>	154:37f96f9d4de2	399	return status;
<>	154:37f96f9d4de2	400	}
<>	154:37f96f9d4de2	401
<>	154:37f96f9d4de2	402	/**
<>	154:37f96f9d4de2	403	* @}
<>	154:37f96f9d4de2	404	*/
<>	154:37f96f9d4de2	405
<>	154:37f96f9d4de2	406	/**
<>	154:37f96f9d4de2	407	* @}
<>	154:37f96f9d4de2	408	*/
<>	154:37f96f9d4de2	409
<>	154:37f96f9d4de2	410	/** @addtogroup UTILS_LL_Private_Functions
<>	154:37f96f9d4de2	411	* @{
<>	154:37f96f9d4de2	412	*/
<>	154:37f96f9d4de2	413	/**
<>	154:37f96f9d4de2	414	* @brief Update number of Flash wait states in line with new frequency and current
<>	154:37f96f9d4de2	415	voltage range.
<>	154:37f96f9d4de2	416	* @param Frequency SYSCLK frequency
<>	154:37f96f9d4de2	417	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	418	* - SUCCESS: Latency has been modified
<>	154:37f96f9d4de2	419	* - ERROR: Latency cannot be modified
<>	154:37f96f9d4de2	420	*/
<>	154:37f96f9d4de2	421	#if defined(FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	422	static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
<>	154:37f96f9d4de2	423	{
<>	154:37f96f9d4de2	424	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	425
<>	154:37f96f9d4de2	426	uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
<>	154:37f96f9d4de2	427
<>	154:37f96f9d4de2	428	/* Frequency cannot be equal to 0 */
<>	154:37f96f9d4de2	429	if (Frequency == 0U)
<>	154:37f96f9d4de2	430	{
<>	154:37f96f9d4de2	431	status = ERROR;
<>	154:37f96f9d4de2	432	}
<>	154:37f96f9d4de2	433	else
<>	154:37f96f9d4de2	434	{
<>	154:37f96f9d4de2	435	if (Frequency > UTILS_LATENCY2_FREQ)
<>	154:37f96f9d4de2	436	{
<>	154:37f96f9d4de2	437	/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
<>	154:37f96f9d4de2	438	latency = LL_FLASH_LATENCY_2;
<>	154:37f96f9d4de2	439	}
<>	154:37f96f9d4de2	440	else
<>	154:37f96f9d4de2	441	{
<>	154:37f96f9d4de2	442	if (Frequency > UTILS_LATENCY1_FREQ)
<>	154:37f96f9d4de2	443	{
<>	154:37f96f9d4de2	444	/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
<>	154:37f96f9d4de2	445	latency = LL_FLASH_LATENCY_1;
<>	154:37f96f9d4de2	446	}
<>	154:37f96f9d4de2	447	/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
<>	154:37f96f9d4de2	448	}
<>	154:37f96f9d4de2	449
<>	154:37f96f9d4de2	450	LL_FLASH_SetLatency(latency);
<>	154:37f96f9d4de2	451
<>	154:37f96f9d4de2	452	/* Check that the new number of wait states is taken into account to access the Flash
<>	154:37f96f9d4de2	453	memory by reading the FLASH_ACR register */
<>	154:37f96f9d4de2	454	if (LL_FLASH_GetLatency() != latency)
<>	154:37f96f9d4de2	455	{
<>	154:37f96f9d4de2	456	status = ERROR;
<>	154:37f96f9d4de2	457	}
<>	154:37f96f9d4de2	458	}
<>	154:37f96f9d4de2	459	return status;
<>	154:37f96f9d4de2	460	}
<>	154:37f96f9d4de2	461	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	462
<>	154:37f96f9d4de2	463	/**
<>	154:37f96f9d4de2	464	* @brief Function to check that PLL can be modified
<>	154:37f96f9d4de2	465	* @param PLL_InputFrequency PLL input frequency (in Hz)
<>	154:37f96f9d4de2	466	* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<>	154:37f96f9d4de2	467	* the configuration information for the PLL.
<>	154:37f96f9d4de2	468	* @retval PLL output frequency (in Hz)
<>	154:37f96f9d4de2	469	*/
<>	154:37f96f9d4de2	470	static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
<>	154:37f96f9d4de2	471	{
<>	154:37f96f9d4de2	472	uint32_t pllfreq = 0U;
<>	154:37f96f9d4de2	473
<>	154:37f96f9d4de2	474	/* Check the parameters */
<>	154:37f96f9d4de2	475	assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
<>	154:37f96f9d4de2	476
<>	154:37f96f9d4de2	477	/* Check different PLL parameters according to RM */
<>	154:37f96f9d4de2	478	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	154:37f96f9d4de2	479	pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
<>	154:37f96f9d4de2	480	#elif defined (RCC_PREDIV1_DIV_2_16_SUPPORT)
<>	154:37f96f9d4de2	481	pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
<>	154:37f96f9d4de2	482	#else
<>	154:37f96f9d4de2	483	pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
<>	154:37f96f9d4de2	484	#endif /RCC_PLLSRC_PREDIV1_SUPPORT/
<>	154:37f96f9d4de2	485	assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
<>	154:37f96f9d4de2	486
<>	154:37f96f9d4de2	487	return pllfreq;
<>	154:37f96f9d4de2	488	}
<>	154:37f96f9d4de2	489
<>	154:37f96f9d4de2	490	/**
<>	154:37f96f9d4de2	491	* @brief Function to check that PLL can be modified
<>	154:37f96f9d4de2	492	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	493	* - SUCCESS: PLL modification can be done
<>	154:37f96f9d4de2	494	* - ERROR: PLL is busy
<>	154:37f96f9d4de2	495	*/
<>	154:37f96f9d4de2	496	static ErrorStatus UTILS_PLL_IsBusy(void)
<>	154:37f96f9d4de2	497	{
<>	154:37f96f9d4de2	498	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	499
<>	154:37f96f9d4de2	500	/* Check if PLL is busy*/
<>	154:37f96f9d4de2	501	if (LL_RCC_PLL_IsReady() != 0U)
<>	154:37f96f9d4de2	502	{
<>	154:37f96f9d4de2	503	/* PLL configuration cannot be modified */
<>	154:37f96f9d4de2	504	status = ERROR;
<>	154:37f96f9d4de2	505	}
<>	154:37f96f9d4de2	506	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	507	/* Check if PLL2 is busy*/
<>	154:37f96f9d4de2	508	if (LL_RCC_PLL2_IsReady() != 0U)
<>	154:37f96f9d4de2	509	{
<>	154:37f96f9d4de2	510	/* PLL2 configuration cannot be modified */
<>	154:37f96f9d4de2	511	status = ERROR;
<>	154:37f96f9d4de2	512	}
<>	154:37f96f9d4de2	513	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	514
<>	154:37f96f9d4de2	515	#if defined(RCC_PLL3_SUPPORT)
<>	154:37f96f9d4de2	516	/* Check if PLL3 is busy*/
<>	154:37f96f9d4de2	517	if (LL_RCC_PLL3_IsReady() != 0U)
<>	154:37f96f9d4de2	518	{
<>	154:37f96f9d4de2	519	/* PLL3 configuration cannot be modified */
<>	154:37f96f9d4de2	520	status = ERROR;
<>	154:37f96f9d4de2	521	}
<>	154:37f96f9d4de2	522	#endif /* RCC_PLL3_SUPPORT */
<>	154:37f96f9d4de2	523
<>	154:37f96f9d4de2	524	return status;
<>	154:37f96f9d4de2	525	}
<>	154:37f96f9d4de2	526
<>	154:37f96f9d4de2	527	/**
<>	154:37f96f9d4de2	528	* @brief Function to enable PLL and switch system clock to PLL
<>	154:37f96f9d4de2	529	* @param SYSCLK_Frequency SYSCLK frequency
<>	154:37f96f9d4de2	530	* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<>	154:37f96f9d4de2	531	* the configuration information for the BUS prescalers.
<>	154:37f96f9d4de2	532	* @retval An ErrorStatus enumeration value:
<>	154:37f96f9d4de2	533	* - SUCCESS: No problem to switch system to PLL
<>	154:37f96f9d4de2	534	* - ERROR: Problem to switch system to PLL
<>	154:37f96f9d4de2	535	*/
<>	154:37f96f9d4de2	536	static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<>	154:37f96f9d4de2	537	{
<>	154:37f96f9d4de2	538	ErrorStatus status = SUCCESS;
<>	154:37f96f9d4de2	539	uint32_t sysclk_frequency_current = 0U;
<>	154:37f96f9d4de2	540
<>	154:37f96f9d4de2	541	assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
<>	154:37f96f9d4de2	542	assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
<>	154:37f96f9d4de2	543	assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
<>	154:37f96f9d4de2	544
<>	154:37f96f9d4de2	545	/* Calculate current SYSCLK frequency */
<>	154:37f96f9d4de2	546	sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]);
<>	154:37f96f9d4de2	547
<>	154:37f96f9d4de2	548	/* Increasing the number of wait states because of higher CPU frequency */
<>	154:37f96f9d4de2	549	#if defined (FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	550	if (sysclk_frequency_current < SYSCLK_Frequency)
<>	154:37f96f9d4de2	551	{
<>	154:37f96f9d4de2	552	/* Set FLASH latency to highest latency */
<>	154:37f96f9d4de2	553	status = UTILS_SetFlashLatency(SYSCLK_Frequency);
<>	154:37f96f9d4de2	554	}
<>	154:37f96f9d4de2	555	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	556
<>	154:37f96f9d4de2	557	/* Update system clock configuration */
<>	154:37f96f9d4de2	558	if (status == SUCCESS)
<>	154:37f96f9d4de2	559	{
<>	154:37f96f9d4de2	560	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	561	/* Enable PLL2 */
<>	154:37f96f9d4de2	562	LL_RCC_PLL2_Enable();
<>	154:37f96f9d4de2	563	while (LL_RCC_PLL2_IsReady() != 1U)
<>	154:37f96f9d4de2	564	{
<>	154:37f96f9d4de2	565	/* Wait for PLL2 ready */
<>	154:37f96f9d4de2	566	}
<>	154:37f96f9d4de2	567
<>	154:37f96f9d4de2	568	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	569	/* Enable PLL */
<>	154:37f96f9d4de2	570	LL_RCC_PLL_Enable();
<>	154:37f96f9d4de2	571	while (LL_RCC_PLL_IsReady() != 1U)
<>	154:37f96f9d4de2	572	{
<>	154:37f96f9d4de2	573	/* Wait for PLL ready */
<>	154:37f96f9d4de2	574	}
<>	154:37f96f9d4de2	575
<>	154:37f96f9d4de2	576	/* Sysclk activation on the main PLL */
<>	154:37f96f9d4de2	577	LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
<>	154:37f96f9d4de2	578	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
<>	154:37f96f9d4de2	579	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
<>	154:37f96f9d4de2	580	{
<>	154:37f96f9d4de2	581	/* Wait for system clock switch to PLL */
<>	154:37f96f9d4de2	582	}
<>	154:37f96f9d4de2	583
<>	154:37f96f9d4de2	584	/* Set APB1 & APB2 prescaler*/
<>	154:37f96f9d4de2	585	LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
<>	154:37f96f9d4de2	586	LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
<>	154:37f96f9d4de2	587	}
<>	154:37f96f9d4de2	588
<>	154:37f96f9d4de2	589	/* Decreasing the number of wait states because of lower CPU frequency */
<>	154:37f96f9d4de2	590	#if defined (FLASH_ACR_LATENCY)
<>	154:37f96f9d4de2	591	if (sysclk_frequency_current > SYSCLK_Frequency)
<>	154:37f96f9d4de2	592	{
<>	154:37f96f9d4de2	593	/* Set FLASH latency to lowest latency */
<>	154:37f96f9d4de2	594	status = UTILS_SetFlashLatency(SYSCLK_Frequency);
<>	154:37f96f9d4de2	595	}
<>	154:37f96f9d4de2	596	#endif /* FLASH_ACR_LATENCY */
<>	154:37f96f9d4de2	597
<>	154:37f96f9d4de2	598	/* Update SystemCoreClock variable */
<>	154:37f96f9d4de2	599	if (status == SUCCESS)
<>	154:37f96f9d4de2	600	{
<>	154:37f96f9d4de2	601	LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
<>	154:37f96f9d4de2	602	}
<>	154:37f96f9d4de2	603
<>	154:37f96f9d4de2	604	return status;
<>	154:37f96f9d4de2	605	}
<>	154:37f96f9d4de2	606
<>	154:37f96f9d4de2	607	/**
<>	154:37f96f9d4de2	608	* @}
<>	154:37f96f9d4de2	609	*/
<>	154:37f96f9d4de2	610
<>	154:37f96f9d4de2	611	/**
<>	154:37f96f9d4de2	612	* @}
<>	154:37f96f9d4de2	613	*/
<>	154:37f96f9d4de2	614
<>	154:37f96f9d4de2	615	/**
<>	154:37f96f9d4de2	616	* @}
<>	154:37f96f9d4de2	617	*/
<>	154:37f96f9d4de2	618
<>	154:37f96f9d4de2	619	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/