mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_ll_sdmmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @brief SDIO Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * This file provides firmware functions to manage the following
AnnaBridge 165:e614a9f1c9e2 8 * functionalities of the SDIO peripheral:
<> 144:ef7eb2e8f9f7 9 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + I/O operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### SDMMC peripheral features #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
AnnaBridge 165:e614a9f1c9e2 18 [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
AnnaBridge 165:e614a9f1c9e2 19 peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
<> 144:ef7eb2e8f9f7 20 devices.
AnnaBridge 165:e614a9f1c9e2 21
AnnaBridge 165:e614a9f1c9e2 22 [..] The SDMMC features include the following:
<> 144:ef7eb2e8f9f7 23 (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
<> 144:ef7eb2e8f9f7 24 for three different databus modes: 1-bit (default), 4-bit and 8-bit
<> 144:ef7eb2e8f9f7 25 (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
<> 144:ef7eb2e8f9f7 26 (+) Full compliance with SD Memory Card Specifications Version 2.0
<> 144:ef7eb2e8f9f7 27 (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
<> 144:ef7eb2e8f9f7 28 different data bus modes: 1-bit (default) and 4-bit
<> 144:ef7eb2e8f9f7 29 (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
<> 144:ef7eb2e8f9f7 30 Rev1.1)
<> 144:ef7eb2e8f9f7 31 (+) Data transfer up to 48 MHz for the 8 bit mode
<> 144:ef7eb2e8f9f7 32 (+) Data and command output enable signals to control external bidirectional drivers.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 36 ==============================================================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 This driver is a considered as a driver of service for external devices drivers
AnnaBridge 165:e614a9f1c9e2 39 that interfaces with the SDMMC peripheral.
AnnaBridge 165:e614a9f1c9e2 40 According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
AnnaBridge 165:e614a9f1c9e2 41 is used in the device's driver to perform SDMMC operations and functionalities.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 This driver is almost transparent for the final user, it is only used to implement other
<> 144:ef7eb2e8f9f7 44 functionalities of the external device.
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 [..]
<> 144:ef7eb2e8f9f7 47 (+) The SDIO peripheral uses two clock signals:
<> 144:ef7eb2e8f9f7 48 (++) SDIO adapter clock (SDIOCLK = HCLK)
<> 144:ef7eb2e8f9f7 49 (++) AHB bus clock (HCLK/2)
<> 144:ef7eb2e8f9f7 50
AnnaBridge 165:e614a9f1c9e2 51 -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
AnnaBridge 165:e614a9f1c9e2 52 Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
<> 144:ef7eb2e8f9f7 53
AnnaBridge 165:e614a9f1c9e2 54 (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
<> 144:ef7eb2e8f9f7 55 peripheral.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
<> 144:ef7eb2e8f9f7 58 function and disable it using the function SDIO_PowerState_OFF(SDIOx).
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
<> 144:ef7eb2e8f9f7 63 and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 (+) When using the DMA mode
<> 144:ef7eb2e8f9f7 66 (++) Configure the DMA in the MSP layer of the external device
<> 144:ef7eb2e8f9f7 67 (++) Active the needed channel Request
<> 144:ef7eb2e8f9f7 68 (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
<> 144:ef7eb2e8f9f7 69 __SDIO_DMA_DISABLE().
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 (+) To control the CPSM (Command Path State Machine) and send
<> 144:ef7eb2e8f9f7 72 commands to the card use the SDIO_SendCommand(),
<> 144:ef7eb2e8f9f7 73 SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
<> 144:ef7eb2e8f9f7 74 to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
<> 144:ef7eb2e8f9f7 75 to the selected command to be sent.
<> 144:ef7eb2e8f9f7 76 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 77 (++) Command Argument
<> 144:ef7eb2e8f9f7 78 (++) Command Index
<> 144:ef7eb2e8f9f7 79 (++) Command Response type
<> 144:ef7eb2e8f9f7 80 (++) Command Wait
<> 144:ef7eb2e8f9f7 81 (++) CPSM Status (Enable or Disable).
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 -@@- To check if the command is well received, read the SDIO_CMDRESP
<> 144:ef7eb2e8f9f7 84 register using the SDIO_GetCommandResponse().
AnnaBridge 165:e614a9f1c9e2 85 The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the
<> 144:ef7eb2e8f9f7 86 SDIO_GetResponse() function.
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 (+) To control the DPSM (Data Path State Machine) and send/receive
AnnaBridge 165:e614a9f1c9e2 89 data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(),
<> 144:ef7eb2e8f9f7 90 SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 *** Read Operations ***
<> 144:ef7eb2e8f9f7 93 =======================
<> 144:ef7eb2e8f9f7 94 [..]
<> 144:ef7eb2e8f9f7 95 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 96 SDIO_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 97 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 98 (++) Data TimeOut
<> 144:ef7eb2e8f9f7 99 (++) Data Length
<> 144:ef7eb2e8f9f7 100 (++) Data Block size
AnnaBridge 165:e614a9f1c9e2 101 (++) Data Transfer direction: should be from card (To SDMMC)
<> 144:ef7eb2e8f9f7 102 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 103 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 104
AnnaBridge 165:e614a9f1c9e2 105 (#) Configure the SDMMC resources to receive the data from the card
AnnaBridge 165:e614a9f1c9e2 106 according to selected transfer mode (Refer to Step 8, 9 and 10).
<> 144:ef7eb2e8f9f7 107
AnnaBridge 165:e614a9f1c9e2 108 (#) Send the selected Read command (refer to step 11).
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 (#) Use the SDIO flags/interrupts to check the transfer status.
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 *** Write Operations ***
<> 144:ef7eb2e8f9f7 113 ========================
<> 144:ef7eb2e8f9f7 114 [..]
<> 144:ef7eb2e8f9f7 115 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 116 SDIO_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 117 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 118 (++) Data TimeOut
<> 144:ef7eb2e8f9f7 119 (++) Data Length
<> 144:ef7eb2e8f9f7 120 (++) Data Block size
<> 144:ef7eb2e8f9f7 121 (++) Data Transfer direction: should be to card (To CARD)
<> 144:ef7eb2e8f9f7 122 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 123 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 124
AnnaBridge 165:e614a9f1c9e2 125 (#) Configure the SDMMC resources to send the data to the card according to
<> 144:ef7eb2e8f9f7 126 selected transfer mode.
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 (#) Send the selected Write command.
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 (#) Use the SDIO flags/interrupts to check the transfer status.
AnnaBridge 165:e614a9f1c9e2 131
AnnaBridge 165:e614a9f1c9e2 132 *** Command management operations ***
AnnaBridge 165:e614a9f1c9e2 133 =====================================
AnnaBridge 165:e614a9f1c9e2 134 [..]
AnnaBridge 165:e614a9f1c9e2 135 (#) The commands used for Read/Write//Erase operations are managed in
AnnaBridge 165:e614a9f1c9e2 136 separate functions.
AnnaBridge 165:e614a9f1c9e2 137 Each function allows to send the needed command with the related argument,
AnnaBridge 165:e614a9f1c9e2 138 then check the response.
AnnaBridge 165:e614a9f1c9e2 139 By the same approach, you could implement a command and check the response.
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 @endverbatim
<> 144:ef7eb2e8f9f7 142 ******************************************************************************
<> 144:ef7eb2e8f9f7 143 * @attention
<> 144:ef7eb2e8f9f7 144 *
AnnaBridge 165:e614a9f1c9e2 145 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 148 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 149 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 150 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 151 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 152 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 153 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 154 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 155 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 156 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 157 *
<> 144:ef7eb2e8f9f7 158 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 159 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 160 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 161 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 162 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 163 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 164 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 165 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 166 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 167 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 168 *
<> 144:ef7eb2e8f9f7 169 ******************************************************************************
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** @defgroup SDMMC_LL SDMMC Low Layer
AnnaBridge 165:e614a9f1c9e2 183 * @brief Low layer module for SD
<> 144:ef7eb2e8f9f7 184 * @{
<> 144:ef7eb2e8f9f7 185 */
AnnaBridge 165:e614a9f1c9e2 186 #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 189 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 190 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 191 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 192 /* Private function prototypes -----------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 193 static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 194 static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
AnnaBridge 165:e614a9f1c9e2 195 static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 196 static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 197 static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 198 static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
<> 144:ef7eb2e8f9f7 199
AnnaBridge 165:e614a9f1c9e2 200 /* Exported functions --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 201
AnnaBridge 165:e614a9f1c9e2 202 /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
<> 144:ef7eb2e8f9f7 203 * @{
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
AnnaBridge 165:e614a9f1c9e2 206 /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
<> 144:ef7eb2e8f9f7 207 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 208 *
<> 144:ef7eb2e8f9f7 209 @verbatim
<> 144:ef7eb2e8f9f7 210 ===============================================================================
<> 144:ef7eb2e8f9f7 211 ##### Initialization/de-initialization functions #####
<> 144:ef7eb2e8f9f7 212 ===============================================================================
<> 144:ef7eb2e8f9f7 213 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 @endverbatim
<> 144:ef7eb2e8f9f7 216 * @{
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /**
AnnaBridge 165:e614a9f1c9e2 220 * @brief Initializes the SDMMC according to the specified
AnnaBridge 165:e614a9f1c9e2 221 * parameters in the SDMMC_InitTypeDef and create the associated handle.
AnnaBridge 165:e614a9f1c9e2 222 * @param SDIOx: Pointer to SDMMC register base
AnnaBridge 165:e614a9f1c9e2 223 * @param Init: SDMMC initialization structure
<> 144:ef7eb2e8f9f7 224 * @retval HAL status
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
<> 144:ef7eb2e8f9f7 227 {
AnnaBridge 165:e614a9f1c9e2 228 uint32_t tmpreg = 0U;
AnnaBridge 165:e614a9f1c9e2 229
<> 144:ef7eb2e8f9f7 230 /* Check the parameters */
<> 144:ef7eb2e8f9f7 231 assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
<> 144:ef7eb2e8f9f7 232 assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
<> 144:ef7eb2e8f9f7 233 assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
<> 144:ef7eb2e8f9f7 234 assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
<> 144:ef7eb2e8f9f7 235 assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
<> 144:ef7eb2e8f9f7 236 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
<> 144:ef7eb2e8f9f7 237 assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
<> 144:ef7eb2e8f9f7 238
AnnaBridge 165:e614a9f1c9e2 239 /* Set SDMMC configuration parameters */
AnnaBridge 165:e614a9f1c9e2 240 tmpreg |= (Init.ClockEdge |\
AnnaBridge 165:e614a9f1c9e2 241 Init.ClockBypass |\
AnnaBridge 165:e614a9f1c9e2 242 Init.ClockPowerSave |\
AnnaBridge 165:e614a9f1c9e2 243 Init.BusWide |\
AnnaBridge 165:e614a9f1c9e2 244 Init.HardwareFlowControl |\
AnnaBridge 165:e614a9f1c9e2 245 Init.ClockDiv
AnnaBridge 165:e614a9f1c9e2 246 );
AnnaBridge 165:e614a9f1c9e2 247
AnnaBridge 165:e614a9f1c9e2 248 /* Write to SDMMC CLKCR */
AnnaBridge 165:e614a9f1c9e2 249 MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 return HAL_OK;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
AnnaBridge 165:e614a9f1c9e2 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 260 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 261 *
<> 144:ef7eb2e8f9f7 262 @verbatim
<> 144:ef7eb2e8f9f7 263 ===============================================================================
AnnaBridge 165:e614a9f1c9e2 264 ##### I/O operation functions #####
AnnaBridge 165:e614a9f1c9e2 265 ===============================================================================
<> 144:ef7eb2e8f9f7 266 [..]
AnnaBridge 165:e614a9f1c9e2 267 This subsection provides a set of functions allowing to manage the SDMMC data
<> 144:ef7eb2e8f9f7 268 transfers.
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 @endverbatim
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief Read data (word) from Rx FIFO in blocking mode (polling)
AnnaBridge 165:e614a9f1c9e2 276 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 277 * @retval HAL status
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* Read data from Rx FIFO */
<> 144:ef7eb2e8f9f7 282 return (SDIOx->FIFO);
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Write data (word) to Tx FIFO in blocking mode (polling)
AnnaBridge 165:e614a9f1c9e2 287 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 288 * @param pWriteData: pointer to data to write
<> 144:ef7eb2e8f9f7 289 * @retval HAL status
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* Write data to FIFO */
<> 144:ef7eb2e8f9f7 294 SDIOx->FIFO = *pWriteData;
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 return HAL_OK;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 304 * @brief management functions
<> 144:ef7eb2e8f9f7 305 *
<> 144:ef7eb2e8f9f7 306 @verbatim
<> 144:ef7eb2e8f9f7 307 ===============================================================================
<> 144:ef7eb2e8f9f7 308 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 309 ===============================================================================
<> 144:ef7eb2e8f9f7 310 [..]
AnnaBridge 165:e614a9f1c9e2 311 This subsection provides a set of functions allowing to control the SDMMC data
<> 144:ef7eb2e8f9f7 312 transfers.
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 @endverbatim
<> 144:ef7eb2e8f9f7 315 * @{
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
AnnaBridge 165:e614a9f1c9e2 319 * @brief Set SDMMC Power state to ON.
AnnaBridge 165:e614a9f1c9e2 320 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 321 * @retval HAL status
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 /* Set power state to ON */
<> 144:ef7eb2e8f9f7 326 SDIOx->POWER = SDIO_POWER_PWRCTRL;
<> 144:ef7eb2e8f9f7 327
AnnaBridge 165:e614a9f1c9e2 328 return HAL_OK;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
AnnaBridge 165:e614a9f1c9e2 332 * @brief Set SDMMC Power state to OFF.
AnnaBridge 165:e614a9f1c9e2 333 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 334 * @retval HAL status
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 /* Set power state to OFF */
AnnaBridge 165:e614a9f1c9e2 339 SDIOx->POWER = 0x00000000U;
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 return HAL_OK;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
AnnaBridge 165:e614a9f1c9e2 345 * @brief Get SDMMC Power state.
AnnaBridge 165:e614a9f1c9e2 346 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 347 * @retval Power status of the controller. The returned value can be one of the
<> 144:ef7eb2e8f9f7 348 * following values:
<> 144:ef7eb2e8f9f7 349 * - 0x00: Power OFF
<> 144:ef7eb2e8f9f7 350 * - 0x02: Power UP
<> 144:ef7eb2e8f9f7 351 * - 0x03: Power ON
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /**
AnnaBridge 165:e614a9f1c9e2 359 * @brief Configure the SDMMC command path according to the specified parameters in
<> 144:ef7eb2e8f9f7 360 * SDIO_CmdInitTypeDef structure and send the command
AnnaBridge 165:e614a9f1c9e2 361 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 362 * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 363 * the configuration information for the SDMMC command
<> 144:ef7eb2e8f9f7 364 * @retval HAL status
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
<> 144:ef7eb2e8f9f7 367 {
AnnaBridge 165:e614a9f1c9e2 368 uint32_t tmpreg = 0U;
AnnaBridge 165:e614a9f1c9e2 369
<> 144:ef7eb2e8f9f7 370 /* Check the parameters */
<> 144:ef7eb2e8f9f7 371 assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
<> 144:ef7eb2e8f9f7 372 assert_param(IS_SDIO_RESPONSE(Command->Response));
<> 144:ef7eb2e8f9f7 373 assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
<> 144:ef7eb2e8f9f7 374 assert_param(IS_SDIO_CPSM(Command->CPSM));
<> 144:ef7eb2e8f9f7 375
AnnaBridge 165:e614a9f1c9e2 376 /* Set the SDMMC Argument value */
<> 144:ef7eb2e8f9f7 377 SDIOx->ARG = Command->Argument;
<> 144:ef7eb2e8f9f7 378
AnnaBridge 165:e614a9f1c9e2 379 /* Set SDMMC command parameters */
AnnaBridge 165:e614a9f1c9e2 380 tmpreg |= (uint32_t)(Command->CmdIndex |\
AnnaBridge 165:e614a9f1c9e2 381 Command->Response |\
AnnaBridge 165:e614a9f1c9e2 382 Command->WaitForInterrupt |\
AnnaBridge 165:e614a9f1c9e2 383 Command->CPSM);
AnnaBridge 165:e614a9f1c9e2 384
AnnaBridge 165:e614a9f1c9e2 385 /* Write to SDMMC CMD register */
AnnaBridge 165:e614a9f1c9e2 386 MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 return HAL_OK;
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @brief Return the command index of last command for which response received
AnnaBridge 165:e614a9f1c9e2 393 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 394 * @retval Command index of the last command response received
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 return (uint8_t)(SDIOx->RESPCMD);
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @brief Return the response received from the card for the last command
AnnaBridge 165:e614a9f1c9e2 404 * @param SDIOx: Pointer to SDMMC register base
AnnaBridge 165:e614a9f1c9e2 405 * @param Response: Specifies the SDMMC response register.
<> 144:ef7eb2e8f9f7 406 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 407 * @arg SDIO_RESP1: Response Register 1
<> 144:ef7eb2e8f9f7 408 * @arg SDIO_RESP2: Response Register 2
<> 144:ef7eb2e8f9f7 409 * @arg SDIO_RESP3: Response Register 3
<> 144:ef7eb2e8f9f7 410 * @arg SDIO_RESP4: Response Register 4
<> 144:ef7eb2e8f9f7 411 * @retval The Corresponding response register value
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
<> 144:ef7eb2e8f9f7 414 {
AnnaBridge 165:e614a9f1c9e2 415 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Check the parameters */
<> 144:ef7eb2e8f9f7 418 assert_param(IS_SDIO_RESP(Response));
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Get the response */
AnnaBridge 165:e614a9f1c9e2 421 tmp = (uint32_t)&(SDIOx->RESP1) + Response;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 return (*(__IO uint32_t *) tmp);
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
AnnaBridge 165:e614a9f1c9e2 427 * @brief Configure the SDMMC data path according to the specified
<> 144:ef7eb2e8f9f7 428 * parameters in the SDIO_DataInitTypeDef.
AnnaBridge 165:e614a9f1c9e2 429 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 430 * @param Data : pointer to a SDIO_DataInitTypeDef structure
AnnaBridge 165:e614a9f1c9e2 431 * that contains the configuration information for the SDMMC data.
<> 144:ef7eb2e8f9f7 432 * @retval HAL status
<> 144:ef7eb2e8f9f7 433 */
AnnaBridge 165:e614a9f1c9e2 434 HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
<> 144:ef7eb2e8f9f7 435 {
AnnaBridge 165:e614a9f1c9e2 436 uint32_t tmpreg = 0U;
AnnaBridge 165:e614a9f1c9e2 437
<> 144:ef7eb2e8f9f7 438 /* Check the parameters */
<> 144:ef7eb2e8f9f7 439 assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
<> 144:ef7eb2e8f9f7 440 assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
<> 144:ef7eb2e8f9f7 441 assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
<> 144:ef7eb2e8f9f7 442 assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
<> 144:ef7eb2e8f9f7 443 assert_param(IS_SDIO_DPSM(Data->DPSM));
<> 144:ef7eb2e8f9f7 444
AnnaBridge 165:e614a9f1c9e2 445 /* Set the SDMMC Data TimeOut value */
<> 144:ef7eb2e8f9f7 446 SDIOx->DTIMER = Data->DataTimeOut;
<> 144:ef7eb2e8f9f7 447
AnnaBridge 165:e614a9f1c9e2 448 /* Set the SDMMC DataLength value */
<> 144:ef7eb2e8f9f7 449 SDIOx->DLEN = Data->DataLength;
<> 144:ef7eb2e8f9f7 450
AnnaBridge 165:e614a9f1c9e2 451 /* Set the SDMMC data configuration parameters */
AnnaBridge 165:e614a9f1c9e2 452 tmpreg |= (uint32_t)(Data->DataBlockSize |\
AnnaBridge 165:e614a9f1c9e2 453 Data->TransferDir |\
AnnaBridge 165:e614a9f1c9e2 454 Data->TransferMode |\
AnnaBridge 165:e614a9f1c9e2 455 Data->DPSM);
AnnaBridge 165:e614a9f1c9e2 456
AnnaBridge 165:e614a9f1c9e2 457 /* Write to SDMMC DCTRL */
AnnaBridge 165:e614a9f1c9e2 458 MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 return HAL_OK;
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @brief Returns number of remaining data bytes to be transferred.
AnnaBridge 165:e614a9f1c9e2 466 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 467 * @retval Number of remaining data bytes to be transferred
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 return (SDIOx->DCOUNT);
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /**
<> 144:ef7eb2e8f9f7 475 * @brief Get the FIFO data
AnnaBridge 165:e614a9f1c9e2 476 * @param SDIOx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 477 * @retval Data received
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 return (SDIOx->FIFO);
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @brief Sets one of the two options of inserting read wait interval.
AnnaBridge 165:e614a9f1c9e2 486 * @param SDIOx: Pointer to SDMMC register base
AnnaBridge 165:e614a9f1c9e2 487 * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
<> 144:ef7eb2e8f9f7 488 * This parameter can be:
AnnaBridge 165:e614a9f1c9e2 489 * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
AnnaBridge 165:e614a9f1c9e2 490 * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
<> 144:ef7eb2e8f9f7 491 * @retval None
<> 144:ef7eb2e8f9f7 492 */
AnnaBridge 165:e614a9f1c9e2 493 HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 /* Check the parameters */
<> 144:ef7eb2e8f9f7 496 assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
AnnaBridge 165:e614a9f1c9e2 497
AnnaBridge 165:e614a9f1c9e2 498 /* Set SDMMC read wait mode */
AnnaBridge 165:e614a9f1c9e2 499 MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 return HAL_OK;
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
AnnaBridge 165:e614a9f1c9e2 504 /**
AnnaBridge 165:e614a9f1c9e2 505 * @}
AnnaBridge 165:e614a9f1c9e2 506 */
AnnaBridge 165:e614a9f1c9e2 507
AnnaBridge 165:e614a9f1c9e2 508
AnnaBridge 165:e614a9f1c9e2 509 /** @defgroup HAL_SDMMC_LL_Group4 Command management functions
AnnaBridge 165:e614a9f1c9e2 510 * @brief Data transfers functions
AnnaBridge 165:e614a9f1c9e2 511 *
AnnaBridge 165:e614a9f1c9e2 512 @verbatim
AnnaBridge 165:e614a9f1c9e2 513 ===============================================================================
AnnaBridge 165:e614a9f1c9e2 514 ##### Commands management functions #####
AnnaBridge 165:e614a9f1c9e2 515 ===============================================================================
AnnaBridge 165:e614a9f1c9e2 516 [..]
AnnaBridge 165:e614a9f1c9e2 517 This subsection provides a set of functions allowing to manage the needed commands.
AnnaBridge 165:e614a9f1c9e2 518
AnnaBridge 165:e614a9f1c9e2 519 @endverbatim
AnnaBridge 165:e614a9f1c9e2 520 * @{
AnnaBridge 165:e614a9f1c9e2 521 */
AnnaBridge 165:e614a9f1c9e2 522
AnnaBridge 165:e614a9f1c9e2 523 /**
AnnaBridge 165:e614a9f1c9e2 524 * @brief Send the Data Block Lenght command and check the response
AnnaBridge 165:e614a9f1c9e2 525 * @param SDIOx: Pointer to SDMMC register base
AnnaBridge 165:e614a9f1c9e2 526 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 527 */
AnnaBridge 165:e614a9f1c9e2 528 uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
AnnaBridge 165:e614a9f1c9e2 529 {
AnnaBridge 165:e614a9f1c9e2 530 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 531 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 532
AnnaBridge 165:e614a9f1c9e2 533 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 534 sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
AnnaBridge 165:e614a9f1c9e2 535 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
AnnaBridge 165:e614a9f1c9e2 536 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 537 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 538 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 539 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 540
AnnaBridge 165:e614a9f1c9e2 541 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 542 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 543
AnnaBridge 165:e614a9f1c9e2 544 return errorstate;
AnnaBridge 165:e614a9f1c9e2 545 }
AnnaBridge 165:e614a9f1c9e2 546
AnnaBridge 165:e614a9f1c9e2 547 /**
AnnaBridge 165:e614a9f1c9e2 548 * @brief Send the Read Single Block command and check the response
AnnaBridge 165:e614a9f1c9e2 549 * @param SDIOx: Pointer to SDMMC register base
AnnaBridge 165:e614a9f1c9e2 550 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 551 */
AnnaBridge 165:e614a9f1c9e2 552 uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
AnnaBridge 165:e614a9f1c9e2 553 {
AnnaBridge 165:e614a9f1c9e2 554 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 555 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 556
AnnaBridge 165:e614a9f1c9e2 557 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 558 sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
AnnaBridge 165:e614a9f1c9e2 559 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
AnnaBridge 165:e614a9f1c9e2 560 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 561 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 562 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 563 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 564
AnnaBridge 165:e614a9f1c9e2 565 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 566 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 567
AnnaBridge 165:e614a9f1c9e2 568 return errorstate;
AnnaBridge 165:e614a9f1c9e2 569 }
AnnaBridge 165:e614a9f1c9e2 570
AnnaBridge 165:e614a9f1c9e2 571 /**
AnnaBridge 165:e614a9f1c9e2 572 * @brief Send the Read Multi Block command and check the response
AnnaBridge 165:e614a9f1c9e2 573 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 574 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 575 */
AnnaBridge 165:e614a9f1c9e2 576 uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
AnnaBridge 165:e614a9f1c9e2 577 {
AnnaBridge 165:e614a9f1c9e2 578 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 579 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 580
AnnaBridge 165:e614a9f1c9e2 581 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 582 sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
AnnaBridge 165:e614a9f1c9e2 583 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
AnnaBridge 165:e614a9f1c9e2 584 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 585 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 586 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 587 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 588
AnnaBridge 165:e614a9f1c9e2 589 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 590 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 591
AnnaBridge 165:e614a9f1c9e2 592 return errorstate;
AnnaBridge 165:e614a9f1c9e2 593 }
AnnaBridge 165:e614a9f1c9e2 594
AnnaBridge 165:e614a9f1c9e2 595 /**
AnnaBridge 165:e614a9f1c9e2 596 * @brief Send the Write Single Block command and check the response
AnnaBridge 165:e614a9f1c9e2 597 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 598 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 599 */
AnnaBridge 165:e614a9f1c9e2 600 uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
AnnaBridge 165:e614a9f1c9e2 601 {
AnnaBridge 165:e614a9f1c9e2 602 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 603 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 604
AnnaBridge 165:e614a9f1c9e2 605 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 606 sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
AnnaBridge 165:e614a9f1c9e2 607 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
AnnaBridge 165:e614a9f1c9e2 608 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 609 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 610 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 611 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 612
AnnaBridge 165:e614a9f1c9e2 613 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 614 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 615
AnnaBridge 165:e614a9f1c9e2 616 return errorstate;
AnnaBridge 165:e614a9f1c9e2 617 }
AnnaBridge 165:e614a9f1c9e2 618
AnnaBridge 165:e614a9f1c9e2 619 /**
AnnaBridge 165:e614a9f1c9e2 620 * @brief Send the Write Multi Block command and check the response
AnnaBridge 165:e614a9f1c9e2 621 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 622 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 623 */
AnnaBridge 165:e614a9f1c9e2 624 uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
AnnaBridge 165:e614a9f1c9e2 625 {
AnnaBridge 165:e614a9f1c9e2 626 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 627 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 628
AnnaBridge 165:e614a9f1c9e2 629 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 630 sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
AnnaBridge 165:e614a9f1c9e2 631 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
AnnaBridge 165:e614a9f1c9e2 632 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 633 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 634 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 635 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 636
AnnaBridge 165:e614a9f1c9e2 637 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 638 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 639
AnnaBridge 165:e614a9f1c9e2 640 return errorstate;
AnnaBridge 165:e614a9f1c9e2 641 }
AnnaBridge 165:e614a9f1c9e2 642
AnnaBridge 165:e614a9f1c9e2 643 /**
AnnaBridge 165:e614a9f1c9e2 644 * @brief Send the Start Address Erase command for SD and check the response
AnnaBridge 165:e614a9f1c9e2 645 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 646 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 647 */
AnnaBridge 165:e614a9f1c9e2 648 uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
AnnaBridge 165:e614a9f1c9e2 649 {
AnnaBridge 165:e614a9f1c9e2 650 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 651 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 652
AnnaBridge 165:e614a9f1c9e2 653 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 654 sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
AnnaBridge 165:e614a9f1c9e2 655 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
AnnaBridge 165:e614a9f1c9e2 656 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 657 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 658 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 659 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 660
AnnaBridge 165:e614a9f1c9e2 661 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 662 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 663
AnnaBridge 165:e614a9f1c9e2 664 return errorstate;
AnnaBridge 165:e614a9f1c9e2 665 }
AnnaBridge 165:e614a9f1c9e2 666
AnnaBridge 165:e614a9f1c9e2 667 /**
AnnaBridge 165:e614a9f1c9e2 668 * @brief Send the End Address Erase command for SD and check the response
AnnaBridge 165:e614a9f1c9e2 669 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 670 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 671 */
AnnaBridge 165:e614a9f1c9e2 672 uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
AnnaBridge 165:e614a9f1c9e2 673 {
AnnaBridge 165:e614a9f1c9e2 674 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 675 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 676
AnnaBridge 165:e614a9f1c9e2 677 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 678 sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
AnnaBridge 165:e614a9f1c9e2 679 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
AnnaBridge 165:e614a9f1c9e2 680 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 681 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 682 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 683 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 684
AnnaBridge 165:e614a9f1c9e2 685 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 686 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 687
AnnaBridge 165:e614a9f1c9e2 688 return errorstate;
AnnaBridge 165:e614a9f1c9e2 689 }
AnnaBridge 165:e614a9f1c9e2 690
AnnaBridge 165:e614a9f1c9e2 691 /**
AnnaBridge 165:e614a9f1c9e2 692 * @brief Send the Start Address Erase command and check the response
AnnaBridge 165:e614a9f1c9e2 693 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 694 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 695 */
AnnaBridge 165:e614a9f1c9e2 696 uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
AnnaBridge 165:e614a9f1c9e2 697 {
AnnaBridge 165:e614a9f1c9e2 698 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 699 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 700
AnnaBridge 165:e614a9f1c9e2 701 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 702 sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
AnnaBridge 165:e614a9f1c9e2 703 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START;
AnnaBridge 165:e614a9f1c9e2 704 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 705 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 706 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 707 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 708
AnnaBridge 165:e614a9f1c9e2 709 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 710 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 711
AnnaBridge 165:e614a9f1c9e2 712 return errorstate;
AnnaBridge 165:e614a9f1c9e2 713 }
AnnaBridge 165:e614a9f1c9e2 714
AnnaBridge 165:e614a9f1c9e2 715 /**
AnnaBridge 165:e614a9f1c9e2 716 * @brief Send the End Address Erase command and check the response
AnnaBridge 165:e614a9f1c9e2 717 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 718 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 719 */
AnnaBridge 165:e614a9f1c9e2 720 uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
AnnaBridge 165:e614a9f1c9e2 721 {
AnnaBridge 165:e614a9f1c9e2 722 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 723 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 724
AnnaBridge 165:e614a9f1c9e2 725 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 726 sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
AnnaBridge 165:e614a9f1c9e2 727 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END;
AnnaBridge 165:e614a9f1c9e2 728 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 729 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 730 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 731 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 732
AnnaBridge 165:e614a9f1c9e2 733 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 734 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 735
AnnaBridge 165:e614a9f1c9e2 736 return errorstate;
AnnaBridge 165:e614a9f1c9e2 737 }
AnnaBridge 165:e614a9f1c9e2 738
AnnaBridge 165:e614a9f1c9e2 739 /**
AnnaBridge 165:e614a9f1c9e2 740 * @brief Send the Erase command and check the response
AnnaBridge 165:e614a9f1c9e2 741 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 742 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 743 */
AnnaBridge 165:e614a9f1c9e2 744 uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 745 {
AnnaBridge 165:e614a9f1c9e2 746 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 747 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 748
AnnaBridge 165:e614a9f1c9e2 749 /* Set Block Size for Card */
AnnaBridge 165:e614a9f1c9e2 750 sdmmc_cmdinit.Argument = 0U;
AnnaBridge 165:e614a9f1c9e2 751 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
AnnaBridge 165:e614a9f1c9e2 752 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 753 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 754 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 755 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 756
AnnaBridge 165:e614a9f1c9e2 757 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 758 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
AnnaBridge 165:e614a9f1c9e2 759
AnnaBridge 165:e614a9f1c9e2 760 return errorstate;
AnnaBridge 165:e614a9f1c9e2 761 }
AnnaBridge 165:e614a9f1c9e2 762
AnnaBridge 165:e614a9f1c9e2 763 /**
AnnaBridge 165:e614a9f1c9e2 764 * @brief Send the Stop Transfer command and check the response.
AnnaBridge 165:e614a9f1c9e2 765 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 766 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 767 */
AnnaBridge 165:e614a9f1c9e2 768 uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 769 {
AnnaBridge 165:e614a9f1c9e2 770 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 771 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 772
AnnaBridge 165:e614a9f1c9e2 773 /* Send CMD12 STOP_TRANSMISSION */
AnnaBridge 165:e614a9f1c9e2 774 sdmmc_cmdinit.Argument = 0U;
AnnaBridge 165:e614a9f1c9e2 775 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
AnnaBridge 165:e614a9f1c9e2 776 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 777 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 778 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 779 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 780
AnnaBridge 165:e614a9f1c9e2 781 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 782 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, 100000000U);
AnnaBridge 165:e614a9f1c9e2 783
AnnaBridge 165:e614a9f1c9e2 784 return errorstate;
AnnaBridge 165:e614a9f1c9e2 785 }
AnnaBridge 165:e614a9f1c9e2 786
AnnaBridge 165:e614a9f1c9e2 787 /**
AnnaBridge 165:e614a9f1c9e2 788 * @brief Send the Select Deselect command and check the response.
AnnaBridge 165:e614a9f1c9e2 789 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 790 * @param addr: Address of the card to be selected
AnnaBridge 165:e614a9f1c9e2 791 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 792 */
AnnaBridge 165:e614a9f1c9e2 793 uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
AnnaBridge 165:e614a9f1c9e2 794 {
AnnaBridge 165:e614a9f1c9e2 795 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 796 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 797
AnnaBridge 165:e614a9f1c9e2 798 /* Send CMD7 SDMMC_SEL_DESEL_CARD */
AnnaBridge 165:e614a9f1c9e2 799 sdmmc_cmdinit.Argument = (uint32_t)Addr;
AnnaBridge 165:e614a9f1c9e2 800 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
AnnaBridge 165:e614a9f1c9e2 801 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 802 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 803 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 804 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 805
AnnaBridge 165:e614a9f1c9e2 806 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 807 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 808
AnnaBridge 165:e614a9f1c9e2 809 return errorstate;
AnnaBridge 165:e614a9f1c9e2 810 }
AnnaBridge 165:e614a9f1c9e2 811
AnnaBridge 165:e614a9f1c9e2 812 /**
AnnaBridge 165:e614a9f1c9e2 813 * @brief Send the Go Idle State command and check the response.
AnnaBridge 165:e614a9f1c9e2 814 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 815 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 816 */
AnnaBridge 165:e614a9f1c9e2 817 uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 818 {
AnnaBridge 165:e614a9f1c9e2 819 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 820 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 821
AnnaBridge 165:e614a9f1c9e2 822 sdmmc_cmdinit.Argument = 0U;
AnnaBridge 165:e614a9f1c9e2 823 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
AnnaBridge 165:e614a9f1c9e2 824 sdmmc_cmdinit.Response = SDIO_RESPONSE_NO;
AnnaBridge 165:e614a9f1c9e2 825 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 826 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 827 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 828
AnnaBridge 165:e614a9f1c9e2 829 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 830 errorstate = SDMMC_GetCmdError(SDIOx);
AnnaBridge 165:e614a9f1c9e2 831
AnnaBridge 165:e614a9f1c9e2 832 return errorstate;
AnnaBridge 165:e614a9f1c9e2 833 }
AnnaBridge 165:e614a9f1c9e2 834
AnnaBridge 165:e614a9f1c9e2 835 /**
AnnaBridge 165:e614a9f1c9e2 836 * @brief Send the Operating Condition command and check the response.
AnnaBridge 165:e614a9f1c9e2 837 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 838 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 839 */
AnnaBridge 165:e614a9f1c9e2 840 uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 841 {
AnnaBridge 165:e614a9f1c9e2 842 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 843 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 844
AnnaBridge 165:e614a9f1c9e2 845 /* Send CMD8 to verify SD card interface operating condition */
AnnaBridge 165:e614a9f1c9e2 846 /* Argument: - [31:12]: Reserved (shall be set to '0')
AnnaBridge 165:e614a9f1c9e2 847 - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
AnnaBridge 165:e614a9f1c9e2 848 - [7:0]: Check Pattern (recommended 0xAA) */
AnnaBridge 165:e614a9f1c9e2 849 /* CMD Response: R7 */
AnnaBridge 165:e614a9f1c9e2 850 sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN;
AnnaBridge 165:e614a9f1c9e2 851 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
AnnaBridge 165:e614a9f1c9e2 852 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 853 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 854 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 855 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 856
AnnaBridge 165:e614a9f1c9e2 857 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 858 errorstate = SDMMC_GetCmdResp7(SDIOx);
AnnaBridge 165:e614a9f1c9e2 859
AnnaBridge 165:e614a9f1c9e2 860 return errorstate;
AnnaBridge 165:e614a9f1c9e2 861 }
AnnaBridge 165:e614a9f1c9e2 862
AnnaBridge 165:e614a9f1c9e2 863 /**
AnnaBridge 165:e614a9f1c9e2 864 * @brief Send the Application command to verify that that the next command
AnnaBridge 165:e614a9f1c9e2 865 * is an application specific com-mand rather than a standard command
AnnaBridge 165:e614a9f1c9e2 866 * and check the response.
AnnaBridge 165:e614a9f1c9e2 867 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 868 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 869 */
AnnaBridge 165:e614a9f1c9e2 870 uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
AnnaBridge 165:e614a9f1c9e2 871 {
AnnaBridge 165:e614a9f1c9e2 872 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 873 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 874
AnnaBridge 165:e614a9f1c9e2 875 sdmmc_cmdinit.Argument = (uint32_t)Argument;
AnnaBridge 165:e614a9f1c9e2 876 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
AnnaBridge 165:e614a9f1c9e2 877 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 878 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 879 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 880 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 881
AnnaBridge 165:e614a9f1c9e2 882 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 883 /* If there is a HAL_ERROR, it is a MMC card, else
AnnaBridge 165:e614a9f1c9e2 884 it is a SD card: SD card 2.0 (voltage range mismatch)
AnnaBridge 165:e614a9f1c9e2 885 or SD card 1.x */
AnnaBridge 165:e614a9f1c9e2 886 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 887
AnnaBridge 165:e614a9f1c9e2 888 return errorstate;
AnnaBridge 165:e614a9f1c9e2 889 }
AnnaBridge 165:e614a9f1c9e2 890
AnnaBridge 165:e614a9f1c9e2 891 /**
AnnaBridge 165:e614a9f1c9e2 892 * @brief Send the command asking the accessed card to send its operating
AnnaBridge 165:e614a9f1c9e2 893 * condition register (OCR)
AnnaBridge 165:e614a9f1c9e2 894 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 895 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 896 */
AnnaBridge 165:e614a9f1c9e2 897 uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType)
AnnaBridge 165:e614a9f1c9e2 898 {
AnnaBridge 165:e614a9f1c9e2 899 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 900 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 901
AnnaBridge 165:e614a9f1c9e2 902 sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType;
AnnaBridge 165:e614a9f1c9e2 903 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
AnnaBridge 165:e614a9f1c9e2 904 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 905 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 906 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 907 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 908
AnnaBridge 165:e614a9f1c9e2 909 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 910 errorstate = SDMMC_GetCmdResp3(SDIOx);
AnnaBridge 165:e614a9f1c9e2 911
AnnaBridge 165:e614a9f1c9e2 912 return errorstate;
AnnaBridge 165:e614a9f1c9e2 913 }
AnnaBridge 165:e614a9f1c9e2 914
AnnaBridge 165:e614a9f1c9e2 915 /**
AnnaBridge 165:e614a9f1c9e2 916 * @brief Send the Bus Width command and check the response.
AnnaBridge 165:e614a9f1c9e2 917 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 918 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 919 */
AnnaBridge 165:e614a9f1c9e2 920 uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
AnnaBridge 165:e614a9f1c9e2 921 {
AnnaBridge 165:e614a9f1c9e2 922 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 923 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 924
AnnaBridge 165:e614a9f1c9e2 925 sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
AnnaBridge 165:e614a9f1c9e2 926 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
AnnaBridge 165:e614a9f1c9e2 927 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 928 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 929 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 930 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 931
AnnaBridge 165:e614a9f1c9e2 932 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 933 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 934
AnnaBridge 165:e614a9f1c9e2 935 return errorstate;
AnnaBridge 165:e614a9f1c9e2 936 }
AnnaBridge 165:e614a9f1c9e2 937
AnnaBridge 165:e614a9f1c9e2 938 /**
AnnaBridge 165:e614a9f1c9e2 939 * @brief Send the Send SCR command and check the response.
AnnaBridge 165:e614a9f1c9e2 940 * @param SDIOx: Pointer to SDMMC register base
AnnaBridge 165:e614a9f1c9e2 941 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 942 */
AnnaBridge 165:e614a9f1c9e2 943 uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 944 {
AnnaBridge 165:e614a9f1c9e2 945 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 946 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 947
AnnaBridge 165:e614a9f1c9e2 948 /* Send CMD51 SD_APP_SEND_SCR */
AnnaBridge 165:e614a9f1c9e2 949 sdmmc_cmdinit.Argument = 0U;
AnnaBridge 165:e614a9f1c9e2 950 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
AnnaBridge 165:e614a9f1c9e2 951 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 952 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 953 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 954 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 955
AnnaBridge 165:e614a9f1c9e2 956 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 957 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 958
AnnaBridge 165:e614a9f1c9e2 959 return errorstate;
AnnaBridge 165:e614a9f1c9e2 960 }
AnnaBridge 165:e614a9f1c9e2 961
AnnaBridge 165:e614a9f1c9e2 962 /**
AnnaBridge 165:e614a9f1c9e2 963 * @brief Send the Send CID command and check the response.
AnnaBridge 165:e614a9f1c9e2 964 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 965 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 966 */
AnnaBridge 165:e614a9f1c9e2 967 uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 968 {
AnnaBridge 165:e614a9f1c9e2 969 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 970 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 971
AnnaBridge 165:e614a9f1c9e2 972 /* Send CMD2 ALL_SEND_CID */
AnnaBridge 165:e614a9f1c9e2 973 sdmmc_cmdinit.Argument = 0U;
AnnaBridge 165:e614a9f1c9e2 974 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
AnnaBridge 165:e614a9f1c9e2 975 sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
AnnaBridge 165:e614a9f1c9e2 976 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 977 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 978 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 979
AnnaBridge 165:e614a9f1c9e2 980 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 981 errorstate = SDMMC_GetCmdResp2(SDIOx);
AnnaBridge 165:e614a9f1c9e2 982
AnnaBridge 165:e614a9f1c9e2 983 return errorstate;
AnnaBridge 165:e614a9f1c9e2 984 }
AnnaBridge 165:e614a9f1c9e2 985
AnnaBridge 165:e614a9f1c9e2 986 /**
AnnaBridge 165:e614a9f1c9e2 987 * @brief Send the Send CSD command and check the response.
AnnaBridge 165:e614a9f1c9e2 988 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 989 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 990 */
AnnaBridge 165:e614a9f1c9e2 991 uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
AnnaBridge 165:e614a9f1c9e2 992 {
AnnaBridge 165:e614a9f1c9e2 993 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 994 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 995
AnnaBridge 165:e614a9f1c9e2 996 /* Send CMD9 SEND_CSD */
AnnaBridge 165:e614a9f1c9e2 997 sdmmc_cmdinit.Argument = (uint32_t)Argument;
AnnaBridge 165:e614a9f1c9e2 998 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
AnnaBridge 165:e614a9f1c9e2 999 sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
AnnaBridge 165:e614a9f1c9e2 1000 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 1001 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 1002 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 1003
AnnaBridge 165:e614a9f1c9e2 1004 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 1005 errorstate = SDMMC_GetCmdResp2(SDIOx);
AnnaBridge 165:e614a9f1c9e2 1006
AnnaBridge 165:e614a9f1c9e2 1007 return errorstate;
AnnaBridge 165:e614a9f1c9e2 1008 }
AnnaBridge 165:e614a9f1c9e2 1009
AnnaBridge 165:e614a9f1c9e2 1010 /**
AnnaBridge 165:e614a9f1c9e2 1011 * @brief Send the Send CSD command and check the response.
AnnaBridge 165:e614a9f1c9e2 1012 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 1013 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 1014 */
AnnaBridge 165:e614a9f1c9e2 1015 uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
AnnaBridge 165:e614a9f1c9e2 1016 {
AnnaBridge 165:e614a9f1c9e2 1017 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 1018 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1019
AnnaBridge 165:e614a9f1c9e2 1020 /* Send CMD3 SD_CMD_SET_REL_ADDR */
AnnaBridge 165:e614a9f1c9e2 1021 sdmmc_cmdinit.Argument = 0U;
AnnaBridge 165:e614a9f1c9e2 1022 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
AnnaBridge 165:e614a9f1c9e2 1023 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 1024 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 1025 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 1026 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 1027
AnnaBridge 165:e614a9f1c9e2 1028 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 1029 errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
AnnaBridge 165:e614a9f1c9e2 1030
AnnaBridge 165:e614a9f1c9e2 1031 return errorstate;
AnnaBridge 165:e614a9f1c9e2 1032 }
AnnaBridge 165:e614a9f1c9e2 1033
AnnaBridge 165:e614a9f1c9e2 1034 /**
AnnaBridge 165:e614a9f1c9e2 1035 * @brief Send the Status command and check the response.
AnnaBridge 165:e614a9f1c9e2 1036 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 1037 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 1038 */
AnnaBridge 165:e614a9f1c9e2 1039 uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
AnnaBridge 165:e614a9f1c9e2 1040 {
AnnaBridge 165:e614a9f1c9e2 1041 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 1042 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1043
AnnaBridge 165:e614a9f1c9e2 1044 sdmmc_cmdinit.Argument = (uint32_t)Argument;
AnnaBridge 165:e614a9f1c9e2 1045 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
AnnaBridge 165:e614a9f1c9e2 1046 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 1047 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 1048 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 1049 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 1050
AnnaBridge 165:e614a9f1c9e2 1051 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 1052 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1053
AnnaBridge 165:e614a9f1c9e2 1054 return errorstate;
AnnaBridge 165:e614a9f1c9e2 1055 }
AnnaBridge 165:e614a9f1c9e2 1056
AnnaBridge 165:e614a9f1c9e2 1057 /**
AnnaBridge 165:e614a9f1c9e2 1058 * @brief Send the Status register command and check the response.
AnnaBridge 165:e614a9f1c9e2 1059 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 1060 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 1061 */
AnnaBridge 165:e614a9f1c9e2 1062 uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 1063 {
AnnaBridge 165:e614a9f1c9e2 1064 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 1065 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1066
AnnaBridge 165:e614a9f1c9e2 1067 sdmmc_cmdinit.Argument = 0U;
AnnaBridge 165:e614a9f1c9e2 1068 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
AnnaBridge 165:e614a9f1c9e2 1069 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 1070 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 1071 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 1072 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 1073
AnnaBridge 165:e614a9f1c9e2 1074 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 1075 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1076
AnnaBridge 165:e614a9f1c9e2 1077 return errorstate;
AnnaBridge 165:e614a9f1c9e2 1078 }
AnnaBridge 165:e614a9f1c9e2 1079
AnnaBridge 165:e614a9f1c9e2 1080 /**
AnnaBridge 165:e614a9f1c9e2 1081 * @brief Sends host capacity support information and activates the card's
AnnaBridge 165:e614a9f1c9e2 1082 * initialization process. Send SDMMC_CMD_SEND_OP_COND command
AnnaBridge 165:e614a9f1c9e2 1083 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 1084 * @parame Argument: Argument used for the command
AnnaBridge 165:e614a9f1c9e2 1085 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 1086 */
AnnaBridge 165:e614a9f1c9e2 1087 uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
AnnaBridge 165:e614a9f1c9e2 1088 {
AnnaBridge 165:e614a9f1c9e2 1089 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 1090 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1091
AnnaBridge 165:e614a9f1c9e2 1092 sdmmc_cmdinit.Argument = Argument;
AnnaBridge 165:e614a9f1c9e2 1093 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
AnnaBridge 165:e614a9f1c9e2 1094 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 1095 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 1096 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 1097 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 1098
AnnaBridge 165:e614a9f1c9e2 1099 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 1100 errorstate = SDMMC_GetCmdResp3(SDIOx);
AnnaBridge 165:e614a9f1c9e2 1101
AnnaBridge 165:e614a9f1c9e2 1102 return errorstate;
AnnaBridge 165:e614a9f1c9e2 1103 }
AnnaBridge 165:e614a9f1c9e2 1104
AnnaBridge 165:e614a9f1c9e2 1105 /**
AnnaBridge 165:e614a9f1c9e2 1106 * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
AnnaBridge 165:e614a9f1c9e2 1107 * @param SDIOx: Pointer to SDIO register base
AnnaBridge 165:e614a9f1c9e2 1108 * @parame Argument: Argument used for the command
AnnaBridge 165:e614a9f1c9e2 1109 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 1110 */
AnnaBridge 165:e614a9f1c9e2 1111 uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
AnnaBridge 165:e614a9f1c9e2 1112 {
AnnaBridge 165:e614a9f1c9e2 1113 SDIO_CmdInitTypeDef sdmmc_cmdinit;
AnnaBridge 165:e614a9f1c9e2 1114 uint32_t errorstate = SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1115
AnnaBridge 165:e614a9f1c9e2 1116 sdmmc_cmdinit.Argument = Argument;
AnnaBridge 165:e614a9f1c9e2 1117 sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
AnnaBridge 165:e614a9f1c9e2 1118 sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
AnnaBridge 165:e614a9f1c9e2 1119 sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
AnnaBridge 165:e614a9f1c9e2 1120 sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
AnnaBridge 165:e614a9f1c9e2 1121 SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
AnnaBridge 165:e614a9f1c9e2 1122
AnnaBridge 165:e614a9f1c9e2 1123 /* Check for error conditions */
AnnaBridge 165:e614a9f1c9e2 1124 errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1125
AnnaBridge 165:e614a9f1c9e2 1126 return errorstate;
AnnaBridge 165:e614a9f1c9e2 1127 }
AnnaBridge 165:e614a9f1c9e2 1128
AnnaBridge 165:e614a9f1c9e2 1129 /**
AnnaBridge 165:e614a9f1c9e2 1130 * @}
AnnaBridge 165:e614a9f1c9e2 1131 */
AnnaBridge 165:e614a9f1c9e2 1132
AnnaBridge 165:e614a9f1c9e2 1133 /* Private function ----------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 1134 /** @addtogroup SD_Private_Functions
AnnaBridge 165:e614a9f1c9e2 1135 * @{
AnnaBridge 165:e614a9f1c9e2 1136 */
AnnaBridge 165:e614a9f1c9e2 1137
AnnaBridge 165:e614a9f1c9e2 1138 /**
AnnaBridge 165:e614a9f1c9e2 1139 * @brief Checks for error conditions for CMD0.
AnnaBridge 165:e614a9f1c9e2 1140 * @param hsd: SD handle
AnnaBridge 165:e614a9f1c9e2 1141 * @retval SD Card error state
AnnaBridge 165:e614a9f1c9e2 1142 */
AnnaBridge 165:e614a9f1c9e2 1143 static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 1144 {
AnnaBridge 165:e614a9f1c9e2 1145 /* 8 is the number of required instructions cycles for the below loop statement.
AnnaBridge 165:e614a9f1c9e2 1146 The SDMMC_CMDTIMEOUT is expressed in ms */
AnnaBridge 165:e614a9f1c9e2 1147 register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
AnnaBridge 165:e614a9f1c9e2 1148
AnnaBridge 165:e614a9f1c9e2 1149 do
AnnaBridge 165:e614a9f1c9e2 1150 {
AnnaBridge 165:e614a9f1c9e2 1151 if (count-- == 0U)
AnnaBridge 165:e614a9f1c9e2 1152 {
AnnaBridge 165:e614a9f1c9e2 1153 return SDMMC_ERROR_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1154 }
AnnaBridge 165:e614a9f1c9e2 1155
AnnaBridge 165:e614a9f1c9e2 1156 }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
AnnaBridge 165:e614a9f1c9e2 1157
AnnaBridge 165:e614a9f1c9e2 1158 /* Clear all the static flags */
AnnaBridge 165:e614a9f1c9e2 1159 __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
AnnaBridge 165:e614a9f1c9e2 1160
AnnaBridge 165:e614a9f1c9e2 1161 return SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1162 }
AnnaBridge 165:e614a9f1c9e2 1163
AnnaBridge 165:e614a9f1c9e2 1164 /**
AnnaBridge 165:e614a9f1c9e2 1165 * @brief Checks for error conditions for R1 response.
AnnaBridge 165:e614a9f1c9e2 1166 * @param hsd: SD handle
AnnaBridge 165:e614a9f1c9e2 1167 * @param SD_CMD: The sent command index
AnnaBridge 165:e614a9f1c9e2 1168 * @retval SD Card error state
AnnaBridge 165:e614a9f1c9e2 1169 */
AnnaBridge 165:e614a9f1c9e2 1170 static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
AnnaBridge 165:e614a9f1c9e2 1171 {
AnnaBridge 165:e614a9f1c9e2 1172 uint32_t response_r1;
AnnaBridge 165:e614a9f1c9e2 1173
AnnaBridge 165:e614a9f1c9e2 1174 /* 8 is the number of required instructions cycles for the below loop statement.
AnnaBridge 165:e614a9f1c9e2 1175 The Timeout is expressed in ms */
AnnaBridge 165:e614a9f1c9e2 1176 register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
AnnaBridge 165:e614a9f1c9e2 1177
AnnaBridge 165:e614a9f1c9e2 1178 do
AnnaBridge 165:e614a9f1c9e2 1179 {
AnnaBridge 165:e614a9f1c9e2 1180 if (count-- == 0U)
AnnaBridge 165:e614a9f1c9e2 1181 {
AnnaBridge 165:e614a9f1c9e2 1182 return SDMMC_ERROR_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1183 }
AnnaBridge 165:e614a9f1c9e2 1184
AnnaBridge 165:e614a9f1c9e2 1185 }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
AnnaBridge 165:e614a9f1c9e2 1186
AnnaBridge 165:e614a9f1c9e2 1187 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
AnnaBridge 165:e614a9f1c9e2 1188 {
AnnaBridge 165:e614a9f1c9e2 1189 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1190
AnnaBridge 165:e614a9f1c9e2 1191 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1192 }
AnnaBridge 165:e614a9f1c9e2 1193 else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
AnnaBridge 165:e614a9f1c9e2 1194 {
AnnaBridge 165:e614a9f1c9e2 1195 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
AnnaBridge 165:e614a9f1c9e2 1196
AnnaBridge 165:e614a9f1c9e2 1197 return SDMMC_ERROR_CMD_CRC_FAIL;
AnnaBridge 165:e614a9f1c9e2 1198 }
AnnaBridge 165:e614a9f1c9e2 1199
AnnaBridge 165:e614a9f1c9e2 1200 /* Check response received is of desired command */
AnnaBridge 165:e614a9f1c9e2 1201 if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
AnnaBridge 165:e614a9f1c9e2 1202 {
AnnaBridge 165:e614a9f1c9e2 1203 return SDMMC_ERROR_CMD_CRC_FAIL;
AnnaBridge 165:e614a9f1c9e2 1204 }
AnnaBridge 165:e614a9f1c9e2 1205
AnnaBridge 165:e614a9f1c9e2 1206 /* Clear all the static flags */
AnnaBridge 165:e614a9f1c9e2 1207 __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
AnnaBridge 165:e614a9f1c9e2 1208
AnnaBridge 165:e614a9f1c9e2 1209 /* We have received response, retrieve it for analysis */
AnnaBridge 165:e614a9f1c9e2 1210 response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
AnnaBridge 165:e614a9f1c9e2 1211
AnnaBridge 165:e614a9f1c9e2 1212 if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
AnnaBridge 165:e614a9f1c9e2 1213 {
AnnaBridge 165:e614a9f1c9e2 1214 return SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1215 }
AnnaBridge 165:e614a9f1c9e2 1216 else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
AnnaBridge 165:e614a9f1c9e2 1217 {
AnnaBridge 165:e614a9f1c9e2 1218 return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
AnnaBridge 165:e614a9f1c9e2 1219 }
AnnaBridge 165:e614a9f1c9e2 1220 else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
AnnaBridge 165:e614a9f1c9e2 1221 {
AnnaBridge 165:e614a9f1c9e2 1222 return SDMMC_ERROR_ADDR_MISALIGNED;
AnnaBridge 165:e614a9f1c9e2 1223 }
AnnaBridge 165:e614a9f1c9e2 1224 else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
AnnaBridge 165:e614a9f1c9e2 1225 {
AnnaBridge 165:e614a9f1c9e2 1226 return SDMMC_ERROR_BLOCK_LEN_ERR;
AnnaBridge 165:e614a9f1c9e2 1227 }
AnnaBridge 165:e614a9f1c9e2 1228 else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
AnnaBridge 165:e614a9f1c9e2 1229 {
AnnaBridge 165:e614a9f1c9e2 1230 return SDMMC_ERROR_ERASE_SEQ_ERR;
AnnaBridge 165:e614a9f1c9e2 1231 }
AnnaBridge 165:e614a9f1c9e2 1232 else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
AnnaBridge 165:e614a9f1c9e2 1233 {
AnnaBridge 165:e614a9f1c9e2 1234 return SDMMC_ERROR_BAD_ERASE_PARAM;
AnnaBridge 165:e614a9f1c9e2 1235 }
AnnaBridge 165:e614a9f1c9e2 1236 else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
AnnaBridge 165:e614a9f1c9e2 1237 {
AnnaBridge 165:e614a9f1c9e2 1238 return SDMMC_ERROR_WRITE_PROT_VIOLATION;
AnnaBridge 165:e614a9f1c9e2 1239 }
AnnaBridge 165:e614a9f1c9e2 1240 else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
AnnaBridge 165:e614a9f1c9e2 1241 {
AnnaBridge 165:e614a9f1c9e2 1242 return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
AnnaBridge 165:e614a9f1c9e2 1243 }
AnnaBridge 165:e614a9f1c9e2 1244 else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
AnnaBridge 165:e614a9f1c9e2 1245 {
AnnaBridge 165:e614a9f1c9e2 1246 return SDMMC_ERROR_COM_CRC_FAILED;
AnnaBridge 165:e614a9f1c9e2 1247 }
AnnaBridge 165:e614a9f1c9e2 1248 else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
AnnaBridge 165:e614a9f1c9e2 1249 {
AnnaBridge 165:e614a9f1c9e2 1250 return SDMMC_ERROR_ILLEGAL_CMD;
AnnaBridge 165:e614a9f1c9e2 1251 }
AnnaBridge 165:e614a9f1c9e2 1252 else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
AnnaBridge 165:e614a9f1c9e2 1253 {
AnnaBridge 165:e614a9f1c9e2 1254 return SDMMC_ERROR_CARD_ECC_FAILED;
AnnaBridge 165:e614a9f1c9e2 1255 }
AnnaBridge 165:e614a9f1c9e2 1256 else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
AnnaBridge 165:e614a9f1c9e2 1257 {
AnnaBridge 165:e614a9f1c9e2 1258 return SDMMC_ERROR_CC_ERR;
AnnaBridge 165:e614a9f1c9e2 1259 }
AnnaBridge 165:e614a9f1c9e2 1260 else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
AnnaBridge 165:e614a9f1c9e2 1261 {
AnnaBridge 165:e614a9f1c9e2 1262 return SDMMC_ERROR_STREAM_READ_UNDERRUN;
AnnaBridge 165:e614a9f1c9e2 1263 }
AnnaBridge 165:e614a9f1c9e2 1264 else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
AnnaBridge 165:e614a9f1c9e2 1265 {
AnnaBridge 165:e614a9f1c9e2 1266 return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
AnnaBridge 165:e614a9f1c9e2 1267 }
AnnaBridge 165:e614a9f1c9e2 1268 else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
AnnaBridge 165:e614a9f1c9e2 1269 {
AnnaBridge 165:e614a9f1c9e2 1270 return SDMMC_ERROR_CID_CSD_OVERWRITE;
AnnaBridge 165:e614a9f1c9e2 1271 }
AnnaBridge 165:e614a9f1c9e2 1272 else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
AnnaBridge 165:e614a9f1c9e2 1273 {
AnnaBridge 165:e614a9f1c9e2 1274 return SDMMC_ERROR_WP_ERASE_SKIP;
AnnaBridge 165:e614a9f1c9e2 1275 }
AnnaBridge 165:e614a9f1c9e2 1276 else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
AnnaBridge 165:e614a9f1c9e2 1277 {
AnnaBridge 165:e614a9f1c9e2 1278 return SDMMC_ERROR_CARD_ECC_DISABLED;
AnnaBridge 165:e614a9f1c9e2 1279 }
AnnaBridge 165:e614a9f1c9e2 1280 else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
AnnaBridge 165:e614a9f1c9e2 1281 {
AnnaBridge 165:e614a9f1c9e2 1282 return SDMMC_ERROR_ERASE_RESET;
AnnaBridge 165:e614a9f1c9e2 1283 }
AnnaBridge 165:e614a9f1c9e2 1284 else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
AnnaBridge 165:e614a9f1c9e2 1285 {
AnnaBridge 165:e614a9f1c9e2 1286 return SDMMC_ERROR_AKE_SEQ_ERR;
AnnaBridge 165:e614a9f1c9e2 1287 }
AnnaBridge 165:e614a9f1c9e2 1288 else
AnnaBridge 165:e614a9f1c9e2 1289 {
AnnaBridge 165:e614a9f1c9e2 1290 return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
AnnaBridge 165:e614a9f1c9e2 1291 }
AnnaBridge 165:e614a9f1c9e2 1292 }
AnnaBridge 165:e614a9f1c9e2 1293
AnnaBridge 165:e614a9f1c9e2 1294 /**
AnnaBridge 165:e614a9f1c9e2 1295 * @brief Checks for error conditions for R2 (CID or CSD) response.
AnnaBridge 165:e614a9f1c9e2 1296 * @param hsd: SD handle
AnnaBridge 165:e614a9f1c9e2 1297 * @retval SD Card error state
AnnaBridge 165:e614a9f1c9e2 1298 */
AnnaBridge 165:e614a9f1c9e2 1299 static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 1300 {
AnnaBridge 165:e614a9f1c9e2 1301 /* 8 is the number of required instructions cycles for the below loop statement.
AnnaBridge 165:e614a9f1c9e2 1302 The SDMMC_CMDTIMEOUT is expressed in ms */
AnnaBridge 165:e614a9f1c9e2 1303 register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
AnnaBridge 165:e614a9f1c9e2 1304
AnnaBridge 165:e614a9f1c9e2 1305 do
AnnaBridge 165:e614a9f1c9e2 1306 {
AnnaBridge 165:e614a9f1c9e2 1307 if (count-- == 0U)
AnnaBridge 165:e614a9f1c9e2 1308 {
AnnaBridge 165:e614a9f1c9e2 1309 return SDMMC_ERROR_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1310 }
AnnaBridge 165:e614a9f1c9e2 1311
AnnaBridge 165:e614a9f1c9e2 1312 }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
AnnaBridge 165:e614a9f1c9e2 1313
AnnaBridge 165:e614a9f1c9e2 1314 if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
AnnaBridge 165:e614a9f1c9e2 1315 {
AnnaBridge 165:e614a9f1c9e2 1316 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1317
AnnaBridge 165:e614a9f1c9e2 1318 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1319 }
AnnaBridge 165:e614a9f1c9e2 1320 else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
AnnaBridge 165:e614a9f1c9e2 1321 {
AnnaBridge 165:e614a9f1c9e2 1322 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
AnnaBridge 165:e614a9f1c9e2 1323
AnnaBridge 165:e614a9f1c9e2 1324 return SDMMC_ERROR_CMD_CRC_FAIL;
AnnaBridge 165:e614a9f1c9e2 1325 }
AnnaBridge 165:e614a9f1c9e2 1326 else
AnnaBridge 165:e614a9f1c9e2 1327 {
AnnaBridge 165:e614a9f1c9e2 1328 /* No error flag set */
AnnaBridge 165:e614a9f1c9e2 1329 /* Clear all the static flags */
AnnaBridge 165:e614a9f1c9e2 1330 __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
AnnaBridge 165:e614a9f1c9e2 1331 }
AnnaBridge 165:e614a9f1c9e2 1332
AnnaBridge 165:e614a9f1c9e2 1333 return SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1334 }
AnnaBridge 165:e614a9f1c9e2 1335
AnnaBridge 165:e614a9f1c9e2 1336 /**
AnnaBridge 165:e614a9f1c9e2 1337 * @brief Checks for error conditions for R3 (OCR) response.
AnnaBridge 165:e614a9f1c9e2 1338 * @param hsd: SD handle
AnnaBridge 165:e614a9f1c9e2 1339 * @retval SD Card error state
AnnaBridge 165:e614a9f1c9e2 1340 */
AnnaBridge 165:e614a9f1c9e2 1341 static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 1342 {
AnnaBridge 165:e614a9f1c9e2 1343 /* 8 is the number of required instructions cycles for the below loop statement.
AnnaBridge 165:e614a9f1c9e2 1344 The SDMMC_CMDTIMEOUT is expressed in ms */
AnnaBridge 165:e614a9f1c9e2 1345 register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
AnnaBridge 165:e614a9f1c9e2 1346
AnnaBridge 165:e614a9f1c9e2 1347 do
AnnaBridge 165:e614a9f1c9e2 1348 {
AnnaBridge 165:e614a9f1c9e2 1349 if (count-- == 0U)
AnnaBridge 165:e614a9f1c9e2 1350 {
AnnaBridge 165:e614a9f1c9e2 1351 return SDMMC_ERROR_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1352 }
AnnaBridge 165:e614a9f1c9e2 1353
AnnaBridge 165:e614a9f1c9e2 1354 }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
AnnaBridge 165:e614a9f1c9e2 1355
AnnaBridge 165:e614a9f1c9e2 1356 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
AnnaBridge 165:e614a9f1c9e2 1357 {
AnnaBridge 165:e614a9f1c9e2 1358 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1359
AnnaBridge 165:e614a9f1c9e2 1360 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1361 }
AnnaBridge 165:e614a9f1c9e2 1362 else
AnnaBridge 165:e614a9f1c9e2 1363
AnnaBridge 165:e614a9f1c9e2 1364 {
AnnaBridge 165:e614a9f1c9e2 1365 /* Clear all the static flags */
AnnaBridge 165:e614a9f1c9e2 1366 __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
AnnaBridge 165:e614a9f1c9e2 1367 }
AnnaBridge 165:e614a9f1c9e2 1368
AnnaBridge 165:e614a9f1c9e2 1369 return SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1370 }
AnnaBridge 165:e614a9f1c9e2 1371
AnnaBridge 165:e614a9f1c9e2 1372 /**
AnnaBridge 165:e614a9f1c9e2 1373 * @brief Checks for error conditions for R6 (RCA) response.
AnnaBridge 165:e614a9f1c9e2 1374 * @param hsd: SD handle
AnnaBridge 165:e614a9f1c9e2 1375 * @param SD_CMD: The sent command index
AnnaBridge 165:e614a9f1c9e2 1376 * @param pRCA: Pointer to the variable that will contain the SD card relative
AnnaBridge 165:e614a9f1c9e2 1377 * address RCA
AnnaBridge 165:e614a9f1c9e2 1378 * @retval SD Card error state
AnnaBridge 165:e614a9f1c9e2 1379 */
AnnaBridge 165:e614a9f1c9e2 1380 static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
AnnaBridge 165:e614a9f1c9e2 1381 {
AnnaBridge 165:e614a9f1c9e2 1382 uint32_t response_r1;
AnnaBridge 165:e614a9f1c9e2 1383
AnnaBridge 165:e614a9f1c9e2 1384 /* 8 is the number of required instructions cycles for the below loop statement.
AnnaBridge 165:e614a9f1c9e2 1385 The SDMMC_CMDTIMEOUT is expressed in ms */
AnnaBridge 165:e614a9f1c9e2 1386 register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
AnnaBridge 165:e614a9f1c9e2 1387
AnnaBridge 165:e614a9f1c9e2 1388 do
AnnaBridge 165:e614a9f1c9e2 1389 {
AnnaBridge 165:e614a9f1c9e2 1390 if (count-- == 0U)
AnnaBridge 165:e614a9f1c9e2 1391 {
AnnaBridge 165:e614a9f1c9e2 1392 return SDMMC_ERROR_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1393 }
AnnaBridge 165:e614a9f1c9e2 1394
AnnaBridge 165:e614a9f1c9e2 1395 }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
AnnaBridge 165:e614a9f1c9e2 1396
AnnaBridge 165:e614a9f1c9e2 1397 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
AnnaBridge 165:e614a9f1c9e2 1398 {
AnnaBridge 165:e614a9f1c9e2 1399 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1400
AnnaBridge 165:e614a9f1c9e2 1401 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1402 }
AnnaBridge 165:e614a9f1c9e2 1403 else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
AnnaBridge 165:e614a9f1c9e2 1404 {
AnnaBridge 165:e614a9f1c9e2 1405 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
AnnaBridge 165:e614a9f1c9e2 1406
AnnaBridge 165:e614a9f1c9e2 1407 return SDMMC_ERROR_CMD_CRC_FAIL;
AnnaBridge 165:e614a9f1c9e2 1408 }
AnnaBridge 165:e614a9f1c9e2 1409
AnnaBridge 165:e614a9f1c9e2 1410 /* Check response received is of desired command */
AnnaBridge 165:e614a9f1c9e2 1411 if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
AnnaBridge 165:e614a9f1c9e2 1412 {
AnnaBridge 165:e614a9f1c9e2 1413 return SDMMC_ERROR_CMD_CRC_FAIL;
AnnaBridge 165:e614a9f1c9e2 1414 }
AnnaBridge 165:e614a9f1c9e2 1415
AnnaBridge 165:e614a9f1c9e2 1416 /* Clear all the static flags */
AnnaBridge 165:e614a9f1c9e2 1417 __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
AnnaBridge 165:e614a9f1c9e2 1418
AnnaBridge 165:e614a9f1c9e2 1419 /* We have received response, retrieve it. */
AnnaBridge 165:e614a9f1c9e2 1420 response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
AnnaBridge 165:e614a9f1c9e2 1421
AnnaBridge 165:e614a9f1c9e2 1422 if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
AnnaBridge 165:e614a9f1c9e2 1423 {
AnnaBridge 165:e614a9f1c9e2 1424 *pRCA = (uint16_t) (response_r1 >> 16);
AnnaBridge 165:e614a9f1c9e2 1425
AnnaBridge 165:e614a9f1c9e2 1426 return SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1427 }
AnnaBridge 165:e614a9f1c9e2 1428 else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
AnnaBridge 165:e614a9f1c9e2 1429 {
AnnaBridge 165:e614a9f1c9e2 1430 return SDMMC_ERROR_ILLEGAL_CMD;
AnnaBridge 165:e614a9f1c9e2 1431 }
AnnaBridge 165:e614a9f1c9e2 1432 else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
AnnaBridge 165:e614a9f1c9e2 1433 {
AnnaBridge 165:e614a9f1c9e2 1434 return SDMMC_ERROR_COM_CRC_FAILED;
AnnaBridge 165:e614a9f1c9e2 1435 }
AnnaBridge 165:e614a9f1c9e2 1436 else
AnnaBridge 165:e614a9f1c9e2 1437 {
AnnaBridge 165:e614a9f1c9e2 1438 return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
AnnaBridge 165:e614a9f1c9e2 1439 }
AnnaBridge 165:e614a9f1c9e2 1440 }
AnnaBridge 165:e614a9f1c9e2 1441
AnnaBridge 165:e614a9f1c9e2 1442 /**
AnnaBridge 165:e614a9f1c9e2 1443 * @brief Checks for error conditions for R7 response.
AnnaBridge 165:e614a9f1c9e2 1444 * @param hsd: SD handle
AnnaBridge 165:e614a9f1c9e2 1445 * @retval SD Card error state
AnnaBridge 165:e614a9f1c9e2 1446 */
AnnaBridge 165:e614a9f1c9e2 1447 static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
AnnaBridge 165:e614a9f1c9e2 1448 {
AnnaBridge 165:e614a9f1c9e2 1449 /* 8 is the number of required instructions cycles for the below loop statement.
AnnaBridge 165:e614a9f1c9e2 1450 The SDIO_CMDTIMEOUT is expressed in ms */
AnnaBridge 165:e614a9f1c9e2 1451 register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
AnnaBridge 165:e614a9f1c9e2 1452
AnnaBridge 165:e614a9f1c9e2 1453 do
AnnaBridge 165:e614a9f1c9e2 1454 {
AnnaBridge 165:e614a9f1c9e2 1455 if (count-- == 0U)
AnnaBridge 165:e614a9f1c9e2 1456 {
AnnaBridge 165:e614a9f1c9e2 1457 return SDMMC_ERROR_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1458 }
AnnaBridge 165:e614a9f1c9e2 1459
AnnaBridge 165:e614a9f1c9e2 1460 }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
AnnaBridge 165:e614a9f1c9e2 1461
AnnaBridge 165:e614a9f1c9e2 1462 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
AnnaBridge 165:e614a9f1c9e2 1463 {
AnnaBridge 165:e614a9f1c9e2 1464 /* Card is SD V2.0 compliant */
AnnaBridge 165:e614a9f1c9e2 1465 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
AnnaBridge 165:e614a9f1c9e2 1466
AnnaBridge 165:e614a9f1c9e2 1467 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 1468 }
AnnaBridge 165:e614a9f1c9e2 1469
AnnaBridge 165:e614a9f1c9e2 1470 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
AnnaBridge 165:e614a9f1c9e2 1471 {
AnnaBridge 165:e614a9f1c9e2 1472 /* Card is SD V2.0 compliant */
AnnaBridge 165:e614a9f1c9e2 1473 __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
AnnaBridge 165:e614a9f1c9e2 1474 }
AnnaBridge 165:e614a9f1c9e2 1475
AnnaBridge 165:e614a9f1c9e2 1476 return SDMMC_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 1477
AnnaBridge 165:e614a9f1c9e2 1478 }
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /**
<> 144:ef7eb2e8f9f7 1481 * @}
<> 144:ef7eb2e8f9f7 1482 */
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 /**
<> 144:ef7eb2e8f9f7 1485 * @}
<> 144:ef7eb2e8f9f7 1486 */
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 /**
<> 144:ef7eb2e8f9f7 1493 * @}
<> 144:ef7eb2e8f9f7 1494 */
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 /**
<> 144:ef7eb2e8f9f7 1497 * @}
<> 144:ef7eb2e8f9f7 1498 */
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/