mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_sdmmc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_ll_sdmmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief SDMMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the SDMMC peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + I/O operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### SDMMC peripheral features #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
<> 144:ef7eb2e8f9f7 21 peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
<> 144:ef7eb2e8f9f7 22 devices.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 [..] The SDIO features include the following:
<> 144:ef7eb2e8f9f7 25 (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
<> 144:ef7eb2e8f9f7 26 for three different databus modes: 1-bit (default), 4-bit and 8-bit
<> 144:ef7eb2e8f9f7 27 (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
<> 144:ef7eb2e8f9f7 28 (+) Full compliance with SD Memory Card Specifications Version 2.0
<> 144:ef7eb2e8f9f7 29 (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
<> 144:ef7eb2e8f9f7 30 different data bus modes: 1-bit (default) and 4-bit
<> 144:ef7eb2e8f9f7 31 (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
<> 144:ef7eb2e8f9f7 32 Rev1.1)
<> 144:ef7eb2e8f9f7 33 (+) Data transfer up to 48 MHz for the 8 bit mode
<> 144:ef7eb2e8f9f7 34 (+) Data and command output enable signals to control external bidirectional drivers.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 38 ==============================================================================
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 This driver is a considered as a driver of service for external devices drivers
<> 144:ef7eb2e8f9f7 41 that interfaces with the SDIO peripheral.
<> 144:ef7eb2e8f9f7 42 According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs
<> 144:ef7eb2e8f9f7 43 is used in the device's driver to perform SDIO operations and functionalities.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 This driver is almost transparent for the final user, it is only used to implement other
<> 144:ef7eb2e8f9f7 46 functionalities of the external device.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 (+) The SDIO peripheral uses two clock signals:
<> 144:ef7eb2e8f9f7 50 (++) SDIO adapter clock (SDIOCLK = HCLK)
<> 144:ef7eb2e8f9f7 51 (++) AHB bus clock (HCLK/2)
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
<> 144:ef7eb2e8f9f7 54 Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
<> 144:ef7eb2e8f9f7 57 peripheral.
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
<> 144:ef7eb2e8f9f7 60 function and disable it using the function SDIO_PowerState_OFF(SDIOx).
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
<> 144:ef7eb2e8f9f7 65 and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (+) When using the DMA mode
<> 144:ef7eb2e8f9f7 68 (++) Configure the DMA in the MSP layer of the external device
<> 144:ef7eb2e8f9f7 69 (++) Active the needed channel Request
<> 144:ef7eb2e8f9f7 70 (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
<> 144:ef7eb2e8f9f7 71 __SDIO_DMA_DISABLE().
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 (+) To control the CPSM (Command Path State Machine) and send
<> 144:ef7eb2e8f9f7 74 commands to the card use the SDIO_SendCommand(),
<> 144:ef7eb2e8f9f7 75 SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
<> 144:ef7eb2e8f9f7 76 to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
<> 144:ef7eb2e8f9f7 77 to the selected command to be sent.
<> 144:ef7eb2e8f9f7 78 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 79 (++) Command Argument
<> 144:ef7eb2e8f9f7 80 (++) Command Index
<> 144:ef7eb2e8f9f7 81 (++) Command Response type
<> 144:ef7eb2e8f9f7 82 (++) Command Wait
<> 144:ef7eb2e8f9f7 83 (++) CPSM Status (Enable or Disable).
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 -@@- To check if the command is well received, read the SDIO_CMDRESP
<> 144:ef7eb2e8f9f7 86 register using the SDIO_GetCommandResponse().
<> 144:ef7eb2e8f9f7 87 The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
<> 144:ef7eb2e8f9f7 88 SDIO_GetResponse() function.
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 (+) To control the DPSM (Data Path State Machine) and send/receive
<> 144:ef7eb2e8f9f7 91 data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
<> 144:ef7eb2e8f9f7 92 SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** Read Operations ***
<> 144:ef7eb2e8f9f7 95 =======================
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 98 SDIO_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 99 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 100 (++) Data TimeOut
<> 144:ef7eb2e8f9f7 101 (++) Data Length
<> 144:ef7eb2e8f9f7 102 (++) Data Block size
<> 144:ef7eb2e8f9f7 103 (++) Data Transfer direction: should be from card (To SDIO)
<> 144:ef7eb2e8f9f7 104 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 105 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 (#) Configure the SDIO resources to receive the data from the card
<> 144:ef7eb2e8f9f7 108 according to selected transfer mode.
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 (#) Send the selected Read command.
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 (#) Use the SDIO flags/interrupts to check the transfer status.
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 *** Write Operations ***
<> 144:ef7eb2e8f9f7 115 ========================
<> 144:ef7eb2e8f9f7 116 [..]
<> 144:ef7eb2e8f9f7 117 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 118 SDIO_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 119 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 120 (++) Data TimeOut
<> 144:ef7eb2e8f9f7 121 (++) Data Length
<> 144:ef7eb2e8f9f7 122 (++) Data Block size
<> 144:ef7eb2e8f9f7 123 (++) Data Transfer direction: should be to card (To CARD)
<> 144:ef7eb2e8f9f7 124 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 125 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 (#) Configure the SDIO resources to send the data to the card according to
<> 144:ef7eb2e8f9f7 128 selected transfer mode.
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 (#) Send the selected Write command.
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 (#) Use the SDIO flags/interrupts to check the transfer status.
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 @endverbatim
<> 144:ef7eb2e8f9f7 135 ******************************************************************************
<> 144:ef7eb2e8f9f7 136 * @attention
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 139 *
<> 144:ef7eb2e8f9f7 140 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 141 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 142 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 143 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 144 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 145 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 146 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 147 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 148 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 149 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 150 *
<> 144:ef7eb2e8f9f7 151 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 152 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 153 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 154 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 155 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 156 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 157 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 158 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 159 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 160 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 161 *
<> 144:ef7eb2e8f9f7 162 ******************************************************************************
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 166 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 173 * @{
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup SDMMC_LL SDMMC Low Layer
<> 144:ef7eb2e8f9f7 177 * @brief Low layer module for SD and MMC driver
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 182 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 183 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 184 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 185 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 186 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
<> 144:ef7eb2e8f9f7 189 * @{
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /** @defgroup HAL_SDMMC_LL_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 193 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 194 *
<> 144:ef7eb2e8f9f7 195 @verbatim
<> 144:ef7eb2e8f9f7 196 ===============================================================================
<> 144:ef7eb2e8f9f7 197 ##### Initialization/de-initialization functions #####
<> 144:ef7eb2e8f9f7 198 ===============================================================================
<> 144:ef7eb2e8f9f7 199 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 @endverbatim
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief Initializes the SDIO according to the specified
<> 144:ef7eb2e8f9f7 207 * parameters in the SDIO_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 208 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 209 * @param Init: SDIO initialization structure
<> 144:ef7eb2e8f9f7 210 * @retval HAL status
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 /* Check the parameters */
<> 144:ef7eb2e8f9f7 215 assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
<> 144:ef7eb2e8f9f7 216 assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
<> 144:ef7eb2e8f9f7 218 assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
<> 144:ef7eb2e8f9f7 220 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
<> 144:ef7eb2e8f9f7 221 assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Set SDIO configuration parameters */
<> 144:ef7eb2e8f9f7 224 /* Write to SDIO CLKCR */
<> 144:ef7eb2e8f9f7 225 MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\
<> 144:ef7eb2e8f9f7 226 Init.ClockBypass |\
<> 144:ef7eb2e8f9f7 227 Init.ClockPowerSave |\
<> 144:ef7eb2e8f9f7 228 Init.BusWide |\
<> 144:ef7eb2e8f9f7 229 Init.HardwareFlowControl |\
<> 144:ef7eb2e8f9f7 230 Init.ClockDiv);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 return HAL_OK;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 240 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 241 *
<> 144:ef7eb2e8f9f7 242 @verbatim
<> 144:ef7eb2e8f9f7 243 ===============================================================================
<> 144:ef7eb2e8f9f7 244 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 245 ===============================================================================
<> 144:ef7eb2e8f9f7 246 [..]
<> 144:ef7eb2e8f9f7 247 This subsection provides a set of functions allowing to manage the SDIO data
<> 144:ef7eb2e8f9f7 248 transfers.
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 @endverbatim
<> 144:ef7eb2e8f9f7 251 * @{
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @brief Read data (word) from Rx FIFO in blocking mode (polling)
<> 144:ef7eb2e8f9f7 256 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 257 * @retval HAL status
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 260 {
<> 144:ef7eb2e8f9f7 261 /* Read data from Rx FIFO */
<> 144:ef7eb2e8f9f7 262 return (SDIOx->FIFO);
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @brief Write data (word) to Tx FIFO in blocking mode (polling)
<> 144:ef7eb2e8f9f7 267 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 268 * @param pWriteData: pointer to data to write
<> 144:ef7eb2e8f9f7 269 * @retval HAL status
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 /* Write data to FIFO */
<> 144:ef7eb2e8f9f7 274 SDIOx->FIFO = *pWriteData;
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 return HAL_OK;
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 284 * @brief management functions
<> 144:ef7eb2e8f9f7 285 *
<> 144:ef7eb2e8f9f7 286 @verbatim
<> 144:ef7eb2e8f9f7 287 ===============================================================================
<> 144:ef7eb2e8f9f7 288 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 289 ===============================================================================
<> 144:ef7eb2e8f9f7 290 [..]
<> 144:ef7eb2e8f9f7 291 This subsection provides a set of functions allowing to control the SDIO data
<> 144:ef7eb2e8f9f7 292 transfers.
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 @endverbatim
<> 144:ef7eb2e8f9f7 295 * @{
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief Set SDIO Power state to ON.
<> 144:ef7eb2e8f9f7 300 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 301 * @retval HAL status
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* Set power state to ON */
<> 144:ef7eb2e8f9f7 306 SDIOx->POWER = SDIO_POWER_PWRCTRL;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 return HAL_OK;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @brief Set SDIO Power state to OFF.
<> 144:ef7eb2e8f9f7 313 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 314 * @retval HAL status
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 /* Set power state to OFF */
<> 144:ef7eb2e8f9f7 319 SDIOx->POWER = (uint32_t)0x00000000;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 return HAL_OK;
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @brief Get SDIO Power state.
<> 144:ef7eb2e8f9f7 326 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 327 * @retval Power status of the controller. The returned value can be one of the
<> 144:ef7eb2e8f9f7 328 * following values:
<> 144:ef7eb2e8f9f7 329 * - 0x00: Power OFF
<> 144:ef7eb2e8f9f7 330 * - 0x02: Power UP
<> 144:ef7eb2e8f9f7 331 * - 0x03: Power ON
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @brief Configure the SDIO command path according to the specified parameters in
<> 144:ef7eb2e8f9f7 340 * SDIO_CmdInitTypeDef structure and send the command
<> 144:ef7eb2e8f9f7 341 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 342 * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 343 * the configuration information for the SDIO command
<> 144:ef7eb2e8f9f7 344 * @retval HAL status
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 /* Check the parameters */
<> 144:ef7eb2e8f9f7 349 assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
<> 144:ef7eb2e8f9f7 350 assert_param(IS_SDIO_RESPONSE(Command->Response));
<> 144:ef7eb2e8f9f7 351 assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
<> 144:ef7eb2e8f9f7 352 assert_param(IS_SDIO_CPSM(Command->CPSM));
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Set the SDIO Argument value */
<> 144:ef7eb2e8f9f7 355 SDIOx->ARG = Command->Argument;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Set SDIO command parameters */
<> 144:ef7eb2e8f9f7 358 /* Write to SDIO CMD register */
<> 144:ef7eb2e8f9f7 359 MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, Command->CmdIndex |\
<> 144:ef7eb2e8f9f7 360 Command->Response |\
<> 144:ef7eb2e8f9f7 361 Command->WaitForInterrupt |\
<> 144:ef7eb2e8f9f7 362 Command->CPSM);
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 return HAL_OK;
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @brief Return the command index of last command for which response received
<> 144:ef7eb2e8f9f7 369 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 370 * @retval Command index of the last command response received
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 return (uint8_t)(SDIOx->RESPCMD);
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @brief Return the response received from the card for the last command
<> 144:ef7eb2e8f9f7 380 * @param SDIO_RESP: Specifies the SDIO response register.
<> 144:ef7eb2e8f9f7 381 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 382 * @arg SDIO_RESP1: Response Register 1
<> 144:ef7eb2e8f9f7 383 * @arg SDIO_RESP2: Response Register 2
<> 144:ef7eb2e8f9f7 384 * @arg SDIO_RESP3: Response Register 3
<> 144:ef7eb2e8f9f7 385 * @arg SDIO_RESP4: Response Register 4
<> 144:ef7eb2e8f9f7 386 * @retval The Corresponding response register value
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 __IO uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Check the parameters */
<> 144:ef7eb2e8f9f7 393 assert_param(IS_SDIO_RESP(Response));
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Get the response */
<> 144:ef7eb2e8f9f7 396 tmp = SDIO_RESP_ADDR + Response;
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 return (*(__IO uint32_t *) tmp);
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /**
<> 144:ef7eb2e8f9f7 402 * @brief Configure the SDIO data path according to the specified
<> 144:ef7eb2e8f9f7 403 * parameters in the SDIO_DataInitTypeDef.
<> 144:ef7eb2e8f9f7 404 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 405 * @param Data : pointer to a SDIO_DataInitTypeDef structure
<> 144:ef7eb2e8f9f7 406 * that contains the configuration information for the SDIO data.
<> 144:ef7eb2e8f9f7 407 * @retval HAL status
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 /* Check the parameters */
<> 144:ef7eb2e8f9f7 412 assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
<> 144:ef7eb2e8f9f7 413 assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
<> 144:ef7eb2e8f9f7 414 assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
<> 144:ef7eb2e8f9f7 415 assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
<> 144:ef7eb2e8f9f7 416 assert_param(IS_SDIO_DPSM(Data->DPSM));
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Set the SDIO Data TimeOut value */
<> 144:ef7eb2e8f9f7 419 SDIOx->DTIMER = Data->DataTimeOut;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Set the SDIO DataLength value */
<> 144:ef7eb2e8f9f7 422 SDIOx->DLEN = Data->DataLength;
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Set the SDIO data configuration parameters */
<> 144:ef7eb2e8f9f7 425 /* Write to SDIO DCTRL */
<> 144:ef7eb2e8f9f7 426 MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\
<> 144:ef7eb2e8f9f7 427 Data->TransferDir |\
<> 144:ef7eb2e8f9f7 428 Data->TransferMode |\
<> 144:ef7eb2e8f9f7 429 Data->DPSM);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 return HAL_OK;
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @brief Returns number of remaining data bytes to be transferred.
<> 144:ef7eb2e8f9f7 437 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 438 * @retval Number of remaining data bytes to be transferred
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 return (SDIOx->DCOUNT);
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /**
<> 144:ef7eb2e8f9f7 446 * @brief Get the FIFO data
<> 144:ef7eb2e8f9f7 447 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 448 * @retval Data received
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 return (SDIOx->FIFO);
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @brief Sets one of the two options of inserting read wait interval.
<> 144:ef7eb2e8f9f7 458 * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
<> 144:ef7eb2e8f9f7 459 * This parameter can be:
<> 144:ef7eb2e8f9f7 460 * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
<> 144:ef7eb2e8f9f7 461 * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
<> 144:ef7eb2e8f9f7 462 * @retval None
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 /* Check the parameters */
<> 144:ef7eb2e8f9f7 467 assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Set SDIO read wait mode */
<> 144:ef7eb2e8f9f7 470 MODIFY_REG(SDIO->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 return HAL_OK;
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @}
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/