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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Timer Extended peripheral:
<> 144:ef7eb2e8f9f7 8 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 9 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 10 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 11 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 12 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The Timer Extended features include:
<> 144:ef7eb2e8f9f7 19 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 20 (++) Output Compare
<> 144:ef7eb2e8f9f7 21 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 22 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 23 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 24 interconnect several timers together.
<> 144:ef7eb2e8f9f7 25 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 26 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 27 positioning purposes
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 30 ==============================================================================
<> 144:ef7eb2e8f9f7 31 [..]
<> 144:ef7eb2e8f9f7 32 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 33 depending from feature used :
<> 144:ef7eb2e8f9f7 34 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 35 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 36 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 37 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 40 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 41 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 42 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 43 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 44 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 47 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 48 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 49 any start function.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 52 initialization function of this driver:
<> 144:ef7eb2e8f9f7 53 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 54 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 55 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 56 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 57 the commutation event).
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 60 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
<> 144:ef7eb2e8f9f7 61 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 62 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 @endverbatim
<> 144:ef7eb2e8f9f7 67 ******************************************************************************
<> 144:ef7eb2e8f9f7 68 * @attention
<> 144:ef7eb2e8f9f7 69 *
<> 144:ef7eb2e8f9f7 70 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 73 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 74 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 75 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 76 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 77 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 78 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 79 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 80 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 81 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 82 *
<> 144:ef7eb2e8f9f7 83 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 84 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 86 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 89 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 90 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 91 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 92 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 93 *
<> 144:ef7eb2e8f9f7 94 ******************************************************************************
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 101 * @{
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 105 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 118 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 119 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 120 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 128 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 129 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 139 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 @verbatim
<> 144:ef7eb2e8f9f7 142 ==============================================================================
<> 144:ef7eb2e8f9f7 143 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 144 ==============================================================================
<> 144:ef7eb2e8f9f7 145 [..]
<> 144:ef7eb2e8f9f7 146 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 147 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 148 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 149 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 150 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 151 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 152 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 153 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 154 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 @endverbatim
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 161 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 162 * @param sConfig : TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 163 * @retval HAL status
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 170 if(htim == NULL)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 176 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge 165:e614a9f1c9e2 178 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 179 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 186 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 189 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 193 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 196 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 199 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 202 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 203 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 204 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 207 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 210 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 211 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 214 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 215 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 218 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 219 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 220 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 221 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 222 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 223 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 224 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 229 register to 101 */
<> 144:ef7eb2e8f9f7 230 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 231 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 234 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 return HAL_OK;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /**
<> 144:ef7eb2e8f9f7 240 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 241 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 242 * @retval HAL status
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 /* Check the parameters */
<> 144:ef7eb2e8f9f7 247 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 252 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 255 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Change TIM state */
<> 144:ef7eb2e8f9f7 258 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Release Lock */
<> 144:ef7eb2e8f9f7 261 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 return HAL_OK;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 268 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 269 * @retval None
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 274 UNUSED(htim);
<> 144:ef7eb2e8f9f7 275 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 276 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 282 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 283 * @retval None
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 288 UNUSED(htim);
<> 144:ef7eb2e8f9f7 289 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 290 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 296 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 297 * @retval HAL status
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 /* Check the parameters */
<> 144:ef7eb2e8f9f7 302 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 305 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 309 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Return function status */
<> 144:ef7eb2e8f9f7 312 return HAL_OK;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 317 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 318 * @retval HAL status
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 /* Check the parameters */
<> 144:ef7eb2e8f9f7 323 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 326 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 327 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 330 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Return function status */
<> 144:ef7eb2e8f9f7 333 return HAL_OK;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 338 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 339 * @retval HAL status
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 /* Check the parameters */
<> 144:ef7eb2e8f9f7 344 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 347 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 350 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 351 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 354 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Return function status */
<> 144:ef7eb2e8f9f7 357 return HAL_OK;
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 362 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 363 * @retval HAL status
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 /* Check the parameters */
<> 144:ef7eb2e8f9f7 368 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 371 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 372 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 375 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 378 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Return function status */
<> 144:ef7eb2e8f9f7 381 return HAL_OK;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 386 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 387 * @param pData : The destination Buffer address.
<> 144:ef7eb2e8f9f7 388 * @param Length : The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 389 * @retval HAL status
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 /* Check the parameters */
<> 144:ef7eb2e8f9f7 394 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 401 {
AnnaBridge 165:e614a9f1c9e2 402 if(((uint32_t)pData == 0U) && (Length > 0U))
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 else
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 412 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 413 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 416 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 417 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 418 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Enable the DMA channel for Capture 1*/
<> 144:ef7eb2e8f9f7 421 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 424 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 427 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Return function status */
<> 144:ef7eb2e8f9f7 430 return HAL_OK;
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 435 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 436 * @retval HAL status
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 /* Check the parameters */
<> 144:ef7eb2e8f9f7 441 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 444 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 445 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 449 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 452 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Return function status */
<> 144:ef7eb2e8f9f7 455 return HAL_OK;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 463 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 464 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 467 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 468 *
<> 144:ef7eb2e8f9f7 469 @verbatim
<> 144:ef7eb2e8f9f7 470 ==============================================================================
<> 144:ef7eb2e8f9f7 471 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 472 ==============================================================================
<> 144:ef7eb2e8f9f7 473 [..]
<> 144:ef7eb2e8f9f7 474 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 475 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 476 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 477 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 478 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 479 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 480 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 @endverbatim
<> 144:ef7eb2e8f9f7 483 * @{
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /**
<> 144:ef7eb2e8f9f7 487 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 488 * output.
<> 144:ef7eb2e8f9f7 489 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 490 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 491 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 492 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 493 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 494 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 495 * @retval HAL status
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* Check the parameters */
<> 144:ef7eb2e8f9f7 500 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 503 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 506 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 509 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Return function status */
<> 144:ef7eb2e8f9f7 512 return HAL_OK;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /**
<> 144:ef7eb2e8f9f7 516 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 517 * output.
<> 144:ef7eb2e8f9f7 518 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 519 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 520 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 521 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 522 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 523 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 524 * @retval HAL status
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 /* Check the parameters */
<> 144:ef7eb2e8f9f7 529 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 532 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 535 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 538 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Return function status */
<> 144:ef7eb2e8f9f7 541 return HAL_OK;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 546 * on the complementary output.
<> 144:ef7eb2e8f9f7 547 * @param htim : TIM OC handle
<> 144:ef7eb2e8f9f7 548 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 549 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 550 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 551 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 552 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 553 * @retval HAL status
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Check the parameters */
<> 144:ef7eb2e8f9f7 558 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 switch (Channel)
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 565 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567 break;
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 572 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 break;
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 579 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581 break;
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 default:
<> 144:ef7eb2e8f9f7 584 break;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 588 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 591 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 594 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 597 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Return function status */
<> 144:ef7eb2e8f9f7 600 return HAL_OK;
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 605 * on the complementary output.
<> 144:ef7eb2e8f9f7 606 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 607 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 608 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 609 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 610 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 611 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 612 * @retval HAL status
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 615 {
AnnaBridge 165:e614a9f1c9e2 616 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Check the parameters */
<> 144:ef7eb2e8f9f7 619 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 switch (Channel)
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 626 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 break;
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 633 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 break;
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 640 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642 break;
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 default:
<> 144:ef7eb2e8f9f7 645 break;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 649 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 652 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 653 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 659 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 662 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Return function status */
<> 144:ef7eb2e8f9f7 665 return HAL_OK;
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 670 * on the complementary output.
<> 144:ef7eb2e8f9f7 671 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 672 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 673 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 674 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 675 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 676 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 677 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 678 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 679 * @retval HAL status
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 /* Check the parameters */
<> 144:ef7eb2e8f9f7 684 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 691 {
AnnaBridge 165:e614a9f1c9e2 692 if(((uint32_t)pData == 0U) && (Length > 0U))
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696 else
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701 switch (Channel)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 706 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 709 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 712 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 715 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717 break;
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 720 {
<> 144:ef7eb2e8f9f7 721 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 722 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 725 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 728 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 731 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 break;
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 case TIM_CHANNEL_3:
AnnaBridge 187:0387e8f68319 736 {
<> 144:ef7eb2e8f9f7 737 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 738 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 741 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 744 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 747 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749 break;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 default:
<> 144:ef7eb2e8f9f7 752 break;
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 756 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 759 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 762 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Return function status */
<> 144:ef7eb2e8f9f7 765 return HAL_OK;
<> 144:ef7eb2e8f9f7 766 }
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /**
<> 144:ef7eb2e8f9f7 769 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 770 * on the complementary output.
<> 144:ef7eb2e8f9f7 771 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 772 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 773 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 774 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 775 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 776 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 777 * @retval HAL status
<> 144:ef7eb2e8f9f7 778 */
<> 144:ef7eb2e8f9f7 779 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 /* Check the parameters */
<> 144:ef7eb2e8f9f7 782 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 switch (Channel)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 789 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 break;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 796 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798 break;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 803 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 804 }
<> 144:ef7eb2e8f9f7 805 break;
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 default:
<> 144:ef7eb2e8f9f7 808 break;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 812 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 815 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 818 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Change the htim state */
<> 144:ef7eb2e8f9f7 821 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Return function status */
<> 144:ef7eb2e8f9f7 824 return HAL_OK;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /**
<> 144:ef7eb2e8f9f7 828 * @}
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 832 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 833 *
<> 144:ef7eb2e8f9f7 834 @verbatim
<> 144:ef7eb2e8f9f7 835 ==============================================================================
<> 144:ef7eb2e8f9f7 836 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 837 ==============================================================================
<> 144:ef7eb2e8f9f7 838 [..]
<> 144:ef7eb2e8f9f7 839 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 840 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 841 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 842 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 843 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 844 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 845 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 846 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 847 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 848 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 849 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 850 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 851 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 852 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 853 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 854 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 855 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 @endverbatim
<> 144:ef7eb2e8f9f7 858 * @{
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /**
<> 144:ef7eb2e8f9f7 862 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 863 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 864 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 865 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 866 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 867 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 868 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 869 * @retval HAL status
<> 144:ef7eb2e8f9f7 870 */
<> 144:ef7eb2e8f9f7 871 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 /* Check the parameters */
<> 144:ef7eb2e8f9f7 874 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 877 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 880 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 883 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Return function status */
<> 144:ef7eb2e8f9f7 886 return HAL_OK;
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /**
<> 144:ef7eb2e8f9f7 890 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 891 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 892 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 893 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 894 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 895 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 896 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 897 * @retval HAL status
<> 144:ef7eb2e8f9f7 898 */
<> 144:ef7eb2e8f9f7 899 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 /* Check the parameters */
<> 144:ef7eb2e8f9f7 902 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 905 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 908 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 911 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* Return function status */
<> 144:ef7eb2e8f9f7 914 return HAL_OK;
<> 144:ef7eb2e8f9f7 915 }
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /**
<> 144:ef7eb2e8f9f7 918 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 919 * complementary output.
<> 144:ef7eb2e8f9f7 920 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 921 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 922 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 923 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 924 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 925 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 926 * @retval HAL status
<> 144:ef7eb2e8f9f7 927 */
<> 144:ef7eb2e8f9f7 928 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 /* Check the parameters */
<> 144:ef7eb2e8f9f7 931 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 switch (Channel)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 936 {
<> 144:ef7eb2e8f9f7 937 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 938 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940 break;
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 945 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947 break;
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 950 {
<> 144:ef7eb2e8f9f7 951 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 952 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 953 }
<> 144:ef7eb2e8f9f7 954 break;
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 default:
<> 144:ef7eb2e8f9f7 957 break;
<> 144:ef7eb2e8f9f7 958 }
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 961 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 964 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 967 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 970 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /* Return function status */
<> 144:ef7eb2e8f9f7 973 return HAL_OK;
<> 144:ef7eb2e8f9f7 974 }
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /**
<> 144:ef7eb2e8f9f7 977 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 978 * complementary output.
<> 144:ef7eb2e8f9f7 979 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 980 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 981 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 982 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 983 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 984 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 985 * @retval HAL status
<> 144:ef7eb2e8f9f7 986 */
AnnaBridge 187:0387e8f68319 987 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 988 {
AnnaBridge 165:e614a9f1c9e2 989 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Check the parameters */
<> 144:ef7eb2e8f9f7 992 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 switch (Channel)
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 997 {
<> 144:ef7eb2e8f9f7 998 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 999 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001 break;
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1006 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1007 }
<> 144:ef7eb2e8f9f7 1008 break;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1013 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015 break;
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 default:
<> 144:ef7eb2e8f9f7 1018 break;
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1022 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1025 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1026 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1027 {
<> 144:ef7eb2e8f9f7 1028 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1029 }
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1032 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1035 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Return function status */
<> 144:ef7eb2e8f9f7 1038 return HAL_OK;
<> 144:ef7eb2e8f9f7 1039 }
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /**
<> 144:ef7eb2e8f9f7 1042 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1043 * complementary output
<> 144:ef7eb2e8f9f7 1044 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1045 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1046 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1047 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1048 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1049 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1050 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 1051 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1052 * @retval HAL status
<> 144:ef7eb2e8f9f7 1053 */
<> 144:ef7eb2e8f9f7 1054 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1055 {
<> 144:ef7eb2e8f9f7 1056 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1057 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1062 }
<> 144:ef7eb2e8f9f7 1063 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1064 {
AnnaBridge 165:e614a9f1c9e2 1065 if(((uint32_t)pData == 0U) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069 else
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074 switch (Channel)
<> 144:ef7eb2e8f9f7 1075 {
<> 144:ef7eb2e8f9f7 1076 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1079 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1082 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1085 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1088 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1089 }
<> 144:ef7eb2e8f9f7 1090 break;
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1095 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1098 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1101 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1104 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106 break;
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1111 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1114 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1117 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1120 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1121 }
<> 144:ef7eb2e8f9f7 1122 break;
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 default:
<> 144:ef7eb2e8f9f7 1125 break;
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Enable the complementary PWM output */
AnnaBridge 187:0387e8f68319 1129 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* Enable the Main Ouput */
AnnaBridge 187:0387e8f68319 1132 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1135 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /* Return function status */
<> 144:ef7eb2e8f9f7 1138 return HAL_OK;
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /**
<> 144:ef7eb2e8f9f7 1142 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1143 * output
<> 144:ef7eb2e8f9f7 1144 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1145 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1146 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1147 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1148 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1149 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1150 * @retval HAL status
<> 144:ef7eb2e8f9f7 1151 */
<> 144:ef7eb2e8f9f7 1152 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1153 {
<> 144:ef7eb2e8f9f7 1154 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1155 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 switch (Channel)
<> 144:ef7eb2e8f9f7 1158 {
<> 144:ef7eb2e8f9f7 1159 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1160 {
<> 144:ef7eb2e8f9f7 1161 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1162 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1163 }
<> 144:ef7eb2e8f9f7 1164 break;
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1167 {
<> 144:ef7eb2e8f9f7 1168 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1169 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1170 }
<> 144:ef7eb2e8f9f7 1171 break;
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1176 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1177 }
<> 144:ef7eb2e8f9f7 1178 break;
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 default:
<> 144:ef7eb2e8f9f7 1181 break;
<> 144:ef7eb2e8f9f7 1182 }
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Disable the complementary PWM output */
AnnaBridge 187:0387e8f68319 1185 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Disable the Main Ouput */
AnnaBridge 187:0387e8f68319 1188 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1191 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1194 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /* Return function status */
<> 144:ef7eb2e8f9f7 1197 return HAL_OK;
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /**
<> 144:ef7eb2e8f9f7 1201 * @}
<> 144:ef7eb2e8f9f7 1202 */
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1205 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1206 *
<> 144:ef7eb2e8f9f7 1207 @verbatim
<> 144:ef7eb2e8f9f7 1208 ==============================================================================
<> 144:ef7eb2e8f9f7 1209 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1210 ==============================================================================
<> 144:ef7eb2e8f9f7 1211 [..]
<> 144:ef7eb2e8f9f7 1212 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1213 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1214 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1215 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1216 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 @endverbatim
<> 144:ef7eb2e8f9f7 1219 * @{
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /**
<> 144:ef7eb2e8f9f7 1223 * @brief Starts the TIM One Pulse signal generation on the complemetary
<> 144:ef7eb2e8f9f7 1224 * output.
<> 144:ef7eb2e8f9f7 1225 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1226 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1227 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1228 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1229 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1230 * @retval HAL status
<> 144:ef7eb2e8f9f7 1231 */
<> 144:ef7eb2e8f9f7 1232 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
AnnaBridge 187:0387e8f68319 1233 {
<> 144:ef7eb2e8f9f7 1234 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1235 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1238 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1241 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /* Return function status */
<> 144:ef7eb2e8f9f7 1244 return HAL_OK;
<> 144:ef7eb2e8f9f7 1245 }
<> 144:ef7eb2e8f9f7 1246
<> 144:ef7eb2e8f9f7 1247 /**
<> 144:ef7eb2e8f9f7 1248 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1249 * output.
<> 144:ef7eb2e8f9f7 1250 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1251 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1252 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1253 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1254 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1255 * @retval HAL status
<> 144:ef7eb2e8f9f7 1256 */
<> 144:ef7eb2e8f9f7 1257 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1258 {
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1261 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1264 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1267 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1270 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Return function status */
<> 144:ef7eb2e8f9f7 1273 return HAL_OK;
<> 144:ef7eb2e8f9f7 1274 }
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /**
<> 144:ef7eb2e8f9f7 1277 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1278 * complementary channel.
<> 144:ef7eb2e8f9f7 1279 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1280 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1281 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1282 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1283 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1284 * @retval HAL status
<> 144:ef7eb2e8f9f7 1285 */
<> 144:ef7eb2e8f9f7 1286 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1287 {
<> 144:ef7eb2e8f9f7 1288 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1289 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1292 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1295 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1298 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1301 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 /* Return function status */
<> 144:ef7eb2e8f9f7 1304 return HAL_OK;
AnnaBridge 187:0387e8f68319 1305 }
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /**
<> 144:ef7eb2e8f9f7 1308 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1309 * complementary channel.
<> 144:ef7eb2e8f9f7 1310 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1311 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1312 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1313 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1314 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1315 * @retval HAL status
<> 144:ef7eb2e8f9f7 1316 */
<> 144:ef7eb2e8f9f7 1317 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1318 {
<> 144:ef7eb2e8f9f7 1319 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1320 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1323 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1326 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1329 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1332 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /* Disable the Peripheral */
AnnaBridge 187:0387e8f68319 1335 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Return function status */
<> 144:ef7eb2e8f9f7 1338 return HAL_OK;
<> 144:ef7eb2e8f9f7 1339 }
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /**
<> 144:ef7eb2e8f9f7 1342 * @}
<> 144:ef7eb2e8f9f7 1343 */
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1346 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1347 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
AnnaBridge 187:0387e8f68319 1350 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1351 *
<> 144:ef7eb2e8f9f7 1352 @verbatim
<> 144:ef7eb2e8f9f7 1353 ==============================================================================
<> 144:ef7eb2e8f9f7 1354 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1355 ==============================================================================
<> 144:ef7eb2e8f9f7 1356 [..]
<> 144:ef7eb2e8f9f7 1357 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1358 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1359 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1360 (+) Configure Master synchronization.
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 @endverbatim
<> 144:ef7eb2e8f9f7 1363 * @{
<> 144:ef7eb2e8f9f7 1364 */
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 1367 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 1368 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /**
<> 144:ef7eb2e8f9f7 1371 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1372 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1373 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1374 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1375 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1376 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1377 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1378 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1379 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1380 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1381 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1382 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1383 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1384 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1385 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1386 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1387 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1388 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1389 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1390 * @retval HAL status
<> 144:ef7eb2e8f9f7 1391 */
<> 144:ef7eb2e8f9f7 1392 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1393 {
<> 144:ef7eb2e8f9f7 1394 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1395 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1396 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1401 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1402 {
<> 144:ef7eb2e8f9f7 1403 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1404 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1405 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1409 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1410 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1411 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1412 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 return HAL_OK;
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 /**
<> 144:ef7eb2e8f9f7 1420 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1421 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1422 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1423 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1424 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1425 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1426 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1427 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1428 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1429 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1430 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1431 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1432 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1433 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1434 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1435 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1436 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1437 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1438 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1439 * @retval HAL status
<> 144:ef7eb2e8f9f7 1440 */
<> 144:ef7eb2e8f9f7 1441 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1442 {
<> 144:ef7eb2e8f9f7 1443 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1444 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1445 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1450 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1451 {
<> 144:ef7eb2e8f9f7 1452 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1453 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1454 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1455 }
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1458 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1459 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1460 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1461 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1464 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 return HAL_OK;
<> 144:ef7eb2e8f9f7 1469 }
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 /**
<> 144:ef7eb2e8f9f7 1472 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1473 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1474 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1475 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1476 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1477 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1478 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1479 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1480 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1481 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1482 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1483 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1484 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1485 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1486 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1487 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1488 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1489 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1490 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1491 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1492 * @retval HAL status
<> 144:ef7eb2e8f9f7 1493 */
<> 144:ef7eb2e8f9f7 1494 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1495 {
<> 144:ef7eb2e8f9f7 1496 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1497 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1498 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1503 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1504 {
<> 144:ef7eb2e8f9f7 1505 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1506 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1507 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1508 }
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1511 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1512 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1513 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1514 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1517 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1518 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1519 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1520 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1523 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 return HAL_OK;
<> 144:ef7eb2e8f9f7 1528 }
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /**
<> 144:ef7eb2e8f9f7 1531 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1532 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 1533 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1534 * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1535 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1536 * @retval HAL status
<> 144:ef7eb2e8f9f7 1537 */
<> 144:ef7eb2e8f9f7 1538 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1539 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1540 {
AnnaBridge 165:e614a9f1c9e2 1541 uint32_t tmpbdtr = 0U;
AnnaBridge 165:e614a9f1c9e2 1542
<> 144:ef7eb2e8f9f7 1543 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1544 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1545 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1546 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1547 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 1548 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1549 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1550 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1551 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /* Process Locked */
<> 144:ef7eb2e8f9f7 1554 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 1557 the OSSI State, the dead time value and the Automatic Output Enable Bit */
AnnaBridge 187:0387e8f68319 1558
AnnaBridge 165:e614a9f1c9e2 1559 /* Set the BDTR bits */
AnnaBridge 165:e614a9f1c9e2 1560 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
AnnaBridge 165:e614a9f1c9e2 1561 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
AnnaBridge 165:e614a9f1c9e2 1562 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
AnnaBridge 165:e614a9f1c9e2 1563 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
AnnaBridge 165:e614a9f1c9e2 1564 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
AnnaBridge 165:e614a9f1c9e2 1565 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
AnnaBridge 165:e614a9f1c9e2 1566 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
AnnaBridge 165:e614a9f1c9e2 1567 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
AnnaBridge 187:0387e8f68319 1568
AnnaBridge 165:e614a9f1c9e2 1569 /* Set TIMx_BDTR */
AnnaBridge 165:e614a9f1c9e2 1570 htim->Instance->BDTR = tmpbdtr;
AnnaBridge 187:0387e8f68319 1571
<> 144:ef7eb2e8f9f7 1572 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574 return HAL_OK;
<> 144:ef7eb2e8f9f7 1575 }
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1578 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1579 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 /**
<> 144:ef7eb2e8f9f7 1582 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 1583 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 1584 * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1585 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1586 * mode.
<> 144:ef7eb2e8f9f7 1587 * @retval HAL status
<> 144:ef7eb2e8f9f7 1588 */
<> 144:ef7eb2e8f9f7 1589 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1590 {
<> 144:ef7eb2e8f9f7 1591 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1592 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1593 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1594 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1597
<> 144:ef7eb2e8f9f7 1598 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1601 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1602 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1603 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1606 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1607 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1608 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 return HAL_OK;
<> 144:ef7eb2e8f9f7 1615 }
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /**
<> 144:ef7eb2e8f9f7 1618 * @}
<> 144:ef7eb2e8f9f7 1619 */
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1622 * @brief Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1623 *
<> 144:ef7eb2e8f9f7 1624 @verbatim
<> 144:ef7eb2e8f9f7 1625 ==============================================================================
<> 144:ef7eb2e8f9f7 1626 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 1627 ==============================================================================
<> 144:ef7eb2e8f9f7 1628 [..]
<> 144:ef7eb2e8f9f7 1629 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 1630 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 1631 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 @endverbatim
<> 144:ef7eb2e8f9f7 1634 * @{
<> 144:ef7eb2e8f9f7 1635 */
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /**
<> 144:ef7eb2e8f9f7 1638 * @brief Hall commutation changed callback in non blocking mode
<> 144:ef7eb2e8f9f7 1639 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1640 * @retval None
<> 144:ef7eb2e8f9f7 1641 */
<> 144:ef7eb2e8f9f7 1642 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1643 {
<> 144:ef7eb2e8f9f7 1644 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1645 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1646 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1647 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1648 */
<> 144:ef7eb2e8f9f7 1649 }
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 /**
<> 144:ef7eb2e8f9f7 1652 * @brief Hall Break detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 1653 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1654 * @retval None
<> 144:ef7eb2e8f9f7 1655 */
<> 144:ef7eb2e8f9f7 1656 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1657 {
<> 144:ef7eb2e8f9f7 1658 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1659 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1660 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1661 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1662 */
<> 144:ef7eb2e8f9f7 1663 }
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 /**
<> 144:ef7eb2e8f9f7 1666 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 1667 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 1668 * @retval None
<> 144:ef7eb2e8f9f7 1669 */
<> 144:ef7eb2e8f9f7 1670 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1671 {
<> 144:ef7eb2e8f9f7 1672 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 1677 }
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 /**
<> 144:ef7eb2e8f9f7 1680 * @}
<> 144:ef7eb2e8f9f7 1681 */
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 1684 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 1685 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1688 * @brief Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1689 *
<> 144:ef7eb2e8f9f7 1690 @verbatim
<> 144:ef7eb2e8f9f7 1691 ==============================================================================
<> 144:ef7eb2e8f9f7 1692 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1693 ==============================================================================
<> 144:ef7eb2e8f9f7 1694 [..]
<> 144:ef7eb2e8f9f7 1695 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1696 and the data flow.
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 @endverbatim
<> 144:ef7eb2e8f9f7 1699 * @{
<> 144:ef7eb2e8f9f7 1700 */
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 /**
<> 144:ef7eb2e8f9f7 1703 * @brief Return the TIM Hall Sensor interface state
<> 144:ef7eb2e8f9f7 1704 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 1705 * @retval HAL state
<> 144:ef7eb2e8f9f7 1706 */
<> 144:ef7eb2e8f9f7 1707 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1708 {
<> 144:ef7eb2e8f9f7 1709 return htim->State;
<> 144:ef7eb2e8f9f7 1710 }
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 /**
<> 144:ef7eb2e8f9f7 1713 * @}
<> 144:ef7eb2e8f9f7 1714 */
<> 144:ef7eb2e8f9f7 1715 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1716 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1717 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 /**
<> 144:ef7eb2e8f9f7 1720 * @}
<> 144:ef7eb2e8f9f7 1721 */
<> 144:ef7eb2e8f9f7 1722
<> 144:ef7eb2e8f9f7 1723 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 1724 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 1725 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 1726
<> 144:ef7eb2e8f9f7 1727 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 1728 * @{
<> 144:ef7eb2e8f9f7 1729 */
<> 144:ef7eb2e8f9f7 1730
<> 144:ef7eb2e8f9f7 1731 /**
<> 144:ef7eb2e8f9f7 1732 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 1733 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 1734 * @param Channel : specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1735 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1736 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1737 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1738 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1739 * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 1740 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 1741 * @retval None
<> 144:ef7eb2e8f9f7 1742 */
<> 144:ef7eb2e8f9f7 1743 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 1744 {
AnnaBridge 165:e614a9f1c9e2 1745 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 1746
<> 144:ef7eb2e8f9f7 1747 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 1748
<> 144:ef7eb2e8f9f7 1749 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1750 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 1751
<> 144:ef7eb2e8f9f7 1752 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1753 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 1754 }
<> 144:ef7eb2e8f9f7 1755
<> 144:ef7eb2e8f9f7 1756 /**
<> 144:ef7eb2e8f9f7 1757 * @}
<> 144:ef7eb2e8f9f7 1758 */
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1761 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1762 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1765 /**
<> 144:ef7eb2e8f9f7 1766 * @}
<> 144:ef7eb2e8f9f7 1767 */
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 /**
<> 144:ef7eb2e8f9f7 1770 * @}
<> 144:ef7eb2e8f9f7 1771 */
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/