mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer Extended peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The Timer Extended features include:
<> 144:ef7eb2e8f9f7 21 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 22 (++) Output Compare
<> 144:ef7eb2e8f9f7 23 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 24 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 25 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 26 interconnect several timers together.
<> 144:ef7eb2e8f9f7 27 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 28 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 29 positioning purposes
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 32 ==============================================================================
<> 144:ef7eb2e8f9f7 33 [..]
<> 144:ef7eb2e8f9f7 34 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 35 depending from feature used :
<> 144:ef7eb2e8f9f7 36 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 37 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 38 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 39 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 42 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 43 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 44 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 45 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 46 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 49 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 50 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 51 any start function.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 54 initialization function of this driver:
<> 144:ef7eb2e8f9f7 55 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 56 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 57 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 58 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 59 the commutation event).
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 62 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 64 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 65 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 @endverbatim
<> 144:ef7eb2e8f9f7 69 ******************************************************************************
<> 144:ef7eb2e8f9f7 70 * @attention
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 75 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 76 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 77 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 78 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 79 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 80 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 81 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 82 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 83 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 88 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 92 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 93 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 94 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 107 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 120 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 121 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 122 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 130 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 131 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 141 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 142 *
<> 144:ef7eb2e8f9f7 143 @verbatim
<> 144:ef7eb2e8f9f7 144 ==============================================================================
<> 144:ef7eb2e8f9f7 145 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 146 ==============================================================================
<> 144:ef7eb2e8f9f7 147 [..]
<> 144:ef7eb2e8f9f7 148 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 149 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 150 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 151 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 152 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 153 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 154 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 155 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 156 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 @endverbatim
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 163 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 164 * @param sConfig : TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 165 * @retval HAL status
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 172 if(htim == NULL)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 178 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 179 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 187 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 190 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 194 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 197 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 200 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 203 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 204 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 205 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 208 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 211 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 212 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 215 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 216 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 219 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 220 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 221 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 222 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 223 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 224 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 225 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 230 register to 101 */
<> 144:ef7eb2e8f9f7 231 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 232 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 235 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 return HAL_OK;
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 242 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 243 * @retval HAL status
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 /* Check the parameters */
<> 144:ef7eb2e8f9f7 248 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 253 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 256 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Change TIM state */
<> 144:ef7eb2e8f9f7 259 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Release Lock */
<> 144:ef7eb2e8f9f7 262 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 return HAL_OK;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 269 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 270 * @retval None
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 275 UNUSED(htim);
<> 144:ef7eb2e8f9f7 276 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 277 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 283 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 284 * @retval None
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 289 UNUSED(htim);
<> 144:ef7eb2e8f9f7 290 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 291 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 297 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 298 * @retval HAL status
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 /* Check the parameters */
<> 144:ef7eb2e8f9f7 303 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 306 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 307 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 310 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Return function status */
<> 144:ef7eb2e8f9f7 313 return HAL_OK;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 318 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 319 * @retval HAL status
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Check the parameters */
<> 144:ef7eb2e8f9f7 324 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 327 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 328 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 331 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Return function status */
<> 144:ef7eb2e8f9f7 334 return HAL_OK;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 339 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 340 * @retval HAL status
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 /* Check the parameters */
<> 144:ef7eb2e8f9f7 345 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 348 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 351 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 352 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 355 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Return function status */
<> 144:ef7eb2e8f9f7 358 return HAL_OK;
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 363 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 364 * @retval HAL status
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 /* Check the parameters */
<> 144:ef7eb2e8f9f7 369 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 372 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 373 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 376 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 379 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Return function status */
<> 144:ef7eb2e8f9f7 382 return HAL_OK;
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 387 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 388 * @param pData : The destination Buffer address.
<> 144:ef7eb2e8f9f7 389 * @param Length : The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 390 * @retval HAL status
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 /* Check the parameters */
<> 144:ef7eb2e8f9f7 395 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 else
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 413 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 417 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 418 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 419 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Enable the DMA channel for Capture 1*/
<> 144:ef7eb2e8f9f7 422 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 425 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 428 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Return function status */
<> 144:ef7eb2e8f9f7 431 return HAL_OK;
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /**
<> 144:ef7eb2e8f9f7 435 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 436 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 437 * @retval HAL status
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 /* Check the parameters */
<> 144:ef7eb2e8f9f7 442 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 445 (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 446 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 450 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 453 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Return function status */
<> 144:ef7eb2e8f9f7 456 return HAL_OK;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @}
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 464 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 465 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 468 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 469 *
<> 144:ef7eb2e8f9f7 470 @verbatim
<> 144:ef7eb2e8f9f7 471 ==============================================================================
<> 144:ef7eb2e8f9f7 472 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 473 ==============================================================================
<> 144:ef7eb2e8f9f7 474 [..]
<> 144:ef7eb2e8f9f7 475 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 476 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 477 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 478 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 479 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 480 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 481 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 @endverbatim
<> 144:ef7eb2e8f9f7 484 * @{
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 489 * output.
<> 144:ef7eb2e8f9f7 490 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 491 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 492 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 493 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 494 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 495 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 496 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 497 * @retval HAL status
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 /* Check the parameters */
<> 144:ef7eb2e8f9f7 502 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 505 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 508 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 511 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Return function status */
<> 144:ef7eb2e8f9f7 514 return HAL_OK;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 519 * output.
<> 144:ef7eb2e8f9f7 520 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 521 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 522 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 523 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 524 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 525 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 526 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 527 * @retval HAL status
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 /* Check the parameters */
<> 144:ef7eb2e8f9f7 532 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 535 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 538 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 541 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Return function status */
<> 144:ef7eb2e8f9f7 544 return HAL_OK;
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 549 * on the complementary output.
<> 144:ef7eb2e8f9f7 550 * @param htim : TIM OC handle
<> 144:ef7eb2e8f9f7 551 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 552 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 553 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 554 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 555 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 556 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 557 * @retval HAL status
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 /* Check the parameters */
<> 144:ef7eb2e8f9f7 562 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 switch (Channel)
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 569 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571 break;
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 576 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 break;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 583 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585 break;
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 590 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 591 }
<> 144:ef7eb2e8f9f7 592 break;
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 default:
<> 144:ef7eb2e8f9f7 595 break;
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 599 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 602 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 605 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 608 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Return function status */
<> 144:ef7eb2e8f9f7 611 return HAL_OK;
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 616 * on the complementary output.
<> 144:ef7eb2e8f9f7 617 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 618 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 619 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 620 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 621 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 622 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 623 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 624 * @retval HAL status
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Check the parameters */
<> 144:ef7eb2e8f9f7 631 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 switch (Channel)
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 638 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 break;
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 645 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 break;
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 652 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 break;
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 659 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 break;
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 default:
<> 144:ef7eb2e8f9f7 664 break;
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 668 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 671 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 672 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 678 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 681 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Return function status */
<> 144:ef7eb2e8f9f7 684 return HAL_OK;
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 689 * on the complementary output.
<> 144:ef7eb2e8f9f7 690 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 691 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 692 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 693 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 694 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 695 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 696 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 697 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 698 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 699 * @retval HAL status
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 /* Check the parameters */
<> 144:ef7eb2e8f9f7 704 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716 else
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 switch (Channel)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 726 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 729 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 732 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 735 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737 break;
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 742 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 745 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 748 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 751 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753 break;
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 758 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 761 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 764 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 767 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769 break;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 774 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 777 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 780 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 783 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 784 }
<> 144:ef7eb2e8f9f7 785 break;
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 default:
<> 144:ef7eb2e8f9f7 788 break;
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 792 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 795 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 798 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Return function status */
<> 144:ef7eb2e8f9f7 801 return HAL_OK;
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /**
<> 144:ef7eb2e8f9f7 805 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 806 * on the complementary output.
<> 144:ef7eb2e8f9f7 807 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 808 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 809 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 810 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 811 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 812 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 813 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 814 * @retval HAL status
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 /* Check the parameters */
<> 144:ef7eb2e8f9f7 819 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 switch (Channel)
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 826 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828 break;
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 831 {
<> 144:ef7eb2e8f9f7 832 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 833 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 break;
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 840 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 break;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 847 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 break;
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 default:
<> 144:ef7eb2e8f9f7 852 break;
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 856 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 859 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 862 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Change the htim state */
<> 144:ef7eb2e8f9f7 865 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* Return function status */
<> 144:ef7eb2e8f9f7 868 return HAL_OK;
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /**
<> 144:ef7eb2e8f9f7 872 * @}
<> 144:ef7eb2e8f9f7 873 */
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 876 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 877 *
<> 144:ef7eb2e8f9f7 878 @verbatim
<> 144:ef7eb2e8f9f7 879 ==============================================================================
<> 144:ef7eb2e8f9f7 880 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 881 ==============================================================================
<> 144:ef7eb2e8f9f7 882 [..]
<> 144:ef7eb2e8f9f7 883 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 884 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 885 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 886 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 887 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 888 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 889 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 890 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 891 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 892 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 893 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 894 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 895 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 896 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 897 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 898 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 899 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 @endverbatim
<> 144:ef7eb2e8f9f7 902 * @{
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /**
<> 144:ef7eb2e8f9f7 906 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 907 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 908 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 909 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 910 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 911 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 912 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 913 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 914 * @retval HAL status
<> 144:ef7eb2e8f9f7 915 */
<> 144:ef7eb2e8f9f7 916 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 /* Check the parameters */
<> 144:ef7eb2e8f9f7 919 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 922 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 925 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 928 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Return function status */
<> 144:ef7eb2e8f9f7 931 return HAL_OK;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /**
<> 144:ef7eb2e8f9f7 935 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 936 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 937 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 938 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 939 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 940 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 941 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 942 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 943 * @retval HAL status
<> 144:ef7eb2e8f9f7 944 */
<> 144:ef7eb2e8f9f7 945 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 /* Check the parameters */
<> 144:ef7eb2e8f9f7 948 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 951 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 954 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 957 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Return function status */
<> 144:ef7eb2e8f9f7 960 return HAL_OK;
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /**
<> 144:ef7eb2e8f9f7 964 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 965 * complementary output.
<> 144:ef7eb2e8f9f7 966 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 967 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 968 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 969 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 970 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 971 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 972 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 973 * @retval HAL status
<> 144:ef7eb2e8f9f7 974 */
<> 144:ef7eb2e8f9f7 975 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 /* Check the parameters */
<> 144:ef7eb2e8f9f7 978 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 switch (Channel)
<> 144:ef7eb2e8f9f7 981 {
<> 144:ef7eb2e8f9f7 982 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 985 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 986 }
<> 144:ef7eb2e8f9f7 987 break;
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 992 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994 break;
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 997 {
<> 144:ef7eb2e8f9f7 998 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 999 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001 break;
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1006 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1007 }
<> 144:ef7eb2e8f9f7 1008 break;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 default:
<> 144:ef7eb2e8f9f7 1011 break;
<> 144:ef7eb2e8f9f7 1012 }
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1015 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1018 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1021 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1024 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Return function status */
<> 144:ef7eb2e8f9f7 1027 return HAL_OK;
<> 144:ef7eb2e8f9f7 1028 }
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /**
<> 144:ef7eb2e8f9f7 1031 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1032 * complementary output.
<> 144:ef7eb2e8f9f7 1033 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1034 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1035 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1036 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1037 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1038 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1039 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1040 * @retval HAL status
<> 144:ef7eb2e8f9f7 1041 */
<> 144:ef7eb2e8f9f7 1042 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1047 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 switch (Channel)
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1052 {
<> 144:ef7eb2e8f9f7 1053 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1054 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1055 }
<> 144:ef7eb2e8f9f7 1056 break;
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1061 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1062 }
<> 144:ef7eb2e8f9f7 1063 break;
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1068 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 break;
<> 144:ef7eb2e8f9f7 1071
<> 144:ef7eb2e8f9f7 1072 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1075 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1076 }
<> 144:ef7eb2e8f9f7 1077 break;
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 default:
<> 144:ef7eb2e8f9f7 1080 break;
<> 144:ef7eb2e8f9f7 1081 }
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1084 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1087 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1088 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1089 {
<> 144:ef7eb2e8f9f7 1090 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1094 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1097 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /* Return function status */
<> 144:ef7eb2e8f9f7 1100 return HAL_OK;
<> 144:ef7eb2e8f9f7 1101 }
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /**
<> 144:ef7eb2e8f9f7 1104 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1105 * complementary output
<> 144:ef7eb2e8f9f7 1106 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1107 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1108 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1109 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1110 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1111 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1112 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1113 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 1114 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1115 * @retval HAL status
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1120 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1123 {
<> 144:ef7eb2e8f9f7 1124 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132 else
<> 144:ef7eb2e8f9f7 1133 {
<> 144:ef7eb2e8f9f7 1134 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1135 }
<> 144:ef7eb2e8f9f7 1136 }
<> 144:ef7eb2e8f9f7 1137 switch (Channel)
<> 144:ef7eb2e8f9f7 1138 {
<> 144:ef7eb2e8f9f7 1139 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1142 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1145 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1148 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1151 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1152 }
<> 144:ef7eb2e8f9f7 1153 break;
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1156 {
<> 144:ef7eb2e8f9f7 1157 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1158 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1161 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1164 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1167 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 break;
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1172 {
<> 144:ef7eb2e8f9f7 1173 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1174 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1177 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1180 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1183 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185 break;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1188 {
<> 144:ef7eb2e8f9f7 1189 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1190 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1193 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1196 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1199 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1200 }
<> 144:ef7eb2e8f9f7 1201 break;
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 default:
<> 144:ef7eb2e8f9f7 1204 break;
<> 144:ef7eb2e8f9f7 1205 }
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1208 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1211 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1214 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /* Return function status */
<> 144:ef7eb2e8f9f7 1217 return HAL_OK;
<> 144:ef7eb2e8f9f7 1218 }
<> 144:ef7eb2e8f9f7 1219
<> 144:ef7eb2e8f9f7 1220 /**
<> 144:ef7eb2e8f9f7 1221 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1222 * output
<> 144:ef7eb2e8f9f7 1223 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1224 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1225 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1226 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1227 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1228 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1229 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1230 * @retval HAL status
<> 144:ef7eb2e8f9f7 1231 */
<> 144:ef7eb2e8f9f7 1232 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1233 {
<> 144:ef7eb2e8f9f7 1234 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1235 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 switch (Channel)
<> 144:ef7eb2e8f9f7 1238 {
<> 144:ef7eb2e8f9f7 1239 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1240 {
<> 144:ef7eb2e8f9f7 1241 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1242 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1243 }
<> 144:ef7eb2e8f9f7 1244 break;
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1247 {
<> 144:ef7eb2e8f9f7 1248 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1249 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1250 }
<> 144:ef7eb2e8f9f7 1251 break;
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1254 {
<> 144:ef7eb2e8f9f7 1255 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1256 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1257 }
<> 144:ef7eb2e8f9f7 1258 break;
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1261 {
<> 144:ef7eb2e8f9f7 1262 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1263 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1264 }
<> 144:ef7eb2e8f9f7 1265 break;
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 default:
<> 144:ef7eb2e8f9f7 1268 break;
<> 144:ef7eb2e8f9f7 1269 }
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1272 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1275 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1278 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1281 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /* Return function status */
<> 144:ef7eb2e8f9f7 1284 return HAL_OK;
<> 144:ef7eb2e8f9f7 1285 }
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /**
<> 144:ef7eb2e8f9f7 1288 * @}
<> 144:ef7eb2e8f9f7 1289 */
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1292 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1293 *
<> 144:ef7eb2e8f9f7 1294 @verbatim
<> 144:ef7eb2e8f9f7 1295 ==============================================================================
<> 144:ef7eb2e8f9f7 1296 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1297 ==============================================================================
<> 144:ef7eb2e8f9f7 1298 [..]
<> 144:ef7eb2e8f9f7 1299 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1300 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1301 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1302 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1303 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 @endverbatim
<> 144:ef7eb2e8f9f7 1306 * @{
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /**
<> 144:ef7eb2e8f9f7 1310 * @brief Starts the TIM One Pulse signal generation on the complemetary
<> 144:ef7eb2e8f9f7 1311 * output.
<> 144:ef7eb2e8f9f7 1312 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1313 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1314 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1315 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1316 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1317 * @retval HAL status
<> 144:ef7eb2e8f9f7 1318 */
<> 144:ef7eb2e8f9f7 1319 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1322 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1325 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1328 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /* Return function status */
<> 144:ef7eb2e8f9f7 1331 return HAL_OK;
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /**
<> 144:ef7eb2e8f9f7 1335 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1336 * output.
<> 144:ef7eb2e8f9f7 1337 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1338 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1339 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1340 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1341 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1342 * @retval HAL status
<> 144:ef7eb2e8f9f7 1343 */
<> 144:ef7eb2e8f9f7 1344 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1345 {
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1348 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1351 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1354 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1357 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /* Return function status */
<> 144:ef7eb2e8f9f7 1360 return HAL_OK;
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363 /**
<> 144:ef7eb2e8f9f7 1364 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1365 * complementary channel.
<> 144:ef7eb2e8f9f7 1366 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1367 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1368 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1369 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1370 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1371 * @retval HAL status
<> 144:ef7eb2e8f9f7 1372 */
<> 144:ef7eb2e8f9f7 1373 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1374 {
<> 144:ef7eb2e8f9f7 1375 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1376 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1379 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1382 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1385 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1388 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Return function status */
<> 144:ef7eb2e8f9f7 1391 return HAL_OK;
<> 144:ef7eb2e8f9f7 1392 }
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /**
<> 144:ef7eb2e8f9f7 1395 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1396 * complementary channel.
<> 144:ef7eb2e8f9f7 1397 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1398 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1399 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1402 * @retval HAL status
<> 144:ef7eb2e8f9f7 1403 */
<> 144:ef7eb2e8f9f7 1404 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1405 {
<> 144:ef7eb2e8f9f7 1406 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1407 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1410 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1413 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1416 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1419 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1422 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /* Return function status */
<> 144:ef7eb2e8f9f7 1425 return HAL_OK;
<> 144:ef7eb2e8f9f7 1426 }
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 /**
<> 144:ef7eb2e8f9f7 1429 * @}
<> 144:ef7eb2e8f9f7 1430 */
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1433 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1434 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1437 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1438 *
<> 144:ef7eb2e8f9f7 1439 @verbatim
<> 144:ef7eb2e8f9f7 1440 ==============================================================================
<> 144:ef7eb2e8f9f7 1441 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1442 ==============================================================================
<> 144:ef7eb2e8f9f7 1443 [..]
<> 144:ef7eb2e8f9f7 1444 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1445 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1446 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1447 (+) Configure Master synchronization.
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 @endverbatim
<> 144:ef7eb2e8f9f7 1450 * @{
<> 144:ef7eb2e8f9f7 1451 */
<> 144:ef7eb2e8f9f7 1452
<> 144:ef7eb2e8f9f7 1453 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 1454 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 1455 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /**
<> 144:ef7eb2e8f9f7 1458 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1459 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1460 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1461 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1462 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1463 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1464 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1465 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1466 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1467 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1468 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1469 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1470 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1471 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1472 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1473 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1474 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1475 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1476 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1477 * @retval HAL status
<> 144:ef7eb2e8f9f7 1478 */
<> 144:ef7eb2e8f9f7 1479 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1480 {
<> 144:ef7eb2e8f9f7 1481 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1482 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1483 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1488 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1489 {
<> 144:ef7eb2e8f9f7 1490 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1491 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1492 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1493 }
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1496 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1497 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1498 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1499 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503 return HAL_OK;
<> 144:ef7eb2e8f9f7 1504 }
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /**
<> 144:ef7eb2e8f9f7 1507 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1508 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1509 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1510 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1511 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1512 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1513 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1514 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1515 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1516 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1517 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1518 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1519 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1520 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1521 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1522 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1523 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1524 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1525 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1526 * @retval HAL status
<> 144:ef7eb2e8f9f7 1527 */
<> 144:ef7eb2e8f9f7 1528 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1529 {
<> 144:ef7eb2e8f9f7 1530 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1531 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1532 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1537 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1538 {
<> 144:ef7eb2e8f9f7 1539 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1540 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1541 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1542 }
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1545 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1546 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1547 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1548 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1551 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 return HAL_OK;
<> 144:ef7eb2e8f9f7 1556 }
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 /**
<> 144:ef7eb2e8f9f7 1559 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1560 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1561 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1562 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1563 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1564 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1565 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1566 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1567 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1568 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1569 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1570 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1571 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1572 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1573 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1574 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1575 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1576 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1577 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1578 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1579 * @retval HAL status
<> 144:ef7eb2e8f9f7 1580 */
<> 144:ef7eb2e8f9f7 1581 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1582 {
<> 144:ef7eb2e8f9f7 1583 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1584 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1585 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1590 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1591 {
<> 144:ef7eb2e8f9f7 1592 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1593 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1594 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1595 }
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1598 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1599 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1600 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1601 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1602
<> 144:ef7eb2e8f9f7 1603 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1604 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1605 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1606 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1607 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1610 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 return HAL_OK;
<> 144:ef7eb2e8f9f7 1615 }
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /**
<> 144:ef7eb2e8f9f7 1618 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1619 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 1620 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1621 * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1622 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1623 * @retval HAL status
<> 144:ef7eb2e8f9f7 1624 */
<> 144:ef7eb2e8f9f7 1625 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1626 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1627 {
<> 144:ef7eb2e8f9f7 1628 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1629 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1630 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1631 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1632 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 1633 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1634 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1635 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1636 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 /* Process Locked */
<> 144:ef7eb2e8f9f7 1639 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1640
<> 144:ef7eb2e8f9f7 1641 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 1644 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 144:ef7eb2e8f9f7 1645 htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
<> 144:ef7eb2e8f9f7 1646 sBreakDeadTimeConfig->OffStateIDLEMode |
<> 144:ef7eb2e8f9f7 1647 sBreakDeadTimeConfig->LockLevel |
<> 144:ef7eb2e8f9f7 1648 sBreakDeadTimeConfig->DeadTime |
<> 144:ef7eb2e8f9f7 1649 sBreakDeadTimeConfig->BreakState |
<> 144:ef7eb2e8f9f7 1650 sBreakDeadTimeConfig->BreakPolarity |
<> 144:ef7eb2e8f9f7 1651 sBreakDeadTimeConfig->AutomaticOutput;
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658 return HAL_OK;
<> 144:ef7eb2e8f9f7 1659 }
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1662 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1663 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 /**
<> 144:ef7eb2e8f9f7 1666 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 1667 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 1668 * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1669 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1670 * mode.
<> 144:ef7eb2e8f9f7 1671 * @retval HAL status
<> 144:ef7eb2e8f9f7 1672 */
<> 144:ef7eb2e8f9f7 1673 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1674 {
<> 144:ef7eb2e8f9f7 1675 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1676 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1677 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1678 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1679
<> 144:ef7eb2e8f9f7 1680 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1681
<> 144:ef7eb2e8f9f7 1682 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1685 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1686 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1687 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1690 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1691 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1692 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 return HAL_OK;
<> 144:ef7eb2e8f9f7 1699 }
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 /**
<> 144:ef7eb2e8f9f7 1702 * @}
<> 144:ef7eb2e8f9f7 1703 */
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1706 * @brief Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1707 *
<> 144:ef7eb2e8f9f7 1708 @verbatim
<> 144:ef7eb2e8f9f7 1709 ==============================================================================
<> 144:ef7eb2e8f9f7 1710 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 1711 ==============================================================================
<> 144:ef7eb2e8f9f7 1712 [..]
<> 144:ef7eb2e8f9f7 1713 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 1714 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 1715 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 @endverbatim
<> 144:ef7eb2e8f9f7 1718 * @{
<> 144:ef7eb2e8f9f7 1719 */
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /**
<> 144:ef7eb2e8f9f7 1722 * @brief Hall commutation changed callback in non blocking mode
<> 144:ef7eb2e8f9f7 1723 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1724 * @retval None
<> 144:ef7eb2e8f9f7 1725 */
<> 144:ef7eb2e8f9f7 1726 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1727 {
<> 144:ef7eb2e8f9f7 1728 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1729 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1730 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1731 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1732 */
<> 144:ef7eb2e8f9f7 1733 }
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 /**
<> 144:ef7eb2e8f9f7 1736 * @brief Hall Break detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 1737 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1738 * @retval None
<> 144:ef7eb2e8f9f7 1739 */
<> 144:ef7eb2e8f9f7 1740 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1741 {
<> 144:ef7eb2e8f9f7 1742 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1743 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1744 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1745 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1746 */
<> 144:ef7eb2e8f9f7 1747 }
<> 144:ef7eb2e8f9f7 1748
<> 144:ef7eb2e8f9f7 1749 /**
<> 144:ef7eb2e8f9f7 1750 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 1751 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 1752 * @retval None
<> 144:ef7eb2e8f9f7 1753 */
<> 144:ef7eb2e8f9f7 1754 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1755 {
<> 144:ef7eb2e8f9f7 1756 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 1761 }
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /**
<> 144:ef7eb2e8f9f7 1764 * @}
<> 144:ef7eb2e8f9f7 1765 */
<> 144:ef7eb2e8f9f7 1766
<> 144:ef7eb2e8f9f7 1767 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 1768 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 1769 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1772 * @brief Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1773 *
<> 144:ef7eb2e8f9f7 1774 @verbatim
<> 144:ef7eb2e8f9f7 1775 ==============================================================================
<> 144:ef7eb2e8f9f7 1776 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1777 ==============================================================================
<> 144:ef7eb2e8f9f7 1778 [..]
<> 144:ef7eb2e8f9f7 1779 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1780 and the data flow.
<> 144:ef7eb2e8f9f7 1781
<> 144:ef7eb2e8f9f7 1782 @endverbatim
<> 144:ef7eb2e8f9f7 1783 * @{
<> 144:ef7eb2e8f9f7 1784 */
<> 144:ef7eb2e8f9f7 1785
<> 144:ef7eb2e8f9f7 1786 /**
<> 144:ef7eb2e8f9f7 1787 * @brief Return the TIM Hall Sensor interface state
<> 144:ef7eb2e8f9f7 1788 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 1789 * @retval HAL state
<> 144:ef7eb2e8f9f7 1790 */
<> 144:ef7eb2e8f9f7 1791 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1792 {
<> 144:ef7eb2e8f9f7 1793 return htim->State;
<> 144:ef7eb2e8f9f7 1794 }
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 /**
<> 144:ef7eb2e8f9f7 1797 * @}
<> 144:ef7eb2e8f9f7 1798 */
<> 144:ef7eb2e8f9f7 1799 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1800 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1801 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 /**
<> 144:ef7eb2e8f9f7 1804 * @}
<> 144:ef7eb2e8f9f7 1805 */
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 #if defined (STM32F100xB) || defined (STM32F100xE) || \
<> 144:ef7eb2e8f9f7 1808 defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
<> 144:ef7eb2e8f9f7 1809 defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 1812 * @{
<> 144:ef7eb2e8f9f7 1813 */
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /**
<> 144:ef7eb2e8f9f7 1816 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 1817 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 1818 * @param Channel : specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1819 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1820 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1821 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1822 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1823 * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 1824 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 1825 * @retval None
<> 144:ef7eb2e8f9f7 1826 */
<> 144:ef7eb2e8f9f7 1827 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 1828 {
<> 144:ef7eb2e8f9f7 1829 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 1832
<> 144:ef7eb2e8f9f7 1833 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1834 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 1835
<> 144:ef7eb2e8f9f7 1836 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1837 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 1838 }
<> 144:ef7eb2e8f9f7 1839
<> 144:ef7eb2e8f9f7 1840 /**
<> 144:ef7eb2e8f9f7 1841 * @}
<> 144:ef7eb2e8f9f7 1842 */
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
<> 144:ef7eb2e8f9f7 1845 /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
<> 144:ef7eb2e8f9f7 1846 /* defined(STM32F105xC) || defined(STM32F107xC) */
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1849 /**
<> 144:ef7eb2e8f9f7 1850 * @}
<> 144:ef7eb2e8f9f7 1851 */
<> 144:ef7eb2e8f9f7 1852
<> 144:ef7eb2e8f9f7 1853 /**
<> 144:ef7eb2e8f9f7 1854 * @}
<> 144:ef7eb2e8f9f7 1855 */
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/