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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f1xx_hal_rcc.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief RCC HAL module driver.
<>	144:ef7eb2e8f9f7	6	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	7	* functionalities of the Reset and Clock Control (RCC) peripheral:
<>	144:ef7eb2e8f9f7	8	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	9	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	@verbatim
<>	144:ef7eb2e8f9f7	12	==============================================================================
<>	144:ef7eb2e8f9f7	13	##### RCC specific features #####
<>	144:ef7eb2e8f9f7	14	==============================================================================
<>	144:ef7eb2e8f9f7	15	[..]
<>	144:ef7eb2e8f9f7	16	After reset the device is running from Internal High Speed oscillator
<>	144:ef7eb2e8f9f7	17	(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
<>	144:ef7eb2e8f9f7	18	and all peripherals are off except internal SRAM, Flash and JTAG.
<>	144:ef7eb2e8f9f7	19	(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
<>	144:ef7eb2e8f9f7	20	all peripherals mapped on these buses are running at HSI speed.
<>	144:ef7eb2e8f9f7	21	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
<>	144:ef7eb2e8f9f7	22	(+) All GPIOs are in input floating state, except the JTAG pins which
<>	144:ef7eb2e8f9f7	23	are assigned to be used for debug purpose.
<>	144:ef7eb2e8f9f7	24	[..] Once the device started from reset, the user application has to:
<>	144:ef7eb2e8f9f7	25	(+) Configure the clock source to be used to drive the System clock
<>	144:ef7eb2e8f9f7	26	(if the application needs higher frequency/performance)
<>	144:ef7eb2e8f9f7	27	(+) Configure the System clock frequency and Flash settings
<>	144:ef7eb2e8f9f7	28	(+) Configure the AHB and APB buses prescalers
<>	144:ef7eb2e8f9f7	29	(+) Enable the clock for the peripheral(s) to be used
<>	144:ef7eb2e8f9f7	30	(+) Configure the clock source(s) for peripherals whose clocks are not
<>	144:ef7eb2e8f9f7	31	derived from the System clock (I2S, RTC, ADC, USB OTG FS)
<>	144:ef7eb2e8f9f7	32
<>	144:ef7eb2e8f9f7	33	##### RCC Limitations #####
<>	144:ef7eb2e8f9f7	34	==============================================================================
<>	144:ef7eb2e8f9f7	35	[..]
<>	144:ef7eb2e8f9f7	36	A delay between an RCC peripheral clock enable and the effective peripheral
<>	144:ef7eb2e8f9f7	37	enabling should be taken into account in order to manage the peripheral read/write
<>	144:ef7eb2e8f9f7	38	from/to registers.
<>	144:ef7eb2e8f9f7	39	(+) This delay depends on the peripheral mapping.
<>	144:ef7eb2e8f9f7	40	(++) AHB & APB peripherals, 1 dummy read is necessary
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	[..]
<>	144:ef7eb2e8f9f7	43	Workarounds:
<>	144:ef7eb2e8f9f7	44	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<>	144:ef7eb2e8f9f7	45	inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	@endverbatim
<>	144:ef7eb2e8f9f7	48	******************************************************************************
<>	144:ef7eb2e8f9f7	49	* @attention
<>	144:ef7eb2e8f9f7	50	*
<>	144:ef7eb2e8f9f7	51	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	52	*
<>	144:ef7eb2e8f9f7	53	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	54	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	55	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	56	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	57	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	58	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	59	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	60	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	61	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	62	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	63	*
<>	144:ef7eb2e8f9f7	64	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	65	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	66	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	67	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	68	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	69	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	70	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	71	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	72	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	73	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	74	*
<>	144:ef7eb2e8f9f7	75	******************************************************************************
<>	144:ef7eb2e8f9f7	76	*/
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	79	#include "stm32f1xx_hal.h"
<>	144:ef7eb2e8f9f7	80
<>	144:ef7eb2e8f9f7	81	/** @addtogroup STM32F1xx_HAL_Driver
<>	144:ef7eb2e8f9f7	82	* @{
<>	144:ef7eb2e8f9f7	83	*/
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	/** @defgroup RCC RCC
<>	144:ef7eb2e8f9f7	86	* @brief RCC HAL module driver
<>	144:ef7eb2e8f9f7	87	* @{
<>	144:ef7eb2e8f9f7	88	*/
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	#ifdef HAL_RCC_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	93	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	94	/** @defgroup RCC_Private_Constants RCC Private Constants
<>	144:ef7eb2e8f9f7	95	* @{
<>	144:ef7eb2e8f9f7	96	*/
<>	144:ef7eb2e8f9f7	97	/**
<>	144:ef7eb2e8f9f7	98	* @}
<>	144:ef7eb2e8f9f7	99	*/
<>	144:ef7eb2e8f9f7	100	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	101	/** @defgroup RCC_Private_Macros RCC Private Macros
<>	144:ef7eb2e8f9f7	102	* @{
<>	144:ef7eb2e8f9f7	103	*/
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<>	144:ef7eb2e8f9f7	106	#define MCO1_GPIO_PORT GPIOA
<>	144:ef7eb2e8f9f7	107	#define MCO1_PIN GPIO_PIN_8
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	/**
<>	144:ef7eb2e8f9f7	110	* @}
<>	144:ef7eb2e8f9f7	111	*/
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	114	/** @defgroup RCC_Private_Variables RCC Private Variables
<>	144:ef7eb2e8f9f7	115	* @{
<>	144:ef7eb2e8f9f7	116	*/
<>	144:ef7eb2e8f9f7	117	/**
<>	144:ef7eb2e8f9f7	118	* @}
<>	144:ef7eb2e8f9f7	119	*/
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	/* Private function prototypes -----------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	122	static void RCC_Delay(uint32_t mdelay);
AnnaBridge	165:e614a9f1c9e2	123
AnnaBridge	165:e614a9f1c9e2	124	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	/** @defgroup RCC_Exported_Functions RCC Exported Functions
<>	144:ef7eb2e8f9f7	127	* @{
<>	144:ef7eb2e8f9f7	128	*/
<>	144:ef7eb2e8f9f7	129
<>	144:ef7eb2e8f9f7	130	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	131	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	132	*
<>	144:ef7eb2e8f9f7	133	@verbatim
<>	144:ef7eb2e8f9f7	134	===============================================================================
<>	144:ef7eb2e8f9f7	135	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	136	===============================================================================
<>	144:ef7eb2e8f9f7	137	[..]
<>	144:ef7eb2e8f9f7	138	This section provides functions allowing to configure the internal/external oscillators
<>	144:ef7eb2e8f9f7	139	(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
<>	144:ef7eb2e8f9f7	140	and APB2).
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	[..] Internal/external clock and PLL configuration
<>	144:ef7eb2e8f9f7	143	(#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
<>	144:ef7eb2e8f9f7	144	the PLL as System clock source.
<>	144:ef7eb2e8f9f7	145	(#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
<>	144:ef7eb2e8f9f7	146	clock source.
<>	144:ef7eb2e8f9f7	147
<>	144:ef7eb2e8f9f7	148	(#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
<>	144:ef7eb2e8f9f7	149	through the PLL as System clock source. Can be used also as RTC clock source.
<>	144:ef7eb2e8f9f7	150
<>	144:ef7eb2e8f9f7	151	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	(#) PLL (clocked by HSI or HSE), featuring different output clocks:
<>	144:ef7eb2e8f9f7	154	(++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
<>	144:ef7eb2e8f9f7	155	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
<>	144:ef7eb2e8f9f7	158	and if a HSE clock failure occurs(HSE used directly or through PLL as System
<>	144:ef7eb2e8f9f7	159	clock source), the System clocks automatically switched to HSI and an interrupt
<>	144:ef7eb2e8f9f7	160	is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
<>	144:ef7eb2e8f9f7	161	(Non-Maskable Interrupt) exception vector.
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	(#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
<>	144:ef7eb2e8f9f7	164	HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	[..] System, AHB and APB buses clocks configuration
<>	144:ef7eb2e8f9f7	167	(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
<>	144:ef7eb2e8f9f7	168	HSE and PLL.
<>	144:ef7eb2e8f9f7	169	The AHB clock (HCLK) is derived from System clock through configurable
<>	144:ef7eb2e8f9f7	170	prescaler and used to clock the CPU, memory and peripherals mapped
<>	144:ef7eb2e8f9f7	171	on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
<>	144:ef7eb2e8f9f7	172	from AHB clock through configurable prescalers and used to clock
<>	144:ef7eb2e8f9f7	173	the peripherals mapped on these buses. You can use
<>	144:ef7eb2e8f9f7	174	"@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<>	144:ef7eb2e8f9f7	175
<>	144:ef7eb2e8f9f7	176	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
<>	144:ef7eb2e8f9f7	177	(+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
<>	144:ef7eb2e8f9f7	178	divided by 128.
<>	144:ef7eb2e8f9f7	179	(+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
<>	144:ef7eb2e8f9f7	180	to work correctly. This clock is derived of the main PLL through PLL Multiplier.
<>	144:ef7eb2e8f9f7	181	(+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
<>	144:ef7eb2e8f9f7	182	(+@) IWDG clock which is always the LSI clock.
<>	144:ef7eb2e8f9f7	183
<>	144:ef7eb2e8f9f7	184	(#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
<>	144:ef7eb2e8f9f7	185	For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
<>	144:ef7eb2e8f9f7	186	Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
<>	144:ef7eb2e8f9f7	187	@endverbatim
<>	144:ef7eb2e8f9f7	188	* @{
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	/*
<>	144:ef7eb2e8f9f7	192	Additional consideration on the SYSCLK based on Latency settings:
<>	144:ef7eb2e8f9f7	193	+-----------------------------------------------+
<>	144:ef7eb2e8f9f7	194	\| Latency \| SYSCLK clock frequency (MHz) \|
<>	144:ef7eb2e8f9f7	195	\|---------------\|-------------------------------\|
<>	144:ef7eb2e8f9f7	196	\|0WS(1CPU cycle)\| 0 < SYSCLK <= 24 \|
<>	144:ef7eb2e8f9f7	197	\|---------------\|-------------------------------\|
<>	144:ef7eb2e8f9f7	198	\|1WS(2CPU cycle)\| 24 < SYSCLK <= 48 \|
<>	144:ef7eb2e8f9f7	199	\|---------------\|-------------------------------\|
<>	144:ef7eb2e8f9f7	200	\|2WS(3CPU cycle)\| 48 < SYSCLK <= 72 \|
<>	144:ef7eb2e8f9f7	201	+-----------------------------------------------+
<>	144:ef7eb2e8f9f7	202	*/
<>	144:ef7eb2e8f9f7	203
<>	144:ef7eb2e8f9f7	204	/**
<>	144:ef7eb2e8f9f7	205	* @brief Resets the RCC clock configuration to the default reset state.
<>	144:ef7eb2e8f9f7	206	* @note The default reset state of the clock configuration is given below:
<>	144:ef7eb2e8f9f7	207	* - HSI ON and used as system clock source
AnnaBridge	187:0387e8f68319	208	* - HSE, PLL, PLL2 and PLL3 are OFF
<>	144:ef7eb2e8f9f7	209	* - AHB, APB1 and APB2 prescaler set to 1.
<>	144:ef7eb2e8f9f7	210	* - CSS and MCO1 OFF
<>	144:ef7eb2e8f9f7	211	* - All interrupts disabled
AnnaBridge	187:0387e8f68319	212	* - All flags are cleared
<>	144:ef7eb2e8f9f7	213	* @note This function does not modify the configuration of the
<>	144:ef7eb2e8f9f7	214	* - Peripheral clocks
<>	144:ef7eb2e8f9f7	215	* - LSI, LSE and RTC clocks
AnnaBridge	187:0387e8f68319	216	* @retval HAL_StatusTypeDef
<>	144:ef7eb2e8f9f7	217	*/
AnnaBridge	187:0387e8f68319	218	HAL_StatusTypeDef HAL_RCC_DeInit(void)
<>	144:ef7eb2e8f9f7	219	{
AnnaBridge	187:0387e8f68319	220	uint32_t tickstart;
AnnaBridge	187:0387e8f68319	221
AnnaBridge	187:0387e8f68319	222	/* Get Start Tick */
AnnaBridge	187:0387e8f68319	223	tickstart = HAL_GetTick();
AnnaBridge	187:0387e8f68319	224
AnnaBridge	187:0387e8f68319	225	/* Set HSION bit */
AnnaBridge	187:0387e8f68319	226	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	187:0387e8f68319	227
AnnaBridge	187:0387e8f68319	228	/* Wait till HSI is ready */
AnnaBridge	187:0387e8f68319	229	while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
AnnaBridge	187:0387e8f68319	230	{
AnnaBridge	187:0387e8f68319	231	if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
AnnaBridge	187:0387e8f68319	232	{
AnnaBridge	187:0387e8f68319	233	return HAL_TIMEOUT;
AnnaBridge	187:0387e8f68319	234	}
AnnaBridge	187:0387e8f68319	235	}
AnnaBridge	187:0387e8f68319	236
AnnaBridge	187:0387e8f68319	237	/* Set HSITRIM bits to the reset value */
AnnaBridge	187:0387e8f68319	238	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
AnnaBridge	187:0387e8f68319	239
AnnaBridge	187:0387e8f68319	240	/* Get Start Tick */
AnnaBridge	187:0387e8f68319	241	tickstart = HAL_GetTick();
AnnaBridge	187:0387e8f68319	242
AnnaBridge	187:0387e8f68319	243	/* Reset CFGR register */
AnnaBridge	187:0387e8f68319	244	CLEAR_REG(RCC->CFGR);
AnnaBridge	187:0387e8f68319	245
AnnaBridge	187:0387e8f68319	246	/* Wait till clock switch is ready */
AnnaBridge	187:0387e8f68319	247	while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
AnnaBridge	187:0387e8f68319	248	{
AnnaBridge	187:0387e8f68319	249	if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
AnnaBridge	187:0387e8f68319	250	{
AnnaBridge	187:0387e8f68319	251	return HAL_TIMEOUT;
AnnaBridge	187:0387e8f68319	252	}
AnnaBridge	187:0387e8f68319	253	}
AnnaBridge	187:0387e8f68319	254
AnnaBridge	187:0387e8f68319	255	/* Update the SystemCoreClock global variable */
AnnaBridge	187:0387e8f68319	256	SystemCoreClock = HSI_VALUE;
<>	144:ef7eb2e8f9f7	257
AnnaBridge	187:0387e8f68319	258	/* Adapt Systick interrupt period */
AnnaBridge	187:0387e8f68319	259	if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
AnnaBridge	187:0387e8f68319	260	{
AnnaBridge	187:0387e8f68319	261	return HAL_ERROR;
AnnaBridge	187:0387e8f68319	262	}
AnnaBridge	187:0387e8f68319	263
AnnaBridge	187:0387e8f68319	264	/* Get Start Tick */
AnnaBridge	187:0387e8f68319	265	tickstart = HAL_GetTick();
AnnaBridge	187:0387e8f68319	266
AnnaBridge	187:0387e8f68319	267	/* Second step is to clear PLLON bit */
AnnaBridge	187:0387e8f68319	268	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	187:0387e8f68319	269
AnnaBridge	187:0387e8f68319	270	/* Wait till PLL is disabled */
AnnaBridge	187:0387e8f68319	271	while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
AnnaBridge	187:0387e8f68319	272	{
AnnaBridge	187:0387e8f68319	273	if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
AnnaBridge	187:0387e8f68319	274	{
AnnaBridge	187:0387e8f68319	275	return HAL_TIMEOUT;
AnnaBridge	187:0387e8f68319	276	}
AnnaBridge	187:0387e8f68319	277	}
AnnaBridge	187:0387e8f68319	278
AnnaBridge	187:0387e8f68319	279	/* Ensure to reset PLLSRC and PLLMUL bits */
AnnaBridge	187:0387e8f68319	280	CLEAR_REG(RCC->CFGR);
AnnaBridge	187:0387e8f68319	281
AnnaBridge	187:0387e8f68319	282	/* Get Start Tick */
AnnaBridge	187:0387e8f68319	283	tickstart = HAL_GetTick();
AnnaBridge	187:0387e8f68319	284
AnnaBridge	187:0387e8f68319	285	/* Reset HSEON & CSSON bits */
AnnaBridge	187:0387e8f68319	286	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON);
AnnaBridge	187:0387e8f68319	287
AnnaBridge	187:0387e8f68319	288	/* Wait till HSE is disabled */
AnnaBridge	187:0387e8f68319	289	while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
AnnaBridge	187:0387e8f68319	290	{
AnnaBridge	187:0387e8f68319	291	if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
AnnaBridge	187:0387e8f68319	292	{
AnnaBridge	187:0387e8f68319	293	return HAL_TIMEOUT;
AnnaBridge	187:0387e8f68319	294	}
AnnaBridge	187:0387e8f68319	295	}
AnnaBridge	187:0387e8f68319	296
<>	144:ef7eb2e8f9f7	297	/* Reset HSEBYP bit */
<>	144:ef7eb2e8f9f7	298	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	187:0387e8f68319	299
AnnaBridge	187:0387e8f68319	300	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	187:0387e8f68319	301	/* Get Start Tick */
AnnaBridge	187:0387e8f68319	302	tickstart = HAL_GetTick();
AnnaBridge	187:0387e8f68319	303
AnnaBridge	187:0387e8f68319	304	/* Clear PLL2ON bit */
AnnaBridge	187:0387e8f68319	305	CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
AnnaBridge	187:0387e8f68319	306
AnnaBridge	187:0387e8f68319	307	/* Wait till PLL2 is disabled */
AnnaBridge	187:0387e8f68319	308	while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)
AnnaBridge	187:0387e8f68319	309	{
AnnaBridge	187:0387e8f68319	310	if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
AnnaBridge	187:0387e8f68319	311	{
AnnaBridge	187:0387e8f68319	312	return HAL_TIMEOUT;
AnnaBridge	187:0387e8f68319	313	}
AnnaBridge	187:0387e8f68319	314	}
AnnaBridge	187:0387e8f68319	315	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	187:0387e8f68319	316
AnnaBridge	187:0387e8f68319	317	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	187:0387e8f68319	318	/* Get Start Tick */
AnnaBridge	187:0387e8f68319	319	tickstart = HAL_GetTick();
AnnaBridge	187:0387e8f68319	320
AnnaBridge	187:0387e8f68319	321	/* Clear PLL3ON bit */
AnnaBridge	187:0387e8f68319	322	CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
AnnaBridge	187:0387e8f68319	323
AnnaBridge	187:0387e8f68319	324	/* Wait till PLL3 is disabled */
AnnaBridge	187:0387e8f68319	325	while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)
AnnaBridge	187:0387e8f68319	326	{
AnnaBridge	187:0387e8f68319	327	if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
AnnaBridge	187:0387e8f68319	328	{
AnnaBridge	187:0387e8f68319	329	return HAL_TIMEOUT;
AnnaBridge	187:0387e8f68319	330	}
AnnaBridge	187:0387e8f68319	331	}
AnnaBridge	187:0387e8f68319	332	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	187:0387e8f68319	333
AnnaBridge	187:0387e8f68319	334	#if defined(RCC_CFGR2_PREDIV1)
<>	144:ef7eb2e8f9f7	335	/* Reset CFGR2 register */
<>	144:ef7eb2e8f9f7	336	CLEAR_REG(RCC->CFGR2);
AnnaBridge	187:0387e8f68319	337	#endif /* RCC_CFGR2_PREDIV1 */
<>	144:ef7eb2e8f9f7	338
AnnaBridge	187:0387e8f68319	339	/* Reset all CSR flags */
AnnaBridge	187:0387e8f68319	340	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	187:0387e8f68319	341
<>	144:ef7eb2e8f9f7	342	/* Disable all interrupts */
<>	144:ef7eb2e8f9f7	343	CLEAR_REG(RCC->CIR);
<>	144:ef7eb2e8f9f7	344
AnnaBridge	187:0387e8f68319	345	return HAL_OK;
<>	144:ef7eb2e8f9f7	346	}
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/**
<>	144:ef7eb2e8f9f7	349	* @brief Initializes the RCC Oscillators according to the specified parameters in the
<>	144:ef7eb2e8f9f7	350	* RCC_OscInitTypeDef.
<>	144:ef7eb2e8f9f7	351	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<>	144:ef7eb2e8f9f7	352	* contains the configuration information for the RCC Oscillators.
<>	144:ef7eb2e8f9f7	353	* @note The PLL is not disabled when used as system clock.
<>	144:ef7eb2e8f9f7	354	* @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
<>	144:ef7eb2e8f9f7	355	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<>	144:ef7eb2e8f9f7	356	* supported by this macro. User should request a transition to LSE Off
<>	144:ef7eb2e8f9f7	357	* first and then LSE On or LSE Bypass.
<>	144:ef7eb2e8f9f7	358	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<>	144:ef7eb2e8f9f7	359	* supported by this macro. User should request a transition to HSE Off
<>	144:ef7eb2e8f9f7	360	* first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	361	* @retval HAL status
<>	144:ef7eb2e8f9f7	362	*/
<>	144:ef7eb2e8f9f7	363	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<>	144:ef7eb2e8f9f7	364	{
AnnaBridge	165:e614a9f1c9e2	365	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/* Check the parameters */
<>	144:ef7eb2e8f9f7	368	assert_param(RCC_OscInitStruct != NULL);
<>	144:ef7eb2e8f9f7	369	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<>	144:ef7eb2e8f9f7	370
<>	144:ef7eb2e8f9f7	371	/------------------------------- HSE Configuration ------------------------/
<>	144:ef7eb2e8f9f7	372	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<>	144:ef7eb2e8f9f7	373	{
<>	144:ef7eb2e8f9f7	374	/* Check the parameters */
<>	144:ef7eb2e8f9f7	375	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
<>	144:ef7eb2e8f9f7	378	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
<>	144:ef7eb2e8f9f7	379	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
<>	144:ef7eb2e8f9f7	380	{
<>	144:ef7eb2e8f9f7	381	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<>	144:ef7eb2e8f9f7	382	{
<>	144:ef7eb2e8f9f7	383	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	384	}
<>	144:ef7eb2e8f9f7	385	}
<>	144:ef7eb2e8f9f7	386	else
<>	144:ef7eb2e8f9f7	387	{
<>	144:ef7eb2e8f9f7	388	/* Set the new HSE configuration ---------------------------------------*/
<>	144:ef7eb2e8f9f7	389	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	/* Check the HSE State */
<>	144:ef7eb2e8f9f7	393	if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<>	144:ef7eb2e8f9f7	394	{
<>	144:ef7eb2e8f9f7	395	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	396	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/* Wait till HSE is ready */
<>	144:ef7eb2e8f9f7	399	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<>	144:ef7eb2e8f9f7	400	{
<>	144:ef7eb2e8f9f7	401	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	402	{
<>	144:ef7eb2e8f9f7	403	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	404	}
<>	144:ef7eb2e8f9f7	405	}
<>	144:ef7eb2e8f9f7	406	}
<>	144:ef7eb2e8f9f7	407	else
<>	144:ef7eb2e8f9f7	408	{
<>	144:ef7eb2e8f9f7	409	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	410	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	/* Wait till HSE is disabled */
<>	144:ef7eb2e8f9f7	413	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<>	144:ef7eb2e8f9f7	414	{
<>	144:ef7eb2e8f9f7	415	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	416	{
<>	144:ef7eb2e8f9f7	417	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	418	}
<>	144:ef7eb2e8f9f7	419	}
<>	144:ef7eb2e8f9f7	420	}
<>	144:ef7eb2e8f9f7	421	}
<>	144:ef7eb2e8f9f7	422	}
<>	144:ef7eb2e8f9f7	423	/----------------------------- HSI Configuration --------------------------/
<>	144:ef7eb2e8f9f7	424	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<>	144:ef7eb2e8f9f7	425	{
<>	144:ef7eb2e8f9f7	426	/* Check the parameters */
<>	144:ef7eb2e8f9f7	427	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<>	144:ef7eb2e8f9f7	428	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<>	144:ef7eb2e8f9f7	431	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
<>	144:ef7eb2e8f9f7	432	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
<>	144:ef7eb2e8f9f7	433	{
<>	144:ef7eb2e8f9f7	434	/* When HSI is used as system clock it will not disabled */
<>	144:ef7eb2e8f9f7	435	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<>	144:ef7eb2e8f9f7	436	{
<>	144:ef7eb2e8f9f7	437	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	438	}
<>	144:ef7eb2e8f9f7	439	/* Otherwise, just the calibration is allowed */
<>	144:ef7eb2e8f9f7	440	else
<>	144:ef7eb2e8f9f7	441	{
<>	144:ef7eb2e8f9f7	442	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<>	144:ef7eb2e8f9f7	443	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<>	144:ef7eb2e8f9f7	444	}
<>	144:ef7eb2e8f9f7	445	}
<>	144:ef7eb2e8f9f7	446	else
<>	144:ef7eb2e8f9f7	447	{
<>	144:ef7eb2e8f9f7	448	/* Check the HSI State */
<>	144:ef7eb2e8f9f7	449	if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
<>	144:ef7eb2e8f9f7	450	{
<>	144:ef7eb2e8f9f7	451	/* Enable the Internal High Speed oscillator (HSI). */
<>	144:ef7eb2e8f9f7	452	__HAL_RCC_HSI_ENABLE();
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	455	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	/* Wait till HSI is ready */
<>	144:ef7eb2e8f9f7	458	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<>	144:ef7eb2e8f9f7	459	{
<>	144:ef7eb2e8f9f7	460	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	461	{
<>	144:ef7eb2e8f9f7	462	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	463	}
<>	144:ef7eb2e8f9f7	464	}
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<>	144:ef7eb2e8f9f7	467	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<>	144:ef7eb2e8f9f7	468	}
<>	144:ef7eb2e8f9f7	469	else
<>	144:ef7eb2e8f9f7	470	{
<>	144:ef7eb2e8f9f7	471	/* Disable the Internal High Speed oscillator (HSI). */
<>	144:ef7eb2e8f9f7	472	__HAL_RCC_HSI_DISABLE();
<>	144:ef7eb2e8f9f7	473
<>	144:ef7eb2e8f9f7	474	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	475	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	/* Wait till HSI is disabled */
<>	144:ef7eb2e8f9f7	478	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<>	144:ef7eb2e8f9f7	479	{
<>	144:ef7eb2e8f9f7	480	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	481	{
<>	144:ef7eb2e8f9f7	482	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	483	}
<>	144:ef7eb2e8f9f7	484	}
<>	144:ef7eb2e8f9f7	485	}
<>	144:ef7eb2e8f9f7	486	}
<>	144:ef7eb2e8f9f7	487	}
<>	144:ef7eb2e8f9f7	488	/------------------------------ LSI Configuration -------------------------/
<>	144:ef7eb2e8f9f7	489	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<>	144:ef7eb2e8f9f7	490	{
<>	144:ef7eb2e8f9f7	491	/* Check the parameters */
<>	144:ef7eb2e8f9f7	492	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	/* Check the LSI State */
<>	144:ef7eb2e8f9f7	495	if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
<>	144:ef7eb2e8f9f7	496	{
<>	144:ef7eb2e8f9f7	497	/* Enable the Internal Low Speed oscillator (LSI). */
<>	144:ef7eb2e8f9f7	498	__HAL_RCC_LSI_ENABLE();
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	501	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/* Wait till LSI is ready */
<>	144:ef7eb2e8f9f7	504	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<>	144:ef7eb2e8f9f7	505	{
<>	144:ef7eb2e8f9f7	506	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	507	{
<>	144:ef7eb2e8f9f7	508	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	509	}
<>	144:ef7eb2e8f9f7	510	}
<>	144:ef7eb2e8f9f7	511	/* To have a fully stabilized clock in the specified range, a software delay of 1ms
<>	144:ef7eb2e8f9f7	512	should be added.*/
AnnaBridge	165:e614a9f1c9e2	513	RCC_Delay(1);
<>	144:ef7eb2e8f9f7	514	}
<>	144:ef7eb2e8f9f7	515	else
<>	144:ef7eb2e8f9f7	516	{
<>	144:ef7eb2e8f9f7	517	/* Disable the Internal Low Speed oscillator (LSI). */
<>	144:ef7eb2e8f9f7	518	__HAL_RCC_LSI_DISABLE();
<>	144:ef7eb2e8f9f7	519
<>	144:ef7eb2e8f9f7	520	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	521	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/* Wait till LSI is disabled */
<>	144:ef7eb2e8f9f7	524	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<>	144:ef7eb2e8f9f7	525	{
<>	144:ef7eb2e8f9f7	526	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	527	{
<>	144:ef7eb2e8f9f7	528	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	529	}
<>	144:ef7eb2e8f9f7	530	}
<>	144:ef7eb2e8f9f7	531	}
<>	144:ef7eb2e8f9f7	532	}
<>	144:ef7eb2e8f9f7	533	/------------------------------ LSE Configuration -------------------------/
<>	144:ef7eb2e8f9f7	534	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<>	144:ef7eb2e8f9f7	535	{
AnnaBridge	165:e614a9f1c9e2	536	FlagStatus pwrclkchanged = RESET;
AnnaBridge	165:e614a9f1c9e2	537
<>	144:ef7eb2e8f9f7	538	/* Check the parameters */
<>	144:ef7eb2e8f9f7	539	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<>	144:ef7eb2e8f9f7	540
AnnaBridge	165:e614a9f1c9e2	541	/* Update LSE configuration in Backup Domain control register */
AnnaBridge	165:e614a9f1c9e2	542	/* Requires to enable write access to Backup Domain of necessary */
AnnaBridge	165:e614a9f1c9e2	543	if(__HAL_RCC_PWR_IS_CLK_DISABLED())
AnnaBridge	165:e614a9f1c9e2	544	{
<>	144:ef7eb2e8f9f7	545	__HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge	165:e614a9f1c9e2	546	pwrclkchanged = SET;
AnnaBridge	165:e614a9f1c9e2	547	}
<>	144:ef7eb2e8f9f7	548
AnnaBridge	165:e614a9f1c9e2	549	if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
AnnaBridge	165:e614a9f1c9e2	550	{
<>	144:ef7eb2e8f9f7	551	/* Enable write access to Backup domain */
<>	144:ef7eb2e8f9f7	552	SET_BIT(PWR->CR, PWR_CR_DBP);
<>	144:ef7eb2e8f9f7	553
<>	144:ef7eb2e8f9f7	554	/* Wait for Backup domain Write protection disable */
<>	144:ef7eb2e8f9f7	555	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	556
AnnaBridge	165:e614a9f1c9e2	557	while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<>	144:ef7eb2e8f9f7	558	{
<>	144:ef7eb2e8f9f7	559	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	560	{
<>	144:ef7eb2e8f9f7	561	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	562	}
<>	144:ef7eb2e8f9f7	563	}
AnnaBridge	165:e614a9f1c9e2	564	}
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	/* Set the new LSE configuration -----------------------------------------*/
<>	144:ef7eb2e8f9f7	567	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<>	144:ef7eb2e8f9f7	568	/* Check the LSE State */
<>	144:ef7eb2e8f9f7	569	if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
<>	144:ef7eb2e8f9f7	570	{
<>	144:ef7eb2e8f9f7	571	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	572	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/* Wait till LSE is ready */
<>	144:ef7eb2e8f9f7	575	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<>	144:ef7eb2e8f9f7	576	{
<>	144:ef7eb2e8f9f7	577	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	578	{
<>	144:ef7eb2e8f9f7	579	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	580	}
<>	144:ef7eb2e8f9f7	581	}
<>	144:ef7eb2e8f9f7	582	}
<>	144:ef7eb2e8f9f7	583	else
<>	144:ef7eb2e8f9f7	584	{
<>	144:ef7eb2e8f9f7	585	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	586	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	587
<>	144:ef7eb2e8f9f7	588	/* Wait till LSE is disabled */
<>	144:ef7eb2e8f9f7	589	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<>	144:ef7eb2e8f9f7	590	{
<>	144:ef7eb2e8f9f7	591	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	592	{
<>	144:ef7eb2e8f9f7	593	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	594	}
<>	144:ef7eb2e8f9f7	595	}
<>	144:ef7eb2e8f9f7	596	}
AnnaBridge	165:e614a9f1c9e2	597
AnnaBridge	165:e614a9f1c9e2	598	/* Require to disable power clock if necessary */
AnnaBridge	165:e614a9f1c9e2	599	if(pwrclkchanged == SET)
AnnaBridge	165:e614a9f1c9e2	600	{
AnnaBridge	165:e614a9f1c9e2	601	__HAL_RCC_PWR_CLK_DISABLE();
AnnaBridge	165:e614a9f1c9e2	602	}
<>	144:ef7eb2e8f9f7	603	}
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	#if defined(RCC_CR_PLL2ON)
<>	144:ef7eb2e8f9f7	606	/-------------------------------- PLL2 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	607	/* Check the parameters */
<>	144:ef7eb2e8f9f7	608	assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
<>	144:ef7eb2e8f9f7	609	if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
<>	144:ef7eb2e8f9f7	610	{
<>	144:ef7eb2e8f9f7	611	/* This bit can not be cleared if the PLL2 clock is used indirectly as system
<>	144:ef7eb2e8f9f7	612	clock (i.e. it is used as PLL clock entry that is used as system clock). */
<>	144:ef7eb2e8f9f7	613	if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
<>	144:ef7eb2e8f9f7	614	(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
<>	144:ef7eb2e8f9f7	615	((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
<>	144:ef7eb2e8f9f7	616	{
<>	144:ef7eb2e8f9f7	617	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	618	}
<>	144:ef7eb2e8f9f7	619	else
<>	144:ef7eb2e8f9f7	620	{
<>	144:ef7eb2e8f9f7	621	if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
<>	144:ef7eb2e8f9f7	622	{
<>	144:ef7eb2e8f9f7	623	/* Check the parameters */
<>	144:ef7eb2e8f9f7	624	assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
<>	144:ef7eb2e8f9f7	625	assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
<>	144:ef7eb2e8f9f7	626
<>	144:ef7eb2e8f9f7	627	/* Prediv2 can be written only when the PLLI2S is disabled. */
<>	144:ef7eb2e8f9f7	628	/* Return an error only if new value is different from the programmed value */
<>	144:ef7eb2e8f9f7	629	if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
<>	144:ef7eb2e8f9f7	630	(__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
<>	144:ef7eb2e8f9f7	631	{
<>	144:ef7eb2e8f9f7	632	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	633	}
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	/* Disable the main PLL2. */
<>	144:ef7eb2e8f9f7	636	__HAL_RCC_PLL2_DISABLE();
<>	144:ef7eb2e8f9f7	637
<>	144:ef7eb2e8f9f7	638	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	639	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	640
<>	144:ef7eb2e8f9f7	641	/* Wait till PLL2 is disabled */
<>	144:ef7eb2e8f9f7	642	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<>	144:ef7eb2e8f9f7	643	{
<>	144:ef7eb2e8f9f7	644	if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	645	{
<>	144:ef7eb2e8f9f7	646	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	647	}
<>	144:ef7eb2e8f9f7	648	}
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	/* Configure the HSE prediv2 factor --------------------------------*/
<>	144:ef7eb2e8f9f7	651	__HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/* Configure the main PLL2 multiplication factors. */
<>	144:ef7eb2e8f9f7	654	__HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/* Enable the main PLL2. */
<>	144:ef7eb2e8f9f7	657	__HAL_RCC_PLL2_ENABLE();
<>	144:ef7eb2e8f9f7	658
<>	144:ef7eb2e8f9f7	659	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	660	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	/* Wait till PLL2 is ready */
<>	144:ef7eb2e8f9f7	663	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
<>	144:ef7eb2e8f9f7	664	{
<>	144:ef7eb2e8f9f7	665	if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	666	{
<>	144:ef7eb2e8f9f7	667	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	668	}
<>	144:ef7eb2e8f9f7	669	}
<>	144:ef7eb2e8f9f7	670	}
<>	144:ef7eb2e8f9f7	671	else
<>	144:ef7eb2e8f9f7	672	{
<>	144:ef7eb2e8f9f7	673	/* Set PREDIV1 source to HSE */
<>	144:ef7eb2e8f9f7	674	CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	/* Disable the main PLL2. */
<>	144:ef7eb2e8f9f7	677	__HAL_RCC_PLL2_DISABLE();
<>	144:ef7eb2e8f9f7	678
<>	144:ef7eb2e8f9f7	679	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	680	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	/* Wait till PLL2 is disabled */
<>	144:ef7eb2e8f9f7	683	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<>	144:ef7eb2e8f9f7	684	{
<>	144:ef7eb2e8f9f7	685	if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	686	{
<>	144:ef7eb2e8f9f7	687	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	688	}
<>	144:ef7eb2e8f9f7	689	}
<>	144:ef7eb2e8f9f7	690	}
<>	144:ef7eb2e8f9f7	691	}
<>	144:ef7eb2e8f9f7	692	}
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	#endif /* RCC_CR_PLL2ON */
<>	144:ef7eb2e8f9f7	695	/-------------------------------- PLL Configuration -----------------------/
<>	144:ef7eb2e8f9f7	696	/* Check the parameters */
<>	144:ef7eb2e8f9f7	697	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<>	144:ef7eb2e8f9f7	698	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<>	144:ef7eb2e8f9f7	699	{
<>	144:ef7eb2e8f9f7	700	/* Check if the PLL is used as system clock or not */
<>	144:ef7eb2e8f9f7	701	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<>	144:ef7eb2e8f9f7	702	{
<>	144:ef7eb2e8f9f7	703	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<>	144:ef7eb2e8f9f7	704	{
<>	144:ef7eb2e8f9f7	705	/* Check the parameters */
<>	144:ef7eb2e8f9f7	706	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<>	144:ef7eb2e8f9f7	707	assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
<>	144:ef7eb2e8f9f7	708
<>	144:ef7eb2e8f9f7	709	/* Disable the main PLL. */
<>	144:ef7eb2e8f9f7	710	__HAL_RCC_PLL_DISABLE();
<>	144:ef7eb2e8f9f7	711
<>	144:ef7eb2e8f9f7	712	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	713	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	714
<>	144:ef7eb2e8f9f7	715	/* Wait till PLL is disabled */
<>	144:ef7eb2e8f9f7	716	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<>	144:ef7eb2e8f9f7	717	{
<>	144:ef7eb2e8f9f7	718	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	719	{
<>	144:ef7eb2e8f9f7	720	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	721	}
<>	144:ef7eb2e8f9f7	722	}
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/* Configure the HSE prediv factor --------------------------------*/
<>	144:ef7eb2e8f9f7	725	/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
<>	144:ef7eb2e8f9f7	726	if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
<>	144:ef7eb2e8f9f7	727	{
<>	144:ef7eb2e8f9f7	728	/* Check the parameter */
<>	144:ef7eb2e8f9f7	729	assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
<>	144:ef7eb2e8f9f7	730	#if defined(RCC_CFGR2_PREDIV1SRC)
<>	144:ef7eb2e8f9f7	731	assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
<>	144:ef7eb2e8f9f7	732
<>	144:ef7eb2e8f9f7	733	/* Set PREDIV1 source */
<>	144:ef7eb2e8f9f7	734	SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
<>	144:ef7eb2e8f9f7	735	#endif /* RCC_CFGR2_PREDIV1SRC */
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/* Set PREDIV1 Value */
<>	144:ef7eb2e8f9f7	738	__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
<>	144:ef7eb2e8f9f7	739	}
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/* Configure the main PLL clock source and multiplication factors. */
<>	144:ef7eb2e8f9f7	742	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<>	144:ef7eb2e8f9f7	743	RCC_OscInitStruct->PLL.PLLMUL);
<>	144:ef7eb2e8f9f7	744	/* Enable the main PLL. */
<>	144:ef7eb2e8f9f7	745	__HAL_RCC_PLL_ENABLE();
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	748	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/* Wait till PLL is ready */
<>	144:ef7eb2e8f9f7	751	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<>	144:ef7eb2e8f9f7	752	{
<>	144:ef7eb2e8f9f7	753	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	754	{
<>	144:ef7eb2e8f9f7	755	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	756	}
<>	144:ef7eb2e8f9f7	757	}
<>	144:ef7eb2e8f9f7	758	}
<>	144:ef7eb2e8f9f7	759	else
<>	144:ef7eb2e8f9f7	760	{
<>	144:ef7eb2e8f9f7	761	/* Disable the main PLL. */
<>	144:ef7eb2e8f9f7	762	__HAL_RCC_PLL_DISABLE();
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	765	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/* Wait till PLL is disabled */
<>	144:ef7eb2e8f9f7	768	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<>	144:ef7eb2e8f9f7	769	{
<>	144:ef7eb2e8f9f7	770	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	771	{
<>	144:ef7eb2e8f9f7	772	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	773	}
<>	144:ef7eb2e8f9f7	774	}
<>	144:ef7eb2e8f9f7	775	}
<>	144:ef7eb2e8f9f7	776	}
<>	144:ef7eb2e8f9f7	777	else
<>	144:ef7eb2e8f9f7	778	{
<>	144:ef7eb2e8f9f7	779	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	780	}
<>	144:ef7eb2e8f9f7	781	}
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	return HAL_OK;
<>	144:ef7eb2e8f9f7	784	}
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	/**
<>	144:ef7eb2e8f9f7	787	* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
<>	144:ef7eb2e8f9f7	788	* parameters in the RCC_ClkInitStruct.
<>	144:ef7eb2e8f9f7	789	* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
<>	144:ef7eb2e8f9f7	790	* contains the configuration information for the RCC peripheral.
<>	144:ef7eb2e8f9f7	791	* @param FLatency FLASH Latency
<>	144:ef7eb2e8f9f7	792	* The value of this parameter depend on device used within the same series
<>	144:ef7eb2e8f9f7	793	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<>	144:ef7eb2e8f9f7	794	* and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
<>	144:ef7eb2e8f9f7	795	*
<>	144:ef7eb2e8f9f7	796	* @note The HSI is used (enabled by hardware) as system clock source after
<>	144:ef7eb2e8f9f7	797	* start-up from Reset, wake-up from STOP and STANDBY mode, or in case
<>	144:ef7eb2e8f9f7	798	* of failure of the HSE used directly or indirectly as system clock
<>	144:ef7eb2e8f9f7	799	* (if the Clock Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	800	*
<>	144:ef7eb2e8f9f7	801	* @note A switch from one clock source to another occurs only if the target
<>	144:ef7eb2e8f9f7	802	* clock source is ready (clock stable after start-up delay or PLL locked).
<>	144:ef7eb2e8f9f7	803	* If a clock source which is not yet ready is selected, the switch will
<>	144:ef7eb2e8f9f7	804	* occur when the clock source will be ready.
<>	144:ef7eb2e8f9f7	805	* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
<>	144:ef7eb2e8f9f7	806	* currently used as system clock source.
<>	144:ef7eb2e8f9f7	807	* @retval HAL status
<>	144:ef7eb2e8f9f7	808	*/
<>	144:ef7eb2e8f9f7	809	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<>	144:ef7eb2e8f9f7	810	{
AnnaBridge	165:e614a9f1c9e2	811	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	812
<>	144:ef7eb2e8f9f7	813	/* Check the parameters */
<>	144:ef7eb2e8f9f7	814	assert_param(RCC_ClkInitStruct != NULL);
<>	144:ef7eb2e8f9f7	815	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<>	144:ef7eb2e8f9f7	816	assert_param(IS_FLASH_LATENCY(FLatency));
<>	144:ef7eb2e8f9f7	817
<>	144:ef7eb2e8f9f7	818	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
<>	144:ef7eb2e8f9f7	819	must be correctly programmed according to the frequency of the CPU clock
<>	144:ef7eb2e8f9f7	820	(HCLK) of the device. */
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	#if defined(FLASH_ACR_LATENCY)
<>	144:ef7eb2e8f9f7	823	/* Increasing the number of wait states because of higher CPU frequency */
<>	144:ef7eb2e8f9f7	824	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<>	144:ef7eb2e8f9f7	825	{
<>	144:ef7eb2e8f9f7	826	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<>	144:ef7eb2e8f9f7	827	__HAL_FLASH_SET_LATENCY(FLatency);
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/* Check that the new number of wait states is taken into account to access the Flash
<>	144:ef7eb2e8f9f7	830	memory by reading the FLASH_ACR register */
<>	144:ef7eb2e8f9f7	831	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<>	144:ef7eb2e8f9f7	832	{
<>	144:ef7eb2e8f9f7	833	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	834	}
<>	144:ef7eb2e8f9f7	835	}
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	#endif /* FLASH_ACR_LATENCY */
<>	144:ef7eb2e8f9f7	838	/-------------------------- HCLK Configuration --------------------------/
<>	144:ef7eb2e8f9f7	839	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<>	144:ef7eb2e8f9f7	840	{
<>	144:ef7eb2e8f9f7	841	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<>	144:ef7eb2e8f9f7	842	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<>	144:ef7eb2e8f9f7	843	}
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/------------------------- SYSCLK Configuration ---------------------------/
<>	144:ef7eb2e8f9f7	846	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<>	144:ef7eb2e8f9f7	847	{
<>	144:ef7eb2e8f9f7	848	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
<>	144:ef7eb2e8f9f7	849
<>	144:ef7eb2e8f9f7	850	/* HSE is selected as System Clock Source */
<>	144:ef7eb2e8f9f7	851	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<>	144:ef7eb2e8f9f7	852	{
<>	144:ef7eb2e8f9f7	853	/* Check the HSE ready flag */
<>	144:ef7eb2e8f9f7	854	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<>	144:ef7eb2e8f9f7	855	{
<>	144:ef7eb2e8f9f7	856	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	857	}
<>	144:ef7eb2e8f9f7	858	}
<>	144:ef7eb2e8f9f7	859	/* PLL is selected as System Clock Source */
<>	144:ef7eb2e8f9f7	860	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<>	144:ef7eb2e8f9f7	861	{
<>	144:ef7eb2e8f9f7	862	/* Check the PLL ready flag */
<>	144:ef7eb2e8f9f7	863	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<>	144:ef7eb2e8f9f7	864	{
<>	144:ef7eb2e8f9f7	865	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	866	}
<>	144:ef7eb2e8f9f7	867	}
<>	144:ef7eb2e8f9f7	868	/* HSI is selected as System Clock Source */
<>	144:ef7eb2e8f9f7	869	else
<>	144:ef7eb2e8f9f7	870	{
<>	144:ef7eb2e8f9f7	871	/* Check the HSI ready flag */
<>	144:ef7eb2e8f9f7	872	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<>	144:ef7eb2e8f9f7	873	{
<>	144:ef7eb2e8f9f7	874	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	875	}
<>	144:ef7eb2e8f9f7	876	}
<>	144:ef7eb2e8f9f7	877	__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
<>	144:ef7eb2e8f9f7	878
<>	144:ef7eb2e8f9f7	879	/* Get Start Tick */
<>	144:ef7eb2e8f9f7	880	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<>	144:ef7eb2e8f9f7	883	{
<>	144:ef7eb2e8f9f7	884	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<>	144:ef7eb2e8f9f7	885	{
<>	144:ef7eb2e8f9f7	886	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	887	{
<>	144:ef7eb2e8f9f7	888	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	889	}
<>	144:ef7eb2e8f9f7	890	}
<>	144:ef7eb2e8f9f7	891	}
<>	144:ef7eb2e8f9f7	892	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<>	144:ef7eb2e8f9f7	893	{
<>	144:ef7eb2e8f9f7	894	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<>	144:ef7eb2e8f9f7	895	{
<>	144:ef7eb2e8f9f7	896	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	897	{
<>	144:ef7eb2e8f9f7	898	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	899	}
<>	144:ef7eb2e8f9f7	900	}
<>	144:ef7eb2e8f9f7	901	}
<>	144:ef7eb2e8f9f7	902	else
<>	144:ef7eb2e8f9f7	903	{
<>	144:ef7eb2e8f9f7	904	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
<>	144:ef7eb2e8f9f7	905	{
<>	144:ef7eb2e8f9f7	906	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	907	{
<>	144:ef7eb2e8f9f7	908	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	909	}
<>	144:ef7eb2e8f9f7	910	}
<>	144:ef7eb2e8f9f7	911	}
<>	144:ef7eb2e8f9f7	912	}
<>	144:ef7eb2e8f9f7	913	#if defined(FLASH_ACR_LATENCY)
<>	144:ef7eb2e8f9f7	914	/* Decreasing the number of wait states because of lower CPU frequency */
<>	144:ef7eb2e8f9f7	915	if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
<>	144:ef7eb2e8f9f7	916	{
<>	144:ef7eb2e8f9f7	917	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<>	144:ef7eb2e8f9f7	918	__HAL_FLASH_SET_LATENCY(FLatency);
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	/* Check that the new number of wait states is taken into account to access the Flash
<>	144:ef7eb2e8f9f7	921	memory by reading the FLASH_ACR register */
<>	144:ef7eb2e8f9f7	922	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<>	144:ef7eb2e8f9f7	923	{
<>	144:ef7eb2e8f9f7	924	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	925	}
<>	144:ef7eb2e8f9f7	926	}
<>	144:ef7eb2e8f9f7	927	#endif /* FLASH_ACR_LATENCY */
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	/-------------------------- PCLK1 Configuration ---------------------------/
<>	144:ef7eb2e8f9f7	930	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<>	144:ef7eb2e8f9f7	931	{
<>	144:ef7eb2e8f9f7	932	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<>	144:ef7eb2e8f9f7	933	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
<>	144:ef7eb2e8f9f7	934	}
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	/-------------------------- PCLK2 Configuration ---------------------------/
<>	144:ef7eb2e8f9f7	937	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
<>	144:ef7eb2e8f9f7	938	{
<>	144:ef7eb2e8f9f7	939	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
<>	144:ef7eb2e8f9f7	940	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
<>	144:ef7eb2e8f9f7	941	}
<>	144:ef7eb2e8f9f7	942
<>	144:ef7eb2e8f9f7	943	/* Update the SystemCoreClock global variable */
AnnaBridge	165:e614a9f1c9e2	944	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
<>	144:ef7eb2e8f9f7	945
<>	144:ef7eb2e8f9f7	946	/* Configure the source of time base considering new system clocks settings*/
<>	144:ef7eb2e8f9f7	947	HAL_InitTick (TICK_INT_PRIORITY);
<>	144:ef7eb2e8f9f7	948
<>	144:ef7eb2e8f9f7	949	return HAL_OK;
<>	144:ef7eb2e8f9f7	950	}
<>	144:ef7eb2e8f9f7	951
<>	144:ef7eb2e8f9f7	952	/**
<>	144:ef7eb2e8f9f7	953	* @}
<>	144:ef7eb2e8f9f7	954	*/
<>	144:ef7eb2e8f9f7	955
<>	144:ef7eb2e8f9f7	956	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<>	144:ef7eb2e8f9f7	957	* @brief RCC clocks control functions
<>	144:ef7eb2e8f9f7	958	*
<>	144:ef7eb2e8f9f7	959	@verbatim
<>	144:ef7eb2e8f9f7	960	===============================================================================
<>	144:ef7eb2e8f9f7	961	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	962	===============================================================================
<>	144:ef7eb2e8f9f7	963	[..]
<>	144:ef7eb2e8f9f7	964	This subsection provides a set of functions allowing to control the RCC Clocks
<>	144:ef7eb2e8f9f7	965	frequencies.
<>	144:ef7eb2e8f9f7	966
<>	144:ef7eb2e8f9f7	967	@endverbatim
<>	144:ef7eb2e8f9f7	968	* @{
<>	144:ef7eb2e8f9f7	969	*/
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971	/**
<>	144:ef7eb2e8f9f7	972	* @brief Selects the clock source to output on MCO pin.
<>	144:ef7eb2e8f9f7	973	* @note MCO pin should be configured in alternate function mode.
<>	144:ef7eb2e8f9f7	974	* @param RCC_MCOx specifies the output direction for the clock source.
<>	144:ef7eb2e8f9f7	975	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	976	* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
<>	144:ef7eb2e8f9f7	977	* @param RCC_MCOSource specifies the clock source to output.
<>	144:ef7eb2e8f9f7	978	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	979	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<>	144:ef7eb2e8f9f7	980	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
<>	144:ef7eb2e8f9f7	981	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<>	144:ef7eb2e8f9f7	982	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<>	144:ef7eb2e8f9f7	983	@if STM32F105xC
<>	144:ef7eb2e8f9f7	984	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
<>	144:ef7eb2e8f9f7	985	* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
<>	144:ef7eb2e8f9f7	986	* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
<>	144:ef7eb2e8f9f7	987	* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
<>	144:ef7eb2e8f9f7	988	* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
<>	144:ef7eb2e8f9f7	989	@endif
<>	144:ef7eb2e8f9f7	990	@if STM32F107xC
<>	144:ef7eb2e8f9f7	991	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
<>	144:ef7eb2e8f9f7	992	* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
<>	144:ef7eb2e8f9f7	993	* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
<>	144:ef7eb2e8f9f7	994	* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
<>	144:ef7eb2e8f9f7	995	* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
<>	144:ef7eb2e8f9f7	996	@endif
<>	144:ef7eb2e8f9f7	997	* @param RCC_MCODiv specifies the MCO DIV.
<>	144:ef7eb2e8f9f7	998	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	999	* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
<>	144:ef7eb2e8f9f7	1000	* @retval None
<>	144:ef7eb2e8f9f7	1001	*/
<>	144:ef7eb2e8f9f7	1002	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<>	144:ef7eb2e8f9f7	1003	{
AnnaBridge	165:e614a9f1c9e2	1004	GPIO_InitTypeDef gpio = {0U};
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1007	assert_param(IS_RCC_MCO(RCC_MCOx));
<>	144:ef7eb2e8f9f7	1008	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<>	144:ef7eb2e8f9f7	1009	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
AnnaBridge	165:e614a9f1c9e2	1010
AnnaBridge	165:e614a9f1c9e2	1011	/* Prevent unused argument(s) compilation warning */
AnnaBridge	165:e614a9f1c9e2	1012	UNUSED(RCC_MCOx);
AnnaBridge	165:e614a9f1c9e2	1013	UNUSED(RCC_MCODiv);
AnnaBridge	165:e614a9f1c9e2	1014
<>	144:ef7eb2e8f9f7	1015	/* Configure the MCO1 pin in alternate function mode */
<>	144:ef7eb2e8f9f7	1016	gpio.Mode = GPIO_MODE_AF_PP;
<>	144:ef7eb2e8f9f7	1017	gpio.Speed = GPIO_SPEED_FREQ_HIGH;
<>	144:ef7eb2e8f9f7	1018	gpio.Pull = GPIO_NOPULL;
<>	144:ef7eb2e8f9f7	1019	gpio.Pin = MCO1_PIN;
<>	144:ef7eb2e8f9f7	1020
<>	144:ef7eb2e8f9f7	1021	/* MCO1 Clock Enable */
<>	144:ef7eb2e8f9f7	1022	MCO1_CLK_ENABLE();
AnnaBridge	165:e614a9f1c9e2	1023
<>	144:ef7eb2e8f9f7	1024	HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
AnnaBridge	165:e614a9f1c9e2	1025
<>	144:ef7eb2e8f9f7	1026	/* Configure the MCO clock source */
<>	144:ef7eb2e8f9f7	1027	__HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
<>	144:ef7eb2e8f9f7	1028	}
<>	144:ef7eb2e8f9f7	1029
<>	144:ef7eb2e8f9f7	1030	/**
<>	144:ef7eb2e8f9f7	1031	* @brief Enables the Clock Security System.
<>	144:ef7eb2e8f9f7	1032	* @note If a failure is detected on the HSE oscillator clock, this oscillator
<>	144:ef7eb2e8f9f7	1033	* is automatically disabled and an interrupt is generated to inform the
<>	144:ef7eb2e8f9f7	1034	* software about the failure (Clock Security System Interrupt, CSSI),
<>	144:ef7eb2e8f9f7	1035	* allowing the MCU to perform rescue operations. The CSSI is linked to
<>	144:ef7eb2e8f9f7	1036	* the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
<>	144:ef7eb2e8f9f7	1037	* @retval None
<>	144:ef7eb2e8f9f7	1038	*/
<>	144:ef7eb2e8f9f7	1039	void HAL_RCC_EnableCSS(void)
<>	144:ef7eb2e8f9f7	1040	{
<>	144:ef7eb2e8f9f7	1041	(__IO uint32_t ) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
<>	144:ef7eb2e8f9f7	1042	}
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	/**
<>	144:ef7eb2e8f9f7	1045	* @brief Disables the Clock Security System.
<>	144:ef7eb2e8f9f7	1046	* @retval None
<>	144:ef7eb2e8f9f7	1047	*/
<>	144:ef7eb2e8f9f7	1048	void HAL_RCC_DisableCSS(void)
<>	144:ef7eb2e8f9f7	1049	{
<>	144:ef7eb2e8f9f7	1050	(__IO uint32_t ) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
<>	144:ef7eb2e8f9f7	1051	}
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	/**
<>	144:ef7eb2e8f9f7	1054	* @brief Returns the SYSCLK frequency
<>	144:ef7eb2e8f9f7	1055	* @note The system frequency computed by this function is not the real
<>	144:ef7eb2e8f9f7	1056	* frequency in the chip. It is calculated based on the predefined
<>	144:ef7eb2e8f9f7	1057	* constant and the selected clock source:
<>	144:ef7eb2e8f9f7	1058	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
<>	144:ef7eb2e8f9f7	1059	* @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
<>	144:ef7eb2e8f9f7	1060	* divided by PREDIV factor(**)
<>	144:ef7eb2e8f9f7	1061	* @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
<>	144:ef7eb2e8f9f7	1062	* divided by PREDIV factor(*) or HSI_VALUE() multiplied by the PLL factor.
<>	144:ef7eb2e8f9f7	1063	* @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
<>	144:ef7eb2e8f9f7	1064	* 8 MHz) but the real value may vary depending on the variations
<>	144:ef7eb2e8f9f7	1065	* in voltage and temperature.
<>	144:ef7eb2e8f9f7	1066	* @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
<>	144:ef7eb2e8f9f7	1067	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
<>	144:ef7eb2e8f9f7	1068	* frequency of the crystal used. Otherwise, this function may
<>	144:ef7eb2e8f9f7	1069	* have wrong result.
<>	144:ef7eb2e8f9f7	1070	*
<>	144:ef7eb2e8f9f7	1071	* @note The result of this function could be not correct when using fractional
<>	144:ef7eb2e8f9f7	1072	* value for HSE crystal.
<>	144:ef7eb2e8f9f7	1073	*
<>	144:ef7eb2e8f9f7	1074	* @note This function can be used by the user application to compute the
<>	144:ef7eb2e8f9f7	1075	* baud-rate for the communication peripherals or configure other parameters.
<>	144:ef7eb2e8f9f7	1076	*
<>	144:ef7eb2e8f9f7	1077	* @note Each time SYSCLK changes, this function must be called to update the
<>	144:ef7eb2e8f9f7	1078	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<>	144:ef7eb2e8f9f7	1079	*
<>	144:ef7eb2e8f9f7	1080	* @retval SYSCLK frequency
<>	144:ef7eb2e8f9f7	1081	*/
<>	144:ef7eb2e8f9f7	1082	uint32_t HAL_RCC_GetSysClockFreq(void)
<>	144:ef7eb2e8f9f7	1083	{
AnnaBridge	165:e614a9f1c9e2	1084	#if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge	165:e614a9f1c9e2	1085	const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
AnnaBridge	165:e614a9f1c9e2	1086	const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
<>	144:ef7eb2e8f9f7	1087	#else
AnnaBridge	165:e614a9f1c9e2	1088	const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
<>	144:ef7eb2e8f9f7	1089	#if defined(RCC_CFGR2_PREDIV1)
AnnaBridge	165:e614a9f1c9e2	1090	const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
<>	144:ef7eb2e8f9f7	1091	#else
AnnaBridge	165:e614a9f1c9e2	1092	const uint8_t aPredivFactorTable[2] = {1, 2};
<>	144:ef7eb2e8f9f7	1093	#endif /RCC_CFGR2_PREDIV1/
<>	144:ef7eb2e8f9f7	1094
<>	144:ef7eb2e8f9f7	1095	#endif
AnnaBridge	165:e614a9f1c9e2	1096	uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
AnnaBridge	165:e614a9f1c9e2	1097	uint32_t sysclockfreq = 0U;
<>	144:ef7eb2e8f9f7	1098	#if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge	165:e614a9f1c9e2	1099	uint32_t prediv2 = 0U, pll2mul = 0U;
<>	144:ef7eb2e8f9f7	1100	#endif /RCC_CFGR2_PREDIV1SRC/
AnnaBridge	187:0387e8f68319	1101
<>	144:ef7eb2e8f9f7	1102	tmpreg = RCC->CFGR;
AnnaBridge	187:0387e8f68319	1103
<>	144:ef7eb2e8f9f7	1104	/* Get SYSCLK source -------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1105	switch (tmpreg & RCC_CFGR_SWS)
<>	144:ef7eb2e8f9f7	1106	{
<>	144:ef7eb2e8f9f7	1107	case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
<>	144:ef7eb2e8f9f7	1108	{
<>	144:ef7eb2e8f9f7	1109	sysclockfreq = HSE_VALUE;
<>	144:ef7eb2e8f9f7	1110	break;
<>	144:ef7eb2e8f9f7	1111	}
<>	144:ef7eb2e8f9f7	1112	case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
<>	144:ef7eb2e8f9f7	1113	{
AnnaBridge	165:e614a9f1c9e2	1114	pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
<>	144:ef7eb2e8f9f7	1115	if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
<>	144:ef7eb2e8f9f7	1116	{
<>	144:ef7eb2e8f9f7	1117	#if defined(RCC_CFGR2_PREDIV1)
AnnaBridge	165:e614a9f1c9e2	1118	prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
<>	144:ef7eb2e8f9f7	1119	#else
AnnaBridge	165:e614a9f1c9e2	1120	prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
<>	144:ef7eb2e8f9f7	1121	#endif /RCC_CFGR2_PREDIV1/
<>	144:ef7eb2e8f9f7	1122	#if defined(RCC_CFGR2_PREDIV1SRC)
<>	144:ef7eb2e8f9f7	1123
<>	144:ef7eb2e8f9f7	1124	if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
<>	144:ef7eb2e8f9f7	1125	{
<>	144:ef7eb2e8f9f7	1126	/* PLL2 selected as Prediv1 source */
<>	144:ef7eb2e8f9f7	1127	/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
AnnaBridge	165:e614a9f1c9e2	1128	prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
AnnaBridge	165:e614a9f1c9e2	1129	pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
AnnaBridge	187:0387e8f68319	1130	pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
<>	144:ef7eb2e8f9f7	1131	}
<>	144:ef7eb2e8f9f7	1132	else
<>	144:ef7eb2e8f9f7	1133	{
<>	144:ef7eb2e8f9f7	1134	/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
AnnaBridge	187:0387e8f68319	1135	pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
<>	144:ef7eb2e8f9f7	1136	}
AnnaBridge	187:0387e8f68319	1137
<>	144:ef7eb2e8f9f7	1138	/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
<>	144:ef7eb2e8f9f7	1139	/* In this case need to divide pllclk by 2 */
AnnaBridge	165:e614a9f1c9e2	1140	if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
<>	144:ef7eb2e8f9f7	1141	{
<>	144:ef7eb2e8f9f7	1142	pllclk = pllclk / 2;
<>	144:ef7eb2e8f9f7	1143	}
<>	144:ef7eb2e8f9f7	1144	#else
<>	144:ef7eb2e8f9f7	1145	/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
AnnaBridge	187:0387e8f68319	1146	pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
<>	144:ef7eb2e8f9f7	1147	#endif /RCC_CFGR2_PREDIV1SRC/
<>	144:ef7eb2e8f9f7	1148	}
<>	144:ef7eb2e8f9f7	1149	else
<>	144:ef7eb2e8f9f7	1150	{
<>	144:ef7eb2e8f9f7	1151	/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<>	144:ef7eb2e8f9f7	1152	pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
<>	144:ef7eb2e8f9f7	1153	}
<>	144:ef7eb2e8f9f7	1154	sysclockfreq = pllclk;
<>	144:ef7eb2e8f9f7	1155	break;
<>	144:ef7eb2e8f9f7	1156	}
<>	144:ef7eb2e8f9f7	1157	case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<>	144:ef7eb2e8f9f7	1158	default: /* HSI used as system clock */
<>	144:ef7eb2e8f9f7	1159	{
<>	144:ef7eb2e8f9f7	1160	sysclockfreq = HSI_VALUE;
<>	144:ef7eb2e8f9f7	1161	break;
<>	144:ef7eb2e8f9f7	1162	}
<>	144:ef7eb2e8f9f7	1163	}
<>	144:ef7eb2e8f9f7	1164	return sysclockfreq;
<>	144:ef7eb2e8f9f7	1165	}
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	/**
<>	144:ef7eb2e8f9f7	1168	* @brief Returns the HCLK frequency
<>	144:ef7eb2e8f9f7	1169	* @note Each time HCLK changes, this function must be called to update the
<>	144:ef7eb2e8f9f7	1170	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
<>	144:ef7eb2e8f9f7	1171	*
<>	144:ef7eb2e8f9f7	1172	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<>	144:ef7eb2e8f9f7	1173	* and updated within this function
<>	144:ef7eb2e8f9f7	1174	* @retval HCLK frequency
<>	144:ef7eb2e8f9f7	1175	*/
<>	144:ef7eb2e8f9f7	1176	uint32_t HAL_RCC_GetHCLKFreq(void)
<>	144:ef7eb2e8f9f7	1177	{
<>	144:ef7eb2e8f9f7	1178	return SystemCoreClock;
<>	144:ef7eb2e8f9f7	1179	}
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/**
<>	144:ef7eb2e8f9f7	1182	* @brief Returns the PCLK1 frequency
<>	144:ef7eb2e8f9f7	1183	* @note Each time PCLK1 changes, this function must be called to update the
<>	144:ef7eb2e8f9f7	1184	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<>	144:ef7eb2e8f9f7	1185	* @retval PCLK1 frequency
<>	144:ef7eb2e8f9f7	1186	*/
<>	144:ef7eb2e8f9f7	1187	uint32_t HAL_RCC_GetPCLK1Freq(void)
<>	144:ef7eb2e8f9f7	1188	{
<>	144:ef7eb2e8f9f7	1189	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
AnnaBridge	165:e614a9f1c9e2	1190	return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
<>	144:ef7eb2e8f9f7	1191	}
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193	/**
<>	144:ef7eb2e8f9f7	1194	* @brief Returns the PCLK2 frequency
<>	144:ef7eb2e8f9f7	1195	* @note Each time PCLK2 changes, this function must be called to update the
<>	144:ef7eb2e8f9f7	1196	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
<>	144:ef7eb2e8f9f7	1197	* @retval PCLK2 frequency
<>	144:ef7eb2e8f9f7	1198	*/
<>	144:ef7eb2e8f9f7	1199	uint32_t HAL_RCC_GetPCLK2Freq(void)
<>	144:ef7eb2e8f9f7	1200	{
<>	144:ef7eb2e8f9f7	1201	/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
AnnaBridge	165:e614a9f1c9e2	1202	return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
<>	144:ef7eb2e8f9f7	1203	}
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/**
<>	144:ef7eb2e8f9f7	1206	* @brief Configures the RCC_OscInitStruct according to the internal
<>	144:ef7eb2e8f9f7	1207	* RCC configuration registers.
<>	144:ef7eb2e8f9f7	1208	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<>	144:ef7eb2e8f9f7	1209	* will be configured.
<>	144:ef7eb2e8f9f7	1210	* @retval None
<>	144:ef7eb2e8f9f7	1211	*/
<>	144:ef7eb2e8f9f7	1212	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<>	144:ef7eb2e8f9f7	1213	{
<>	144:ef7eb2e8f9f7	1214	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1215	assert_param(RCC_OscInitStruct != NULL);
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/* Set all possible values for the Oscillator type parameter ---------------*/
<>	144:ef7eb2e8f9f7	1218	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \
<>	144:ef7eb2e8f9f7	1219	\| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	#if defined(RCC_CFGR2_PREDIV1SRC)
<>	144:ef7eb2e8f9f7	1222	/* Get the Prediv1 source --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1223	RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
<>	144:ef7eb2e8f9f7	1224	#endif /* RCC_CFGR2_PREDIV1SRC */
<>	144:ef7eb2e8f9f7	1225
<>	144:ef7eb2e8f9f7	1226	/* Get the HSE configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1227	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<>	144:ef7eb2e8f9f7	1228	{
<>	144:ef7eb2e8f9f7	1229	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<>	144:ef7eb2e8f9f7	1230	}
<>	144:ef7eb2e8f9f7	1231	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<>	144:ef7eb2e8f9f7	1232	{
<>	144:ef7eb2e8f9f7	1233	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<>	144:ef7eb2e8f9f7	1234	}
<>	144:ef7eb2e8f9f7	1235	else
<>	144:ef7eb2e8f9f7	1236	{
<>	144:ef7eb2e8f9f7	1237	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<>	144:ef7eb2e8f9f7	1238	}
<>	144:ef7eb2e8f9f7	1239	RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
<>	144:ef7eb2e8f9f7	1240
<>	144:ef7eb2e8f9f7	1241	/* Get the HSI configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1242	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
<>	144:ef7eb2e8f9f7	1243	{
<>	144:ef7eb2e8f9f7	1244	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
<>	144:ef7eb2e8f9f7	1245	}
<>	144:ef7eb2e8f9f7	1246	else
<>	144:ef7eb2e8f9f7	1247	{
<>	144:ef7eb2e8f9f7	1248	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
<>	144:ef7eb2e8f9f7	1249	}
<>	144:ef7eb2e8f9f7	1250
AnnaBridge	165:e614a9f1c9e2	1251	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/* Get the LSE configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1254	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
<>	144:ef7eb2e8f9f7	1255	{
<>	144:ef7eb2e8f9f7	1256	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<>	144:ef7eb2e8f9f7	1257	}
<>	144:ef7eb2e8f9f7	1258	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
<>	144:ef7eb2e8f9f7	1259	{
<>	144:ef7eb2e8f9f7	1260	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<>	144:ef7eb2e8f9f7	1261	}
<>	144:ef7eb2e8f9f7	1262	else
<>	144:ef7eb2e8f9f7	1263	{
<>	144:ef7eb2e8f9f7	1264	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<>	144:ef7eb2e8f9f7	1265	}
<>	144:ef7eb2e8f9f7	1266
<>	144:ef7eb2e8f9f7	1267	/* Get the LSI configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1268	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<>	144:ef7eb2e8f9f7	1269	{
<>	144:ef7eb2e8f9f7	1270	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<>	144:ef7eb2e8f9f7	1271	}
<>	144:ef7eb2e8f9f7	1272	else
<>	144:ef7eb2e8f9f7	1273	{
<>	144:ef7eb2e8f9f7	1274	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<>	144:ef7eb2e8f9f7	1275	}
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	/* Get the PLL configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1279	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	1280	{
<>	144:ef7eb2e8f9f7	1281	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<>	144:ef7eb2e8f9f7	1282	}
<>	144:ef7eb2e8f9f7	1283	else
<>	144:ef7eb2e8f9f7	1284	{
<>	144:ef7eb2e8f9f7	1285	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<>	144:ef7eb2e8f9f7	1286	}
<>	144:ef7eb2e8f9f7	1287	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
<>	144:ef7eb2e8f9f7	1288	RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
<>	144:ef7eb2e8f9f7	1289	#if defined(RCC_CR_PLL2ON)
<>	144:ef7eb2e8f9f7	1290	/* Get the PLL2 configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1291	if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
<>	144:ef7eb2e8f9f7	1292	{
<>	144:ef7eb2e8f9f7	1293	RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
<>	144:ef7eb2e8f9f7	1294	}
<>	144:ef7eb2e8f9f7	1295	else
<>	144:ef7eb2e8f9f7	1296	{
<>	144:ef7eb2e8f9f7	1297	RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
<>	144:ef7eb2e8f9f7	1298	}
<>	144:ef7eb2e8f9f7	1299	RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
<>	144:ef7eb2e8f9f7	1300	RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
<>	144:ef7eb2e8f9f7	1301	#endif /* RCC_CR_PLL2ON */
<>	144:ef7eb2e8f9f7	1302	}
<>	144:ef7eb2e8f9f7	1303
<>	144:ef7eb2e8f9f7	1304	/**
<>	144:ef7eb2e8f9f7	1305	* @brief Get the RCC_ClkInitStruct according to the internal
<>	144:ef7eb2e8f9f7	1306	* RCC configuration registers.
<>	144:ef7eb2e8f9f7	1307	* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
<>	144:ef7eb2e8f9f7	1308	* contains the current clock configuration.
<>	144:ef7eb2e8f9f7	1309	* @param pFLatency Pointer on the Flash Latency.
<>	144:ef7eb2e8f9f7	1310	* @retval None
<>	144:ef7eb2e8f9f7	1311	*/
<>	144:ef7eb2e8f9f7	1312	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
<>	144:ef7eb2e8f9f7	1313	{
<>	144:ef7eb2e8f9f7	1314	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1315	assert_param(RCC_ClkInitStruct != NULL);
<>	144:ef7eb2e8f9f7	1316	assert_param(pFLatency != NULL);
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	/* Set all possible values for the Clock type parameter --------------------*/
<>	144:ef7eb2e8f9f7	1319	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	/* Get the SYSCLK configuration --------------------------------------------*/
<>	144:ef7eb2e8f9f7	1322	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/* Get the HCLK configuration ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1325	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	/* Get the APB1 configuration ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1328	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
<>	144:ef7eb2e8f9f7	1329
<>	144:ef7eb2e8f9f7	1330	/* Get the APB2 configuration ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1331	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	#if defined(FLASH_ACR_LATENCY)
<>	144:ef7eb2e8f9f7	1334	/* Get the Flash Wait State (Latency) configuration ------------------------*/
<>	144:ef7eb2e8f9f7	1335	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<>	144:ef7eb2e8f9f7	1336	#else
<>	144:ef7eb2e8f9f7	1337	/* For VALUE lines devices, only LATENCY_0 can be set*/
<>	144:ef7eb2e8f9f7	1338	*pFLatency = (uint32_t)FLASH_LATENCY_0;
<>	144:ef7eb2e8f9f7	1339	#endif
<>	144:ef7eb2e8f9f7	1340	}
<>	144:ef7eb2e8f9f7	1341
<>	144:ef7eb2e8f9f7	1342	/**
<>	144:ef7eb2e8f9f7	1343	* @brief This function handles the RCC CSS interrupt request.
<>	144:ef7eb2e8f9f7	1344	* @note This API should be called under the NMI_Handler().
<>	144:ef7eb2e8f9f7	1345	* @retval None
<>	144:ef7eb2e8f9f7	1346	*/
<>	144:ef7eb2e8f9f7	1347	void HAL_RCC_NMI_IRQHandler(void)
<>	144:ef7eb2e8f9f7	1348	{
<>	144:ef7eb2e8f9f7	1349	/* Check RCC CSSF flag */
<>	144:ef7eb2e8f9f7	1350	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<>	144:ef7eb2e8f9f7	1351	{
<>	144:ef7eb2e8f9f7	1352	/* RCC Clock Security System interrupt user callback */
<>	144:ef7eb2e8f9f7	1353	HAL_RCC_CSSCallback();
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	/* Clear RCC CSS pending bit */
<>	144:ef7eb2e8f9f7	1356	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<>	144:ef7eb2e8f9f7	1357	}
<>	144:ef7eb2e8f9f7	1358	}
<>	144:ef7eb2e8f9f7	1359
<>	144:ef7eb2e8f9f7	1360	/**
AnnaBridge	165:e614a9f1c9e2	1361	* @brief This function provides delay (in milliseconds) based on CPU cycles method.
AnnaBridge	165:e614a9f1c9e2	1362	* @param mdelay: specifies the delay time length, in milliseconds.
AnnaBridge	165:e614a9f1c9e2	1363	* @retval None
AnnaBridge	165:e614a9f1c9e2	1364	*/
AnnaBridge	165:e614a9f1c9e2	1365	static void RCC_Delay(uint32_t mdelay)
AnnaBridge	165:e614a9f1c9e2	1366	{
AnnaBridge	165:e614a9f1c9e2	1367	__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
AnnaBridge	165:e614a9f1c9e2	1368	do
AnnaBridge	165:e614a9f1c9e2	1369	{
AnnaBridge	165:e614a9f1c9e2	1370	__NOP();
AnnaBridge	165:e614a9f1c9e2	1371	}
AnnaBridge	165:e614a9f1c9e2	1372	while (Delay --);
AnnaBridge	165:e614a9f1c9e2	1373	}
AnnaBridge	165:e614a9f1c9e2	1374
AnnaBridge	165:e614a9f1c9e2	1375	/**
<>	144:ef7eb2e8f9f7	1376	* @brief RCC Clock Security System interrupt callback
<>	144:ef7eb2e8f9f7	1377	* @retval none
<>	144:ef7eb2e8f9f7	1378	*/
<>	144:ef7eb2e8f9f7	1379	__weak void HAL_RCC_CSSCallback(void)
<>	144:ef7eb2e8f9f7	1380	{
<>	144:ef7eb2e8f9f7	1381	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1382	the HAL_RCC_CSSCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1383	*/
<>	144:ef7eb2e8f9f7	1384	}
<>	144:ef7eb2e8f9f7	1385
<>	144:ef7eb2e8f9f7	1386	/**
<>	144:ef7eb2e8f9f7	1387	* @}
<>	144:ef7eb2e8f9f7	1388	*/
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	/**
<>	144:ef7eb2e8f9f7	1391	* @}
<>	144:ef7eb2e8f9f7	1392	*/
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	#endif /* HAL_RCC_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	1395	/**
<>	144:ef7eb2e8f9f7	1396	* @}
<>	144:ef7eb2e8f9f7	1397	*/
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399	/**
<>	144:ef7eb2e8f9f7	1400	* @}
<>	144:ef7eb2e8f9f7	1401	*/
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/