mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
154:37f96f9d4de2
Child:
187:0387e8f68319
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### RCC specific features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 After reset the device is running from Internal High Speed oscillator
<> 144:ef7eb2e8f9f7 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
<> 144:ef7eb2e8f9f7 20 and all peripherals are off except internal SRAM, Flash and JTAG.
<> 144:ef7eb2e8f9f7 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
<> 144:ef7eb2e8f9f7 22 all peripherals mapped on these buses are running at HSI speed.
<> 144:ef7eb2e8f9f7 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
<> 144:ef7eb2e8f9f7 24 (+) All GPIOs are in input floating state, except the JTAG pins which
<> 144:ef7eb2e8f9f7 25 are assigned to be used for debug purpose.
<> 144:ef7eb2e8f9f7 26 [..] Once the device started from reset, the user application has to:
<> 144:ef7eb2e8f9f7 27 (+) Configure the clock source to be used to drive the System clock
<> 144:ef7eb2e8f9f7 28 (if the application needs higher frequency/performance)
<> 144:ef7eb2e8f9f7 29 (+) Configure the System clock frequency and Flash settings
<> 144:ef7eb2e8f9f7 30 (+) Configure the AHB and APB buses prescalers
<> 144:ef7eb2e8f9f7 31 (+) Enable the clock for the peripheral(s) to be used
<> 144:ef7eb2e8f9f7 32 (+) Configure the clock source(s) for peripherals whose clocks are not
<> 144:ef7eb2e8f9f7 33 derived from the System clock (I2S, RTC, ADC, USB OTG FS)
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 ##### RCC Limitations #####
<> 144:ef7eb2e8f9f7 36 ==============================================================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 A delay between an RCC peripheral clock enable and the effective peripheral
<> 144:ef7eb2e8f9f7 39 enabling should be taken into account in order to manage the peripheral read/write
<> 144:ef7eb2e8f9f7 40 from/to registers.
<> 144:ef7eb2e8f9f7 41 (+) This delay depends on the peripheral mapping.
<> 144:ef7eb2e8f9f7 42 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 [..]
<> 144:ef7eb2e8f9f7 45 Workarounds:
<> 144:ef7eb2e8f9f7 46 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 144:ef7eb2e8f9f7 47 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 @endverbatim
<> 144:ef7eb2e8f9f7 50 ******************************************************************************
<> 144:ef7eb2e8f9f7 51 * @attention
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 56 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 57 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 58 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 60 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 61 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 63 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 64 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 ******************************************************************************
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup RCC RCC
<> 144:ef7eb2e8f9f7 88 * @brief RCC HAL module driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /** @defgroup RCC_Private_Constants RCC Private Constants
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @}
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 /** @defgroup RCC_Private_Macros RCC Private Macros
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 108 #define MCO1_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 109 #define MCO1_PIN GPIO_PIN_8
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /**
<> 144:ef7eb2e8f9f7 112 * @}
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /** @defgroup RCC_Private_Variables RCC Private Variables
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 /**
<> 144:ef7eb2e8f9f7 120 * @}
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Private function prototypes -----------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 124 static void RCC_Delay(uint32_t mdelay);
AnnaBridge 165:e614a9f1c9e2 125
AnnaBridge 165:e614a9f1c9e2 126 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /** @defgroup RCC_Exported_Functions RCC Exported Functions
<> 144:ef7eb2e8f9f7 129 * @{
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 133 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 134 *
<> 144:ef7eb2e8f9f7 135 @verbatim
<> 144:ef7eb2e8f9f7 136 ===============================================================================
<> 144:ef7eb2e8f9f7 137 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 138 ===============================================================================
<> 144:ef7eb2e8f9f7 139 [..]
<> 144:ef7eb2e8f9f7 140 This section provides functions allowing to configure the internal/external oscillators
<> 144:ef7eb2e8f9f7 141 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
<> 144:ef7eb2e8f9f7 142 and APB2).
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 [..] Internal/external clock and PLL configuration
<> 144:ef7eb2e8f9f7 145 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
<> 144:ef7eb2e8f9f7 146 the PLL as System clock source.
<> 144:ef7eb2e8f9f7 147 (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
<> 144:ef7eb2e8f9f7 148 clock source.
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
<> 144:ef7eb2e8f9f7 151 through the PLL as System clock source. Can be used also as RTC clock source.
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 (#) PLL (clocked by HSI or HSE), featuring different output clocks:
<> 144:ef7eb2e8f9f7 156 (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
<> 144:ef7eb2e8f9f7 157 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
<> 144:ef7eb2e8f9f7 160 and if a HSE clock failure occurs(HSE used directly or through PLL as System
<> 144:ef7eb2e8f9f7 161 clock source), the System clocks automatically switched to HSI and an interrupt
<> 144:ef7eb2e8f9f7 162 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
<> 144:ef7eb2e8f9f7 163 (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
<> 144:ef7eb2e8f9f7 166 HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 [..] System, AHB and APB buses clocks configuration
<> 144:ef7eb2e8f9f7 169 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
<> 144:ef7eb2e8f9f7 170 HSE and PLL.
<> 144:ef7eb2e8f9f7 171 The AHB clock (HCLK) is derived from System clock through configurable
<> 144:ef7eb2e8f9f7 172 prescaler and used to clock the CPU, memory and peripherals mapped
<> 144:ef7eb2e8f9f7 173 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
<> 144:ef7eb2e8f9f7 174 from AHB clock through configurable prescalers and used to clock
<> 144:ef7eb2e8f9f7 175 the peripherals mapped on these buses. You can use
<> 144:ef7eb2e8f9f7 176 "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
<> 144:ef7eb2e8f9f7 179 (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
<> 144:ef7eb2e8f9f7 180 divided by 128.
<> 144:ef7eb2e8f9f7 181 (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
<> 144:ef7eb2e8f9f7 182 to work correctly. This clock is derived of the main PLL through PLL Multiplier.
<> 144:ef7eb2e8f9f7 183 (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
<> 144:ef7eb2e8f9f7 184 (+@) IWDG clock which is always the LSI clock.
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
<> 144:ef7eb2e8f9f7 187 For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
<> 144:ef7eb2e8f9f7 188 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
<> 144:ef7eb2e8f9f7 189 @endverbatim
<> 144:ef7eb2e8f9f7 190 * @{
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /*
<> 144:ef7eb2e8f9f7 194 Additional consideration on the SYSCLK based on Latency settings:
<> 144:ef7eb2e8f9f7 195 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 196 | Latency | SYSCLK clock frequency (MHz) |
<> 144:ef7eb2e8f9f7 197 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 198 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
<> 144:ef7eb2e8f9f7 199 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 200 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
<> 144:ef7eb2e8f9f7 201 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 202 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
<> 144:ef7eb2e8f9f7 203 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief Resets the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 208 * @note The default reset state of the clock configuration is given below:
<> 144:ef7eb2e8f9f7 209 * - HSI ON and used as system clock source
<> 144:ef7eb2e8f9f7 210 * - HSE and PLL OFF
<> 144:ef7eb2e8f9f7 211 * - AHB, APB1 and APB2 prescaler set to 1.
<> 144:ef7eb2e8f9f7 212 * - CSS and MCO1 OFF
<> 144:ef7eb2e8f9f7 213 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 214 * @note This function does not modify the configuration of the
<> 144:ef7eb2e8f9f7 215 * - Peripheral clocks
<> 144:ef7eb2e8f9f7 216 * - LSI, LSE and RTC clocks
<> 144:ef7eb2e8f9f7 217 * @retval None
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 void HAL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Switch SYSCLK to HSI */
<> 144:ef7eb2e8f9f7 222 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Reset HSEON, CSSON, & PLLON bits */
<> 144:ef7eb2e8f9f7 225 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 228 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 231 CLEAR_REG(RCC->CFGR);
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Set HSITRIM bits to the reset value */
AnnaBridge 165:e614a9f1c9e2 234 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
<> 144:ef7eb2e8f9f7 235
AnnaBridge 165:e614a9f1c9e2 236 #if defined(RCC_CFGR2_SUPPORT)
<> 144:ef7eb2e8f9f7 237 /* Reset CFGR2 register */
<> 144:ef7eb2e8f9f7 238 CLEAR_REG(RCC->CFGR2);
<> 144:ef7eb2e8f9f7 239
AnnaBridge 165:e614a9f1c9e2 240 #endif /* RCC_CFGR2_SUPPORT */
<> 144:ef7eb2e8f9f7 241 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 242 CLEAR_REG(RCC->CIR);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 245 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief Initializes the RCC Oscillators according to the specified parameters in the
<> 144:ef7eb2e8f9f7 250 * RCC_OscInitTypeDef.
<> 144:ef7eb2e8f9f7 251 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 252 * contains the configuration information for the RCC Oscillators.
<> 144:ef7eb2e8f9f7 253 * @note The PLL is not disabled when used as system clock.
<> 144:ef7eb2e8f9f7 254 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
<> 144:ef7eb2e8f9f7 255 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<> 144:ef7eb2e8f9f7 256 * supported by this macro. User should request a transition to LSE Off
<> 144:ef7eb2e8f9f7 257 * first and then LSE On or LSE Bypass.
<> 144:ef7eb2e8f9f7 258 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 259 * supported by this macro. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 260 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 261 * @retval HAL status
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 264 {
AnnaBridge 165:e614a9f1c9e2 265 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Check the parameters */
<> 144:ef7eb2e8f9f7 268 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 269 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /*------------------------------- HSE Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 272 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 /* Check the parameters */
<> 144:ef7eb2e8f9f7 275 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
<> 144:ef7eb2e8f9f7 278 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 279 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286 else
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Set the new HSE configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 289 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Check the HSE State */
<> 144:ef7eb2e8f9f7 293 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 296 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Wait till HSE is ready */
<> 144:ef7eb2e8f9f7 299 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 else
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 310 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Wait till HSE is disabled */
<> 144:ef7eb2e8f9f7 313 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323 /*----------------------------- HSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 324 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 /* Check the parameters */
<> 144:ef7eb2e8f9f7 327 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<> 144:ef7eb2e8f9f7 328 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<> 144:ef7eb2e8f9f7 331 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 332 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 /* When HSI is used as system clock it will not disabled */
<> 144:ef7eb2e8f9f7 335 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 /* Otherwise, just the calibration is allowed */
<> 144:ef7eb2e8f9f7 340 else
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 343 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346 else
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 /* Check the HSI State */
<> 144:ef7eb2e8f9f7 349 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 /* Enable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 352 __HAL_RCC_HSI_ENABLE();
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 355 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 358 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 367 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369 else
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 /* Disable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 372 __HAL_RCC_HSI_DISABLE();
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 375 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Wait till HSI is disabled */
<> 144:ef7eb2e8f9f7 378 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 379 {
<> 144:ef7eb2e8f9f7 380 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388 /*------------------------------ LSI Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 389 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 /* Check the parameters */
<> 144:ef7eb2e8f9f7 392 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Check the LSI State */
<> 144:ef7eb2e8f9f7 395 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 /* Enable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 398 __HAL_RCC_LSI_ENABLE();
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 401 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 404 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 /* To have a fully stabilized clock in the specified range, a software delay of 1ms
<> 144:ef7eb2e8f9f7 412 should be added.*/
AnnaBridge 165:e614a9f1c9e2 413 RCC_Delay(1);
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 else
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 /* Disable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 418 __HAL_RCC_LSI_DISABLE();
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 421 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Wait till LSI is disabled */
<> 144:ef7eb2e8f9f7 424 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 427 {
<> 144:ef7eb2e8f9f7 428 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 /*------------------------------ LSE Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 434 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<> 144:ef7eb2e8f9f7 435 {
AnnaBridge 165:e614a9f1c9e2 436 FlagStatus pwrclkchanged = RESET;
AnnaBridge 165:e614a9f1c9e2 437
<> 144:ef7eb2e8f9f7 438 /* Check the parameters */
<> 144:ef7eb2e8f9f7 439 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<> 144:ef7eb2e8f9f7 440
AnnaBridge 165:e614a9f1c9e2 441 /* Update LSE configuration in Backup Domain control register */
AnnaBridge 165:e614a9f1c9e2 442 /* Requires to enable write access to Backup Domain of necessary */
AnnaBridge 165:e614a9f1c9e2 443 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
AnnaBridge 165:e614a9f1c9e2 444 {
<> 144:ef7eb2e8f9f7 445 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 165:e614a9f1c9e2 446 pwrclkchanged = SET;
AnnaBridge 165:e614a9f1c9e2 447 }
<> 144:ef7eb2e8f9f7 448
AnnaBridge 165:e614a9f1c9e2 449 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
AnnaBridge 165:e614a9f1c9e2 450 {
<> 144:ef7eb2e8f9f7 451 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 452 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 455 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 456
AnnaBridge 165:e614a9f1c9e2 457 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463 }
AnnaBridge 165:e614a9f1c9e2 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Set the new LSE configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 467 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<> 144:ef7eb2e8f9f7 468 /* Check the LSE State */
<> 144:ef7eb2e8f9f7 469 if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 472 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 475 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483 else
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 486 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Wait till LSE is disabled */
<> 144:ef7eb2e8f9f7 489 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496 }
AnnaBridge 165:e614a9f1c9e2 497
AnnaBridge 165:e614a9f1c9e2 498 /* Require to disable power clock if necessary */
AnnaBridge 165:e614a9f1c9e2 499 if(pwrclkchanged == SET)
AnnaBridge 165:e614a9f1c9e2 500 {
AnnaBridge 165:e614a9f1c9e2 501 __HAL_RCC_PWR_CLK_DISABLE();
AnnaBridge 165:e614a9f1c9e2 502 }
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 #if defined(RCC_CR_PLL2ON)
<> 144:ef7eb2e8f9f7 506 /*-------------------------------- PLL2 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 507 /* Check the parameters */
<> 144:ef7eb2e8f9f7 508 assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
<> 144:ef7eb2e8f9f7 509 if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
<> 144:ef7eb2e8f9f7 512 clock (i.e. it is used as PLL clock entry that is used as system clock). */
<> 144:ef7eb2e8f9f7 513 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
<> 144:ef7eb2e8f9f7 514 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
<> 144:ef7eb2e8f9f7 515 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 else
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Check the parameters */
<> 144:ef7eb2e8f9f7 524 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
<> 144:ef7eb2e8f9f7 525 assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Prediv2 can be written only when the PLLI2S is disabled. */
<> 144:ef7eb2e8f9f7 528 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 529 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
<> 144:ef7eb2e8f9f7 530 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 536 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 539 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 542 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 551 __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Configure the main PLL2 multiplication factors. */
<> 144:ef7eb2e8f9f7 554 __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Enable the main PLL2. */
<> 144:ef7eb2e8f9f7 557 __HAL_RCC_PLL2_ENABLE();
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 560 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Wait till PLL2 is ready */
<> 144:ef7eb2e8f9f7 563 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571 else
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* Set PREDIV1 source to HSE */
<> 144:ef7eb2e8f9f7 574 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 577 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 580 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 583 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591 }
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 #endif /* RCC_CR_PLL2ON */
<> 144:ef7eb2e8f9f7 595 /*-------------------------------- PLL Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 596 /* Check the parameters */
<> 144:ef7eb2e8f9f7 597 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<> 144:ef7eb2e8f9f7 598 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 601 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 /* Check the parameters */
<> 144:ef7eb2e8f9f7 606 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<> 144:ef7eb2e8f9f7 607 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 610 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 613 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 616 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Configure the HSE prediv factor --------------------------------*/
<> 144:ef7eb2e8f9f7 625 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
<> 144:ef7eb2e8f9f7 626 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 /* Check the parameter */
<> 144:ef7eb2e8f9f7 629 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
<> 144:ef7eb2e8f9f7 630 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 631 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Set PREDIV1 source */
<> 144:ef7eb2e8f9f7 634 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
<> 144:ef7eb2e8f9f7 635 #endif /* RCC_CFGR2_PREDIV1SRC */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /* Set PREDIV1 Value */
<> 144:ef7eb2e8f9f7 638 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Configure the main PLL clock source and multiplication factors. */
<> 144:ef7eb2e8f9f7 642 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 144:ef7eb2e8f9f7 643 RCC_OscInitStruct->PLL.PLLMUL);
<> 144:ef7eb2e8f9f7 644 /* Enable the main PLL. */
<> 144:ef7eb2e8f9f7 645 __HAL_RCC_PLL_ENABLE();
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 648 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 651 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659 else
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 662 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 665 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 668 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677 else
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 return HAL_OK;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
<> 144:ef7eb2e8f9f7 688 * parameters in the RCC_ClkInitStruct.
<> 144:ef7eb2e8f9f7 689 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 690 * contains the configuration information for the RCC peripheral.
<> 144:ef7eb2e8f9f7 691 * @param FLatency FLASH Latency
<> 144:ef7eb2e8f9f7 692 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 693 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 694 * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
<> 144:ef7eb2e8f9f7 695 *
<> 144:ef7eb2e8f9f7 696 * @note The HSI is used (enabled by hardware) as system clock source after
<> 144:ef7eb2e8f9f7 697 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
<> 144:ef7eb2e8f9f7 698 * of failure of the HSE used directly or indirectly as system clock
<> 144:ef7eb2e8f9f7 699 * (if the Clock Security System CSS is enabled).
<> 144:ef7eb2e8f9f7 700 *
<> 144:ef7eb2e8f9f7 701 * @note A switch from one clock source to another occurs only if the target
<> 144:ef7eb2e8f9f7 702 * clock source is ready (clock stable after start-up delay or PLL locked).
<> 144:ef7eb2e8f9f7 703 * If a clock source which is not yet ready is selected, the switch will
<> 144:ef7eb2e8f9f7 704 * occur when the clock source will be ready.
<> 144:ef7eb2e8f9f7 705 * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
<> 144:ef7eb2e8f9f7 706 * currently used as system clock source.
<> 144:ef7eb2e8f9f7 707 * @retval HAL status
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<> 144:ef7eb2e8f9f7 710 {
AnnaBridge 165:e614a9f1c9e2 711 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Check the parameters */
<> 144:ef7eb2e8f9f7 714 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 715 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<> 144:ef7eb2e8f9f7 716 assert_param(IS_FLASH_LATENCY(FLatency));
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
<> 144:ef7eb2e8f9f7 719 must be correctly programmed according to the frequency of the CPU clock
<> 144:ef7eb2e8f9f7 720 (HCLK) of the device. */
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 #if defined(FLASH_ACR_LATENCY)
<> 144:ef7eb2e8f9f7 723 /* Increasing the number of wait states because of higher CPU frequency */
<> 144:ef7eb2e8f9f7 724 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 727 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 730 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 731 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 #endif /* FLASH_ACR_LATENCY */
<> 144:ef7eb2e8f9f7 738 /*-------------------------- HCLK Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 739 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 742 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /*------------------------- SYSCLK Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 746 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* HSE is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 751 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 752 {
<> 144:ef7eb2e8f9f7 753 /* Check the HSE ready flag */
<> 144:ef7eb2e8f9f7 754 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 /* PLL is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 760 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 /* Check the PLL ready flag */
<> 144:ef7eb2e8f9f7 763 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 766 }
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768 /* HSI is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 769 else
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 /* Check the HSI ready flag */
<> 144:ef7eb2e8f9f7 772 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 775 }
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 780 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802 else
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813 #if defined(FLASH_ACR_LATENCY)
<> 144:ef7eb2e8f9f7 814 /* Decreasing the number of wait states because of lower CPU frequency */
<> 144:ef7eb2e8f9f7 815 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 818 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 821 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 822 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827 #endif /* FLASH_ACR_LATENCY */
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /*-------------------------- PCLK1 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 830 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<> 144:ef7eb2e8f9f7 831 {
<> 144:ef7eb2e8f9f7 832 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 833 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /*-------------------------- PCLK2 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 837 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
<> 144:ef7eb2e8f9f7 840 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Update the SystemCoreClock global variable */
AnnaBridge 165:e614a9f1c9e2 844 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 847 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 return HAL_OK;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /**
<> 144:ef7eb2e8f9f7 853 * @}
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 857 * @brief RCC clocks control functions
<> 144:ef7eb2e8f9f7 858 *
<> 144:ef7eb2e8f9f7 859 @verbatim
<> 144:ef7eb2e8f9f7 860 ===============================================================================
<> 144:ef7eb2e8f9f7 861 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 862 ===============================================================================
<> 144:ef7eb2e8f9f7 863 [..]
<> 144:ef7eb2e8f9f7 864 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 865 frequencies.
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 @endverbatim
<> 144:ef7eb2e8f9f7 868 * @{
<> 144:ef7eb2e8f9f7 869 */
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /**
<> 144:ef7eb2e8f9f7 872 * @brief Selects the clock source to output on MCO pin.
<> 144:ef7eb2e8f9f7 873 * @note MCO pin should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 874 * @param RCC_MCOx specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 875 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 876 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 877 * @param RCC_MCOSource specifies the clock source to output.
<> 144:ef7eb2e8f9f7 878 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 879 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<> 144:ef7eb2e8f9f7 880 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
<> 144:ef7eb2e8f9f7 881 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<> 144:ef7eb2e8f9f7 882 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 883 @if STM32F105xC
<> 144:ef7eb2e8f9f7 884 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 885 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
<> 144:ef7eb2e8f9f7 886 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 887 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
<> 144:ef7eb2e8f9f7 888 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
<> 144:ef7eb2e8f9f7 889 @endif
<> 144:ef7eb2e8f9f7 890 @if STM32F107xC
<> 144:ef7eb2e8f9f7 891 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 892 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
<> 144:ef7eb2e8f9f7 893 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 894 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
<> 144:ef7eb2e8f9f7 895 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
<> 144:ef7eb2e8f9f7 896 @endif
<> 144:ef7eb2e8f9f7 897 * @param RCC_MCODiv specifies the MCO DIV.
<> 144:ef7eb2e8f9f7 898 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 899 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
<> 144:ef7eb2e8f9f7 900 * @retval None
<> 144:ef7eb2e8f9f7 901 */
<> 144:ef7eb2e8f9f7 902 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<> 144:ef7eb2e8f9f7 903 {
AnnaBridge 165:e614a9f1c9e2 904 GPIO_InitTypeDef gpio = {0U};
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /* Check the parameters */
<> 144:ef7eb2e8f9f7 907 assert_param(IS_RCC_MCO(RCC_MCOx));
<> 144:ef7eb2e8f9f7 908 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<> 144:ef7eb2e8f9f7 909 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
AnnaBridge 165:e614a9f1c9e2 910
AnnaBridge 165:e614a9f1c9e2 911 /* Prevent unused argument(s) compilation warning */
AnnaBridge 165:e614a9f1c9e2 912 UNUSED(RCC_MCOx);
AnnaBridge 165:e614a9f1c9e2 913 UNUSED(RCC_MCODiv);
AnnaBridge 165:e614a9f1c9e2 914
<> 144:ef7eb2e8f9f7 915 /* Configure the MCO1 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 916 gpio.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 917 gpio.Speed = GPIO_SPEED_FREQ_HIGH;
<> 144:ef7eb2e8f9f7 918 gpio.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 919 gpio.Pin = MCO1_PIN;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* MCO1 Clock Enable */
<> 144:ef7eb2e8f9f7 922 MCO1_CLK_ENABLE();
AnnaBridge 165:e614a9f1c9e2 923
<> 144:ef7eb2e8f9f7 924 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
AnnaBridge 165:e614a9f1c9e2 925
<> 144:ef7eb2e8f9f7 926 /* Configure the MCO clock source */
<> 144:ef7eb2e8f9f7 927 __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /**
<> 144:ef7eb2e8f9f7 931 * @brief Enables the Clock Security System.
<> 144:ef7eb2e8f9f7 932 * @note If a failure is detected on the HSE oscillator clock, this oscillator
<> 144:ef7eb2e8f9f7 933 * is automatically disabled and an interrupt is generated to inform the
<> 144:ef7eb2e8f9f7 934 * software about the failure (Clock Security System Interrupt, CSSI),
<> 144:ef7eb2e8f9f7 935 * allowing the MCU to perform rescue operations. The CSSI is linked to
<> 144:ef7eb2e8f9f7 936 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 937 * @retval None
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939 void HAL_RCC_EnableCSS(void)
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
<> 144:ef7eb2e8f9f7 942 }
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /**
<> 144:ef7eb2e8f9f7 945 * @brief Disables the Clock Security System.
<> 144:ef7eb2e8f9f7 946 * @retval None
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948 void HAL_RCC_DisableCSS(void)
<> 144:ef7eb2e8f9f7 949 {
<> 144:ef7eb2e8f9f7 950 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /**
<> 144:ef7eb2e8f9f7 954 * @brief Returns the SYSCLK frequency
<> 144:ef7eb2e8f9f7 955 * @note The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 956 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 957 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 958 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 959 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 960 * divided by PREDIV factor(**)
<> 144:ef7eb2e8f9f7 961 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 962 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
<> 144:ef7eb2e8f9f7 963 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 964 * 8 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 965 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 966 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 967 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 968 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 969 * have wrong result.
<> 144:ef7eb2e8f9f7 970 *
<> 144:ef7eb2e8f9f7 971 * @note The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 972 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 973 *
<> 144:ef7eb2e8f9f7 974 * @note This function can be used by the user application to compute the
<> 144:ef7eb2e8f9f7 975 * baud-rate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 976 *
<> 144:ef7eb2e8f9f7 977 * @note Each time SYSCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 978 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 979 *
<> 144:ef7eb2e8f9f7 980 * @retval SYSCLK frequency
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982 uint32_t HAL_RCC_GetSysClockFreq(void)
<> 144:ef7eb2e8f9f7 983 {
AnnaBridge 165:e614a9f1c9e2 984 #if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge 165:e614a9f1c9e2 985 const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
AnnaBridge 165:e614a9f1c9e2 986 const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
<> 144:ef7eb2e8f9f7 987 #else
AnnaBridge 165:e614a9f1c9e2 988 const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
<> 144:ef7eb2e8f9f7 989 #if defined(RCC_CFGR2_PREDIV1)
AnnaBridge 165:e614a9f1c9e2 990 const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
<> 144:ef7eb2e8f9f7 991 #else
AnnaBridge 165:e614a9f1c9e2 992 const uint8_t aPredivFactorTable[2] = {1, 2};
<> 144:ef7eb2e8f9f7 993 #endif /*RCC_CFGR2_PREDIV1*/
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 #endif
AnnaBridge 165:e614a9f1c9e2 996 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
AnnaBridge 165:e614a9f1c9e2 997 uint32_t sysclockfreq = 0U;
<> 144:ef7eb2e8f9f7 998 #if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge 165:e614a9f1c9e2 999 uint32_t prediv2 = 0U, pll2mul = 0U;
<> 144:ef7eb2e8f9f7 1000 #endif /*RCC_CFGR2_PREDIV1SRC*/
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 tmpreg = RCC->CFGR;
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1005 switch (tmpreg & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 1008 {
<> 144:ef7eb2e8f9f7 1009 sysclockfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1010 break;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 1013 {
AnnaBridge 165:e614a9f1c9e2 1014 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
<> 144:ef7eb2e8f9f7 1015 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
<> 144:ef7eb2e8f9f7 1016 {
<> 144:ef7eb2e8f9f7 1017 #if defined(RCC_CFGR2_PREDIV1)
AnnaBridge 165:e614a9f1c9e2 1018 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
<> 144:ef7eb2e8f9f7 1019 #else
AnnaBridge 165:e614a9f1c9e2 1020 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
<> 144:ef7eb2e8f9f7 1021 #endif /*RCC_CFGR2_PREDIV1*/
<> 144:ef7eb2e8f9f7 1022 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 /* PLL2 selected as Prediv1 source */
<> 144:ef7eb2e8f9f7 1027 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
AnnaBridge 165:e614a9f1c9e2 1028 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
AnnaBridge 165:e614a9f1c9e2 1029 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
<> 144:ef7eb2e8f9f7 1030 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032 else
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 1035 pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
<> 144:ef7eb2e8f9f7 1039 /* In this case need to divide pllclk by 2 */
AnnaBridge 165:e614a9f1c9e2 1040 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 pllclk = pllclk / 2;
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044 #else
<> 144:ef7eb2e8f9f7 1045 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 1046 pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
<> 144:ef7eb2e8f9f7 1047 #endif /*RCC_CFGR2_PREDIV1SRC*/
<> 144:ef7eb2e8f9f7 1048 }
<> 144:ef7eb2e8f9f7 1049 else
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<> 144:ef7eb2e8f9f7 1052 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054 sysclockfreq = pllclk;
<> 144:ef7eb2e8f9f7 1055 break;
<> 144:ef7eb2e8f9f7 1056 }
<> 144:ef7eb2e8f9f7 1057 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 1058 default: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1061 break;
<> 144:ef7eb2e8f9f7 1062 }
<> 144:ef7eb2e8f9f7 1063 }
<> 144:ef7eb2e8f9f7 1064 return sysclockfreq;
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /**
<> 144:ef7eb2e8f9f7 1068 * @brief Returns the HCLK frequency
<> 144:ef7eb2e8f9f7 1069 * @note Each time HCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1070 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1071 *
<> 144:ef7eb2e8f9f7 1072 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 1073 * and updated within this function
<> 144:ef7eb2e8f9f7 1074 * @retval HCLK frequency
<> 144:ef7eb2e8f9f7 1075 */
<> 144:ef7eb2e8f9f7 1076 uint32_t HAL_RCC_GetHCLKFreq(void)
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /**
<> 144:ef7eb2e8f9f7 1082 * @brief Returns the PCLK1 frequency
<> 144:ef7eb2e8f9f7 1083 * @note Each time PCLK1 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1084 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1085 * @retval PCLK1 frequency
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087 uint32_t HAL_RCC_GetPCLK1Freq(void)
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
AnnaBridge 165:e614a9f1c9e2 1090 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /**
<> 144:ef7eb2e8f9f7 1094 * @brief Returns the PCLK2 frequency
<> 144:ef7eb2e8f9f7 1095 * @note Each time PCLK2 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1096 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1097 * @retval PCLK2 frequency
<> 144:ef7eb2e8f9f7 1098 */
<> 144:ef7eb2e8f9f7 1099 uint32_t HAL_RCC_GetPCLK2Freq(void)
<> 144:ef7eb2e8f9f7 1100 {
<> 144:ef7eb2e8f9f7 1101 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
AnnaBridge 165:e614a9f1c9e2 1102 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
<> 144:ef7eb2e8f9f7 1103 }
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /**
<> 144:ef7eb2e8f9f7 1106 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1107 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1108 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1109 * will be configured.
<> 144:ef7eb2e8f9f7 1110 * @retval None
<> 144:ef7eb2e8f9f7 1111 */
<> 144:ef7eb2e8f9f7 1112 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1115 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /* Set all possible values for the Oscillator type parameter ---------------*/
<> 144:ef7eb2e8f9f7 1118 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
<> 144:ef7eb2e8f9f7 1119 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 1122 /* Get the Prediv1 source --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1123 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
<> 144:ef7eb2e8f9f7 1124 #endif /* RCC_CFGR2_PREDIV1SRC */
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /* Get the HSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1127 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<> 144:ef7eb2e8f9f7 1130 }
<> 144:ef7eb2e8f9f7 1131 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 1134 }
<> 144:ef7eb2e8f9f7 1135 else
<> 144:ef7eb2e8f9f7 1136 {
<> 144:ef7eb2e8f9f7 1137 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 1138 }
<> 144:ef7eb2e8f9f7 1139 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /* Get the HSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1142 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 1143 {
<> 144:ef7eb2e8f9f7 1144 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 1145 }
<> 144:ef7eb2e8f9f7 1146 else
<> 144:ef7eb2e8f9f7 1147 {
<> 144:ef7eb2e8f9f7 1148 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 1149 }
<> 144:ef7eb2e8f9f7 1150
AnnaBridge 165:e614a9f1c9e2 1151 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /* Get the LSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1154 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162 else
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 1165 }
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /* Get the LSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1168 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1169 {
<> 144:ef7eb2e8f9f7 1170 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172 else
<> 144:ef7eb2e8f9f7 1173 {
<> 144:ef7eb2e8f9f7 1174 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 1175 }
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Get the PLL configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1179 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 1182 }
<> 144:ef7eb2e8f9f7 1183 else
<> 144:ef7eb2e8f9f7 1184 {
<> 144:ef7eb2e8f9f7 1185 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
<> 144:ef7eb2e8f9f7 1188 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
<> 144:ef7eb2e8f9f7 1189 #if defined(RCC_CR_PLL2ON)
<> 144:ef7eb2e8f9f7 1190 /* Get the PLL2 configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1191 if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
<> 144:ef7eb2e8f9f7 1192 {
<> 144:ef7eb2e8f9f7 1193 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195 else
<> 144:ef7eb2e8f9f7 1196 {
<> 144:ef7eb2e8f9f7 1197 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199 RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
<> 144:ef7eb2e8f9f7 1200 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
<> 144:ef7eb2e8f9f7 1201 #endif /* RCC_CR_PLL2ON */
<> 144:ef7eb2e8f9f7 1202 }
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /**
<> 144:ef7eb2e8f9f7 1205 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1206 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1207 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1208 * contains the current clock configuration.
<> 144:ef7eb2e8f9f7 1209 * @param pFLatency Pointer on the Flash Latency.
<> 144:ef7eb2e8f9f7 1210 * @retval None
<> 144:ef7eb2e8f9f7 1211 */
<> 144:ef7eb2e8f9f7 1212 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
<> 144:ef7eb2e8f9f7 1213 {
<> 144:ef7eb2e8f9f7 1214 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1215 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1216 assert_param(pFLatency != NULL);
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Set all possible values for the Clock type parameter --------------------*/
<> 144:ef7eb2e8f9f7 1219 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /* Get the SYSCLK configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1222 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /* Get the HCLK configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1225 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /* Get the APB1 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1228 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /* Get the APB2 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1231 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 #if defined(FLASH_ACR_LATENCY)
<> 144:ef7eb2e8f9f7 1234 /* Get the Flash Wait State (Latency) configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1235 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<> 144:ef7eb2e8f9f7 1236 #else
<> 144:ef7eb2e8f9f7 1237 /* For VALUE lines devices, only LATENCY_0 can be set*/
<> 144:ef7eb2e8f9f7 1238 *pFLatency = (uint32_t)FLASH_LATENCY_0;
<> 144:ef7eb2e8f9f7 1239 #endif
<> 144:ef7eb2e8f9f7 1240 }
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 /**
<> 144:ef7eb2e8f9f7 1243 * @brief This function handles the RCC CSS interrupt request.
<> 144:ef7eb2e8f9f7 1244 * @note This API should be called under the NMI_Handler().
<> 144:ef7eb2e8f9f7 1245 * @retval None
<> 144:ef7eb2e8f9f7 1246 */
<> 144:ef7eb2e8f9f7 1247 void HAL_RCC_NMI_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Check RCC CSSF flag */
<> 144:ef7eb2e8f9f7 1250 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 /* RCC Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 1253 HAL_RCC_CSSCallback();
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 /* Clear RCC CSS pending bit */
<> 144:ef7eb2e8f9f7 1256 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<> 144:ef7eb2e8f9f7 1257 }
<> 144:ef7eb2e8f9f7 1258 }
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /**
AnnaBridge 165:e614a9f1c9e2 1261 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
AnnaBridge 165:e614a9f1c9e2 1262 * @param mdelay: specifies the delay time length, in milliseconds.
AnnaBridge 165:e614a9f1c9e2 1263 * @retval None
AnnaBridge 165:e614a9f1c9e2 1264 */
AnnaBridge 165:e614a9f1c9e2 1265 static void RCC_Delay(uint32_t mdelay)
AnnaBridge 165:e614a9f1c9e2 1266 {
AnnaBridge 165:e614a9f1c9e2 1267 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
AnnaBridge 165:e614a9f1c9e2 1268 do
AnnaBridge 165:e614a9f1c9e2 1269 {
AnnaBridge 165:e614a9f1c9e2 1270 __NOP();
AnnaBridge 165:e614a9f1c9e2 1271 }
AnnaBridge 165:e614a9f1c9e2 1272 while (Delay --);
AnnaBridge 165:e614a9f1c9e2 1273 }
AnnaBridge 165:e614a9f1c9e2 1274
AnnaBridge 165:e614a9f1c9e2 1275 /**
<> 144:ef7eb2e8f9f7 1276 * @brief RCC Clock Security System interrupt callback
<> 144:ef7eb2e8f9f7 1277 * @retval none
<> 144:ef7eb2e8f9f7 1278 */
<> 144:ef7eb2e8f9f7 1279 __weak void HAL_RCC_CSSCallback(void)
<> 144:ef7eb2e8f9f7 1280 {
<> 144:ef7eb2e8f9f7 1281 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1282 the HAL_RCC_CSSCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1283 */
<> 144:ef7eb2e8f9f7 1284 }
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /**
<> 144:ef7eb2e8f9f7 1287 * @}
<> 144:ef7eb2e8f9f7 1288 */
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 /**
<> 144:ef7eb2e8f9f7 1291 * @}
<> 144:ef7eb2e8f9f7 1292 */
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1295 /**
<> 144:ef7eb2e8f9f7 1296 * @}
<> 144:ef7eb2e8f9f7 1297 */
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /**
<> 144:ef7eb2e8f9f7 1300 * @}
<> 144:ef7eb2e8f9f7 1301 */
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/