mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_gpio_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of GPIO HAL Extension module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
AnnaBridge 187:0387e8f68319 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F1xx_HAL_GPIO_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F1xx_HAL_GPIO_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
AnnaBridge 187:0387e8f68319 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @defgroup GPIOEx GPIOEx
<> 144:ef7eb2e8f9f7 52 * @{
AnnaBridge 187:0387e8f68319 53 */
<> 144:ef7eb2e8f9f7 54 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 55 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
<> 144:ef7eb2e8f9f7 58 * @{
AnnaBridge 187:0387e8f68319 59 */
AnnaBridge 187:0387e8f68319 60
<> 144:ef7eb2e8f9f7 61 /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
<> 144:ef7eb2e8f9f7 62 * @brief This section propose definition to use the Cortex EVENTOUT signal.
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
AnnaBridge 187:0387e8f68319 65
AnnaBridge 187:0387e8f68319 66 /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
<> 144:ef7eb2e8f9f7 67 * @{
<> 144:ef7eb2e8f9f7 68 */
AnnaBridge 187:0387e8f68319 69
<> 144:ef7eb2e8f9f7 70 #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
<> 144:ef7eb2e8f9f7 71 #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
<> 144:ef7eb2e8f9f7 72 #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
<> 144:ef7eb2e8f9f7 73 #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
<> 144:ef7eb2e8f9f7 74 #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
<> 144:ef7eb2e8f9f7 75 #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
<> 144:ef7eb2e8f9f7 76 #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
<> 144:ef7eb2e8f9f7 77 #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
<> 144:ef7eb2e8f9f7 78 #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
<> 144:ef7eb2e8f9f7 79 #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
<> 144:ef7eb2e8f9f7 80 #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
<> 144:ef7eb2e8f9f7 81 #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
<> 144:ef7eb2e8f9f7 82 #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
<> 144:ef7eb2e8f9f7 83 #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
<> 144:ef7eb2e8f9f7 84 #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
<> 144:ef7eb2e8f9f7 85 #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
<> 144:ef7eb2e8f9f7 88 ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
<> 144:ef7eb2e8f9f7 89 ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
<> 144:ef7eb2e8f9f7 90 ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
<> 144:ef7eb2e8f9f7 91 ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
<> 144:ef7eb2e8f9f7 92 ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
<> 144:ef7eb2e8f9f7 93 ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
<> 144:ef7eb2e8f9f7 94 ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
<> 144:ef7eb2e8f9f7 95 ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
<> 144:ef7eb2e8f9f7 96 ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
<> 144:ef7eb2e8f9f7 97 ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
<> 144:ef7eb2e8f9f7 98 ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
<> 144:ef7eb2e8f9f7 99 ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
<> 144:ef7eb2e8f9f7 100 ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
<> 144:ef7eb2e8f9f7 101 ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
<> 144:ef7eb2e8f9f7 102 ((__PIN__) == AFIO_EVENTOUT_PIN_15))
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @}
AnnaBridge 187:0387e8f68319 105 */
AnnaBridge 187:0387e8f68319 106
<> 144:ef7eb2e8f9f7 107 /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
AnnaBridge 187:0387e8f68319 110
<> 144:ef7eb2e8f9f7 111 #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
<> 144:ef7eb2e8f9f7 112 #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
<> 144:ef7eb2e8f9f7 113 #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
<> 144:ef7eb2e8f9f7 114 #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
<> 144:ef7eb2e8f9f7 115 #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
<> 144:ef7eb2e8f9f7 118 ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
<> 144:ef7eb2e8f9f7 119 ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
<> 144:ef7eb2e8f9f7 120 ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
<> 144:ef7eb2e8f9f7 121 ((__PORT__) == AFIO_EVENTOUT_PORT_E))
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
AnnaBridge 187:0387e8f68319 125
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
<> 144:ef7eb2e8f9f7 131 * @brief This section propose definition to remap the alternate function to some other port/pins.
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
AnnaBridge 187:0387e8f68319 134
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
<> 144:ef7eb2e8f9f7 137 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
<> 144:ef7eb2e8f9f7 138 * @retval None
<> 144:ef7eb2e8f9f7 139 */
AnnaBridge 187:0387e8f68319 140 #define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
<> 144:ef7eb2e8f9f7 144 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
<> 144:ef7eb2e8f9f7 145 * @retval None
<> 144:ef7eb2e8f9f7 146 */
AnnaBridge 187:0387e8f68319 147 #define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
<> 144:ef7eb2e8f9f7 151 * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
<> 144:ef7eb2e8f9f7 152 * @retval None
<> 144:ef7eb2e8f9f7 153 */
AnnaBridge 187:0387e8f68319 154 #define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
<> 144:ef7eb2e8f9f7 158 * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
<> 144:ef7eb2e8f9f7 159 * @retval None
<> 144:ef7eb2e8f9f7 160 */
AnnaBridge 187:0387e8f68319 161 #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief Enable the remapping of USART1 alternate function TX and RX.
<> 144:ef7eb2e8f9f7 165 * @note ENABLE: Remap (TX/PB6, RX/PB7)
<> 144:ef7eb2e8f9f7 166 * @retval None
<> 144:ef7eb2e8f9f7 167 */
AnnaBridge 187:0387e8f68319 168 #define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @brief Disable the remapping of USART1 alternate function TX and RX.
<> 144:ef7eb2e8f9f7 172 * @note DISABLE: No remap (TX/PA9, RX/PA10)
<> 144:ef7eb2e8f9f7 173 * @retval None
<> 144:ef7eb2e8f9f7 174 */
AnnaBridge 187:0387e8f68319 175 #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 179 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
<> 144:ef7eb2e8f9f7 180 * @retval None
<> 144:ef7eb2e8f9f7 181 */
AnnaBridge 187:0387e8f68319 182 #define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 186 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
<> 144:ef7eb2e8f9f7 187 * @retval None
<> 144:ef7eb2e8f9f7 188 */
AnnaBridge 187:0387e8f68319 189 #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 193 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
<> 144:ef7eb2e8f9f7 194 * @retval None
<> 144:ef7eb2e8f9f7 195 */
AnnaBridge 187:0387e8f68319 196 #define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
AnnaBridge 187:0387e8f68319 197
<> 144:ef7eb2e8f9f7 198 /**
<> 144:ef7eb2e8f9f7 199 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 200 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
<> 144:ef7eb2e8f9f7 201 * @retval None
<> 144:ef7eb2e8f9f7 202 */
AnnaBridge 187:0387e8f68319 203 #define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 207 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
<> 144:ef7eb2e8f9f7 208 * @retval None
<> 144:ef7eb2e8f9f7 209 */
AnnaBridge 187:0387e8f68319 210 #define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
<> 144:ef7eb2e8f9f7 214 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
<> 144:ef7eb2e8f9f7 215 * @retval None
<> 144:ef7eb2e8f9f7 216 */
AnnaBridge 187:0387e8f68319 217 #define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
<> 144:ef7eb2e8f9f7 221 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
<> 144:ef7eb2e8f9f7 222 * @retval None
<> 144:ef7eb2e8f9f7 223 */
AnnaBridge 187:0387e8f68319 224 #define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
<> 144:ef7eb2e8f9f7 228 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
<> 144:ef7eb2e8f9f7 229 * @retval None
<> 144:ef7eb2e8f9f7 230 */
AnnaBridge 187:0387e8f68319 231 #define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 235 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
<> 144:ef7eb2e8f9f7 236 * @retval None
<> 144:ef7eb2e8f9f7 237 */
AnnaBridge 187:0387e8f68319 238 #define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 242 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
<> 144:ef7eb2e8f9f7 243 * @retval None
<> 144:ef7eb2e8f9f7 244 */
AnnaBridge 187:0387e8f68319 245 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 249 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
<> 144:ef7eb2e8f9f7 250 * @retval None
<> 144:ef7eb2e8f9f7 251 */
AnnaBridge 187:0387e8f68319 252 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 256 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
<> 144:ef7eb2e8f9f7 257 * @retval None
<> 144:ef7eb2e8f9f7 258 */
AnnaBridge 187:0387e8f68319 259 #define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
<> 144:ef7eb2e8f9f7 263 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
<> 144:ef7eb2e8f9f7 264 * @note TIM3_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 265 * @retval None
<> 144:ef7eb2e8f9f7 266 */
AnnaBridge 187:0387e8f68319 267 #define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
<> 144:ef7eb2e8f9f7 271 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
<> 144:ef7eb2e8f9f7 272 * @note TIM3_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 273 * @retval None
<> 144:ef7eb2e8f9f7 274 */
AnnaBridge 187:0387e8f68319 275 #define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
<> 144:ef7eb2e8f9f7 279 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
<> 144:ef7eb2e8f9f7 280 * @note TIM3_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 281 * @retval None
<> 144:ef7eb2e8f9f7 282 */
AnnaBridge 187:0387e8f68319 283 #define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
<> 144:ef7eb2e8f9f7 287 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
<> 144:ef7eb2e8f9f7 288 * @note TIM4_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 289 * @retval None
<> 144:ef7eb2e8f9f7 290 */
AnnaBridge 187:0387e8f68319 291 #define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
<> 144:ef7eb2e8f9f7 295 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
<> 144:ef7eb2e8f9f7 296 * @note TIM4_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 297 * @retval None
<> 144:ef7eb2e8f9f7 298 */
AnnaBridge 187:0387e8f68319 299 #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
<> 144:ef7eb2e8f9f7 305 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
<> 144:ef7eb2e8f9f7 306 * @retval None
<> 144:ef7eb2e8f9f7 307 */
AnnaBridge 187:0387e8f68319 308 #define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /**
<> 144:ef7eb2e8f9f7 311 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
<> 144:ef7eb2e8f9f7 312 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
<> 144:ef7eb2e8f9f7 313 * @retval None
<> 144:ef7eb2e8f9f7 314 */
AnnaBridge 187:0387e8f68319 315 #define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
<> 144:ef7eb2e8f9f7 319 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
<> 144:ef7eb2e8f9f7 320 * @retval None
<> 144:ef7eb2e8f9f7 321 */
AnnaBridge 187:0387e8f68319 322 #define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
AnnaBridge 187:0387e8f68319 323
<> 144:ef7eb2e8f9f7 324 #endif
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /**
AnnaBridge 187:0387e8f68319 327 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
AnnaBridge 187:0387e8f68319 328 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
AnnaBridge 187:0387e8f68319 329 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
<> 144:ef7eb2e8f9f7 330 * on 100-pin and 144-pin packages, no need for remapping).
<> 144:ef7eb2e8f9f7 331 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
<> 144:ef7eb2e8f9f7 332 * @retval None
<> 144:ef7eb2e8f9f7 333 */
AnnaBridge 187:0387e8f68319 334 #define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
AnnaBridge 187:0387e8f68319 337 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
AnnaBridge 187:0387e8f68319 338 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
AnnaBridge 187:0387e8f68319 339 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
<> 144:ef7eb2e8f9f7 340 * on 100-pin and 144-pin packages, no need for remapping).
<> 144:ef7eb2e8f9f7 341 * @note DISABLE: No remapping of PD0 and PD1
<> 144:ef7eb2e8f9f7 342 * @retval None
<> 144:ef7eb2e8f9f7 343 */
AnnaBridge 187:0387e8f68319 344 #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @brief Enable the remapping of TIM5CH4.
<> 144:ef7eb2e8f9f7 349 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
<> 144:ef7eb2e8f9f7 350 * @note This function is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 351 * @retval None
<> 144:ef7eb2e8f9f7 352 */
AnnaBridge 187:0387e8f68319 353 #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @brief Disable the remapping of TIM5CH4.
<> 144:ef7eb2e8f9f7 357 * @note DISABLE: TIM5_CH4 is connected to PA3
<> 144:ef7eb2e8f9f7 358 * @note This function is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 359 * @retval None
<> 144:ef7eb2e8f9f7 360 */
AnnaBridge 187:0387e8f68319 361 #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
<> 144:ef7eb2e8f9f7 362 #endif
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 #if defined(AFIO_MAPR_ETH_REMAP)
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @brief Enable the remapping of Ethernet MAC connections with the PHY.
<> 144:ef7eb2e8f9f7 367 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
<> 144:ef7eb2e8f9f7 368 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 369 * @retval None
<> 144:ef7eb2e8f9f7 370 */
AnnaBridge 187:0387e8f68319 371 #define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief Disable the remapping of Ethernet MAC connections with the PHY.
<> 144:ef7eb2e8f9f7 375 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
<> 144:ef7eb2e8f9f7 376 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 377 * @retval None
<> 144:ef7eb2e8f9f7 378 */
AnnaBridge 187:0387e8f68319 379 #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
<> 144:ef7eb2e8f9f7 380 #endif
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 #if defined(AFIO_MAPR_CAN2_REMAP)
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
<> 144:ef7eb2e8f9f7 386 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
<> 144:ef7eb2e8f9f7 387 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 388 * @retval None
<> 144:ef7eb2e8f9f7 389 */
AnnaBridge 187:0387e8f68319 390 #define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /**
<> 144:ef7eb2e8f9f7 393 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
<> 144:ef7eb2e8f9f7 394 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
<> 144:ef7eb2e8f9f7 395 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 396 * @retval None
<> 144:ef7eb2e8f9f7 397 */
AnnaBridge 187:0387e8f68319 398 #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
<> 144:ef7eb2e8f9f7 399 #endif
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #if defined(AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
<> 144:ef7eb2e8f9f7 404 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
<> 144:ef7eb2e8f9f7 405 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 406 * @retval None
<> 144:ef7eb2e8f9f7 407 */
AnnaBridge 187:0387e8f68319 408 #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
<> 144:ef7eb2e8f9f7 412 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
<> 144:ef7eb2e8f9f7 413 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 414 * @retval None
<> 144:ef7eb2e8f9f7 415 */
AnnaBridge 187:0387e8f68319 416 #define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 417 #endif
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 421 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
<> 144:ef7eb2e8f9f7 422 * @retval None
<> 144:ef7eb2e8f9f7 423 */
AnnaBridge 187:0387e8f68319 424 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 428 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
<> 144:ef7eb2e8f9f7 429 * @retval None
<> 144:ef7eb2e8f9f7 430 */
AnnaBridge 187:0387e8f68319 431 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 435 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
<> 144:ef7eb2e8f9f7 436 * @retval None
<> 144:ef7eb2e8f9f7 437 */
AnnaBridge 187:0387e8f68319 438 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 442 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
<> 144:ef7eb2e8f9f7 443 * @retval None
<> 144:ef7eb2e8f9f7 444 */
AnnaBridge 187:0387e8f68319 445 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 451 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
<> 144:ef7eb2e8f9f7 452 * @retval None
<> 144:ef7eb2e8f9f7 453 */
AnnaBridge 187:0387e8f68319 454 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 458 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
<> 144:ef7eb2e8f9f7 459 * @retval None
<> 144:ef7eb2e8f9f7 460 */
AnnaBridge 187:0387e8f68319 461 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 462 #endif
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 468 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
<> 144:ef7eb2e8f9f7 469 * @retval None
<> 144:ef7eb2e8f9f7 470 */
AnnaBridge 187:0387e8f68319 471 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /**
<> 144:ef7eb2e8f9f7 474 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 475 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
<> 144:ef7eb2e8f9f7 476 * @retval None
<> 144:ef7eb2e8f9f7 477 */
AnnaBridge 187:0387e8f68319 478 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 479 #endif
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @brief Enable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 483 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
<> 144:ef7eb2e8f9f7 484 * @retval None
<> 144:ef7eb2e8f9f7 485 */
AnnaBridge 187:0387e8f68319 486 #define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Enable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 490 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
<> 144:ef7eb2e8f9f7 491 * @retval None
<> 144:ef7eb2e8f9f7 492 */
AnnaBridge 187:0387e8f68319 493 #define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @brief Enable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 497 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
<> 144:ef7eb2e8f9f7 498 * @retval None
<> 144:ef7eb2e8f9f7 499 */
AnnaBridge 187:0387e8f68319 500
AnnaBridge 187:0387e8f68319 501 #define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief Disable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 505 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
<> 144:ef7eb2e8f9f7 506 * @retval None
<> 144:ef7eb2e8f9f7 507 */
AnnaBridge 187:0387e8f68319 508 #define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 #if defined(AFIO_MAPR_SPI3_REMAP)
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
<> 144:ef7eb2e8f9f7 514 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
<> 144:ef7eb2e8f9f7 515 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 516 * @retval None
<> 144:ef7eb2e8f9f7 517 */
AnnaBridge 187:0387e8f68319 518 #define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /**
<> 144:ef7eb2e8f9f7 521 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
<> 144:ef7eb2e8f9f7 522 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
<> 144:ef7eb2e8f9f7 523 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 524 * @retval None
<> 144:ef7eb2e8f9f7 525 */
AnnaBridge 187:0387e8f68319 526 #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
<> 144:ef7eb2e8f9f7 527 #endif
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @brief Control of TIM2_ITR1 internal mapping.
<> 144:ef7eb2e8f9f7 533 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
<> 144:ef7eb2e8f9f7 534 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 535 * @retval None
<> 144:ef7eb2e8f9f7 536 */
AnnaBridge 187:0387e8f68319 537 #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @brief Control of TIM2_ITR1 internal mapping.
<> 144:ef7eb2e8f9f7 541 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
<> 144:ef7eb2e8f9f7 542 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 543 * @retval None
<> 144:ef7eb2e8f9f7 544 */
AnnaBridge 187:0387e8f68319 545 #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
<> 144:ef7eb2e8f9f7 546 #endif
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 552 * @note ENABLE: PTP_PPS is output on PB5 pin.
<> 144:ef7eb2e8f9f7 553 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 554 * @retval None
<> 144:ef7eb2e8f9f7 555 */
AnnaBridge 187:0387e8f68319 556 #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /**
<> 144:ef7eb2e8f9f7 559 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 560 * @note DISABLE: PTP_PPS not output on PB5 pin.
<> 144:ef7eb2e8f9f7 561 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 562 * @retval None
<> 144:ef7eb2e8f9f7 563 */
AnnaBridge 187:0387e8f68319 564 #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
<> 144:ef7eb2e8f9f7 565 #endif
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 #if defined(AFIO_MAPR2_TIM9_REMAP)
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
<> 144:ef7eb2e8f9f7 571 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
<> 144:ef7eb2e8f9f7 572 * @retval None
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /**
<> 144:ef7eb2e8f9f7 577 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
<> 144:ef7eb2e8f9f7 578 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
<> 144:ef7eb2e8f9f7 579 * @retval None
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
<> 144:ef7eb2e8f9f7 582 #endif
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 #if defined(AFIO_MAPR2_TIM10_REMAP)
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @brief Enable the remapping of TIM10_CH1.
<> 144:ef7eb2e8f9f7 588 * @note ENABLE: Remap (TIM10_CH1 on PF6).
<> 144:ef7eb2e8f9f7 589 * @retval None
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /**
<> 144:ef7eb2e8f9f7 594 * @brief Disable the remapping of TIM10_CH1.
<> 144:ef7eb2e8f9f7 595 * @note DISABLE: No remap (TIM10_CH1 on PB8).
<> 144:ef7eb2e8f9f7 596 * @retval None
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
<> 144:ef7eb2e8f9f7 599 #endif
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 #if defined(AFIO_MAPR2_TIM11_REMAP)
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @brief Enable the remapping of TIM11_CH1.
<> 144:ef7eb2e8f9f7 604 * @note ENABLE: Remap (TIM11_CH1 on PF7).
<> 144:ef7eb2e8f9f7 605 * @retval None
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /**
<> 144:ef7eb2e8f9f7 610 * @brief Disable the remapping of TIM11_CH1.
<> 144:ef7eb2e8f9f7 611 * @note DISABLE: No remap (TIM11_CH1 on PB9).
<> 144:ef7eb2e8f9f7 612 * @retval None
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
<> 144:ef7eb2e8f9f7 615 #endif
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 #if defined(AFIO_MAPR2_TIM13_REMAP)
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /**
<> 144:ef7eb2e8f9f7 620 * @brief Enable the remapping of TIM13_CH1.
<> 144:ef7eb2e8f9f7 621 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
<> 144:ef7eb2e8f9f7 622 * @retval None
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624 #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /**
<> 144:ef7eb2e8f9f7 627 * @brief Disable the remapping of TIM13_CH1.
<> 144:ef7eb2e8f9f7 628 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
<> 144:ef7eb2e8f9f7 629 * @retval None
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
<> 144:ef7eb2e8f9f7 632 #endif
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 #if defined(AFIO_MAPR2_TIM14_REMAP)
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @brief Enable the remapping of TIM14_CH1.
<> 144:ef7eb2e8f9f7 638 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
<> 144:ef7eb2e8f9f7 639 * @retval None
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641 #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /**
<> 144:ef7eb2e8f9f7 644 * @brief Disable the remapping of TIM14_CH1.
<> 144:ef7eb2e8f9f7 645 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
<> 144:ef7eb2e8f9f7 646 * @retval None
<> 144:ef7eb2e8f9f7 647 */
<> 144:ef7eb2e8f9f7 648 #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
<> 144:ef7eb2e8f9f7 649 #endif
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /**
<> 144:ef7eb2e8f9f7 654 * @brief Controls the use of the optional FSMC_NADV signal.
<> 144:ef7eb2e8f9f7 655 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
<> 144:ef7eb2e8f9f7 656 * @retval None
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658 #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @brief Controls the use of the optional FSMC_NADV signal.
<> 144:ef7eb2e8f9f7 662 * @note CONNECTED: The NADV signal is connected to the output (default).
<> 144:ef7eb2e8f9f7 663 * @retval None
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
<> 144:ef7eb2e8f9f7 666 #endif
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 #if defined(AFIO_MAPR2_TIM15_REMAP)
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
<> 144:ef7eb2e8f9f7 672 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
<> 144:ef7eb2e8f9f7 673 * @retval None
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675 #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
<> 144:ef7eb2e8f9f7 679 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
<> 144:ef7eb2e8f9f7 680 * @retval None
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682 #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
<> 144:ef7eb2e8f9f7 683 #endif
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 #if defined(AFIO_MAPR2_TIM16_REMAP)
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @brief Enable the remapping of TIM16_CH1.
<> 144:ef7eb2e8f9f7 689 * @note ENABLE: Remap (TIM16_CH1 on PA6).
<> 144:ef7eb2e8f9f7 690 * @retval None
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @brief Disable the remapping of TIM16_CH1.
<> 144:ef7eb2e8f9f7 696 * @note DISABLE: No remap (TIM16_CH1 on PB8).
<> 144:ef7eb2e8f9f7 697 * @retval None
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
<> 144:ef7eb2e8f9f7 700 #endif
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 #if defined(AFIO_MAPR2_TIM17_REMAP)
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /**
<> 144:ef7eb2e8f9f7 705 * @brief Enable the remapping of TIM17_CH1.
<> 144:ef7eb2e8f9f7 706 * @note ENABLE: Remap (TIM17_CH1 on PA7).
<> 144:ef7eb2e8f9f7 707 * @retval None
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /**
<> 144:ef7eb2e8f9f7 712 * @brief Disable the remapping of TIM17_CH1.
<> 144:ef7eb2e8f9f7 713 * @note DISABLE: No remap (TIM17_CH1 on PB9).
<> 144:ef7eb2e8f9f7 714 * @retval None
<> 144:ef7eb2e8f9f7 715 */
<> 144:ef7eb2e8f9f7 716 #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
<> 144:ef7eb2e8f9f7 717 #endif
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #if defined(AFIO_MAPR2_CEC_REMAP)
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @brief Enable the remapping of CEC.
<> 144:ef7eb2e8f9f7 723 * @note ENABLE: Remap (CEC on PB10).
<> 144:ef7eb2e8f9f7 724 * @retval None
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @brief Disable the remapping of CEC.
<> 144:ef7eb2e8f9f7 730 * @note DISABLE: No remap (CEC on PB8).
<> 144:ef7eb2e8f9f7 731 * @retval None
<> 144:ef7eb2e8f9f7 732 */
<> 144:ef7eb2e8f9f7 733 #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
<> 144:ef7eb2e8f9f7 734 #endif
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 740 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
<> 144:ef7eb2e8f9f7 741 * @retval None
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743 #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /**
<> 144:ef7eb2e8f9f7 746 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 747 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
<> 144:ef7eb2e8f9f7 748 * @retval None
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750 #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
<> 144:ef7eb2e8f9f7 751 #endif
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /**
<> 144:ef7eb2e8f9f7 756 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 757 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
<> 144:ef7eb2e8f9f7 758 * @retval None
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760 #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /**
<> 144:ef7eb2e8f9f7 763 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 764 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
<> 144:ef7eb2e8f9f7 765 * @retval None
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767 #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
<> 144:ef7eb2e8f9f7 768 #endif
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 #if defined(AFIO_MAPR2_TIM12_REMAP)
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /**
<> 144:ef7eb2e8f9f7 773 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
<> 144:ef7eb2e8f9f7 774 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
<> 144:ef7eb2e8f9f7 775 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 776 * @retval None
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778 #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /**
<> 144:ef7eb2e8f9f7 781 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
<> 144:ef7eb2e8f9f7 782 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
<> 144:ef7eb2e8f9f7 783 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 784 * @retval None
<> 144:ef7eb2e8f9f7 785 */
<> 144:ef7eb2e8f9f7 786 #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
<> 144:ef7eb2e8f9f7 787 #endif
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 #if defined(AFIO_MAPR2_MISC_REMAP)
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /**
<> 144:ef7eb2e8f9f7 792 * @brief Miscellaneous features remapping.
<> 144:ef7eb2e8f9f7 793 * This bit is set and cleared by software. It controls miscellaneous features.
<> 144:ef7eb2e8f9f7 794 * The DMA2 channel 5 interrupt position in the vector table.
<> 144:ef7eb2e8f9f7 795 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
<> 144:ef7eb2e8f9f7 796 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
<> 144:ef7eb2e8f9f7 797 * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
<> 144:ef7eb2e8f9f7 798 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 799 * @retval None
<> 144:ef7eb2e8f9f7 800 */
<> 144:ef7eb2e8f9f7 801 #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /**
<> 144:ef7eb2e8f9f7 804 * @brief Miscellaneous features remapping.
<> 144:ef7eb2e8f9f7 805 * This bit is set and cleared by software. It controls miscellaneous features.
<> 144:ef7eb2e8f9f7 806 * The DMA2 channel 5 interrupt position in the vector table.
<> 144:ef7eb2e8f9f7 807 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
<> 144:ef7eb2e8f9f7 808 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
<> 144:ef7eb2e8f9f7 809 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
<> 144:ef7eb2e8f9f7 810 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 811 * @retval None
<> 144:ef7eb2e8f9f7 812 */
<> 144:ef7eb2e8f9f7 813 #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
<> 144:ef7eb2e8f9f7 814 #endif
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /**
<> 144:ef7eb2e8f9f7 817 * @}
AnnaBridge 187:0387e8f68319 818 */
AnnaBridge 187:0387e8f68319 819
<> 144:ef7eb2e8f9f7 820 /**
<> 144:ef7eb2e8f9f7 821 * @}
<> 144:ef7eb2e8f9f7 822 */
AnnaBridge 187:0387e8f68319 823
<> 144:ef7eb2e8f9f7 824 /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
<> 144:ef7eb2e8f9f7 825 * @{
<> 144:ef7eb2e8f9f7 826 */
<> 144:ef7eb2e8f9f7 827 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
<> 144:ef7eb2e8f9f7 828 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
<> 144:ef7eb2e8f9f7 829 ((__GPIOx__) == (GPIOB))? 1U :\
<> 144:ef7eb2e8f9f7 830 ((__GPIOx__) == (GPIOC))? 2U :3U)
<> 144:ef7eb2e8f9f7 831 #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 832 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
<> 144:ef7eb2e8f9f7 833 ((__GPIOx__) == (GPIOB))? 1U :\
<> 144:ef7eb2e8f9f7 834 ((__GPIOx__) == (GPIOC))? 2U :\
<> 144:ef7eb2e8f9f7 835 ((__GPIOx__) == (GPIOD))? 3U :4U)
<> 144:ef7eb2e8f9f7 836 #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 837 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
<> 144:ef7eb2e8f9f7 838 ((__GPIOx__) == (GPIOB))? 1U :\
<> 144:ef7eb2e8f9f7 839 ((__GPIOx__) == (GPIOC))? 2U :\
<> 144:ef7eb2e8f9f7 840 ((__GPIOx__) == (GPIOD))? 3U :\
<> 144:ef7eb2e8f9f7 841 ((__GPIOx__) == (GPIOE))? 4U :\
<> 144:ef7eb2e8f9f7 842 ((__GPIOx__) == (GPIOF))? 5U :6U)
<> 144:ef7eb2e8f9f7 843 #endif
<> 144:ef7eb2e8f9f7 844
AnnaBridge 187:0387e8f68319 845 #define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
AnnaBridge 187:0387e8f68319 846 tmpreg |= AFIO_MAPR_SWJ_CFG; \
AnnaBridge 187:0387e8f68319 847 tmpreg |= REMAP_PIN; \
AnnaBridge 187:0387e8f68319 848 AFIO->MAPR = tmpreg; \
AnnaBridge 187:0387e8f68319 849 }while(0U)
AnnaBridge 187:0387e8f68319 850
AnnaBridge 187:0387e8f68319 851 #define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
AnnaBridge 187:0387e8f68319 852 tmpreg |= AFIO_MAPR_SWJ_CFG; \
AnnaBridge 187:0387e8f68319 853 tmpreg &= ~REMAP_PIN; \
AnnaBridge 187:0387e8f68319 854 AFIO->MAPR = tmpreg; \
AnnaBridge 187:0387e8f68319 855 }while(0U)
AnnaBridge 187:0387e8f68319 856
AnnaBridge 187:0387e8f68319 857 #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
AnnaBridge 187:0387e8f68319 858 tmpreg &= ~REMAP_PIN_MASK; \
AnnaBridge 187:0387e8f68319 859 tmpreg |= AFIO_MAPR_SWJ_CFG; \
AnnaBridge 187:0387e8f68319 860 tmpreg |= REMAP_PIN; \
AnnaBridge 187:0387e8f68319 861 AFIO->MAPR = tmpreg; \
AnnaBridge 187:0387e8f68319 862 }while(0U)
AnnaBridge 187:0387e8f68319 863
AnnaBridge 187:0387e8f68319 864 #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \
AnnaBridge 187:0387e8f68319 865 tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
AnnaBridge 187:0387e8f68319 866 tmpreg |= DBGAFR_SWJCFG; \
AnnaBridge 187:0387e8f68319 867 AFIO->MAPR = tmpreg; \
AnnaBridge 187:0387e8f68319 868 }while(0U)
AnnaBridge 187:0387e8f68319 869
<> 144:ef7eb2e8f9f7 870 /**
<> 144:ef7eb2e8f9f7 871 * @}
<> 144:ef7eb2e8f9f7 872 */
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 875 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /** @addtogroup GPIOEx_Exported_Functions
<> 144:ef7eb2e8f9f7 878 * @{
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /** @addtogroup GPIOEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 882 * @{
<> 144:ef7eb2e8f9f7 883 */
<> 144:ef7eb2e8f9f7 884 void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
<> 144:ef7eb2e8f9f7 885 void HAL_GPIOEx_EnableEventout(void);
<> 144:ef7eb2e8f9f7 886 void HAL_GPIOEx_DisableEventout(void);
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * @}
AnnaBridge 187:0387e8f68319 890 */
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /**
<> 144:ef7eb2e8f9f7 893 * @}
AnnaBridge 187:0387e8f68319 894 */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @}
AnnaBridge 187:0387e8f68319 898 */
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /**
<> 144:ef7eb2e8f9f7 901 * @}
AnnaBridge 187:0387e8f68319 902 */
AnnaBridge 187:0387e8f68319 903
<> 144:ef7eb2e8f9f7 904 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 905 }
<> 144:ef7eb2e8f9f7 906 #endif
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 #endif /* __STM32F1xx_HAL_GPIO_EX_H */
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/