mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_gpio_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of GPIO HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_GPIO_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_GPIO_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup GPIOEx GPIOEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
<> 144:ef7eb2e8f9f7 66 * @brief This section propose definition to use the Cortex EVENTOUT signal.
<> 144:ef7eb2e8f9f7 67 * @{
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
<> 144:ef7eb2e8f9f7 75 #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
<> 144:ef7eb2e8f9f7 76 #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
<> 144:ef7eb2e8f9f7 77 #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
<> 144:ef7eb2e8f9f7 78 #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
<> 144:ef7eb2e8f9f7 79 #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
<> 144:ef7eb2e8f9f7 80 #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
<> 144:ef7eb2e8f9f7 81 #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
<> 144:ef7eb2e8f9f7 82 #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
<> 144:ef7eb2e8f9f7 83 #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
<> 144:ef7eb2e8f9f7 84 #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
<> 144:ef7eb2e8f9f7 85 #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
<> 144:ef7eb2e8f9f7 86 #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
<> 144:ef7eb2e8f9f7 87 #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
<> 144:ef7eb2e8f9f7 88 #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
<> 144:ef7eb2e8f9f7 89 #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
<> 144:ef7eb2e8f9f7 92 ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
<> 144:ef7eb2e8f9f7 93 ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
<> 144:ef7eb2e8f9f7 94 ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
<> 144:ef7eb2e8f9f7 95 ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
<> 144:ef7eb2e8f9f7 96 ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
<> 144:ef7eb2e8f9f7 97 ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
<> 144:ef7eb2e8f9f7 98 ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
<> 144:ef7eb2e8f9f7 99 ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
<> 144:ef7eb2e8f9f7 100 ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
<> 144:ef7eb2e8f9f7 101 ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
<> 144:ef7eb2e8f9f7 102 ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
<> 144:ef7eb2e8f9f7 103 ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
<> 144:ef7eb2e8f9f7 104 ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
<> 144:ef7eb2e8f9f7 105 ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
<> 144:ef7eb2e8f9f7 106 ((__PIN__) == AFIO_EVENTOUT_PIN_15))
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @}
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
<> 144:ef7eb2e8f9f7 112 * @{
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
<> 144:ef7eb2e8f9f7 116 #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
<> 144:ef7eb2e8f9f7 117 #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
<> 144:ef7eb2e8f9f7 118 #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
<> 144:ef7eb2e8f9f7 119 #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
<> 144:ef7eb2e8f9f7 122 ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
<> 144:ef7eb2e8f9f7 123 ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
<> 144:ef7eb2e8f9f7 124 ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
<> 144:ef7eb2e8f9f7 125 ((__PORT__) == AFIO_EVENTOUT_PORT_E))
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /**
<> 144:ef7eb2e8f9f7 131 * @}
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
<> 144:ef7eb2e8f9f7 135 * @brief This section propose definition to remap the alternate function to some other port/pins.
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
<> 144:ef7eb2e8f9f7 141 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
<> 144:ef7eb2e8f9f7 142 * @retval None
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 #define __HAL_AFIO_REMAP_SPI1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
<> 144:ef7eb2e8f9f7 148 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
<> 144:ef7eb2e8f9f7 149 * @retval None
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 #define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
<> 144:ef7eb2e8f9f7 155 * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
<> 144:ef7eb2e8f9f7 156 * @retval None
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 #define __HAL_AFIO_REMAP_I2C1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /**
<> 144:ef7eb2e8f9f7 161 * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
<> 144:ef7eb2e8f9f7 162 * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
<> 144:ef7eb2e8f9f7 163 * @retval None
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 #define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @brief Enable the remapping of USART1 alternate function TX and RX.
<> 144:ef7eb2e8f9f7 169 * @note ENABLE: Remap (TX/PB6, RX/PB7)
<> 144:ef7eb2e8f9f7 170 * @retval None
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 #define __HAL_AFIO_REMAP_USART1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @brief Disable the remapping of USART1 alternate function TX and RX.
<> 144:ef7eb2e8f9f7 176 * @note DISABLE: No remap (TX/PA9, RX/PA10)
<> 144:ef7eb2e8f9f7 177 * @retval None
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 #define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 183 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
<> 144:ef7eb2e8f9f7 184 * @retval None
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 #define __HAL_AFIO_REMAP_USART2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 190 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
<> 144:ef7eb2e8f9f7 191 * @retval None
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 #define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 197 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
<> 144:ef7eb2e8f9f7 198 * @retval None
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 #define __HAL_AFIO_REMAP_USART3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 204 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
<> 144:ef7eb2e8f9f7 205 * @retval None
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 #define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP)
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
<> 144:ef7eb2e8f9f7 211 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
<> 144:ef7eb2e8f9f7 212 * @retval None
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP)
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
<> 144:ef7eb2e8f9f7 218 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
<> 144:ef7eb2e8f9f7 219 * @retval None
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #define __HAL_AFIO_REMAP_TIM1_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
<> 144:ef7eb2e8f9f7 225 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
<> 144:ef7eb2e8f9f7 226 * @retval None
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 #define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP)
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
<> 144:ef7eb2e8f9f7 232 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
<> 144:ef7eb2e8f9f7 233 * @retval None
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 #define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP)
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 239 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
<> 144:ef7eb2e8f9f7 240 * @retval None
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 #define __HAL_AFIO_REMAP_TIM2_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 246 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
<> 144:ef7eb2e8f9f7 247 * @retval None
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2)
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 253 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
<> 144:ef7eb2e8f9f7 254 * @retval None
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1)
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
<> 144:ef7eb2e8f9f7 260 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
<> 144:ef7eb2e8f9f7 261 * @retval None
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 #define __HAL_AFIO_REMAP_TIM2_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP)
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
<> 144:ef7eb2e8f9f7 267 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
<> 144:ef7eb2e8f9f7 268 * @note TIM3_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 269 * @retval None
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 #define __HAL_AFIO_REMAP_TIM3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
<> 144:ef7eb2e8f9f7 275 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
<> 144:ef7eb2e8f9f7 276 * @note TIM3_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 277 * @retval None
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 #define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP)
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
<> 144:ef7eb2e8f9f7 283 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
<> 144:ef7eb2e8f9f7 284 * @note TIM3_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 285 * @retval None
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 #define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP)
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
<> 144:ef7eb2e8f9f7 291 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
<> 144:ef7eb2e8f9f7 292 * @note TIM4_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 293 * @retval None
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 #define __HAL_AFIO_REMAP_TIM4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
<> 144:ef7eb2e8f9f7 299 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
<> 144:ef7eb2e8f9f7 300 * @note TIM4_ETR on PE0 is not re-mapped.
<> 144:ef7eb2e8f9f7 301 * @retval None
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
<> 144:ef7eb2e8f9f7 309 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
<> 144:ef7eb2e8f9f7 310 * @retval None
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 #define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1)
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
<> 144:ef7eb2e8f9f7 316 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
<> 144:ef7eb2e8f9f7 317 * @retval None
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 #define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2)
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
<> 144:ef7eb2e8f9f7 323 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
<> 144:ef7eb2e8f9f7 324 * @retval None
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 #define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3)
<> 144:ef7eb2e8f9f7 327 #endif
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
<> 144:ef7eb2e8f9f7 331 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
<> 144:ef7eb2e8f9f7 332 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
<> 144:ef7eb2e8f9f7 333 * on 100-pin and 144-pin packages, no need for remapping).
<> 144:ef7eb2e8f9f7 334 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
<> 144:ef7eb2e8f9f7 335 * @retval None
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 #define __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /**
<> 144:ef7eb2e8f9f7 340 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
<> 144:ef7eb2e8f9f7 341 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
<> 144:ef7eb2e8f9f7 342 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
<> 144:ef7eb2e8f9f7 343 * on 100-pin and 144-pin packages, no need for remapping).
<> 144:ef7eb2e8f9f7 344 * @note DISABLE: No remapping of PD0 and PD1
<> 144:ef7eb2e8f9f7 345 * @retval None
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 #define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @brief Enable the remapping of TIM5CH4.
<> 144:ef7eb2e8f9f7 352 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
<> 144:ef7eb2e8f9f7 353 * @note This function is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 354 * @retval None
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @brief Disable the remapping of TIM5CH4.
<> 144:ef7eb2e8f9f7 360 * @note DISABLE: TIM5_CH4 is connected to PA3
<> 144:ef7eb2e8f9f7 361 * @note This function is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 362 * @retval None
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
<> 144:ef7eb2e8f9f7 365 #endif
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #if defined(AFIO_MAPR_ETH_REMAP)
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @brief Enable the remapping of Ethernet MAC connections with the PHY.
<> 144:ef7eb2e8f9f7 370 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
<> 144:ef7eb2e8f9f7 371 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 372 * @retval None
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374 #define __HAL_AFIO_REMAP_ETH_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 * @brief Disable the remapping of Ethernet MAC connections with the PHY.
<> 144:ef7eb2e8f9f7 378 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
<> 144:ef7eb2e8f9f7 379 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 380 * @retval None
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 #define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
<> 144:ef7eb2e8f9f7 383 #endif
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 #if defined(AFIO_MAPR_CAN2_REMAP)
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
<> 144:ef7eb2e8f9f7 389 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
<> 144:ef7eb2e8f9f7 390 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 391 * @retval None
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 #define __HAL_AFIO_REMAP_CAN2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
<> 144:ef7eb2e8f9f7 397 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
<> 144:ef7eb2e8f9f7 398 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 399 * @retval None
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 #define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
<> 144:ef7eb2e8f9f7 402 #endif
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 #if defined(AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
<> 144:ef7eb2e8f9f7 407 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
<> 144:ef7eb2e8f9f7 408 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 409 * @retval None
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /**
<> 144:ef7eb2e8f9f7 414 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
<> 144:ef7eb2e8f9f7 415 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
<> 144:ef7eb2e8f9f7 416 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 417 * @retval None
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 #define __HAL_AFIO_ETH_MII() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 420 #endif
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 424 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
<> 144:ef7eb2e8f9f7 425 * @retval None
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 431 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
<> 144:ef7eb2e8f9f7 432 * @retval None
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /**
<> 144:ef7eb2e8f9f7 437 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 438 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
<> 144:ef7eb2e8f9f7 439 * @retval None
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /**
<> 144:ef7eb2e8f9f7 444 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 445 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
<> 144:ef7eb2e8f9f7 446 * @retval None
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 454 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
<> 144:ef7eb2e8f9f7 455 * @retval None
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
<> 144:ef7eb2e8f9f7 461 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
<> 144:ef7eb2e8f9f7 462 * @retval None
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
<> 144:ef7eb2e8f9f7 465 #endif
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /**
<> 144:ef7eb2e8f9f7 470 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 471 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
<> 144:ef7eb2e8f9f7 472 * @retval None
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 478 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
<> 144:ef7eb2e8f9f7 479 * @retval None
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
<> 144:ef7eb2e8f9f7 482 #endif
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @brief Enable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 486 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
<> 144:ef7eb2e8f9f7 487 * @retval None
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489 #define __HAL_AFIO_REMAP_SWJ_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET)
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /**
<> 144:ef7eb2e8f9f7 492 * @brief Enable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 493 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
<> 144:ef7eb2e8f9f7 494 * @retval None
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 #define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST)
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @brief Enable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 500 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
<> 144:ef7eb2e8f9f7 501 * @retval None
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503 #define __HAL_AFIO_REMAP_SWJ_NOJTAG() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /**
<> 144:ef7eb2e8f9f7 506 * @brief Disable the Serial wire JTAG configuration
<> 144:ef7eb2e8f9f7 507 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
<> 144:ef7eb2e8f9f7 508 * @retval None
<> 144:ef7eb2e8f9f7 509 */
<> 144:ef7eb2e8f9f7 510 #define __HAL_AFIO_REMAP_SWJ_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE)
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 #if defined(AFIO_MAPR_SPI3_REMAP)
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /**
<> 144:ef7eb2e8f9f7 515 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
<> 144:ef7eb2e8f9f7 516 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
<> 144:ef7eb2e8f9f7 517 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 518 * @retval None
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 #define __HAL_AFIO_REMAP_SPI3_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
<> 144:ef7eb2e8f9f7 524 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
<> 144:ef7eb2e8f9f7 525 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 526 * @retval None
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 #define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
<> 144:ef7eb2e8f9f7 529 #endif
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief Control of TIM2_ITR1 internal mapping.
<> 144:ef7eb2e8f9f7 535 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
<> 144:ef7eb2e8f9f7 536 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 537 * @retval None
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 #define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @brief Control of TIM2_ITR1 internal mapping.
<> 144:ef7eb2e8f9f7 543 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
<> 144:ef7eb2e8f9f7 544 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 545 * @retval None
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 #define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
<> 144:ef7eb2e8f9f7 548 #endif
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /**
<> 144:ef7eb2e8f9f7 553 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 554 * @note ENABLE: PTP_PPS is output on PB5 pin.
<> 144:ef7eb2e8f9f7 555 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 556 * @retval None
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
<> 144:ef7eb2e8f9f7 562 * @note DISABLE: PTP_PPS not output on PB5 pin.
<> 144:ef7eb2e8f9f7 563 * @note This bit is available only in connectivity line devices and is reserved otherwise.
<> 144:ef7eb2e8f9f7 564 * @retval None
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
<> 144:ef7eb2e8f9f7 567 #endif
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 #if defined(AFIO_MAPR2_TIM9_REMAP)
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
<> 144:ef7eb2e8f9f7 573 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
<> 144:ef7eb2e8f9f7 574 * @retval None
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /**
<> 144:ef7eb2e8f9f7 579 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
<> 144:ef7eb2e8f9f7 580 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
<> 144:ef7eb2e8f9f7 581 * @retval None
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583 #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
<> 144:ef7eb2e8f9f7 584 #endif
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 #if defined(AFIO_MAPR2_TIM10_REMAP)
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @brief Enable the remapping of TIM10_CH1.
<> 144:ef7eb2e8f9f7 590 * @note ENABLE: Remap (TIM10_CH1 on PF6).
<> 144:ef7eb2e8f9f7 591 * @retval None
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593 #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @brief Disable the remapping of TIM10_CH1.
<> 144:ef7eb2e8f9f7 597 * @note DISABLE: No remap (TIM10_CH1 on PB8).
<> 144:ef7eb2e8f9f7 598 * @retval None
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
<> 144:ef7eb2e8f9f7 601 #endif
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 #if defined(AFIO_MAPR2_TIM11_REMAP)
<> 144:ef7eb2e8f9f7 604 /**
<> 144:ef7eb2e8f9f7 605 * @brief Enable the remapping of TIM11_CH1.
<> 144:ef7eb2e8f9f7 606 * @note ENABLE: Remap (TIM11_CH1 on PF7).
<> 144:ef7eb2e8f9f7 607 * @retval None
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @brief Disable the remapping of TIM11_CH1.
<> 144:ef7eb2e8f9f7 613 * @note DISABLE: No remap (TIM11_CH1 on PB9).
<> 144:ef7eb2e8f9f7 614 * @retval None
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
<> 144:ef7eb2e8f9f7 617 #endif
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 #if defined(AFIO_MAPR2_TIM13_REMAP)
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @brief Enable the remapping of TIM13_CH1.
<> 144:ef7eb2e8f9f7 623 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
<> 144:ef7eb2e8f9f7 624 * @retval None
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626 #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @brief Disable the remapping of TIM13_CH1.
<> 144:ef7eb2e8f9f7 630 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
<> 144:ef7eb2e8f9f7 631 * @retval None
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
<> 144:ef7eb2e8f9f7 634 #endif
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 #if defined(AFIO_MAPR2_TIM14_REMAP)
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @brief Enable the remapping of TIM14_CH1.
<> 144:ef7eb2e8f9f7 640 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
<> 144:ef7eb2e8f9f7 641 * @retval None
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643 #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /**
<> 144:ef7eb2e8f9f7 646 * @brief Disable the remapping of TIM14_CH1.
<> 144:ef7eb2e8f9f7 647 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
<> 144:ef7eb2e8f9f7 648 * @retval None
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650 #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
<> 144:ef7eb2e8f9f7 651 #endif
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @brief Controls the use of the optional FSMC_NADV signal.
<> 144:ef7eb2e8f9f7 657 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
<> 144:ef7eb2e8f9f7 658 * @retval None
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /**
<> 144:ef7eb2e8f9f7 663 * @brief Controls the use of the optional FSMC_NADV signal.
<> 144:ef7eb2e8f9f7 664 * @note CONNECTED: The NADV signal is connected to the output (default).
<> 144:ef7eb2e8f9f7 665 * @retval None
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
<> 144:ef7eb2e8f9f7 668 #endif
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 #if defined(AFIO_MAPR2_TIM15_REMAP)
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
<> 144:ef7eb2e8f9f7 674 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
<> 144:ef7eb2e8f9f7 675 * @retval None
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677 #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
<> 144:ef7eb2e8f9f7 681 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
<> 144:ef7eb2e8f9f7 682 * @retval None
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684 #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
<> 144:ef7eb2e8f9f7 685 #endif
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 #if defined(AFIO_MAPR2_TIM16_REMAP)
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /**
<> 144:ef7eb2e8f9f7 690 * @brief Enable the remapping of TIM16_CH1.
<> 144:ef7eb2e8f9f7 691 * @note ENABLE: Remap (TIM16_CH1 on PA6).
<> 144:ef7eb2e8f9f7 692 * @retval None
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @brief Disable the remapping of TIM16_CH1.
<> 144:ef7eb2e8f9f7 698 * @note DISABLE: No remap (TIM16_CH1 on PB8).
<> 144:ef7eb2e8f9f7 699 * @retval None
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701 #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
<> 144:ef7eb2e8f9f7 702 #endif
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 #if defined(AFIO_MAPR2_TIM17_REMAP)
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @brief Enable the remapping of TIM17_CH1.
<> 144:ef7eb2e8f9f7 708 * @note ENABLE: Remap (TIM17_CH1 on PA7).
<> 144:ef7eb2e8f9f7 709 * @retval None
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /**
<> 144:ef7eb2e8f9f7 714 * @brief Disable the remapping of TIM17_CH1.
<> 144:ef7eb2e8f9f7 715 * @note DISABLE: No remap (TIM17_CH1 on PB9).
<> 144:ef7eb2e8f9f7 716 * @retval None
<> 144:ef7eb2e8f9f7 717 */
<> 144:ef7eb2e8f9f7 718 #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
<> 144:ef7eb2e8f9f7 719 #endif
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 #if defined(AFIO_MAPR2_CEC_REMAP)
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /**
<> 144:ef7eb2e8f9f7 724 * @brief Enable the remapping of CEC.
<> 144:ef7eb2e8f9f7 725 * @note ENABLE: Remap (CEC on PB10).
<> 144:ef7eb2e8f9f7 726 * @retval None
<> 144:ef7eb2e8f9f7 727 */
<> 144:ef7eb2e8f9f7 728 #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /**
<> 144:ef7eb2e8f9f7 731 * @brief Disable the remapping of CEC.
<> 144:ef7eb2e8f9f7 732 * @note DISABLE: No remap (CEC on PB8).
<> 144:ef7eb2e8f9f7 733 * @retval None
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735 #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
<> 144:ef7eb2e8f9f7 736 #endif
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /**
<> 144:ef7eb2e8f9f7 741 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 742 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
<> 144:ef7eb2e8f9f7 743 * @retval None
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745 #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 749 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
<> 144:ef7eb2e8f9f7 750 * @retval None
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752 #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
<> 144:ef7eb2e8f9f7 753 #endif
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /**
<> 144:ef7eb2e8f9f7 758 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 759 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
<> 144:ef7eb2e8f9f7 760 * @retval None
<> 144:ef7eb2e8f9f7 761 */
<> 144:ef7eb2e8f9f7 762 #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /**
<> 144:ef7eb2e8f9f7 765 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
<> 144:ef7eb2e8f9f7 766 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
<> 144:ef7eb2e8f9f7 767 * @retval None
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769 #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
<> 144:ef7eb2e8f9f7 770 #endif
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 #if defined(AFIO_MAPR2_TIM12_REMAP)
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /**
<> 144:ef7eb2e8f9f7 775 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
<> 144:ef7eb2e8f9f7 776 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
<> 144:ef7eb2e8f9f7 777 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 778 * @retval None
<> 144:ef7eb2e8f9f7 779 */
<> 144:ef7eb2e8f9f7 780 #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /**
<> 144:ef7eb2e8f9f7 783 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
<> 144:ef7eb2e8f9f7 784 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
<> 144:ef7eb2e8f9f7 785 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 786 * @retval None
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788 #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
<> 144:ef7eb2e8f9f7 789 #endif
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 #if defined(AFIO_MAPR2_MISC_REMAP)
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /**
<> 144:ef7eb2e8f9f7 794 * @brief Miscellaneous features remapping.
<> 144:ef7eb2e8f9f7 795 * This bit is set and cleared by software. It controls miscellaneous features.
<> 144:ef7eb2e8f9f7 796 * The DMA2 channel 5 interrupt position in the vector table.
<> 144:ef7eb2e8f9f7 797 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
<> 144:ef7eb2e8f9f7 798 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
<> 144:ef7eb2e8f9f7 799 * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
<> 144:ef7eb2e8f9f7 800 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 801 * @retval None
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /**
<> 144:ef7eb2e8f9f7 806 * @brief Miscellaneous features remapping.
<> 144:ef7eb2e8f9f7 807 * This bit is set and cleared by software. It controls miscellaneous features.
<> 144:ef7eb2e8f9f7 808 * The DMA2 channel 5 interrupt position in the vector table.
<> 144:ef7eb2e8f9f7 809 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
<> 144:ef7eb2e8f9f7 810 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
<> 144:ef7eb2e8f9f7 811 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
<> 144:ef7eb2e8f9f7 812 * @note This bit is available only in high density value line devices.
<> 144:ef7eb2e8f9f7 813 * @retval None
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815 #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
<> 144:ef7eb2e8f9f7 816 #endif
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /**
<> 144:ef7eb2e8f9f7 819 * @}
<> 144:ef7eb2e8f9f7 820 */
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /**
<> 144:ef7eb2e8f9f7 823 * @}
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
<> 144:ef7eb2e8f9f7 827 * @{
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
<> 144:ef7eb2e8f9f7 830 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
<> 144:ef7eb2e8f9f7 831 ((__GPIOx__) == (GPIOB))? 1U :\
<> 144:ef7eb2e8f9f7 832 ((__GPIOx__) == (GPIOC))? 2U :3U)
<> 144:ef7eb2e8f9f7 833 #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 834 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
<> 144:ef7eb2e8f9f7 835 ((__GPIOx__) == (GPIOB))? 1U :\
<> 144:ef7eb2e8f9f7 836 ((__GPIOx__) == (GPIOC))? 2U :\
<> 144:ef7eb2e8f9f7 837 ((__GPIOx__) == (GPIOD))? 3U :4U)
<> 144:ef7eb2e8f9f7 838 #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 839 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
<> 144:ef7eb2e8f9f7 840 ((__GPIOx__) == (GPIOB))? 1U :\
<> 144:ef7eb2e8f9f7 841 ((__GPIOx__) == (GPIOC))? 2U :\
<> 144:ef7eb2e8f9f7 842 ((__GPIOx__) == (GPIOD))? 3U :\
<> 144:ef7eb2e8f9f7 843 ((__GPIOx__) == (GPIOE))? 4U :\
<> 144:ef7eb2e8f9f7 844 ((__GPIOx__) == (GPIOF))? 5U :6U)
<> 144:ef7eb2e8f9f7 845 #endif
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /**
<> 144:ef7eb2e8f9f7 848 * @}
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 852 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /** @addtogroup GPIOEx_Exported_Functions
<> 144:ef7eb2e8f9f7 855 * @{
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /** @addtogroup GPIOEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 859 * @{
<> 144:ef7eb2e8f9f7 860 */
<> 144:ef7eb2e8f9f7 861 void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
<> 144:ef7eb2e8f9f7 862 void HAL_GPIOEx_EnableEventout(void);
<> 144:ef7eb2e8f9f7 863 void HAL_GPIOEx_DisableEventout(void);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /**
<> 144:ef7eb2e8f9f7 866 * @}
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @}
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /**
<> 144:ef7eb2e8f9f7 874 * @}
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @}
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 #endif
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 #endif /* __STM32F1xx_HAL_GPIO_EX_H */
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/