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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_dma.h
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief Header file of DMA LL module.
<> 156:95d6b41a828b 6 ******************************************************************************
<> 156:95d6b41a828b 7 * @attention
<> 156:95d6b41a828b 8 *
<> 156:95d6b41a828b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 12 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 14 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 17 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 19 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 20 * without specific prior written permission.
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 156:95d6b41a828b 35
<> 156:95d6b41a828b 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 156:95d6b41a828b 37 #ifndef __STM32F0xx_LL_DMA_H
<> 156:95d6b41a828b 38 #define __STM32F0xx_LL_DMA_H
<> 156:95d6b41a828b 39
<> 156:95d6b41a828b 40 #ifdef __cplusplus
<> 156:95d6b41a828b 41 extern "C" {
<> 156:95d6b41a828b 42 #endif
<> 156:95d6b41a828b 43
<> 156:95d6b41a828b 44 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 45 #include "stm32f0xx.h"
<> 156:95d6b41a828b 46
<> 156:95d6b41a828b 47 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 48 * @{
<> 156:95d6b41a828b 49 */
<> 156:95d6b41a828b 50
<> 156:95d6b41a828b 51 #if defined (DMA1) || defined (DMA2)
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 /** @defgroup DMA_LL DMA
<> 156:95d6b41a828b 54 * @{
<> 156:95d6b41a828b 55 */
<> 156:95d6b41a828b 56
<> 156:95d6b41a828b 57 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 58 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 59 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
<> 156:95d6b41a828b 60 * @{
<> 156:95d6b41a828b 61 */
<> 156:95d6b41a828b 62 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<> 156:95d6b41a828b 63 static const uint8_t CHANNEL_OFFSET_TAB[] =
<> 156:95d6b41a828b 64 {
<> 156:95d6b41a828b 65 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<> 156:95d6b41a828b 66 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<> 156:95d6b41a828b 67 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<> 156:95d6b41a828b 68 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<> 156:95d6b41a828b 69 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<> 156:95d6b41a828b 70 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 71 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<> 156:95d6b41a828b 72 #endif /*DMA1_Channel6*/
<> 156:95d6b41a828b 73 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 74 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<> 156:95d6b41a828b 75 #endif /*DMA1_Channel7*/
<> 156:95d6b41a828b 76 };
<> 156:95d6b41a828b 77 /**
<> 156:95d6b41a828b 78 * @}
<> 156:95d6b41a828b 79 */
<> 156:95d6b41a828b 80
<> 156:95d6b41a828b 81 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 82 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
<> 156:95d6b41a828b 83 * @{
<> 156:95d6b41a828b 84 */
<> 156:95d6b41a828b 85 /* Define used to get CSELR register offset */
<> 156:95d6b41a828b 86 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
<> 156:95d6b41a828b 87
<> 156:95d6b41a828b 88 /* Defines used for the bit position in the register and perform offsets */
<> 156:95d6b41a828b 89 #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U)
<> 156:95d6b41a828b 90 /**
<> 156:95d6b41a828b 91 * @}
<> 156:95d6b41a828b 92 */
<> 156:95d6b41a828b 93
<> 156:95d6b41a828b 94 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 95 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 96 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
<> 156:95d6b41a828b 97 * @{
<> 156:95d6b41a828b 98 */
<> 156:95d6b41a828b 99 /**
<> 156:95d6b41a828b 100 * @}
<> 156:95d6b41a828b 101 */
<> 156:95d6b41a828b 102 #endif /*USE_FULL_LL_DRIVER*/
<> 156:95d6b41a828b 103
<> 156:95d6b41a828b 104 /* Exported types ------------------------------------------------------------*/
<> 156:95d6b41a828b 105 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 106 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<> 156:95d6b41a828b 107 * @{
<> 156:95d6b41a828b 108 */
<> 156:95d6b41a828b 109 typedef struct
<> 156:95d6b41a828b 110 {
<> 156:95d6b41a828b 111 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<> 156:95d6b41a828b 112 or as Source base address in case of memory to memory transfer direction.
<> 156:95d6b41a828b 113
<> 156:95d6b41a828b 114 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<> 156:95d6b41a828b 115
<> 156:95d6b41a828b 116 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<> 156:95d6b41a828b 117 or as Destination base address in case of memory to memory transfer direction.
<> 156:95d6b41a828b 118
<> 156:95d6b41a828b 119 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<> 156:95d6b41a828b 120
<> 156:95d6b41a828b 121 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 156:95d6b41a828b 122 from memory to memory or from peripheral to memory.
<> 156:95d6b41a828b 123 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<> 156:95d6b41a828b 124
<> 156:95d6b41a828b 125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<> 156:95d6b41a828b 126
<> 156:95d6b41a828b 127 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<> 156:95d6b41a828b 128 This parameter can be a value of @ref DMA_LL_EC_MODE
<> 156:95d6b41a828b 129 @note: The circular buffer mode cannot be used if the memory to memory
<> 156:95d6b41a828b 130 data transfer direction is configured on the selected Channel
<> 156:95d6b41a828b 131
<> 156:95d6b41a828b 132 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<> 156:95d6b41a828b 133
<> 156:95d6b41a828b 134 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<> 156:95d6b41a828b 135 is incremented or not.
<> 156:95d6b41a828b 136 This parameter can be a value of @ref DMA_LL_EC_PERIPH
<> 156:95d6b41a828b 137
<> 156:95d6b41a828b 138 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<> 156:95d6b41a828b 139
<> 156:95d6b41a828b 140 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<> 156:95d6b41a828b 141 is incremented or not.
<> 156:95d6b41a828b 142 This parameter can be a value of @ref DMA_LL_EC_MEMORY
<> 156:95d6b41a828b 143
<> 156:95d6b41a828b 144 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<> 156:95d6b41a828b 145
<> 156:95d6b41a828b 146 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<> 156:95d6b41a828b 147 in case of memory to memory transfer direction.
<> 156:95d6b41a828b 148 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<> 156:95d6b41a828b 149
<> 156:95d6b41a828b 150 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<> 156:95d6b41a828b 151
<> 156:95d6b41a828b 152 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<> 156:95d6b41a828b 153 in case of memory to memory transfer direction.
<> 156:95d6b41a828b 154 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<> 156:95d6b41a828b 155
<> 156:95d6b41a828b 156 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<> 156:95d6b41a828b 157
<> 156:95d6b41a828b 158 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<> 156:95d6b41a828b 159 The data unit is equal to the source buffer configuration set in PeripheralSize
<> 156:95d6b41a828b 160 or MemorySize parameters depending in the transfer direction.
<> 156:95d6b41a828b 161 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<> 156:95d6b41a828b 162
<> 156:95d6b41a828b 163 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<> 156:95d6b41a828b 164 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 165
<> 156:95d6b41a828b 166 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
<> 156:95d6b41a828b 167 This parameter can be a value of @ref DMA_LL_EC_REQUEST
<> 156:95d6b41a828b 168
<> 156:95d6b41a828b 169 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
<> 156:95d6b41a828b 170 #endif
<> 156:95d6b41a828b 171
<> 156:95d6b41a828b 172 uint32_t Priority; /*!< Specifies the channel priority level.
<> 156:95d6b41a828b 173 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<> 156:95d6b41a828b 174
<> 156:95d6b41a828b 175 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<> 156:95d6b41a828b 176
<> 156:95d6b41a828b 177 } LL_DMA_InitTypeDef;
<> 156:95d6b41a828b 178 /**
<> 156:95d6b41a828b 179 * @}
<> 156:95d6b41a828b 180 */
<> 156:95d6b41a828b 181 #endif /*USE_FULL_LL_DRIVER*/
<> 156:95d6b41a828b 182
<> 156:95d6b41a828b 183 /* Exported constants --------------------------------------------------------*/
<> 156:95d6b41a828b 184 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<> 156:95d6b41a828b 185 * @{
<> 156:95d6b41a828b 186 */
<> 156:95d6b41a828b 187 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 156:95d6b41a828b 188 * @brief Flags defines which can be used with LL_DMA_WriteReg function
<> 156:95d6b41a828b 189 * @{
<> 156:95d6b41a828b 190 */
<> 156:95d6b41a828b 191 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
<> 156:95d6b41a828b 192 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
<> 156:95d6b41a828b 193 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
<> 156:95d6b41a828b 194 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
<> 156:95d6b41a828b 195 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
<> 156:95d6b41a828b 196 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
<> 156:95d6b41a828b 197 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
<> 156:95d6b41a828b 198 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
<> 156:95d6b41a828b 199 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
<> 156:95d6b41a828b 200 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
<> 156:95d6b41a828b 201 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
<> 156:95d6b41a828b 202 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
<> 156:95d6b41a828b 203 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
<> 156:95d6b41a828b 204 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
<> 156:95d6b41a828b 205 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
<> 156:95d6b41a828b 206 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
<> 156:95d6b41a828b 207 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
<> 156:95d6b41a828b 208 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
<> 156:95d6b41a828b 209 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
<> 156:95d6b41a828b 210 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
<> 156:95d6b41a828b 211 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 212 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
<> 156:95d6b41a828b 213 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
<> 156:95d6b41a828b 214 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
<> 156:95d6b41a828b 215 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
<> 156:95d6b41a828b 216 #endif
<> 156:95d6b41a828b 217 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 218 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
<> 156:95d6b41a828b 219 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
<> 156:95d6b41a828b 220 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
<> 156:95d6b41a828b 221 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
<> 156:95d6b41a828b 222 #endif
<> 156:95d6b41a828b 223 /**
<> 156:95d6b41a828b 224 * @}
<> 156:95d6b41a828b 225 */
<> 156:95d6b41a828b 226
<> 156:95d6b41a828b 227 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<> 156:95d6b41a828b 228 * @brief Flags defines which can be used with LL_DMA_ReadReg function
<> 156:95d6b41a828b 229 * @{
<> 156:95d6b41a828b 230 */
<> 156:95d6b41a828b 231 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
<> 156:95d6b41a828b 232 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
<> 156:95d6b41a828b 233 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
<> 156:95d6b41a828b 234 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
<> 156:95d6b41a828b 235 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
<> 156:95d6b41a828b 236 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
<> 156:95d6b41a828b 237 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
<> 156:95d6b41a828b 238 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
<> 156:95d6b41a828b 239 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
<> 156:95d6b41a828b 240 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
<> 156:95d6b41a828b 241 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
<> 156:95d6b41a828b 242 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
<> 156:95d6b41a828b 243 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
<> 156:95d6b41a828b 244 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
<> 156:95d6b41a828b 245 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
<> 156:95d6b41a828b 246 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
<> 156:95d6b41a828b 247 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
<> 156:95d6b41a828b 248 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
<> 156:95d6b41a828b 249 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
<> 156:95d6b41a828b 250 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
<> 156:95d6b41a828b 251 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 252 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
<> 156:95d6b41a828b 253 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
<> 156:95d6b41a828b 254 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
<> 156:95d6b41a828b 255 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
<> 156:95d6b41a828b 256 #endif
<> 156:95d6b41a828b 257 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 258 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
<> 156:95d6b41a828b 259 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
<> 156:95d6b41a828b 260 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
<> 156:95d6b41a828b 261 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
<> 156:95d6b41a828b 262 #endif
<> 156:95d6b41a828b 263 /**
<> 156:95d6b41a828b 264 * @}
<> 156:95d6b41a828b 265 */
<> 156:95d6b41a828b 266
<> 156:95d6b41a828b 267 /** @defgroup DMA_LL_EC_IT IT Defines
<> 156:95d6b41a828b 268 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<> 156:95d6b41a828b 269 * @{
<> 156:95d6b41a828b 270 */
<> 156:95d6b41a828b 271 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
<> 156:95d6b41a828b 272 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
<> 156:95d6b41a828b 273 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
<> 156:95d6b41a828b 274 /**
<> 156:95d6b41a828b 275 * @}
<> 156:95d6b41a828b 276 */
<> 156:95d6b41a828b 277
<> 156:95d6b41a828b 278 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<> 156:95d6b41a828b 279 * @{
<> 156:95d6b41a828b 280 */
Anna Bridge 180:96ed750bd169 281 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
Anna Bridge 180:96ed750bd169 282 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
Anna Bridge 180:96ed750bd169 283 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
Anna Bridge 180:96ed750bd169 284 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
Anna Bridge 180:96ed750bd169 285 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
<> 156:95d6b41a828b 286 #if defined(DMA1_Channel6)
Anna Bridge 180:96ed750bd169 287 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
<> 156:95d6b41a828b 288 #endif
<> 156:95d6b41a828b 289 #if defined(DMA1_Channel7)
Anna Bridge 180:96ed750bd169 290 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
<> 156:95d6b41a828b 291 #endif
<> 156:95d6b41a828b 292 #if defined(USE_FULL_LL_DRIVER)
Anna Bridge 180:96ed750bd169 293 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
<> 156:95d6b41a828b 294 #endif /*USE_FULL_LL_DRIVER*/
<> 156:95d6b41a828b 295 /**
<> 156:95d6b41a828b 296 * @}
<> 156:95d6b41a828b 297 */
<> 156:95d6b41a828b 298
<> 156:95d6b41a828b 299 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<> 156:95d6b41a828b 300 * @{
<> 156:95d6b41a828b 301 */
Anna Bridge 180:96ed750bd169 302 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
<> 156:95d6b41a828b 303 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
<> 156:95d6b41a828b 304 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
<> 156:95d6b41a828b 305 /**
<> 156:95d6b41a828b 306 * @}
<> 156:95d6b41a828b 307 */
<> 156:95d6b41a828b 308
<> 156:95d6b41a828b 309 /** @defgroup DMA_LL_EC_MODE Transfer mode
<> 156:95d6b41a828b 310 * @{
<> 156:95d6b41a828b 311 */
Anna Bridge 180:96ed750bd169 312 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
<> 156:95d6b41a828b 313 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
<> 156:95d6b41a828b 314 /**
<> 156:95d6b41a828b 315 * @}
<> 156:95d6b41a828b 316 */
<> 156:95d6b41a828b 317
<> 156:95d6b41a828b 318 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<> 156:95d6b41a828b 319 * @{
<> 156:95d6b41a828b 320 */
<> 156:95d6b41a828b 321 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
Anna Bridge 180:96ed750bd169 322 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
<> 156:95d6b41a828b 323 /**
<> 156:95d6b41a828b 324 * @}
<> 156:95d6b41a828b 325 */
<> 156:95d6b41a828b 326
<> 156:95d6b41a828b 327 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<> 156:95d6b41a828b 328 * @{
<> 156:95d6b41a828b 329 */
<> 156:95d6b41a828b 330 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
Anna Bridge 180:96ed750bd169 331 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
<> 156:95d6b41a828b 332 /**
<> 156:95d6b41a828b 333 * @}
<> 156:95d6b41a828b 334 */
<> 156:95d6b41a828b 335
<> 156:95d6b41a828b 336 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<> 156:95d6b41a828b 337 * @{
<> 156:95d6b41a828b 338 */
Anna Bridge 180:96ed750bd169 339 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
<> 156:95d6b41a828b 340 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
<> 156:95d6b41a828b 341 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
<> 156:95d6b41a828b 342 /**
<> 156:95d6b41a828b 343 * @}
<> 156:95d6b41a828b 344 */
<> 156:95d6b41a828b 345
<> 156:95d6b41a828b 346 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<> 156:95d6b41a828b 347 * @{
<> 156:95d6b41a828b 348 */
Anna Bridge 180:96ed750bd169 349 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
<> 156:95d6b41a828b 350 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
<> 156:95d6b41a828b 351 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
<> 156:95d6b41a828b 352 /**
<> 156:95d6b41a828b 353 * @}
<> 156:95d6b41a828b 354 */
<> 156:95d6b41a828b 355
<> 156:95d6b41a828b 356 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<> 156:95d6b41a828b 357 * @{
<> 156:95d6b41a828b 358 */
Anna Bridge 180:96ed750bd169 359 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
<> 156:95d6b41a828b 360 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
<> 156:95d6b41a828b 361 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
<> 156:95d6b41a828b 362 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
<> 156:95d6b41a828b 363 /**
<> 156:95d6b41a828b 364 * @}
<> 156:95d6b41a828b 365 */
<> 156:95d6b41a828b 366
<> 156:95d6b41a828b 367 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 368 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
<> 156:95d6b41a828b 369 * @{
<> 156:95d6b41a828b 370 */
Anna Bridge 180:96ed750bd169 371 #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */
Anna Bridge 180:96ed750bd169 372 #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */
Anna Bridge 180:96ed750bd169 373 #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */
Anna Bridge 180:96ed750bd169 374 #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */
Anna Bridge 180:96ed750bd169 375 #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */
Anna Bridge 180:96ed750bd169 376 #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */
Anna Bridge 180:96ed750bd169 377 #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */
Anna Bridge 180:96ed750bd169 378 #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */
Anna Bridge 180:96ed750bd169 379 #define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */
Anna Bridge 180:96ed750bd169 380 #define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */
Anna Bridge 180:96ed750bd169 381 #define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */
Anna Bridge 180:96ed750bd169 382 #define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */
Anna Bridge 180:96ed750bd169 383 #define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */
Anna Bridge 180:96ed750bd169 384 #define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */
Anna Bridge 180:96ed750bd169 385 #define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */
Anna Bridge 180:96ed750bd169 386 #define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */
<> 156:95d6b41a828b 387 /**
<> 156:95d6b41a828b 388 * @}
<> 156:95d6b41a828b 389 */
<> 156:95d6b41a828b 390 #endif
<> 156:95d6b41a828b 391
<> 156:95d6b41a828b 392 /**
<> 156:95d6b41a828b 393 * @}
<> 156:95d6b41a828b 394 */
<> 156:95d6b41a828b 395
<> 156:95d6b41a828b 396 /* Exported macro ------------------------------------------------------------*/
<> 156:95d6b41a828b 397 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<> 156:95d6b41a828b 398 * @{
<> 156:95d6b41a828b 399 */
<> 156:95d6b41a828b 400
<> 156:95d6b41a828b 401 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<> 156:95d6b41a828b 402 * @{
<> 156:95d6b41a828b 403 */
<> 156:95d6b41a828b 404 /**
<> 156:95d6b41a828b 405 * @brief Write a value in DMA register
<> 156:95d6b41a828b 406 * @param __INSTANCE__ DMA Instance
<> 156:95d6b41a828b 407 * @param __REG__ Register to be written
<> 156:95d6b41a828b 408 * @param __VALUE__ Value to be written in the register
<> 156:95d6b41a828b 409 * @retval None
<> 156:95d6b41a828b 410 */
<> 156:95d6b41a828b 411 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 156:95d6b41a828b 412
<> 156:95d6b41a828b 413 /**
<> 156:95d6b41a828b 414 * @brief Read a value in DMA register
<> 156:95d6b41a828b 415 * @param __INSTANCE__ DMA Instance
<> 156:95d6b41a828b 416 * @param __REG__ Register to be read
<> 156:95d6b41a828b 417 * @retval Register value
<> 156:95d6b41a828b 418 */
<> 156:95d6b41a828b 419 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 156:95d6b41a828b 420 /**
<> 156:95d6b41a828b 421 * @}
<> 156:95d6b41a828b 422 */
<> 156:95d6b41a828b 423
<> 156:95d6b41a828b 424 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<> 156:95d6b41a828b 425 * @{
<> 156:95d6b41a828b 426 */
<> 156:95d6b41a828b 427 /**
<> 156:95d6b41a828b 428 * @brief Convert DMAx_Channely into DMAx
<> 156:95d6b41a828b 429 * @param __CHANNEL_INSTANCE__ DMAx_Channely
<> 156:95d6b41a828b 430 * @retval DMAx
<> 156:95d6b41a828b 431 */
<> 156:95d6b41a828b 432 #if defined(DMA2)
<> 156:95d6b41a828b 433 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 434 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<> 156:95d6b41a828b 435 #else
<> 156:95d6b41a828b 436 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<> 156:95d6b41a828b 437 #endif
<> 156:95d6b41a828b 438
<> 156:95d6b41a828b 439 /**
<> 156:95d6b41a828b 440 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<> 156:95d6b41a828b 441 * @param __CHANNEL_INSTANCE__ DMAx_Channely
<> 156:95d6b41a828b 442 * @retval LL_DMA_CHANNEL_y
<> 156:95d6b41a828b 443 */
<> 156:95d6b41a828b 444 #if defined (DMA2)
<> 156:95d6b41a828b 445 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 156:95d6b41a828b 446 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 447 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 448 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 449 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 453 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 454 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 456 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 457 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 458 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 459 LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 460 #else
<> 156:95d6b41a828b 461 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 462 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 463 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 464 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 465 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 466 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 467 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 468 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 469 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 470 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 471 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 472 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 473 LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 474 #endif
<> 156:95d6b41a828b 475 #else
<> 156:95d6b41a828b 476 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
<> 156:95d6b41a828b 477 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 478 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 479 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 480 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 481 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 482 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 483 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 484 LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 485 #elif defined (DMA1_Channel6)
<> 156:95d6b41a828b 486 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 487 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 488 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 489 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 490 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 491 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 492 LL_DMA_CHANNEL_6)
<> 156:95d6b41a828b 493 #else
<> 156:95d6b41a828b 494 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 495 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 496 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 497 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 498 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 499 LL_DMA_CHANNEL_5)
<> 156:95d6b41a828b 500 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 156:95d6b41a828b 501 #endif
<> 156:95d6b41a828b 502
<> 156:95d6b41a828b 503 /**
<> 156:95d6b41a828b 504 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<> 156:95d6b41a828b 505 * @param __DMA_INSTANCE__ DMAx
<> 156:95d6b41a828b 506 * @param __CHANNEL__ LL_DMA_CHANNEL_y
<> 156:95d6b41a828b 507 * @retval DMAx_Channely
<> 156:95d6b41a828b 508 */
<> 156:95d6b41a828b 509 #if defined (DMA2)
<> 156:95d6b41a828b 510 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 156:95d6b41a828b 511 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 512 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 513 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<> 156:95d6b41a828b 514 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 515 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<> 156:95d6b41a828b 516 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 517 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<> 156:95d6b41a828b 518 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 519 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<> 156:95d6b41a828b 520 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 521 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<> 156:95d6b41a828b 522 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 156:95d6b41a828b 523 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<> 156:95d6b41a828b 524 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<> 156:95d6b41a828b 525 DMA2_Channel7)
<> 156:95d6b41a828b 526 #else
<> 156:95d6b41a828b 527 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 528 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 529 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<> 156:95d6b41a828b 530 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 531 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<> 156:95d6b41a828b 532 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 533 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<> 156:95d6b41a828b 534 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 535 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<> 156:95d6b41a828b 536 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 537 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<> 156:95d6b41a828b 538 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 156:95d6b41a828b 539 DMA1_Channel7)
<> 156:95d6b41a828b 540 #endif
<> 156:95d6b41a828b 541 #else
<> 156:95d6b41a828b 542 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
<> 156:95d6b41a828b 543 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 544 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 545 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 546 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 547 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 548 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 549 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 156:95d6b41a828b 550 DMA1_Channel7)
<> 156:95d6b41a828b 551 #elif defined (DMA1_Channel6)
<> 156:95d6b41a828b 552 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 553 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 554 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 555 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 556 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 557 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 558 DMA1_Channel6)
<> 156:95d6b41a828b 559 #else
<> 156:95d6b41a828b 560 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 561 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 562 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 563 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 564 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 565 DMA1_Channel5)
<> 156:95d6b41a828b 566 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 156:95d6b41a828b 567 #endif
<> 156:95d6b41a828b 568
<> 156:95d6b41a828b 569 /**
<> 156:95d6b41a828b 570 * @}
<> 156:95d6b41a828b 571 */
<> 156:95d6b41a828b 572
<> 156:95d6b41a828b 573 /**
<> 156:95d6b41a828b 574 * @}
<> 156:95d6b41a828b 575 */
<> 156:95d6b41a828b 576
<> 156:95d6b41a828b 577 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 578 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<> 156:95d6b41a828b 579 * @{
<> 156:95d6b41a828b 580 */
<> 156:95d6b41a828b 581
<> 156:95d6b41a828b 582 /** @defgroup DMA_LL_EF_Configuration Configuration
<> 156:95d6b41a828b 583 * @{
<> 156:95d6b41a828b 584 */
<> 156:95d6b41a828b 585 /**
<> 156:95d6b41a828b 586 * @brief Enable DMA channel.
<> 156:95d6b41a828b 587 * @rmtoll CCR EN LL_DMA_EnableChannel
<> 156:95d6b41a828b 588 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 589 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 590 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 591 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 592 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 593 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 594 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 595 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 596 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 597 * @retval None
<> 156:95d6b41a828b 598 */
<> 156:95d6b41a828b 599 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 600 {
<> 156:95d6b41a828b 601 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<> 156:95d6b41a828b 602 }
<> 156:95d6b41a828b 603
<> 156:95d6b41a828b 604 /**
<> 156:95d6b41a828b 605 * @brief Disable DMA channel.
<> 156:95d6b41a828b 606 * @rmtoll CCR EN LL_DMA_DisableChannel
<> 156:95d6b41a828b 607 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 608 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 609 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 610 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 611 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 612 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 613 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 614 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 615 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 616 * @retval None
<> 156:95d6b41a828b 617 */
<> 156:95d6b41a828b 618 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 619 {
<> 156:95d6b41a828b 620 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<> 156:95d6b41a828b 621 }
<> 156:95d6b41a828b 622
<> 156:95d6b41a828b 623 /**
<> 156:95d6b41a828b 624 * @brief Check if DMA channel is enabled or disabled.
<> 156:95d6b41a828b 625 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
<> 156:95d6b41a828b 626 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 627 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 628 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 629 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 630 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 631 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 632 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 633 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 634 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 635 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 636 */
<> 156:95d6b41a828b 637 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 638 {
<> 156:95d6b41a828b 639 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 640 DMA_CCR_EN) == (DMA_CCR_EN));
<> 156:95d6b41a828b 641 }
<> 156:95d6b41a828b 642
<> 156:95d6b41a828b 643 /**
<> 156:95d6b41a828b 644 * @brief Configure all parameters link to DMA transfer.
<> 156:95d6b41a828b 645 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 646 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 647 * CCR CIRC LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 648 * CCR PINC LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 649 * CCR MINC LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 650 * CCR PSIZE LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 651 * CCR MSIZE LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 652 * CCR PL LL_DMA_ConfigTransfer
<> 156:95d6b41a828b 653 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 654 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 655 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 656 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 657 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 658 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 659 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 660 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 661 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 662 * @param Configuration This parameter must be a combination of all the following values:
<> 156:95d6b41a828b 663 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 664 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<> 156:95d6b41a828b 665 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<> 156:95d6b41a828b 666 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<> 156:95d6b41a828b 667 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<> 156:95d6b41a828b 668 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<> 156:95d6b41a828b 669 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<> 156:95d6b41a828b 670 * @retval None
<> 156:95d6b41a828b 671 */
<> 156:95d6b41a828b 672 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<> 156:95d6b41a828b 673 {
<> 156:95d6b41a828b 674 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 675 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
<> 156:95d6b41a828b 676 Configuration);
<> 156:95d6b41a828b 677 }
<> 156:95d6b41a828b 678
<> 156:95d6b41a828b 679 /**
<> 156:95d6b41a828b 680 * @brief Set Data transfer direction (read from peripheral or from memory).
<> 156:95d6b41a828b 681 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<> 156:95d6b41a828b 682 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
<> 156:95d6b41a828b 683 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 684 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 685 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 686 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 687 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 688 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 689 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 690 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 691 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 692 * @param Direction This parameter can be one of the following values:
<> 156:95d6b41a828b 693 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 156:95d6b41a828b 694 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 156:95d6b41a828b 695 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 696 * @retval None
<> 156:95d6b41a828b 697 */
<> 156:95d6b41a828b 698 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<> 156:95d6b41a828b 699 {
<> 156:95d6b41a828b 700 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 701 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
<> 156:95d6b41a828b 702 }
<> 156:95d6b41a828b 703
<> 156:95d6b41a828b 704 /**
<> 156:95d6b41a828b 705 * @brief Get Data transfer direction (read from peripheral or from memory).
<> 156:95d6b41a828b 706 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<> 156:95d6b41a828b 707 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
<> 156:95d6b41a828b 708 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 709 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 710 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 711 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 712 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 713 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 714 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 715 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 716 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 717 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 718 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 156:95d6b41a828b 719 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 156:95d6b41a828b 720 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 721 */
<> 156:95d6b41a828b 722 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 723 {
<> 156:95d6b41a828b 724 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 725 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
<> 156:95d6b41a828b 726 }
<> 156:95d6b41a828b 727
<> 156:95d6b41a828b 728 /**
<> 156:95d6b41a828b 729 * @brief Set DMA mode circular or normal.
<> 156:95d6b41a828b 730 * @note The circular buffer mode cannot be used if the memory-to-memory
<> 156:95d6b41a828b 731 * data transfer is configured on the selected Channel.
<> 156:95d6b41a828b 732 * @rmtoll CCR CIRC LL_DMA_SetMode
<> 156:95d6b41a828b 733 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 734 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 735 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 736 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 737 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 738 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 739 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 740 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 741 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 742 * @param Mode This parameter can be one of the following values:
<> 156:95d6b41a828b 743 * @arg @ref LL_DMA_MODE_NORMAL
<> 156:95d6b41a828b 744 * @arg @ref LL_DMA_MODE_CIRCULAR
<> 156:95d6b41a828b 745 * @retval None
<> 156:95d6b41a828b 746 */
<> 156:95d6b41a828b 747 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<> 156:95d6b41a828b 748 {
<> 156:95d6b41a828b 749 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<> 156:95d6b41a828b 750 Mode);
<> 156:95d6b41a828b 751 }
<> 156:95d6b41a828b 752
<> 156:95d6b41a828b 753 /**
<> 156:95d6b41a828b 754 * @brief Get DMA mode circular or normal.
<> 156:95d6b41a828b 755 * @rmtoll CCR CIRC LL_DMA_GetMode
<> 156:95d6b41a828b 756 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 757 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 758 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 759 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 760 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 761 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 762 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 763 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 764 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 765 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 766 * @arg @ref LL_DMA_MODE_NORMAL
<> 156:95d6b41a828b 767 * @arg @ref LL_DMA_MODE_CIRCULAR
<> 156:95d6b41a828b 768 */
<> 156:95d6b41a828b 769 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 770 {
<> 156:95d6b41a828b 771 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 772 DMA_CCR_CIRC));
<> 156:95d6b41a828b 773 }
<> 156:95d6b41a828b 774
<> 156:95d6b41a828b 775 /**
<> 156:95d6b41a828b 776 * @brief Set Peripheral increment mode.
<> 156:95d6b41a828b 777 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<> 156:95d6b41a828b 778 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 779 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 780 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 781 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 782 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 783 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 784 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 785 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 786 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 787 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<> 156:95d6b41a828b 788 * @arg @ref LL_DMA_PERIPH_INCREMENT
<> 156:95d6b41a828b 789 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
<> 156:95d6b41a828b 790 * @retval None
<> 156:95d6b41a828b 791 */
<> 156:95d6b41a828b 792 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<> 156:95d6b41a828b 793 {
<> 156:95d6b41a828b 794 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<> 156:95d6b41a828b 795 PeriphOrM2MSrcIncMode);
<> 156:95d6b41a828b 796 }
<> 156:95d6b41a828b 797
<> 156:95d6b41a828b 798 /**
<> 156:95d6b41a828b 799 * @brief Get Peripheral increment mode.
<> 156:95d6b41a828b 800 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<> 156:95d6b41a828b 801 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 802 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 803 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 804 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 805 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 806 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 807 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 808 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 809 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 810 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 811 * @arg @ref LL_DMA_PERIPH_INCREMENT
<> 156:95d6b41a828b 812 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
<> 156:95d6b41a828b 813 */
<> 156:95d6b41a828b 814 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 815 {
<> 156:95d6b41a828b 816 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 817 DMA_CCR_PINC));
<> 156:95d6b41a828b 818 }
<> 156:95d6b41a828b 819
<> 156:95d6b41a828b 820 /**
<> 156:95d6b41a828b 821 * @brief Set Memory increment mode.
<> 156:95d6b41a828b 822 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<> 156:95d6b41a828b 823 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 824 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 825 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 826 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 827 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 828 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 829 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 830 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 831 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 832 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<> 156:95d6b41a828b 833 * @arg @ref LL_DMA_MEMORY_INCREMENT
<> 156:95d6b41a828b 834 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
<> 156:95d6b41a828b 835 * @retval None
<> 156:95d6b41a828b 836 */
<> 156:95d6b41a828b 837 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<> 156:95d6b41a828b 838 {
<> 156:95d6b41a828b 839 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<> 156:95d6b41a828b 840 MemoryOrM2MDstIncMode);
<> 156:95d6b41a828b 841 }
<> 156:95d6b41a828b 842
<> 156:95d6b41a828b 843 /**
<> 156:95d6b41a828b 844 * @brief Get Memory increment mode.
<> 156:95d6b41a828b 845 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<> 156:95d6b41a828b 846 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 847 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 848 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 849 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 850 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 851 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 852 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 853 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 854 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 855 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 856 * @arg @ref LL_DMA_MEMORY_INCREMENT
<> 156:95d6b41a828b 857 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
<> 156:95d6b41a828b 858 */
<> 156:95d6b41a828b 859 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 860 {
<> 156:95d6b41a828b 861 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 862 DMA_CCR_MINC));
<> 156:95d6b41a828b 863 }
<> 156:95d6b41a828b 864
<> 156:95d6b41a828b 865 /**
<> 156:95d6b41a828b 866 * @brief Set Peripheral size.
<> 156:95d6b41a828b 867 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<> 156:95d6b41a828b 868 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 869 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 870 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 871 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 872 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 873 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 874 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 875 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 876 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 877 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<> 156:95d6b41a828b 878 * @arg @ref LL_DMA_PDATAALIGN_BYTE
<> 156:95d6b41a828b 879 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<> 156:95d6b41a828b 880 * @arg @ref LL_DMA_PDATAALIGN_WORD
<> 156:95d6b41a828b 881 * @retval None
<> 156:95d6b41a828b 882 */
<> 156:95d6b41a828b 883 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<> 156:95d6b41a828b 884 {
<> 156:95d6b41a828b 885 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<> 156:95d6b41a828b 886 PeriphOrM2MSrcDataSize);
<> 156:95d6b41a828b 887 }
<> 156:95d6b41a828b 888
<> 156:95d6b41a828b 889 /**
<> 156:95d6b41a828b 890 * @brief Get Peripheral size.
<> 156:95d6b41a828b 891 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<> 156:95d6b41a828b 892 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 893 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 894 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 895 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 896 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 897 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 898 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 899 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 900 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 901 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 902 * @arg @ref LL_DMA_PDATAALIGN_BYTE
<> 156:95d6b41a828b 903 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<> 156:95d6b41a828b 904 * @arg @ref LL_DMA_PDATAALIGN_WORD
<> 156:95d6b41a828b 905 */
<> 156:95d6b41a828b 906 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 907 {
<> 156:95d6b41a828b 908 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 909 DMA_CCR_PSIZE));
<> 156:95d6b41a828b 910 }
<> 156:95d6b41a828b 911
<> 156:95d6b41a828b 912 /**
<> 156:95d6b41a828b 913 * @brief Set Memory size.
<> 156:95d6b41a828b 914 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<> 156:95d6b41a828b 915 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 916 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 917 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 918 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 919 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 920 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 921 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 922 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 923 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 924 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<> 156:95d6b41a828b 925 * @arg @ref LL_DMA_MDATAALIGN_BYTE
<> 156:95d6b41a828b 926 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<> 156:95d6b41a828b 927 * @arg @ref LL_DMA_MDATAALIGN_WORD
<> 156:95d6b41a828b 928 * @retval None
<> 156:95d6b41a828b 929 */
<> 156:95d6b41a828b 930 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<> 156:95d6b41a828b 931 {
<> 156:95d6b41a828b 932 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<> 156:95d6b41a828b 933 MemoryOrM2MDstDataSize);
<> 156:95d6b41a828b 934 }
<> 156:95d6b41a828b 935
<> 156:95d6b41a828b 936 /**
<> 156:95d6b41a828b 937 * @brief Get Memory size.
<> 156:95d6b41a828b 938 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<> 156:95d6b41a828b 939 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 940 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 941 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 942 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 943 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 944 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 945 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 946 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 947 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 948 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 949 * @arg @ref LL_DMA_MDATAALIGN_BYTE
<> 156:95d6b41a828b 950 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<> 156:95d6b41a828b 951 * @arg @ref LL_DMA_MDATAALIGN_WORD
<> 156:95d6b41a828b 952 */
<> 156:95d6b41a828b 953 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 954 {
<> 156:95d6b41a828b 955 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 956 DMA_CCR_MSIZE));
<> 156:95d6b41a828b 957 }
<> 156:95d6b41a828b 958
<> 156:95d6b41a828b 959 /**
<> 156:95d6b41a828b 960 * @brief Set Channel priority level.
<> 156:95d6b41a828b 961 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<> 156:95d6b41a828b 962 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 963 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 964 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 965 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 966 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 967 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 968 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 969 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 970 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 971 * @param Priority This parameter can be one of the following values:
<> 156:95d6b41a828b 972 * @arg @ref LL_DMA_PRIORITY_LOW
<> 156:95d6b41a828b 973 * @arg @ref LL_DMA_PRIORITY_MEDIUM
<> 156:95d6b41a828b 974 * @arg @ref LL_DMA_PRIORITY_HIGH
<> 156:95d6b41a828b 975 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
<> 156:95d6b41a828b 976 * @retval None
<> 156:95d6b41a828b 977 */
<> 156:95d6b41a828b 978 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<> 156:95d6b41a828b 979 {
<> 156:95d6b41a828b 980 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<> 156:95d6b41a828b 981 Priority);
<> 156:95d6b41a828b 982 }
<> 156:95d6b41a828b 983
<> 156:95d6b41a828b 984 /**
<> 156:95d6b41a828b 985 * @brief Get Channel priority level.
<> 156:95d6b41a828b 986 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<> 156:95d6b41a828b 987 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 988 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 989 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 990 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 991 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 992 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 993 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 994 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 995 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 996 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 997 * @arg @ref LL_DMA_PRIORITY_LOW
<> 156:95d6b41a828b 998 * @arg @ref LL_DMA_PRIORITY_MEDIUM
<> 156:95d6b41a828b 999 * @arg @ref LL_DMA_PRIORITY_HIGH
<> 156:95d6b41a828b 1000 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
<> 156:95d6b41a828b 1001 */
<> 156:95d6b41a828b 1002 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1003 {
<> 156:95d6b41a828b 1004 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 1005 DMA_CCR_PL));
<> 156:95d6b41a828b 1006 }
<> 156:95d6b41a828b 1007
<> 156:95d6b41a828b 1008 /**
<> 156:95d6b41a828b 1009 * @brief Set Number of data to transfer.
<> 156:95d6b41a828b 1010 * @note This action has no effect if
<> 156:95d6b41a828b 1011 * channel is enabled.
<> 156:95d6b41a828b 1012 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
<> 156:95d6b41a828b 1013 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1014 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1015 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1016 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1017 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1018 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1019 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1020 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1021 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1022 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<> 156:95d6b41a828b 1023 * @retval None
<> 156:95d6b41a828b 1024 */
<> 156:95d6b41a828b 1025 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<> 156:95d6b41a828b 1026 {
<> 156:95d6b41a828b 1027 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<> 156:95d6b41a828b 1028 DMA_CNDTR_NDT, NbData);
<> 156:95d6b41a828b 1029 }
<> 156:95d6b41a828b 1030
<> 156:95d6b41a828b 1031 /**
<> 156:95d6b41a828b 1032 * @brief Get Number of data to transfer.
<> 156:95d6b41a828b 1033 * @note Once the channel is enabled, the return value indicate the
<> 156:95d6b41a828b 1034 * remaining bytes to be transmitted.
<> 156:95d6b41a828b 1035 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
<> 156:95d6b41a828b 1036 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1037 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1038 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1039 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1040 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1041 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1042 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1043 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1044 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1045 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1046 */
<> 156:95d6b41a828b 1047 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1048 {
<> 156:95d6b41a828b 1049 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<> 156:95d6b41a828b 1050 DMA_CNDTR_NDT));
<> 156:95d6b41a828b 1051 }
<> 156:95d6b41a828b 1052
<> 156:95d6b41a828b 1053 /**
<> 156:95d6b41a828b 1054 * @brief Configure the Source and Destination addresses.
Anna Bridge 180:96ed750bd169 1055 * @note This API must not be called when the DMA channel is enabled.
Anna Bridge 180:96ed750bd169 1056 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
<> 156:95d6b41a828b 1057 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<> 156:95d6b41a828b 1058 * CMAR MA LL_DMA_ConfigAddresses
<> 156:95d6b41a828b 1059 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1060 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1061 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1062 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1063 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1064 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1065 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1066 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1067 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1068 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1069 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1070 * @param Direction This parameter can be one of the following values:
<> 156:95d6b41a828b 1071 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 156:95d6b41a828b 1072 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 156:95d6b41a828b 1073 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 1074 * @retval None
<> 156:95d6b41a828b 1075 */
<> 156:95d6b41a828b 1076 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<> 156:95d6b41a828b 1077 uint32_t DstAddress, uint32_t Direction)
<> 156:95d6b41a828b 1078 {
<> 156:95d6b41a828b 1079 /* Direction Memory to Periph */
<> 156:95d6b41a828b 1080 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<> 156:95d6b41a828b 1081 {
Anna Bridge 180:96ed750bd169 1082 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
Anna Bridge 180:96ed750bd169 1083 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
<> 156:95d6b41a828b 1084 }
<> 156:95d6b41a828b 1085 /* Direction Periph to Memory and Memory to Memory */
<> 156:95d6b41a828b 1086 else
<> 156:95d6b41a828b 1087 {
Anna Bridge 180:96ed750bd169 1088 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
Anna Bridge 180:96ed750bd169 1089 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
<> 156:95d6b41a828b 1090 }
<> 156:95d6b41a828b 1091 }
<> 156:95d6b41a828b 1092
<> 156:95d6b41a828b 1093 /**
<> 156:95d6b41a828b 1094 * @brief Set the Memory address.
<> 156:95d6b41a828b 1095 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Anna Bridge 180:96ed750bd169 1096 * @note This API must not be called when the DMA channel is enabled.
<> 156:95d6b41a828b 1097 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<> 156:95d6b41a828b 1098 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1099 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1100 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1101 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1102 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1103 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1104 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1105 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1106 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1107 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1108 * @retval None
<> 156:95d6b41a828b 1109 */
<> 156:95d6b41a828b 1110 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 156:95d6b41a828b 1111 {
Anna Bridge 180:96ed750bd169 1112 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
<> 156:95d6b41a828b 1113 }
<> 156:95d6b41a828b 1114
<> 156:95d6b41a828b 1115 /**
<> 156:95d6b41a828b 1116 * @brief Set the Peripheral address.
<> 156:95d6b41a828b 1117 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Anna Bridge 180:96ed750bd169 1118 * @note This API must not be called when the DMA channel is enabled.
<> 156:95d6b41a828b 1119 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<> 156:95d6b41a828b 1120 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1121 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1122 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1123 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1124 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1125 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1126 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1127 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1128 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1129 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1130 * @retval None
<> 156:95d6b41a828b 1131 */
<> 156:95d6b41a828b 1132 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<> 156:95d6b41a828b 1133 {
Anna Bridge 180:96ed750bd169 1134 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
<> 156:95d6b41a828b 1135 }
<> 156:95d6b41a828b 1136
<> 156:95d6b41a828b 1137 /**
<> 156:95d6b41a828b 1138 * @brief Get Memory address.
<> 156:95d6b41a828b 1139 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 156:95d6b41a828b 1140 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<> 156:95d6b41a828b 1141 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1142 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1143 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1144 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1145 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1146 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1147 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1148 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1149 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1150 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1151 */
<> 156:95d6b41a828b 1152 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1153 {
Anna Bridge 180:96ed750bd169 1154 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
<> 156:95d6b41a828b 1155 }
<> 156:95d6b41a828b 1156
<> 156:95d6b41a828b 1157 /**
<> 156:95d6b41a828b 1158 * @brief Get Peripheral address.
<> 156:95d6b41a828b 1159 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 156:95d6b41a828b 1160 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<> 156:95d6b41a828b 1161 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1162 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1163 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1164 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1165 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1166 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1167 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1168 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1169 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1170 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1171 */
<> 156:95d6b41a828b 1172 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1173 {
Anna Bridge 180:96ed750bd169 1174 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
<> 156:95d6b41a828b 1175 }
<> 156:95d6b41a828b 1176
<> 156:95d6b41a828b 1177 /**
<> 156:95d6b41a828b 1178 * @brief Set the Memory to Memory Source address.
<> 156:95d6b41a828b 1179 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Anna Bridge 180:96ed750bd169 1180 * @note This API must not be called when the DMA channel is enabled.
<> 156:95d6b41a828b 1181 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<> 156:95d6b41a828b 1182 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1183 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1184 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1185 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1186 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1187 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1188 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1189 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1190 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1191 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1192 * @retval None
<> 156:95d6b41a828b 1193 */
<> 156:95d6b41a828b 1194 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 156:95d6b41a828b 1195 {
Anna Bridge 180:96ed750bd169 1196 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
<> 156:95d6b41a828b 1197 }
<> 156:95d6b41a828b 1198
<> 156:95d6b41a828b 1199 /**
<> 156:95d6b41a828b 1200 * @brief Set the Memory to Memory Destination address.
<> 156:95d6b41a828b 1201 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Anna Bridge 180:96ed750bd169 1202 * @note This API must not be called when the DMA channel is enabled.
<> 156:95d6b41a828b 1203 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<> 156:95d6b41a828b 1204 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1205 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1206 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1207 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1208 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1209 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1210 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1211 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1212 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1213 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1214 * @retval None
<> 156:95d6b41a828b 1215 */
<> 156:95d6b41a828b 1216 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 156:95d6b41a828b 1217 {
Anna Bridge 180:96ed750bd169 1218 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
<> 156:95d6b41a828b 1219 }
<> 156:95d6b41a828b 1220
<> 156:95d6b41a828b 1221 /**
<> 156:95d6b41a828b 1222 * @brief Get the Memory to Memory Source address.
<> 156:95d6b41a828b 1223 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 156:95d6b41a828b 1224 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<> 156:95d6b41a828b 1225 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1226 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1227 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1228 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1229 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1230 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1231 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1232 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1233 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1234 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1235 */
<> 156:95d6b41a828b 1236 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1237 {
Anna Bridge 180:96ed750bd169 1238 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
<> 156:95d6b41a828b 1239 }
<> 156:95d6b41a828b 1240
<> 156:95d6b41a828b 1241 /**
<> 156:95d6b41a828b 1242 * @brief Get the Memory to Memory Destination address.
<> 156:95d6b41a828b 1243 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 156:95d6b41a828b 1244 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<> 156:95d6b41a828b 1245 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1246 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1247 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1248 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1249 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1250 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1251 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1252 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1253 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1254 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1255 */
<> 156:95d6b41a828b 1256 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1257 {
Anna Bridge 180:96ed750bd169 1258 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
<> 156:95d6b41a828b 1259 }
<> 156:95d6b41a828b 1260
<> 156:95d6b41a828b 1261 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 1262 /**
<> 156:95d6b41a828b 1263 * @brief Set DMA request for DMA instance on Channel x.
<> 156:95d6b41a828b 1264 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
<> 156:95d6b41a828b 1265 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1266 * CSELR C2S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1267 * CSELR C3S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1268 * CSELR C4S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1269 * CSELR C5S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1270 * CSELR C6S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1271 * CSELR C7S LL_DMA_SetPeriphRequest
<> 156:95d6b41a828b 1272 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1273 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1274 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1275 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1276 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1277 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1278 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1279 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1280 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1281 * @param PeriphRequest This parameter can be one of the following values:
<> 156:95d6b41a828b 1282 * @arg @ref LL_DMA_REQUEST_0
<> 156:95d6b41a828b 1283 * @arg @ref LL_DMA_REQUEST_1
<> 156:95d6b41a828b 1284 * @arg @ref LL_DMA_REQUEST_2
<> 156:95d6b41a828b 1285 * @arg @ref LL_DMA_REQUEST_3
<> 156:95d6b41a828b 1286 * @arg @ref LL_DMA_REQUEST_4
<> 156:95d6b41a828b 1287 * @arg @ref LL_DMA_REQUEST_5
<> 156:95d6b41a828b 1288 * @arg @ref LL_DMA_REQUEST_6
<> 156:95d6b41a828b 1289 * @arg @ref LL_DMA_REQUEST_7
<> 156:95d6b41a828b 1290 * @arg @ref LL_DMA_REQUEST_8
<> 156:95d6b41a828b 1291 * @arg @ref LL_DMA_REQUEST_9
<> 156:95d6b41a828b 1292 * @arg @ref LL_DMA_REQUEST_10
<> 156:95d6b41a828b 1293 * @arg @ref LL_DMA_REQUEST_11
<> 156:95d6b41a828b 1294 * @arg @ref LL_DMA_REQUEST_12
<> 156:95d6b41a828b 1295 * @arg @ref LL_DMA_REQUEST_13
<> 156:95d6b41a828b 1296 * @arg @ref LL_DMA_REQUEST_14
<> 156:95d6b41a828b 1297 * @arg @ref LL_DMA_REQUEST_15
<> 156:95d6b41a828b 1298 * @retval None
<> 156:95d6b41a828b 1299 */
<> 156:95d6b41a828b 1300 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
<> 156:95d6b41a828b 1301 {
<> 156:95d6b41a828b 1302 MODIFY_REG(DMAx->CSELR,
<> 156:95d6b41a828b 1303 DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
<> 156:95d6b41a828b 1304 }
<> 156:95d6b41a828b 1305
<> 156:95d6b41a828b 1306 /**
<> 156:95d6b41a828b 1307 * @brief Get DMA request for DMA instance on Channel x.
<> 156:95d6b41a828b 1308 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1309 * CSELR C2S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1310 * CSELR C3S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1311 * CSELR C4S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1312 * CSELR C5S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1313 * CSELR C6S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1314 * CSELR C7S LL_DMA_GetPeriphRequest
<> 156:95d6b41a828b 1315 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1316 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1317 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1318 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1319 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1320 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1321 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1322 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1323 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1324 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 1325 * @arg @ref LL_DMA_REQUEST_0
<> 156:95d6b41a828b 1326 * @arg @ref LL_DMA_REQUEST_1
<> 156:95d6b41a828b 1327 * @arg @ref LL_DMA_REQUEST_2
<> 156:95d6b41a828b 1328 * @arg @ref LL_DMA_REQUEST_3
<> 156:95d6b41a828b 1329 * @arg @ref LL_DMA_REQUEST_4
<> 156:95d6b41a828b 1330 * @arg @ref LL_DMA_REQUEST_5
<> 156:95d6b41a828b 1331 * @arg @ref LL_DMA_REQUEST_6
<> 156:95d6b41a828b 1332 * @arg @ref LL_DMA_REQUEST_7
<> 156:95d6b41a828b 1333 * @arg @ref LL_DMA_REQUEST_8
<> 156:95d6b41a828b 1334 * @arg @ref LL_DMA_REQUEST_9
<> 156:95d6b41a828b 1335 * @arg @ref LL_DMA_REQUEST_10
<> 156:95d6b41a828b 1336 * @arg @ref LL_DMA_REQUEST_11
<> 156:95d6b41a828b 1337 * @arg @ref LL_DMA_REQUEST_12
<> 156:95d6b41a828b 1338 * @arg @ref LL_DMA_REQUEST_13
<> 156:95d6b41a828b 1339 * @arg @ref LL_DMA_REQUEST_14
<> 156:95d6b41a828b 1340 * @arg @ref LL_DMA_REQUEST_15
<> 156:95d6b41a828b 1341 */
<> 156:95d6b41a828b 1342 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1343 {
<> 156:95d6b41a828b 1344 return (READ_BIT(DMAx->CSELR,
<> 156:95d6b41a828b 1345 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
<> 156:95d6b41a828b 1346 }
<> 156:95d6b41a828b 1347 #endif
<> 156:95d6b41a828b 1348
<> 156:95d6b41a828b 1349 /**
<> 156:95d6b41a828b 1350 * @}
<> 156:95d6b41a828b 1351 */
<> 156:95d6b41a828b 1352
<> 156:95d6b41a828b 1353 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<> 156:95d6b41a828b 1354 * @{
<> 156:95d6b41a828b 1355 */
<> 156:95d6b41a828b 1356
<> 156:95d6b41a828b 1357 /**
<> 156:95d6b41a828b 1358 * @brief Get Channel 1 global interrupt flag.
<> 156:95d6b41a828b 1359 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<> 156:95d6b41a828b 1360 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1361 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1362 */
<> 156:95d6b41a828b 1363 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1364 {
<> 156:95d6b41a828b 1365 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<> 156:95d6b41a828b 1366 }
<> 156:95d6b41a828b 1367
<> 156:95d6b41a828b 1368 /**
<> 156:95d6b41a828b 1369 * @brief Get Channel 2 global interrupt flag.
<> 156:95d6b41a828b 1370 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<> 156:95d6b41a828b 1371 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1372 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1373 */
<> 156:95d6b41a828b 1374 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1375 {
<> 156:95d6b41a828b 1376 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<> 156:95d6b41a828b 1377 }
<> 156:95d6b41a828b 1378
<> 156:95d6b41a828b 1379 /**
<> 156:95d6b41a828b 1380 * @brief Get Channel 3 global interrupt flag.
<> 156:95d6b41a828b 1381 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<> 156:95d6b41a828b 1382 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1383 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1384 */
<> 156:95d6b41a828b 1385 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1386 {
<> 156:95d6b41a828b 1387 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<> 156:95d6b41a828b 1388 }
<> 156:95d6b41a828b 1389
<> 156:95d6b41a828b 1390 /**
<> 156:95d6b41a828b 1391 * @brief Get Channel 4 global interrupt flag.
<> 156:95d6b41a828b 1392 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<> 156:95d6b41a828b 1393 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1394 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1395 */
<> 156:95d6b41a828b 1396 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1397 {
<> 156:95d6b41a828b 1398 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<> 156:95d6b41a828b 1399 }
<> 156:95d6b41a828b 1400
<> 156:95d6b41a828b 1401 /**
<> 156:95d6b41a828b 1402 * @brief Get Channel 5 global interrupt flag.
<> 156:95d6b41a828b 1403 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<> 156:95d6b41a828b 1404 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1405 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1406 */
<> 156:95d6b41a828b 1407 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1408 {
<> 156:95d6b41a828b 1409 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<> 156:95d6b41a828b 1410 }
<> 156:95d6b41a828b 1411
<> 156:95d6b41a828b 1412 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1413 /**
<> 156:95d6b41a828b 1414 * @brief Get Channel 6 global interrupt flag.
<> 156:95d6b41a828b 1415 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<> 156:95d6b41a828b 1416 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1417 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1418 */
<> 156:95d6b41a828b 1419 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1420 {
<> 156:95d6b41a828b 1421 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<> 156:95d6b41a828b 1422 }
<> 156:95d6b41a828b 1423 #endif
<> 156:95d6b41a828b 1424
<> 156:95d6b41a828b 1425 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1426 /**
<> 156:95d6b41a828b 1427 * @brief Get Channel 7 global interrupt flag.
<> 156:95d6b41a828b 1428 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<> 156:95d6b41a828b 1429 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1430 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1431 */
<> 156:95d6b41a828b 1432 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1433 {
<> 156:95d6b41a828b 1434 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<> 156:95d6b41a828b 1435 }
<> 156:95d6b41a828b 1436 #endif
<> 156:95d6b41a828b 1437
<> 156:95d6b41a828b 1438 /**
<> 156:95d6b41a828b 1439 * @brief Get Channel 1 transfer complete flag.
<> 156:95d6b41a828b 1440 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<> 156:95d6b41a828b 1441 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1442 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1443 */
<> 156:95d6b41a828b 1444 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1445 {
<> 156:95d6b41a828b 1446 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<> 156:95d6b41a828b 1447 }
<> 156:95d6b41a828b 1448
<> 156:95d6b41a828b 1449 /**
<> 156:95d6b41a828b 1450 * @brief Get Channel 2 transfer complete flag.
<> 156:95d6b41a828b 1451 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<> 156:95d6b41a828b 1452 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1453 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1454 */
<> 156:95d6b41a828b 1455 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1456 {
<> 156:95d6b41a828b 1457 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<> 156:95d6b41a828b 1458 }
<> 156:95d6b41a828b 1459
<> 156:95d6b41a828b 1460 /**
<> 156:95d6b41a828b 1461 * @brief Get Channel 3 transfer complete flag.
<> 156:95d6b41a828b 1462 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<> 156:95d6b41a828b 1463 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1464 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1465 */
<> 156:95d6b41a828b 1466 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1467 {
<> 156:95d6b41a828b 1468 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<> 156:95d6b41a828b 1469 }
<> 156:95d6b41a828b 1470
<> 156:95d6b41a828b 1471 /**
<> 156:95d6b41a828b 1472 * @brief Get Channel 4 transfer complete flag.
<> 156:95d6b41a828b 1473 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<> 156:95d6b41a828b 1474 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1475 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1476 */
<> 156:95d6b41a828b 1477 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1478 {
<> 156:95d6b41a828b 1479 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<> 156:95d6b41a828b 1480 }
<> 156:95d6b41a828b 1481
<> 156:95d6b41a828b 1482 /**
<> 156:95d6b41a828b 1483 * @brief Get Channel 5 transfer complete flag.
<> 156:95d6b41a828b 1484 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<> 156:95d6b41a828b 1485 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1486 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1487 */
<> 156:95d6b41a828b 1488 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1489 {
<> 156:95d6b41a828b 1490 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<> 156:95d6b41a828b 1491 }
<> 156:95d6b41a828b 1492
<> 156:95d6b41a828b 1493 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1494 /**
<> 156:95d6b41a828b 1495 * @brief Get Channel 6 transfer complete flag.
<> 156:95d6b41a828b 1496 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<> 156:95d6b41a828b 1497 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1498 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1499 */
<> 156:95d6b41a828b 1500 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1501 {
<> 156:95d6b41a828b 1502 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<> 156:95d6b41a828b 1503 }
<> 156:95d6b41a828b 1504 #endif
<> 156:95d6b41a828b 1505
<> 156:95d6b41a828b 1506 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1507 /**
<> 156:95d6b41a828b 1508 * @brief Get Channel 7 transfer complete flag.
<> 156:95d6b41a828b 1509 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<> 156:95d6b41a828b 1510 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1511 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1512 */
<> 156:95d6b41a828b 1513 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1514 {
<> 156:95d6b41a828b 1515 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<> 156:95d6b41a828b 1516 }
<> 156:95d6b41a828b 1517 #endif
<> 156:95d6b41a828b 1518
<> 156:95d6b41a828b 1519 /**
<> 156:95d6b41a828b 1520 * @brief Get Channel 1 half transfer flag.
<> 156:95d6b41a828b 1521 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<> 156:95d6b41a828b 1522 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1523 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1524 */
<> 156:95d6b41a828b 1525 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1526 {
<> 156:95d6b41a828b 1527 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<> 156:95d6b41a828b 1528 }
<> 156:95d6b41a828b 1529
<> 156:95d6b41a828b 1530 /**
<> 156:95d6b41a828b 1531 * @brief Get Channel 2 half transfer flag.
<> 156:95d6b41a828b 1532 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<> 156:95d6b41a828b 1533 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1534 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1535 */
<> 156:95d6b41a828b 1536 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1537 {
<> 156:95d6b41a828b 1538 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<> 156:95d6b41a828b 1539 }
<> 156:95d6b41a828b 1540
<> 156:95d6b41a828b 1541 /**
<> 156:95d6b41a828b 1542 * @brief Get Channel 3 half transfer flag.
<> 156:95d6b41a828b 1543 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<> 156:95d6b41a828b 1544 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1545 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1546 */
<> 156:95d6b41a828b 1547 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1548 {
<> 156:95d6b41a828b 1549 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<> 156:95d6b41a828b 1550 }
<> 156:95d6b41a828b 1551
<> 156:95d6b41a828b 1552 /**
<> 156:95d6b41a828b 1553 * @brief Get Channel 4 half transfer flag.
<> 156:95d6b41a828b 1554 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<> 156:95d6b41a828b 1555 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1556 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1557 */
<> 156:95d6b41a828b 1558 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1559 {
<> 156:95d6b41a828b 1560 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<> 156:95d6b41a828b 1561 }
<> 156:95d6b41a828b 1562
<> 156:95d6b41a828b 1563 /**
<> 156:95d6b41a828b 1564 * @brief Get Channel 5 half transfer flag.
<> 156:95d6b41a828b 1565 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<> 156:95d6b41a828b 1566 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1567 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1568 */
<> 156:95d6b41a828b 1569 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1570 {
<> 156:95d6b41a828b 1571 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<> 156:95d6b41a828b 1572 }
<> 156:95d6b41a828b 1573
<> 156:95d6b41a828b 1574 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1575 /**
<> 156:95d6b41a828b 1576 * @brief Get Channel 6 half transfer flag.
<> 156:95d6b41a828b 1577 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<> 156:95d6b41a828b 1578 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1579 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1580 */
<> 156:95d6b41a828b 1581 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1582 {
<> 156:95d6b41a828b 1583 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<> 156:95d6b41a828b 1584 }
<> 156:95d6b41a828b 1585 #endif
<> 156:95d6b41a828b 1586
<> 156:95d6b41a828b 1587 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1588 /**
<> 156:95d6b41a828b 1589 * @brief Get Channel 7 half transfer flag.
<> 156:95d6b41a828b 1590 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<> 156:95d6b41a828b 1591 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1592 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1593 */
<> 156:95d6b41a828b 1594 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1595 {
<> 156:95d6b41a828b 1596 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<> 156:95d6b41a828b 1597 }
<> 156:95d6b41a828b 1598 #endif
<> 156:95d6b41a828b 1599
<> 156:95d6b41a828b 1600 /**
<> 156:95d6b41a828b 1601 * @brief Get Channel 1 transfer error flag.
<> 156:95d6b41a828b 1602 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<> 156:95d6b41a828b 1603 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1604 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1605 */
<> 156:95d6b41a828b 1606 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1607 {
<> 156:95d6b41a828b 1608 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<> 156:95d6b41a828b 1609 }
<> 156:95d6b41a828b 1610
<> 156:95d6b41a828b 1611 /**
<> 156:95d6b41a828b 1612 * @brief Get Channel 2 transfer error flag.
<> 156:95d6b41a828b 1613 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<> 156:95d6b41a828b 1614 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1615 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1616 */
<> 156:95d6b41a828b 1617 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1618 {
<> 156:95d6b41a828b 1619 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<> 156:95d6b41a828b 1620 }
<> 156:95d6b41a828b 1621
<> 156:95d6b41a828b 1622 /**
<> 156:95d6b41a828b 1623 * @brief Get Channel 3 transfer error flag.
<> 156:95d6b41a828b 1624 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<> 156:95d6b41a828b 1625 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1626 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1627 */
<> 156:95d6b41a828b 1628 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1629 {
<> 156:95d6b41a828b 1630 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<> 156:95d6b41a828b 1631 }
<> 156:95d6b41a828b 1632
<> 156:95d6b41a828b 1633 /**
<> 156:95d6b41a828b 1634 * @brief Get Channel 4 transfer error flag.
<> 156:95d6b41a828b 1635 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<> 156:95d6b41a828b 1636 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1637 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1638 */
<> 156:95d6b41a828b 1639 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1640 {
<> 156:95d6b41a828b 1641 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<> 156:95d6b41a828b 1642 }
<> 156:95d6b41a828b 1643
<> 156:95d6b41a828b 1644 /**
<> 156:95d6b41a828b 1645 * @brief Get Channel 5 transfer error flag.
<> 156:95d6b41a828b 1646 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<> 156:95d6b41a828b 1647 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1648 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1649 */
<> 156:95d6b41a828b 1650 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1651 {
<> 156:95d6b41a828b 1652 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<> 156:95d6b41a828b 1653 }
<> 156:95d6b41a828b 1654
<> 156:95d6b41a828b 1655 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1656 /**
<> 156:95d6b41a828b 1657 * @brief Get Channel 6 transfer error flag.
<> 156:95d6b41a828b 1658 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<> 156:95d6b41a828b 1659 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1660 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1661 */
<> 156:95d6b41a828b 1662 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1663 {
<> 156:95d6b41a828b 1664 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<> 156:95d6b41a828b 1665 }
<> 156:95d6b41a828b 1666 #endif
<> 156:95d6b41a828b 1667
<> 156:95d6b41a828b 1668 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1669 /**
<> 156:95d6b41a828b 1670 * @brief Get Channel 7 transfer error flag.
<> 156:95d6b41a828b 1671 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<> 156:95d6b41a828b 1672 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1673 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1674 */
<> 156:95d6b41a828b 1675 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1676 {
<> 156:95d6b41a828b 1677 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<> 156:95d6b41a828b 1678 }
<> 156:95d6b41a828b 1679 #endif
<> 156:95d6b41a828b 1680
<> 156:95d6b41a828b 1681 /**
<> 156:95d6b41a828b 1682 * @brief Clear Channel 1 global interrupt flag.
<> 156:95d6b41a828b 1683 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<> 156:95d6b41a828b 1684 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1685 * @retval None
<> 156:95d6b41a828b 1686 */
<> 156:95d6b41a828b 1687 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1688 {
Anna Bridge 180:96ed750bd169 1689 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
<> 156:95d6b41a828b 1690 }
<> 156:95d6b41a828b 1691
<> 156:95d6b41a828b 1692 /**
<> 156:95d6b41a828b 1693 * @brief Clear Channel 2 global interrupt flag.
<> 156:95d6b41a828b 1694 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<> 156:95d6b41a828b 1695 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1696 * @retval None
<> 156:95d6b41a828b 1697 */
<> 156:95d6b41a828b 1698 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1699 {
Anna Bridge 180:96ed750bd169 1700 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
<> 156:95d6b41a828b 1701 }
<> 156:95d6b41a828b 1702
<> 156:95d6b41a828b 1703 /**
<> 156:95d6b41a828b 1704 * @brief Clear Channel 3 global interrupt flag.
<> 156:95d6b41a828b 1705 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<> 156:95d6b41a828b 1706 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1707 * @retval None
<> 156:95d6b41a828b 1708 */
<> 156:95d6b41a828b 1709 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1710 {
Anna Bridge 180:96ed750bd169 1711 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
<> 156:95d6b41a828b 1712 }
<> 156:95d6b41a828b 1713
<> 156:95d6b41a828b 1714 /**
<> 156:95d6b41a828b 1715 * @brief Clear Channel 4 global interrupt flag.
<> 156:95d6b41a828b 1716 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<> 156:95d6b41a828b 1717 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1718 * @retval None
<> 156:95d6b41a828b 1719 */
<> 156:95d6b41a828b 1720 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1721 {
Anna Bridge 180:96ed750bd169 1722 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
<> 156:95d6b41a828b 1723 }
<> 156:95d6b41a828b 1724
<> 156:95d6b41a828b 1725 /**
<> 156:95d6b41a828b 1726 * @brief Clear Channel 5 global interrupt flag.
<> 156:95d6b41a828b 1727 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<> 156:95d6b41a828b 1728 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1729 * @retval None
<> 156:95d6b41a828b 1730 */
<> 156:95d6b41a828b 1731 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1732 {
Anna Bridge 180:96ed750bd169 1733 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
<> 156:95d6b41a828b 1734 }
<> 156:95d6b41a828b 1735
<> 156:95d6b41a828b 1736 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1737 /**
<> 156:95d6b41a828b 1738 * @brief Clear Channel 6 global interrupt flag.
<> 156:95d6b41a828b 1739 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<> 156:95d6b41a828b 1740 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1741 * @retval None
<> 156:95d6b41a828b 1742 */
<> 156:95d6b41a828b 1743 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1744 {
Anna Bridge 180:96ed750bd169 1745 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
<> 156:95d6b41a828b 1746 }
<> 156:95d6b41a828b 1747 #endif
<> 156:95d6b41a828b 1748
<> 156:95d6b41a828b 1749 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1750 /**
<> 156:95d6b41a828b 1751 * @brief Clear Channel 7 global interrupt flag.
<> 156:95d6b41a828b 1752 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<> 156:95d6b41a828b 1753 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1754 * @retval None
<> 156:95d6b41a828b 1755 */
<> 156:95d6b41a828b 1756 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1757 {
Anna Bridge 180:96ed750bd169 1758 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
<> 156:95d6b41a828b 1759 }
<> 156:95d6b41a828b 1760 #endif
<> 156:95d6b41a828b 1761
<> 156:95d6b41a828b 1762 /**
<> 156:95d6b41a828b 1763 * @brief Clear Channel 1 transfer complete flag.
<> 156:95d6b41a828b 1764 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<> 156:95d6b41a828b 1765 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1766 * @retval None
<> 156:95d6b41a828b 1767 */
<> 156:95d6b41a828b 1768 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1769 {
Anna Bridge 180:96ed750bd169 1770 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
<> 156:95d6b41a828b 1771 }
<> 156:95d6b41a828b 1772
<> 156:95d6b41a828b 1773 /**
<> 156:95d6b41a828b 1774 * @brief Clear Channel 2 transfer complete flag.
<> 156:95d6b41a828b 1775 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<> 156:95d6b41a828b 1776 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1777 * @retval None
<> 156:95d6b41a828b 1778 */
<> 156:95d6b41a828b 1779 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1780 {
Anna Bridge 180:96ed750bd169 1781 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
<> 156:95d6b41a828b 1782 }
<> 156:95d6b41a828b 1783
<> 156:95d6b41a828b 1784 /**
<> 156:95d6b41a828b 1785 * @brief Clear Channel 3 transfer complete flag.
<> 156:95d6b41a828b 1786 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<> 156:95d6b41a828b 1787 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1788 * @retval None
<> 156:95d6b41a828b 1789 */
<> 156:95d6b41a828b 1790 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1791 {
Anna Bridge 180:96ed750bd169 1792 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
<> 156:95d6b41a828b 1793 }
<> 156:95d6b41a828b 1794
<> 156:95d6b41a828b 1795 /**
<> 156:95d6b41a828b 1796 * @brief Clear Channel 4 transfer complete flag.
<> 156:95d6b41a828b 1797 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<> 156:95d6b41a828b 1798 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1799 * @retval None
<> 156:95d6b41a828b 1800 */
<> 156:95d6b41a828b 1801 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1802 {
Anna Bridge 180:96ed750bd169 1803 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
<> 156:95d6b41a828b 1804 }
<> 156:95d6b41a828b 1805
<> 156:95d6b41a828b 1806 /**
<> 156:95d6b41a828b 1807 * @brief Clear Channel 5 transfer complete flag.
<> 156:95d6b41a828b 1808 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<> 156:95d6b41a828b 1809 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1810 * @retval None
<> 156:95d6b41a828b 1811 */
<> 156:95d6b41a828b 1812 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1813 {
Anna Bridge 180:96ed750bd169 1814 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
<> 156:95d6b41a828b 1815 }
<> 156:95d6b41a828b 1816
<> 156:95d6b41a828b 1817 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1818 /**
<> 156:95d6b41a828b 1819 * @brief Clear Channel 6 transfer complete flag.
<> 156:95d6b41a828b 1820 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<> 156:95d6b41a828b 1821 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1822 * @retval None
<> 156:95d6b41a828b 1823 */
<> 156:95d6b41a828b 1824 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1825 {
Anna Bridge 180:96ed750bd169 1826 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
<> 156:95d6b41a828b 1827 }
<> 156:95d6b41a828b 1828 #endif
<> 156:95d6b41a828b 1829
<> 156:95d6b41a828b 1830 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1831 /**
<> 156:95d6b41a828b 1832 * @brief Clear Channel 7 transfer complete flag.
<> 156:95d6b41a828b 1833 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<> 156:95d6b41a828b 1834 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1835 * @retval None
<> 156:95d6b41a828b 1836 */
<> 156:95d6b41a828b 1837 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1838 {
Anna Bridge 180:96ed750bd169 1839 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
<> 156:95d6b41a828b 1840 }
<> 156:95d6b41a828b 1841 #endif
<> 156:95d6b41a828b 1842
<> 156:95d6b41a828b 1843 /**
<> 156:95d6b41a828b 1844 * @brief Clear Channel 1 half transfer flag.
<> 156:95d6b41a828b 1845 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<> 156:95d6b41a828b 1846 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1847 * @retval None
<> 156:95d6b41a828b 1848 */
<> 156:95d6b41a828b 1849 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1850 {
Anna Bridge 180:96ed750bd169 1851 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
<> 156:95d6b41a828b 1852 }
<> 156:95d6b41a828b 1853
<> 156:95d6b41a828b 1854 /**
<> 156:95d6b41a828b 1855 * @brief Clear Channel 2 half transfer flag.
<> 156:95d6b41a828b 1856 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<> 156:95d6b41a828b 1857 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1858 * @retval None
<> 156:95d6b41a828b 1859 */
<> 156:95d6b41a828b 1860 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1861 {
Anna Bridge 180:96ed750bd169 1862 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
<> 156:95d6b41a828b 1863 }
<> 156:95d6b41a828b 1864
<> 156:95d6b41a828b 1865 /**
<> 156:95d6b41a828b 1866 * @brief Clear Channel 3 half transfer flag.
<> 156:95d6b41a828b 1867 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<> 156:95d6b41a828b 1868 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1869 * @retval None
<> 156:95d6b41a828b 1870 */
<> 156:95d6b41a828b 1871 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1872 {
Anna Bridge 180:96ed750bd169 1873 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
<> 156:95d6b41a828b 1874 }
<> 156:95d6b41a828b 1875
<> 156:95d6b41a828b 1876 /**
<> 156:95d6b41a828b 1877 * @brief Clear Channel 4 half transfer flag.
<> 156:95d6b41a828b 1878 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<> 156:95d6b41a828b 1879 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1880 * @retval None
<> 156:95d6b41a828b 1881 */
<> 156:95d6b41a828b 1882 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1883 {
Anna Bridge 180:96ed750bd169 1884 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
<> 156:95d6b41a828b 1885 }
<> 156:95d6b41a828b 1886
<> 156:95d6b41a828b 1887 /**
<> 156:95d6b41a828b 1888 * @brief Clear Channel 5 half transfer flag.
<> 156:95d6b41a828b 1889 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<> 156:95d6b41a828b 1890 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1891 * @retval None
<> 156:95d6b41a828b 1892 */
<> 156:95d6b41a828b 1893 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1894 {
Anna Bridge 180:96ed750bd169 1895 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
<> 156:95d6b41a828b 1896 }
<> 156:95d6b41a828b 1897
<> 156:95d6b41a828b 1898 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1899 /**
<> 156:95d6b41a828b 1900 * @brief Clear Channel 6 half transfer flag.
<> 156:95d6b41a828b 1901 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<> 156:95d6b41a828b 1902 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1903 * @retval None
<> 156:95d6b41a828b 1904 */
<> 156:95d6b41a828b 1905 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1906 {
Anna Bridge 180:96ed750bd169 1907 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
<> 156:95d6b41a828b 1908 }
<> 156:95d6b41a828b 1909 #endif
<> 156:95d6b41a828b 1910
<> 156:95d6b41a828b 1911 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1912 /**
<> 156:95d6b41a828b 1913 * @brief Clear Channel 7 half transfer flag.
<> 156:95d6b41a828b 1914 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<> 156:95d6b41a828b 1915 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1916 * @retval None
<> 156:95d6b41a828b 1917 */
<> 156:95d6b41a828b 1918 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1919 {
Anna Bridge 180:96ed750bd169 1920 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
<> 156:95d6b41a828b 1921 }
<> 156:95d6b41a828b 1922 #endif
<> 156:95d6b41a828b 1923
<> 156:95d6b41a828b 1924 /**
<> 156:95d6b41a828b 1925 * @brief Clear Channel 1 transfer error flag.
<> 156:95d6b41a828b 1926 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<> 156:95d6b41a828b 1927 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1928 * @retval None
<> 156:95d6b41a828b 1929 */
<> 156:95d6b41a828b 1930 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1931 {
Anna Bridge 180:96ed750bd169 1932 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
<> 156:95d6b41a828b 1933 }
<> 156:95d6b41a828b 1934
<> 156:95d6b41a828b 1935 /**
<> 156:95d6b41a828b 1936 * @brief Clear Channel 2 transfer error flag.
<> 156:95d6b41a828b 1937 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<> 156:95d6b41a828b 1938 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1939 * @retval None
<> 156:95d6b41a828b 1940 */
<> 156:95d6b41a828b 1941 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1942 {
Anna Bridge 180:96ed750bd169 1943 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
<> 156:95d6b41a828b 1944 }
<> 156:95d6b41a828b 1945
<> 156:95d6b41a828b 1946 /**
<> 156:95d6b41a828b 1947 * @brief Clear Channel 3 transfer error flag.
<> 156:95d6b41a828b 1948 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<> 156:95d6b41a828b 1949 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1950 * @retval None
<> 156:95d6b41a828b 1951 */
<> 156:95d6b41a828b 1952 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1953 {
Anna Bridge 180:96ed750bd169 1954 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
<> 156:95d6b41a828b 1955 }
<> 156:95d6b41a828b 1956
<> 156:95d6b41a828b 1957 /**
<> 156:95d6b41a828b 1958 * @brief Clear Channel 4 transfer error flag.
<> 156:95d6b41a828b 1959 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<> 156:95d6b41a828b 1960 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1961 * @retval None
<> 156:95d6b41a828b 1962 */
<> 156:95d6b41a828b 1963 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1964 {
Anna Bridge 180:96ed750bd169 1965 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
<> 156:95d6b41a828b 1966 }
<> 156:95d6b41a828b 1967
<> 156:95d6b41a828b 1968 /**
<> 156:95d6b41a828b 1969 * @brief Clear Channel 5 transfer error flag.
<> 156:95d6b41a828b 1970 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<> 156:95d6b41a828b 1971 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1972 * @retval None
<> 156:95d6b41a828b 1973 */
<> 156:95d6b41a828b 1974 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1975 {
Anna Bridge 180:96ed750bd169 1976 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
<> 156:95d6b41a828b 1977 }
<> 156:95d6b41a828b 1978
<> 156:95d6b41a828b 1979 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1980 /**
<> 156:95d6b41a828b 1981 * @brief Clear Channel 6 transfer error flag.
<> 156:95d6b41a828b 1982 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<> 156:95d6b41a828b 1983 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1984 * @retval None
<> 156:95d6b41a828b 1985 */
<> 156:95d6b41a828b 1986 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1987 {
Anna Bridge 180:96ed750bd169 1988 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
<> 156:95d6b41a828b 1989 }
<> 156:95d6b41a828b 1990 #endif
<> 156:95d6b41a828b 1991
<> 156:95d6b41a828b 1992 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1993 /**
<> 156:95d6b41a828b 1994 * @brief Clear Channel 7 transfer error flag.
<> 156:95d6b41a828b 1995 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<> 156:95d6b41a828b 1996 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1997 * @retval None
<> 156:95d6b41a828b 1998 */
<> 156:95d6b41a828b 1999 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 2000 {
Anna Bridge 180:96ed750bd169 2001 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
<> 156:95d6b41a828b 2002 }
<> 156:95d6b41a828b 2003 #endif
<> 156:95d6b41a828b 2004
<> 156:95d6b41a828b 2005 /**
<> 156:95d6b41a828b 2006 * @}
<> 156:95d6b41a828b 2007 */
<> 156:95d6b41a828b 2008
<> 156:95d6b41a828b 2009 /** @defgroup DMA_LL_EF_IT_Management IT_Management
<> 156:95d6b41a828b 2010 * @{
<> 156:95d6b41a828b 2011 */
<> 156:95d6b41a828b 2012 /**
<> 156:95d6b41a828b 2013 * @brief Enable Transfer complete interrupt.
<> 156:95d6b41a828b 2014 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<> 156:95d6b41a828b 2015 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2016 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2017 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2018 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2019 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2020 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2021 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2022 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2023 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2024 * @retval None
<> 156:95d6b41a828b 2025 */
<> 156:95d6b41a828b 2026 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2027 {
<> 156:95d6b41a828b 2028 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<> 156:95d6b41a828b 2029 }
<> 156:95d6b41a828b 2030
<> 156:95d6b41a828b 2031 /**
<> 156:95d6b41a828b 2032 * @brief Enable Half transfer interrupt.
<> 156:95d6b41a828b 2033 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<> 156:95d6b41a828b 2034 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2035 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2036 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2037 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2038 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2039 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2040 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2041 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2042 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2043 * @retval None
<> 156:95d6b41a828b 2044 */
<> 156:95d6b41a828b 2045 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2046 {
<> 156:95d6b41a828b 2047 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<> 156:95d6b41a828b 2048 }
<> 156:95d6b41a828b 2049
<> 156:95d6b41a828b 2050 /**
<> 156:95d6b41a828b 2051 * @brief Enable Transfer error interrupt.
<> 156:95d6b41a828b 2052 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<> 156:95d6b41a828b 2053 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2054 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2055 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2056 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2057 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2058 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2059 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2060 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2061 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2062 * @retval None
<> 156:95d6b41a828b 2063 */
<> 156:95d6b41a828b 2064 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2065 {
<> 156:95d6b41a828b 2066 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<> 156:95d6b41a828b 2067 }
<> 156:95d6b41a828b 2068
<> 156:95d6b41a828b 2069 /**
<> 156:95d6b41a828b 2070 * @brief Disable Transfer complete interrupt.
<> 156:95d6b41a828b 2071 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<> 156:95d6b41a828b 2072 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2073 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2074 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2075 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2076 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2077 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2078 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2079 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2080 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2081 * @retval None
<> 156:95d6b41a828b 2082 */
<> 156:95d6b41a828b 2083 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2084 {
<> 156:95d6b41a828b 2085 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<> 156:95d6b41a828b 2086 }
<> 156:95d6b41a828b 2087
<> 156:95d6b41a828b 2088 /**
<> 156:95d6b41a828b 2089 * @brief Disable Half transfer interrupt.
<> 156:95d6b41a828b 2090 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<> 156:95d6b41a828b 2091 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2092 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2093 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2094 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2095 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2096 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2097 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2098 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2099 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2100 * @retval None
<> 156:95d6b41a828b 2101 */
<> 156:95d6b41a828b 2102 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2103 {
<> 156:95d6b41a828b 2104 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<> 156:95d6b41a828b 2105 }
<> 156:95d6b41a828b 2106
<> 156:95d6b41a828b 2107 /**
<> 156:95d6b41a828b 2108 * @brief Disable Transfer error interrupt.
<> 156:95d6b41a828b 2109 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<> 156:95d6b41a828b 2110 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2111 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2112 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2113 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2114 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2115 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2116 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2117 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2118 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2119 * @retval None
<> 156:95d6b41a828b 2120 */
<> 156:95d6b41a828b 2121 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2122 {
<> 156:95d6b41a828b 2123 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<> 156:95d6b41a828b 2124 }
<> 156:95d6b41a828b 2125
<> 156:95d6b41a828b 2126 /**
<> 156:95d6b41a828b 2127 * @brief Check if Transfer complete Interrupt is enabled.
<> 156:95d6b41a828b 2128 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<> 156:95d6b41a828b 2129 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2130 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2131 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2132 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2133 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2134 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2135 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2136 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2137 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2138 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 2139 */
<> 156:95d6b41a828b 2140 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2141 {
<> 156:95d6b41a828b 2142 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 2143 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<> 156:95d6b41a828b 2144 }
<> 156:95d6b41a828b 2145
<> 156:95d6b41a828b 2146 /**
<> 156:95d6b41a828b 2147 * @brief Check if Half transfer Interrupt is enabled.
<> 156:95d6b41a828b 2148 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<> 156:95d6b41a828b 2149 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2150 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2151 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2152 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2153 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2154 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2155 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2156 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2157 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2158 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 2159 */
<> 156:95d6b41a828b 2160 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2161 {
<> 156:95d6b41a828b 2162 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 2163 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<> 156:95d6b41a828b 2164 }
<> 156:95d6b41a828b 2165
<> 156:95d6b41a828b 2166 /**
<> 156:95d6b41a828b 2167 * @brief Check if Transfer error Interrupt is enabled.
<> 156:95d6b41a828b 2168 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<> 156:95d6b41a828b 2169 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2170 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2171 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2172 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2173 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2174 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2175 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2176 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2177 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2178 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 2179 */
<> 156:95d6b41a828b 2180 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2181 {
<> 156:95d6b41a828b 2182 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 2183 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<> 156:95d6b41a828b 2184 }
<> 156:95d6b41a828b 2185
<> 156:95d6b41a828b 2186 /**
<> 156:95d6b41a828b 2187 * @}
<> 156:95d6b41a828b 2188 */
<> 156:95d6b41a828b 2189
<> 156:95d6b41a828b 2190 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 2191 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<> 156:95d6b41a828b 2192 * @{
<> 156:95d6b41a828b 2193 */
<> 156:95d6b41a828b 2194
<> 156:95d6b41a828b 2195 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
<> 156:95d6b41a828b 2196 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<> 156:95d6b41a828b 2197 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<> 156:95d6b41a828b 2198
<> 156:95d6b41a828b 2199 /**
<> 156:95d6b41a828b 2200 * @}
<> 156:95d6b41a828b 2201 */
<> 156:95d6b41a828b 2202 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 2203
<> 156:95d6b41a828b 2204 /**
<> 156:95d6b41a828b 2205 * @}
<> 156:95d6b41a828b 2206 */
<> 156:95d6b41a828b 2207
<> 156:95d6b41a828b 2208 /**
<> 156:95d6b41a828b 2209 * @}
<> 156:95d6b41a828b 2210 */
<> 156:95d6b41a828b 2211
<> 156:95d6b41a828b 2212 #endif /* DMA1 || DMA2 */
<> 156:95d6b41a828b 2213
<> 156:95d6b41a828b 2214 /**
<> 156:95d6b41a828b 2215 * @}
<> 156:95d6b41a828b 2216 */
<> 156:95d6b41a828b 2217
<> 156:95d6b41a828b 2218 #ifdef __cplusplus
<> 156:95d6b41a828b 2219 }
<> 156:95d6b41a828b 2220 #endif
<> 156:95d6b41a828b 2221
<> 156:95d6b41a828b 2222 #endif /* __STM32F0xx_LL_DMA_H */
<> 156:95d6b41a828b 2223
<> 156:95d6b41a828b 2224 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/