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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_dma.h
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.4.0
<> 156:95d6b41a828b 6 * @date 27-May-2016
<> 156:95d6b41a828b 7 * @brief Header file of DMA LL module.
<> 156:95d6b41a828b 8 ******************************************************************************
<> 156:95d6b41a828b 9 * @attention
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 12 *
<> 156:95d6b41a828b 13 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 14 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 18 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 19 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 21 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 22 * without specific prior written permission.
<> 156:95d6b41a828b 23 *
<> 156:95d6b41a828b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 34 *
<> 156:95d6b41a828b 35 ******************************************************************************
<> 156:95d6b41a828b 36 */
<> 156:95d6b41a828b 37
<> 156:95d6b41a828b 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 156:95d6b41a828b 39 #ifndef __STM32F0xx_LL_DMA_H
<> 156:95d6b41a828b 40 #define __STM32F0xx_LL_DMA_H
<> 156:95d6b41a828b 41
<> 156:95d6b41a828b 42 #ifdef __cplusplus
<> 156:95d6b41a828b 43 extern "C" {
<> 156:95d6b41a828b 44 #endif
<> 156:95d6b41a828b 45
<> 156:95d6b41a828b 46 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 47 #include "stm32f0xx.h"
<> 156:95d6b41a828b 48
<> 156:95d6b41a828b 49 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 50 * @{
<> 156:95d6b41a828b 51 */
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 #if defined (DMA1) || defined (DMA2)
<> 156:95d6b41a828b 54
<> 156:95d6b41a828b 55 /** @defgroup DMA_LL DMA
<> 156:95d6b41a828b 56 * @{
<> 156:95d6b41a828b 57 */
<> 156:95d6b41a828b 58
<> 156:95d6b41a828b 59 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 60 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 61 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
<> 156:95d6b41a828b 62 * @{
<> 156:95d6b41a828b 63 */
<> 156:95d6b41a828b 64 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<> 156:95d6b41a828b 65 static const uint8_t CHANNEL_OFFSET_TAB[] =
<> 156:95d6b41a828b 66 {
<> 156:95d6b41a828b 67 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<> 156:95d6b41a828b 68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<> 156:95d6b41a828b 69 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<> 156:95d6b41a828b 70 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<> 156:95d6b41a828b 71 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<> 156:95d6b41a828b 72 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 73 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<> 156:95d6b41a828b 74 #endif /*DMA1_Channel6*/
<> 156:95d6b41a828b 75 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 76 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<> 156:95d6b41a828b 77 #endif /*DMA1_Channel7*/
<> 156:95d6b41a828b 78 };
<> 156:95d6b41a828b 79 /**
<> 156:95d6b41a828b 80 * @}
<> 156:95d6b41a828b 81 */
<> 156:95d6b41a828b 82
<> 156:95d6b41a828b 83 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 84 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
<> 156:95d6b41a828b 85 * @{
<> 156:95d6b41a828b 86 */
<> 156:95d6b41a828b 87 /* Define used to get CSELR register offset */
<> 156:95d6b41a828b 88 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
<> 156:95d6b41a828b 89
<> 156:95d6b41a828b 90 /* Defines used for the bit position in the register and perform offsets */
<> 156:95d6b41a828b 91 #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U)
<> 156:95d6b41a828b 92 /**
<> 156:95d6b41a828b 93 * @}
<> 156:95d6b41a828b 94 */
<> 156:95d6b41a828b 95
<> 156:95d6b41a828b 96 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 97 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 98 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
<> 156:95d6b41a828b 99 * @{
<> 156:95d6b41a828b 100 */
<> 156:95d6b41a828b 101 /**
<> 156:95d6b41a828b 102 * @}
<> 156:95d6b41a828b 103 */
<> 156:95d6b41a828b 104 #endif /*USE_FULL_LL_DRIVER*/
<> 156:95d6b41a828b 105
<> 156:95d6b41a828b 106 /* Exported types ------------------------------------------------------------*/
<> 156:95d6b41a828b 107 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 108 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<> 156:95d6b41a828b 109 * @{
<> 156:95d6b41a828b 110 */
<> 156:95d6b41a828b 111 typedef struct
<> 156:95d6b41a828b 112 {
<> 156:95d6b41a828b 113 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<> 156:95d6b41a828b 114 or as Source base address in case of memory to memory transfer direction.
<> 156:95d6b41a828b 115
<> 156:95d6b41a828b 116 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<> 156:95d6b41a828b 117
<> 156:95d6b41a828b 118 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<> 156:95d6b41a828b 119 or as Destination base address in case of memory to memory transfer direction.
<> 156:95d6b41a828b 120
<> 156:95d6b41a828b 121 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<> 156:95d6b41a828b 122
<> 156:95d6b41a828b 123 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 156:95d6b41a828b 124 from memory to memory or from peripheral to memory.
<> 156:95d6b41a828b 125 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<> 156:95d6b41a828b 126
<> 156:95d6b41a828b 127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<> 156:95d6b41a828b 128
<> 156:95d6b41a828b 129 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<> 156:95d6b41a828b 130 This parameter can be a value of @ref DMA_LL_EC_MODE
<> 156:95d6b41a828b 131 @note: The circular buffer mode cannot be used if the memory to memory
<> 156:95d6b41a828b 132 data transfer direction is configured on the selected Channel
<> 156:95d6b41a828b 133
<> 156:95d6b41a828b 134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<> 156:95d6b41a828b 135
<> 156:95d6b41a828b 136 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<> 156:95d6b41a828b 137 is incremented or not.
<> 156:95d6b41a828b 138 This parameter can be a value of @ref DMA_LL_EC_PERIPH
<> 156:95d6b41a828b 139
<> 156:95d6b41a828b 140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<> 156:95d6b41a828b 141
<> 156:95d6b41a828b 142 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<> 156:95d6b41a828b 143 is incremented or not.
<> 156:95d6b41a828b 144 This parameter can be a value of @ref DMA_LL_EC_MEMORY
<> 156:95d6b41a828b 145
<> 156:95d6b41a828b 146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<> 156:95d6b41a828b 147
<> 156:95d6b41a828b 148 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<> 156:95d6b41a828b 149 in case of memory to memory transfer direction.
<> 156:95d6b41a828b 150 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<> 156:95d6b41a828b 151
<> 156:95d6b41a828b 152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<> 156:95d6b41a828b 153
<> 156:95d6b41a828b 154 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<> 156:95d6b41a828b 155 in case of memory to memory transfer direction.
<> 156:95d6b41a828b 156 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<> 156:95d6b41a828b 157
<> 156:95d6b41a828b 158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<> 156:95d6b41a828b 159
<> 156:95d6b41a828b 160 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<> 156:95d6b41a828b 161 The data unit is equal to the source buffer configuration set in PeripheralSize
<> 156:95d6b41a828b 162 or MemorySize parameters depending in the transfer direction.
<> 156:95d6b41a828b 163 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<> 156:95d6b41a828b 164
<> 156:95d6b41a828b 165 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<> 156:95d6b41a828b 166 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 167
<> 156:95d6b41a828b 168 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
<> 156:95d6b41a828b 169 This parameter can be a value of @ref DMA_LL_EC_REQUEST
<> 156:95d6b41a828b 170
<> 156:95d6b41a828b 171 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
<> 156:95d6b41a828b 172 #endif
<> 156:95d6b41a828b 173
<> 156:95d6b41a828b 174 uint32_t Priority; /*!< Specifies the channel priority level.
<> 156:95d6b41a828b 175 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<> 156:95d6b41a828b 176
<> 156:95d6b41a828b 177 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<> 156:95d6b41a828b 178
<> 156:95d6b41a828b 179 } LL_DMA_InitTypeDef;
<> 156:95d6b41a828b 180 /**
<> 156:95d6b41a828b 181 * @}
<> 156:95d6b41a828b 182 */
<> 156:95d6b41a828b 183 #endif /*USE_FULL_LL_DRIVER*/
<> 156:95d6b41a828b 184
<> 156:95d6b41a828b 185 /* Exported constants --------------------------------------------------------*/
<> 156:95d6b41a828b 186 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<> 156:95d6b41a828b 187 * @{
<> 156:95d6b41a828b 188 */
<> 156:95d6b41a828b 189 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 156:95d6b41a828b 190 * @brief Flags defines which can be used with LL_DMA_WriteReg function
<> 156:95d6b41a828b 191 * @{
<> 156:95d6b41a828b 192 */
<> 156:95d6b41a828b 193 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
<> 156:95d6b41a828b 194 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
<> 156:95d6b41a828b 195 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
<> 156:95d6b41a828b 196 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
<> 156:95d6b41a828b 197 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
<> 156:95d6b41a828b 198 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
<> 156:95d6b41a828b 199 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
<> 156:95d6b41a828b 200 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
<> 156:95d6b41a828b 201 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
<> 156:95d6b41a828b 202 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
<> 156:95d6b41a828b 203 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
<> 156:95d6b41a828b 204 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
<> 156:95d6b41a828b 205 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
<> 156:95d6b41a828b 206 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
<> 156:95d6b41a828b 207 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
<> 156:95d6b41a828b 208 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
<> 156:95d6b41a828b 209 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
<> 156:95d6b41a828b 210 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
<> 156:95d6b41a828b 211 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
<> 156:95d6b41a828b 212 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
<> 156:95d6b41a828b 213 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 214 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
<> 156:95d6b41a828b 215 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
<> 156:95d6b41a828b 216 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
<> 156:95d6b41a828b 217 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
<> 156:95d6b41a828b 218 #endif
<> 156:95d6b41a828b 219 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 220 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
<> 156:95d6b41a828b 221 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
<> 156:95d6b41a828b 222 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
<> 156:95d6b41a828b 223 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
<> 156:95d6b41a828b 224 #endif
<> 156:95d6b41a828b 225 /**
<> 156:95d6b41a828b 226 * @}
<> 156:95d6b41a828b 227 */
<> 156:95d6b41a828b 228
<> 156:95d6b41a828b 229 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<> 156:95d6b41a828b 230 * @brief Flags defines which can be used with LL_DMA_ReadReg function
<> 156:95d6b41a828b 231 * @{
<> 156:95d6b41a828b 232 */
<> 156:95d6b41a828b 233 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
<> 156:95d6b41a828b 234 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
<> 156:95d6b41a828b 235 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
<> 156:95d6b41a828b 236 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
<> 156:95d6b41a828b 237 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
<> 156:95d6b41a828b 238 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
<> 156:95d6b41a828b 239 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
<> 156:95d6b41a828b 240 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
<> 156:95d6b41a828b 241 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
<> 156:95d6b41a828b 242 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
<> 156:95d6b41a828b 243 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
<> 156:95d6b41a828b 244 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
<> 156:95d6b41a828b 245 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
<> 156:95d6b41a828b 246 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
<> 156:95d6b41a828b 247 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
<> 156:95d6b41a828b 248 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
<> 156:95d6b41a828b 249 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
<> 156:95d6b41a828b 250 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
<> 156:95d6b41a828b 251 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
<> 156:95d6b41a828b 252 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
<> 156:95d6b41a828b 253 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 254 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
<> 156:95d6b41a828b 255 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
<> 156:95d6b41a828b 256 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
<> 156:95d6b41a828b 257 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
<> 156:95d6b41a828b 258 #endif
<> 156:95d6b41a828b 259 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 260 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
<> 156:95d6b41a828b 261 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
<> 156:95d6b41a828b 262 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
<> 156:95d6b41a828b 263 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
<> 156:95d6b41a828b 264 #endif
<> 156:95d6b41a828b 265 /**
<> 156:95d6b41a828b 266 * @}
<> 156:95d6b41a828b 267 */
<> 156:95d6b41a828b 268
<> 156:95d6b41a828b 269 /** @defgroup DMA_LL_EC_IT IT Defines
<> 156:95d6b41a828b 270 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<> 156:95d6b41a828b 271 * @{
<> 156:95d6b41a828b 272 */
<> 156:95d6b41a828b 273 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
<> 156:95d6b41a828b 274 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
<> 156:95d6b41a828b 275 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
<> 156:95d6b41a828b 276 /**
<> 156:95d6b41a828b 277 * @}
<> 156:95d6b41a828b 278 */
<> 156:95d6b41a828b 279
<> 156:95d6b41a828b 280 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<> 156:95d6b41a828b 281 * @{
<> 156:95d6b41a828b 282 */
<> 156:95d6b41a828b 283 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
<> 156:95d6b41a828b 284 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
<> 156:95d6b41a828b 285 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
<> 156:95d6b41a828b 286 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
<> 156:95d6b41a828b 287 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
<> 156:95d6b41a828b 288 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 289 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
<> 156:95d6b41a828b 290 #endif
<> 156:95d6b41a828b 291 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 292 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
<> 156:95d6b41a828b 293 #endif
<> 156:95d6b41a828b 294 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 295 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
<> 156:95d6b41a828b 296 #endif /*USE_FULL_LL_DRIVER*/
<> 156:95d6b41a828b 297 /**
<> 156:95d6b41a828b 298 * @}
<> 156:95d6b41a828b 299 */
<> 156:95d6b41a828b 300
<> 156:95d6b41a828b 301 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<> 156:95d6b41a828b 302 * @{
<> 156:95d6b41a828b 303 */
<> 156:95d6b41a828b 304 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
<> 156:95d6b41a828b 305 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
<> 156:95d6b41a828b 306 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
<> 156:95d6b41a828b 307 /**
<> 156:95d6b41a828b 308 * @}
<> 156:95d6b41a828b 309 */
<> 156:95d6b41a828b 310
<> 156:95d6b41a828b 311 /** @defgroup DMA_LL_EC_MODE Transfer mode
<> 156:95d6b41a828b 312 * @{
<> 156:95d6b41a828b 313 */
<> 156:95d6b41a828b 314 #define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */
<> 156:95d6b41a828b 315 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
<> 156:95d6b41a828b 316 /**
<> 156:95d6b41a828b 317 * @}
<> 156:95d6b41a828b 318 */
<> 156:95d6b41a828b 319
<> 156:95d6b41a828b 320 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<> 156:95d6b41a828b 321 * @{
<> 156:95d6b41a828b 322 */
<> 156:95d6b41a828b 323 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
<> 156:95d6b41a828b 324 #define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
<> 156:95d6b41a828b 325 /**
<> 156:95d6b41a828b 326 * @}
<> 156:95d6b41a828b 327 */
<> 156:95d6b41a828b 328
<> 156:95d6b41a828b 329 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<> 156:95d6b41a828b 330 * @{
<> 156:95d6b41a828b 331 */
<> 156:95d6b41a828b 332 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
<> 156:95d6b41a828b 333 #define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
<> 156:95d6b41a828b 334 /**
<> 156:95d6b41a828b 335 * @}
<> 156:95d6b41a828b 336 */
<> 156:95d6b41a828b 337
<> 156:95d6b41a828b 338 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<> 156:95d6b41a828b 339 * @{
<> 156:95d6b41a828b 340 */
<> 156:95d6b41a828b 341 #define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */
<> 156:95d6b41a828b 342 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
<> 156:95d6b41a828b 343 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
<> 156:95d6b41a828b 344 /**
<> 156:95d6b41a828b 345 * @}
<> 156:95d6b41a828b 346 */
<> 156:95d6b41a828b 347
<> 156:95d6b41a828b 348 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<> 156:95d6b41a828b 349 * @{
<> 156:95d6b41a828b 350 */
<> 156:95d6b41a828b 351 #define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */
<> 156:95d6b41a828b 352 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
<> 156:95d6b41a828b 353 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
<> 156:95d6b41a828b 354 /**
<> 156:95d6b41a828b 355 * @}
<> 156:95d6b41a828b 356 */
<> 156:95d6b41a828b 357
<> 156:95d6b41a828b 358 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<> 156:95d6b41a828b 359 * @{
<> 156:95d6b41a828b 360 */
<> 156:95d6b41a828b 361 #define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */
<> 156:95d6b41a828b 362 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
<> 156:95d6b41a828b 363 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
<> 156:95d6b41a828b 364 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
<> 156:95d6b41a828b 365 /**
<> 156:95d6b41a828b 366 * @}
<> 156:95d6b41a828b 367 */
<> 156:95d6b41a828b 368
<> 156:95d6b41a828b 369 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 370 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
<> 156:95d6b41a828b 371 * @{
<> 156:95d6b41a828b 372 */
<> 156:95d6b41a828b 373 #define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */
<> 156:95d6b41a828b 374 #define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */
<> 156:95d6b41a828b 375 #define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */
<> 156:95d6b41a828b 376 #define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */
<> 156:95d6b41a828b 377 #define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */
<> 156:95d6b41a828b 378 #define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */
<> 156:95d6b41a828b 379 #define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */
<> 156:95d6b41a828b 380 #define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */
<> 156:95d6b41a828b 381 #define LL_DMA_REQUEST_8 ((uint32_t)0x00000008U) /*!< DMA peripheral request 8 */
<> 156:95d6b41a828b 382 #define LL_DMA_REQUEST_9 ((uint32_t)0x00000009U) /*!< DMA peripheral request 9 */
<> 156:95d6b41a828b 383 #define LL_DMA_REQUEST_10 ((uint32_t)0x0000000AU) /*!< DMA peripheral request 10 */
<> 156:95d6b41a828b 384 #define LL_DMA_REQUEST_11 ((uint32_t)0x0000000BU) /*!< DMA peripheral request 11 */
<> 156:95d6b41a828b 385 #define LL_DMA_REQUEST_12 ((uint32_t)0x0000000CU) /*!< DMA peripheral request 12 */
<> 156:95d6b41a828b 386 #define LL_DMA_REQUEST_13 ((uint32_t)0x0000000DU) /*!< DMA peripheral request 13 */
<> 156:95d6b41a828b 387 #define LL_DMA_REQUEST_14 ((uint32_t)0x0000000EU) /*!< DMA peripheral request 14 */
<> 156:95d6b41a828b 388 #define LL_DMA_REQUEST_15 ((uint32_t)0x0000000FU) /*!< DMA peripheral request 15 */
<> 156:95d6b41a828b 389 /**
<> 156:95d6b41a828b 390 * @}
<> 156:95d6b41a828b 391 */
<> 156:95d6b41a828b 392 #endif
<> 156:95d6b41a828b 393
<> 156:95d6b41a828b 394 /**
<> 156:95d6b41a828b 395 * @}
<> 156:95d6b41a828b 396 */
<> 156:95d6b41a828b 397
<> 156:95d6b41a828b 398 /* Exported macro ------------------------------------------------------------*/
<> 156:95d6b41a828b 399 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<> 156:95d6b41a828b 400 * @{
<> 156:95d6b41a828b 401 */
<> 156:95d6b41a828b 402
<> 156:95d6b41a828b 403 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<> 156:95d6b41a828b 404 * @{
<> 156:95d6b41a828b 405 */
<> 156:95d6b41a828b 406 /**
<> 156:95d6b41a828b 407 * @brief Write a value in DMA register
<> 156:95d6b41a828b 408 * @param __INSTANCE__ DMA Instance
<> 156:95d6b41a828b 409 * @param __REG__ Register to be written
<> 156:95d6b41a828b 410 * @param __VALUE__ Value to be written in the register
<> 156:95d6b41a828b 411 * @retval None
<> 156:95d6b41a828b 412 */
<> 156:95d6b41a828b 413 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 156:95d6b41a828b 414
<> 156:95d6b41a828b 415 /**
<> 156:95d6b41a828b 416 * @brief Read a value in DMA register
<> 156:95d6b41a828b 417 * @param __INSTANCE__ DMA Instance
<> 156:95d6b41a828b 418 * @param __REG__ Register to be read
<> 156:95d6b41a828b 419 * @retval Register value
<> 156:95d6b41a828b 420 */
<> 156:95d6b41a828b 421 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 156:95d6b41a828b 422 /**
<> 156:95d6b41a828b 423 * @}
<> 156:95d6b41a828b 424 */
<> 156:95d6b41a828b 425
<> 156:95d6b41a828b 426 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<> 156:95d6b41a828b 427 * @{
<> 156:95d6b41a828b 428 */
<> 156:95d6b41a828b 429 /**
<> 156:95d6b41a828b 430 * @brief Convert DMAx_Channely into DMAx
<> 156:95d6b41a828b 431 * @param __CHANNEL_INSTANCE__ DMAx_Channely
<> 156:95d6b41a828b 432 * @retval DMAx
<> 156:95d6b41a828b 433 */
<> 156:95d6b41a828b 434 #if defined(DMA2)
<> 156:95d6b41a828b 435 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 436 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<> 156:95d6b41a828b 437 #else
<> 156:95d6b41a828b 438 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<> 156:95d6b41a828b 439 #endif
<> 156:95d6b41a828b 440
<> 156:95d6b41a828b 441 /**
<> 156:95d6b41a828b 442 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<> 156:95d6b41a828b 443 * @param __CHANNEL_INSTANCE__ DMAx_Channely
<> 156:95d6b41a828b 444 * @retval LL_DMA_CHANNEL_y
<> 156:95d6b41a828b 445 */
<> 156:95d6b41a828b 446 #if defined (DMA2)
<> 156:95d6b41a828b 447 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 156:95d6b41a828b 448 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 449 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 453 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 454 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 456 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 457 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 458 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 459 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 460 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 461 LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 462 #else
<> 156:95d6b41a828b 463 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 464 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 465 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 466 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 467 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 468 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 469 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 470 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 471 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 472 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 473 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 474 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 475 LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 476 #endif
<> 156:95d6b41a828b 477 #else
<> 156:95d6b41a828b 478 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
<> 156:95d6b41a828b 479 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 480 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 481 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 482 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 483 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 484 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 485 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 156:95d6b41a828b 486 LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 487 #elif defined (DMA1_Channel6)
<> 156:95d6b41a828b 488 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 489 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 490 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 491 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 492 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 493 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 156:95d6b41a828b 494 LL_DMA_CHANNEL_6)
<> 156:95d6b41a828b 495 #else
<> 156:95d6b41a828b 496 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 156:95d6b41a828b 497 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 156:95d6b41a828b 498 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 156:95d6b41a828b 499 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 156:95d6b41a828b 500 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 156:95d6b41a828b 501 LL_DMA_CHANNEL_5)
<> 156:95d6b41a828b 502 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 156:95d6b41a828b 503 #endif
<> 156:95d6b41a828b 504
<> 156:95d6b41a828b 505 /**
<> 156:95d6b41a828b 506 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<> 156:95d6b41a828b 507 * @param __DMA_INSTANCE__ DMAx
<> 156:95d6b41a828b 508 * @param __CHANNEL__ LL_DMA_CHANNEL_y
<> 156:95d6b41a828b 509 * @retval DMAx_Channely
<> 156:95d6b41a828b 510 */
<> 156:95d6b41a828b 511 #if defined (DMA2)
<> 156:95d6b41a828b 512 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 156:95d6b41a828b 513 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 514 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 515 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<> 156:95d6b41a828b 516 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 517 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<> 156:95d6b41a828b 518 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 519 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<> 156:95d6b41a828b 520 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 521 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<> 156:95d6b41a828b 522 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 523 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<> 156:95d6b41a828b 524 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 156:95d6b41a828b 525 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<> 156:95d6b41a828b 526 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<> 156:95d6b41a828b 527 DMA2_Channel7)
<> 156:95d6b41a828b 528 #else
<> 156:95d6b41a828b 529 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 530 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 531 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<> 156:95d6b41a828b 532 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 533 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<> 156:95d6b41a828b 534 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 535 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<> 156:95d6b41a828b 536 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 537 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<> 156:95d6b41a828b 538 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 539 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<> 156:95d6b41a828b 540 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 156:95d6b41a828b 541 DMA1_Channel7)
<> 156:95d6b41a828b 542 #endif
<> 156:95d6b41a828b 543 #else
<> 156:95d6b41a828b 544 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
<> 156:95d6b41a828b 545 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 546 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 547 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 548 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 549 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 550 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 551 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 156:95d6b41a828b 552 DMA1_Channel7)
<> 156:95d6b41a828b 553 #elif defined (DMA1_Channel6)
<> 156:95d6b41a828b 554 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 555 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 556 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 557 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 558 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 559 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 156:95d6b41a828b 560 DMA1_Channel6)
<> 156:95d6b41a828b 561 #else
<> 156:95d6b41a828b 562 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 156:95d6b41a828b 563 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 156:95d6b41a828b 564 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 156:95d6b41a828b 565 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 156:95d6b41a828b 566 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 156:95d6b41a828b 567 DMA1_Channel5)
<> 156:95d6b41a828b 568 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 156:95d6b41a828b 569 #endif
<> 156:95d6b41a828b 570
<> 156:95d6b41a828b 571 /**
<> 156:95d6b41a828b 572 * @}
<> 156:95d6b41a828b 573 */
<> 156:95d6b41a828b 574
<> 156:95d6b41a828b 575 /**
<> 156:95d6b41a828b 576 * @}
<> 156:95d6b41a828b 577 */
<> 156:95d6b41a828b 578
<> 156:95d6b41a828b 579 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 580 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<> 156:95d6b41a828b 581 * @{
<> 156:95d6b41a828b 582 */
<> 156:95d6b41a828b 583
<> 156:95d6b41a828b 584 /** @defgroup DMA_LL_EF_Configuration Configuration
<> 156:95d6b41a828b 585 * @{
<> 156:95d6b41a828b 586 */
<> 156:95d6b41a828b 587 /**
<> 156:95d6b41a828b 588 * @brief Enable DMA channel.
<> 156:95d6b41a828b 589 * @rmtoll CCR EN LL_DMA_EnableChannel
<> 156:95d6b41a828b 590 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 591 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 592 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 593 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 594 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 595 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 596 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 597 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 598 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 599 * @retval None
<> 156:95d6b41a828b 600 */
<> 156:95d6b41a828b 601 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 602 {
<> 156:95d6b41a828b 603 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<> 156:95d6b41a828b 604 }
<> 156:95d6b41a828b 605
<> 156:95d6b41a828b 606 /**
<> 156:95d6b41a828b 607 * @brief Disable DMA channel.
<> 156:95d6b41a828b 608 * @rmtoll CCR EN LL_DMA_DisableChannel
<> 156:95d6b41a828b 609 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 610 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 611 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 612 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 613 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 614 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 615 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 616 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 617 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 618 * @retval None
<> 156:95d6b41a828b 619 */
<> 156:95d6b41a828b 620 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 621 {
<> 156:95d6b41a828b 622 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<> 156:95d6b41a828b 623 }
<> 156:95d6b41a828b 624
<> 156:95d6b41a828b 625 /**
<> 156:95d6b41a828b 626 * @brief Check if DMA channel is enabled or disabled.
<> 156:95d6b41a828b 627 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
<> 156:95d6b41a828b 628 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 629 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 630 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 631 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 632 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 633 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 634 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 635 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 636 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 637 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 638 */
<> 156:95d6b41a828b 639 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 640 {
<> 156:95d6b41a828b 641 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 642 DMA_CCR_EN) == (DMA_CCR_EN));
<> 156:95d6b41a828b 643 }
<> 156:95d6b41a828b 644
<> 156:95d6b41a828b 645 /**
<> 156:95d6b41a828b 646 * @brief Configure all parameters link to DMA transfer.
<> 156:95d6b41a828b 647 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 648 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 649 * CCR CIRC LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 650 * CCR PINC LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 651 * CCR MINC LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 652 * CCR PSIZE LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 653 * CCR MSIZE LL_DMA_ConfigTransfer\n
<> 156:95d6b41a828b 654 * CCR PL LL_DMA_ConfigTransfer
<> 156:95d6b41a828b 655 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 656 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 657 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 658 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 659 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 660 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 661 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 662 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 663 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 664 * @param Configuration This parameter must be a combination of all the following values:
<> 156:95d6b41a828b 665 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 666 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<> 156:95d6b41a828b 667 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<> 156:95d6b41a828b 668 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<> 156:95d6b41a828b 669 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<> 156:95d6b41a828b 670 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<> 156:95d6b41a828b 671 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<> 156:95d6b41a828b 672 * @retval None
<> 156:95d6b41a828b 673 */
<> 156:95d6b41a828b 674 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<> 156:95d6b41a828b 675 {
<> 156:95d6b41a828b 676 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 677 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
<> 156:95d6b41a828b 678 Configuration);
<> 156:95d6b41a828b 679 }
<> 156:95d6b41a828b 680
<> 156:95d6b41a828b 681 /**
<> 156:95d6b41a828b 682 * @brief Set Data transfer direction (read from peripheral or from memory).
<> 156:95d6b41a828b 683 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<> 156:95d6b41a828b 684 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
<> 156:95d6b41a828b 685 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 686 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 687 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 688 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 689 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 690 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 691 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 692 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 693 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 694 * @param Direction This parameter can be one of the following values:
<> 156:95d6b41a828b 695 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 156:95d6b41a828b 696 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 156:95d6b41a828b 697 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 698 * @retval None
<> 156:95d6b41a828b 699 */
<> 156:95d6b41a828b 700 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<> 156:95d6b41a828b 701 {
<> 156:95d6b41a828b 702 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 703 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
<> 156:95d6b41a828b 704 }
<> 156:95d6b41a828b 705
<> 156:95d6b41a828b 706 /**
<> 156:95d6b41a828b 707 * @brief Get Data transfer direction (read from peripheral or from memory).
<> 156:95d6b41a828b 708 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<> 156:95d6b41a828b 709 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
<> 156:95d6b41a828b 710 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 711 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 712 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 713 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 714 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 715 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 716 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 717 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 718 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 719 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 720 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 156:95d6b41a828b 721 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 156:95d6b41a828b 722 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 723 */
<> 156:95d6b41a828b 724 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 725 {
<> 156:95d6b41a828b 726 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 727 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
<> 156:95d6b41a828b 728 }
<> 156:95d6b41a828b 729
<> 156:95d6b41a828b 730 /**
<> 156:95d6b41a828b 731 * @brief Set DMA mode circular or normal.
<> 156:95d6b41a828b 732 * @note The circular buffer mode cannot be used if the memory-to-memory
<> 156:95d6b41a828b 733 * data transfer is configured on the selected Channel.
<> 156:95d6b41a828b 734 * @rmtoll CCR CIRC LL_DMA_SetMode
<> 156:95d6b41a828b 735 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 736 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 737 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 738 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 739 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 740 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 741 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 742 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 743 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 744 * @param Mode This parameter can be one of the following values:
<> 156:95d6b41a828b 745 * @arg @ref LL_DMA_MODE_NORMAL
<> 156:95d6b41a828b 746 * @arg @ref LL_DMA_MODE_CIRCULAR
<> 156:95d6b41a828b 747 * @retval None
<> 156:95d6b41a828b 748 */
<> 156:95d6b41a828b 749 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<> 156:95d6b41a828b 750 {
<> 156:95d6b41a828b 751 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<> 156:95d6b41a828b 752 Mode);
<> 156:95d6b41a828b 753 }
<> 156:95d6b41a828b 754
<> 156:95d6b41a828b 755 /**
<> 156:95d6b41a828b 756 * @brief Get DMA mode circular or normal.
<> 156:95d6b41a828b 757 * @rmtoll CCR CIRC LL_DMA_GetMode
<> 156:95d6b41a828b 758 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 759 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 760 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 761 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 762 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 763 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 764 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 765 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 766 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 767 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 768 * @arg @ref LL_DMA_MODE_NORMAL
<> 156:95d6b41a828b 769 * @arg @ref LL_DMA_MODE_CIRCULAR
<> 156:95d6b41a828b 770 */
<> 156:95d6b41a828b 771 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 772 {
<> 156:95d6b41a828b 773 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 774 DMA_CCR_CIRC));
<> 156:95d6b41a828b 775 }
<> 156:95d6b41a828b 776
<> 156:95d6b41a828b 777 /**
<> 156:95d6b41a828b 778 * @brief Set Peripheral increment mode.
<> 156:95d6b41a828b 779 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<> 156:95d6b41a828b 780 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 781 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 782 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 783 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 784 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 785 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 786 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 787 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 788 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 789 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<> 156:95d6b41a828b 790 * @arg @ref LL_DMA_PERIPH_INCREMENT
<> 156:95d6b41a828b 791 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
<> 156:95d6b41a828b 792 * @retval None
<> 156:95d6b41a828b 793 */
<> 156:95d6b41a828b 794 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<> 156:95d6b41a828b 795 {
<> 156:95d6b41a828b 796 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<> 156:95d6b41a828b 797 PeriphOrM2MSrcIncMode);
<> 156:95d6b41a828b 798 }
<> 156:95d6b41a828b 799
<> 156:95d6b41a828b 800 /**
<> 156:95d6b41a828b 801 * @brief Get Peripheral increment mode.
<> 156:95d6b41a828b 802 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<> 156:95d6b41a828b 803 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 804 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 805 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 806 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 807 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 808 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 809 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 810 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 811 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 812 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 813 * @arg @ref LL_DMA_PERIPH_INCREMENT
<> 156:95d6b41a828b 814 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
<> 156:95d6b41a828b 815 */
<> 156:95d6b41a828b 816 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 817 {
<> 156:95d6b41a828b 818 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 819 DMA_CCR_PINC));
<> 156:95d6b41a828b 820 }
<> 156:95d6b41a828b 821
<> 156:95d6b41a828b 822 /**
<> 156:95d6b41a828b 823 * @brief Set Memory increment mode.
<> 156:95d6b41a828b 824 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<> 156:95d6b41a828b 825 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 826 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 827 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 828 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 829 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 830 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 831 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 832 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 833 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 834 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<> 156:95d6b41a828b 835 * @arg @ref LL_DMA_MEMORY_INCREMENT
<> 156:95d6b41a828b 836 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
<> 156:95d6b41a828b 837 * @retval None
<> 156:95d6b41a828b 838 */
<> 156:95d6b41a828b 839 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<> 156:95d6b41a828b 840 {
<> 156:95d6b41a828b 841 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<> 156:95d6b41a828b 842 MemoryOrM2MDstIncMode);
<> 156:95d6b41a828b 843 }
<> 156:95d6b41a828b 844
<> 156:95d6b41a828b 845 /**
<> 156:95d6b41a828b 846 * @brief Get Memory increment mode.
<> 156:95d6b41a828b 847 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<> 156:95d6b41a828b 848 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 849 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 850 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 851 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 852 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 853 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 854 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 855 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 856 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 857 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 858 * @arg @ref LL_DMA_MEMORY_INCREMENT
<> 156:95d6b41a828b 859 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
<> 156:95d6b41a828b 860 */
<> 156:95d6b41a828b 861 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 862 {
<> 156:95d6b41a828b 863 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 864 DMA_CCR_MINC));
<> 156:95d6b41a828b 865 }
<> 156:95d6b41a828b 866
<> 156:95d6b41a828b 867 /**
<> 156:95d6b41a828b 868 * @brief Set Peripheral size.
<> 156:95d6b41a828b 869 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<> 156:95d6b41a828b 870 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 871 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 872 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 873 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 874 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 875 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 876 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 877 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 878 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 879 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<> 156:95d6b41a828b 880 * @arg @ref LL_DMA_PDATAALIGN_BYTE
<> 156:95d6b41a828b 881 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<> 156:95d6b41a828b 882 * @arg @ref LL_DMA_PDATAALIGN_WORD
<> 156:95d6b41a828b 883 * @retval None
<> 156:95d6b41a828b 884 */
<> 156:95d6b41a828b 885 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<> 156:95d6b41a828b 886 {
<> 156:95d6b41a828b 887 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<> 156:95d6b41a828b 888 PeriphOrM2MSrcDataSize);
<> 156:95d6b41a828b 889 }
<> 156:95d6b41a828b 890
<> 156:95d6b41a828b 891 /**
<> 156:95d6b41a828b 892 * @brief Get Peripheral size.
<> 156:95d6b41a828b 893 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<> 156:95d6b41a828b 894 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 895 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 896 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 897 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 898 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 899 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 900 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 901 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 902 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 903 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 904 * @arg @ref LL_DMA_PDATAALIGN_BYTE
<> 156:95d6b41a828b 905 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<> 156:95d6b41a828b 906 * @arg @ref LL_DMA_PDATAALIGN_WORD
<> 156:95d6b41a828b 907 */
<> 156:95d6b41a828b 908 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 909 {
<> 156:95d6b41a828b 910 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 911 DMA_CCR_PSIZE));
<> 156:95d6b41a828b 912 }
<> 156:95d6b41a828b 913
<> 156:95d6b41a828b 914 /**
<> 156:95d6b41a828b 915 * @brief Set Memory size.
<> 156:95d6b41a828b 916 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<> 156:95d6b41a828b 917 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 918 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 919 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 920 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 921 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 922 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 923 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 924 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 925 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 926 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<> 156:95d6b41a828b 927 * @arg @ref LL_DMA_MDATAALIGN_BYTE
<> 156:95d6b41a828b 928 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<> 156:95d6b41a828b 929 * @arg @ref LL_DMA_MDATAALIGN_WORD
<> 156:95d6b41a828b 930 * @retval None
<> 156:95d6b41a828b 931 */
<> 156:95d6b41a828b 932 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<> 156:95d6b41a828b 933 {
<> 156:95d6b41a828b 934 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<> 156:95d6b41a828b 935 MemoryOrM2MDstDataSize);
<> 156:95d6b41a828b 936 }
<> 156:95d6b41a828b 937
<> 156:95d6b41a828b 938 /**
<> 156:95d6b41a828b 939 * @brief Get Memory size.
<> 156:95d6b41a828b 940 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<> 156:95d6b41a828b 941 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 942 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 943 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 944 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 945 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 946 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 947 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 948 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 949 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 950 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 951 * @arg @ref LL_DMA_MDATAALIGN_BYTE
<> 156:95d6b41a828b 952 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<> 156:95d6b41a828b 953 * @arg @ref LL_DMA_MDATAALIGN_WORD
<> 156:95d6b41a828b 954 */
<> 156:95d6b41a828b 955 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 956 {
<> 156:95d6b41a828b 957 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 958 DMA_CCR_MSIZE));
<> 156:95d6b41a828b 959 }
<> 156:95d6b41a828b 960
<> 156:95d6b41a828b 961 /**
<> 156:95d6b41a828b 962 * @brief Set Channel priority level.
<> 156:95d6b41a828b 963 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<> 156:95d6b41a828b 964 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 965 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 966 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 967 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 968 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 969 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 970 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 971 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 972 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 973 * @param Priority This parameter can be one of the following values:
<> 156:95d6b41a828b 974 * @arg @ref LL_DMA_PRIORITY_LOW
<> 156:95d6b41a828b 975 * @arg @ref LL_DMA_PRIORITY_MEDIUM
<> 156:95d6b41a828b 976 * @arg @ref LL_DMA_PRIORITY_HIGH
<> 156:95d6b41a828b 977 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
<> 156:95d6b41a828b 978 * @retval None
<> 156:95d6b41a828b 979 */
<> 156:95d6b41a828b 980 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<> 156:95d6b41a828b 981 {
<> 156:95d6b41a828b 982 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<> 156:95d6b41a828b 983 Priority);
<> 156:95d6b41a828b 984 }
<> 156:95d6b41a828b 985
<> 156:95d6b41a828b 986 /**
<> 156:95d6b41a828b 987 * @brief Get Channel priority level.
<> 156:95d6b41a828b 988 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<> 156:95d6b41a828b 989 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 990 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 991 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 992 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 993 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 994 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 995 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 996 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 997 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 998 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 999 * @arg @ref LL_DMA_PRIORITY_LOW
<> 156:95d6b41a828b 1000 * @arg @ref LL_DMA_PRIORITY_MEDIUM
<> 156:95d6b41a828b 1001 * @arg @ref LL_DMA_PRIORITY_HIGH
<> 156:95d6b41a828b 1002 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
<> 156:95d6b41a828b 1003 */
<> 156:95d6b41a828b 1004 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1005 {
<> 156:95d6b41a828b 1006 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 1007 DMA_CCR_PL));
<> 156:95d6b41a828b 1008 }
<> 156:95d6b41a828b 1009
<> 156:95d6b41a828b 1010 /**
<> 156:95d6b41a828b 1011 * @brief Set Number of data to transfer.
<> 156:95d6b41a828b 1012 * @note This action has no effect if
<> 156:95d6b41a828b 1013 * channel is enabled.
<> 156:95d6b41a828b 1014 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
<> 156:95d6b41a828b 1015 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1016 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1017 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1018 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1019 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1020 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1021 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1022 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1023 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1024 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<> 156:95d6b41a828b 1025 * @retval None
<> 156:95d6b41a828b 1026 */
<> 156:95d6b41a828b 1027 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<> 156:95d6b41a828b 1028 {
<> 156:95d6b41a828b 1029 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<> 156:95d6b41a828b 1030 DMA_CNDTR_NDT, NbData);
<> 156:95d6b41a828b 1031 }
<> 156:95d6b41a828b 1032
<> 156:95d6b41a828b 1033 /**
<> 156:95d6b41a828b 1034 * @brief Get Number of data to transfer.
<> 156:95d6b41a828b 1035 * @note Once the channel is enabled, the return value indicate the
<> 156:95d6b41a828b 1036 * remaining bytes to be transmitted.
<> 156:95d6b41a828b 1037 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
<> 156:95d6b41a828b 1038 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1039 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1040 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1041 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1042 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1043 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1044 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1045 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1046 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1047 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1048 */
<> 156:95d6b41a828b 1049 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1050 {
<> 156:95d6b41a828b 1051 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<> 156:95d6b41a828b 1052 DMA_CNDTR_NDT));
<> 156:95d6b41a828b 1053 }
<> 156:95d6b41a828b 1054
<> 156:95d6b41a828b 1055 /**
<> 156:95d6b41a828b 1056 * @brief Configure the Source and Destination addresses.
<> 156:95d6b41a828b 1057 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
<> 156:95d6b41a828b 1058 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<> 156:95d6b41a828b 1059 * CMAR MA LL_DMA_ConfigAddresses
<> 156:95d6b41a828b 1060 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1061 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1062 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1063 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1064 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1065 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1066 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1067 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1068 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1069 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1070 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1071 * @param Direction This parameter can be one of the following values:
<> 156:95d6b41a828b 1072 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 156:95d6b41a828b 1073 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 156:95d6b41a828b 1074 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 156:95d6b41a828b 1075 * @retval None
<> 156:95d6b41a828b 1076 */
<> 156:95d6b41a828b 1077 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<> 156:95d6b41a828b 1078 uint32_t DstAddress, uint32_t Direction)
<> 156:95d6b41a828b 1079 {
<> 156:95d6b41a828b 1080 /* Direction Memory to Periph */
<> 156:95d6b41a828b 1081 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<> 156:95d6b41a828b 1082 {
<> 156:95d6b41a828b 1083 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 156:95d6b41a828b 1084 SrcAddress);
<> 156:95d6b41a828b 1085 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 156:95d6b41a828b 1086 DstAddress);
<> 156:95d6b41a828b 1087 }
<> 156:95d6b41a828b 1088 /* Direction Periph to Memory and Memory to Memory */
<> 156:95d6b41a828b 1089 else
<> 156:95d6b41a828b 1090 {
<> 156:95d6b41a828b 1091 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 156:95d6b41a828b 1092 SrcAddress);
<> 156:95d6b41a828b 1093 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 156:95d6b41a828b 1094 DstAddress);
<> 156:95d6b41a828b 1095 }
<> 156:95d6b41a828b 1096 }
<> 156:95d6b41a828b 1097
<> 156:95d6b41a828b 1098 /**
<> 156:95d6b41a828b 1099 * @brief Set the Memory address.
<> 156:95d6b41a828b 1100 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 156:95d6b41a828b 1101 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<> 156:95d6b41a828b 1102 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1103 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1104 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1105 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1106 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1107 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1108 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1109 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1110 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1111 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1112 * @retval None
<> 156:95d6b41a828b 1113 */
<> 156:95d6b41a828b 1114 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 156:95d6b41a828b 1115 {
<> 156:95d6b41a828b 1116 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 156:95d6b41a828b 1117 MemoryAddress);
<> 156:95d6b41a828b 1118 }
<> 156:95d6b41a828b 1119
<> 156:95d6b41a828b 1120 /**
<> 156:95d6b41a828b 1121 * @brief Set the Peripheral address.
<> 156:95d6b41a828b 1122 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 156:95d6b41a828b 1123 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<> 156:95d6b41a828b 1124 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1125 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1126 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1127 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1128 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1129 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1130 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1131 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1132 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1133 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1134 * @retval None
<> 156:95d6b41a828b 1135 */
<> 156:95d6b41a828b 1136 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<> 156:95d6b41a828b 1137 {
<> 156:95d6b41a828b 1138 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 156:95d6b41a828b 1139 PeriphAddress);
<> 156:95d6b41a828b 1140 }
<> 156:95d6b41a828b 1141
<> 156:95d6b41a828b 1142 /**
<> 156:95d6b41a828b 1143 * @brief Get Memory address.
<> 156:95d6b41a828b 1144 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 156:95d6b41a828b 1145 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<> 156:95d6b41a828b 1146 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1147 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1148 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1149 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1150 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1151 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1152 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1153 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1154 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1155 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1156 */
<> 156:95d6b41a828b 1157 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1158 {
<> 156:95d6b41a828b 1159 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<> 156:95d6b41a828b 1160 DMA_CMAR_MA));
<> 156:95d6b41a828b 1161 }
<> 156:95d6b41a828b 1162
<> 156:95d6b41a828b 1163 /**
<> 156:95d6b41a828b 1164 * @brief Get Peripheral address.
<> 156:95d6b41a828b 1165 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 156:95d6b41a828b 1166 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<> 156:95d6b41a828b 1167 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1168 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1169 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1170 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1171 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1172 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1173 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1174 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1175 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1176 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1177 */
<> 156:95d6b41a828b 1178 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1179 {
<> 156:95d6b41a828b 1180 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<> 156:95d6b41a828b 1181 DMA_CPAR_PA));
<> 156:95d6b41a828b 1182 }
<> 156:95d6b41a828b 1183
<> 156:95d6b41a828b 1184 /**
<> 156:95d6b41a828b 1185 * @brief Set the Memory to Memory Source address.
<> 156:95d6b41a828b 1186 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 156:95d6b41a828b 1187 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<> 156:95d6b41a828b 1188 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1189 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1190 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1191 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1192 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1193 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1194 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1195 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1196 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1197 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1198 * @retval None
<> 156:95d6b41a828b 1199 */
<> 156:95d6b41a828b 1200 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 156:95d6b41a828b 1201 {
<> 156:95d6b41a828b 1202 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 156:95d6b41a828b 1203 MemoryAddress);
<> 156:95d6b41a828b 1204 }
<> 156:95d6b41a828b 1205
<> 156:95d6b41a828b 1206 /**
<> 156:95d6b41a828b 1207 * @brief Set the Memory to Memory Destination address.
<> 156:95d6b41a828b 1208 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 156:95d6b41a828b 1209 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<> 156:95d6b41a828b 1210 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1211 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1212 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1213 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1214 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1215 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1216 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1217 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1218 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1219 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1220 * @retval None
<> 156:95d6b41a828b 1221 */
<> 156:95d6b41a828b 1222 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 156:95d6b41a828b 1223 {
<> 156:95d6b41a828b 1224 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 156:95d6b41a828b 1225 MemoryAddress);
<> 156:95d6b41a828b 1226 }
<> 156:95d6b41a828b 1227
<> 156:95d6b41a828b 1228 /**
<> 156:95d6b41a828b 1229 * @brief Get the Memory to Memory Source address.
<> 156:95d6b41a828b 1230 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 156:95d6b41a828b 1231 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<> 156:95d6b41a828b 1232 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1233 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1234 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1235 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1236 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1237 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1238 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1239 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1240 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1241 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1242 */
<> 156:95d6b41a828b 1243 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1244 {
<> 156:95d6b41a828b 1245 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<> 156:95d6b41a828b 1246 DMA_CPAR_PA));
<> 156:95d6b41a828b 1247 }
<> 156:95d6b41a828b 1248
<> 156:95d6b41a828b 1249 /**
<> 156:95d6b41a828b 1250 * @brief Get the Memory to Memory Destination address.
<> 156:95d6b41a828b 1251 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 156:95d6b41a828b 1252 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<> 156:95d6b41a828b 1253 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1254 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1255 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1256 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1257 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1258 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1259 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1260 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1261 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1262 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 156:95d6b41a828b 1263 */
<> 156:95d6b41a828b 1264 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1265 {
<> 156:95d6b41a828b 1266 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<> 156:95d6b41a828b 1267 DMA_CMAR_MA));
<> 156:95d6b41a828b 1268 }
<> 156:95d6b41a828b 1269
<> 156:95d6b41a828b 1270 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 1271 /**
<> 156:95d6b41a828b 1272 * @brief Set DMA request for DMA instance on Channel x.
<> 156:95d6b41a828b 1273 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
<> 156:95d6b41a828b 1274 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1275 * CSELR C2S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1276 * CSELR C3S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1277 * CSELR C4S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1278 * CSELR C5S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1279 * CSELR C6S LL_DMA_SetPeriphRequest\n
<> 156:95d6b41a828b 1280 * CSELR C7S LL_DMA_SetPeriphRequest
<> 156:95d6b41a828b 1281 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1282 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1283 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1284 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1285 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1286 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1287 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1288 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1289 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1290 * @param PeriphRequest This parameter can be one of the following values:
<> 156:95d6b41a828b 1291 * @arg @ref LL_DMA_REQUEST_0
<> 156:95d6b41a828b 1292 * @arg @ref LL_DMA_REQUEST_1
<> 156:95d6b41a828b 1293 * @arg @ref LL_DMA_REQUEST_2
<> 156:95d6b41a828b 1294 * @arg @ref LL_DMA_REQUEST_3
<> 156:95d6b41a828b 1295 * @arg @ref LL_DMA_REQUEST_4
<> 156:95d6b41a828b 1296 * @arg @ref LL_DMA_REQUEST_5
<> 156:95d6b41a828b 1297 * @arg @ref LL_DMA_REQUEST_6
<> 156:95d6b41a828b 1298 * @arg @ref LL_DMA_REQUEST_7
<> 156:95d6b41a828b 1299 * @arg @ref LL_DMA_REQUEST_8
<> 156:95d6b41a828b 1300 * @arg @ref LL_DMA_REQUEST_9
<> 156:95d6b41a828b 1301 * @arg @ref LL_DMA_REQUEST_10
<> 156:95d6b41a828b 1302 * @arg @ref LL_DMA_REQUEST_11
<> 156:95d6b41a828b 1303 * @arg @ref LL_DMA_REQUEST_12
<> 156:95d6b41a828b 1304 * @arg @ref LL_DMA_REQUEST_13
<> 156:95d6b41a828b 1305 * @arg @ref LL_DMA_REQUEST_14
<> 156:95d6b41a828b 1306 * @arg @ref LL_DMA_REQUEST_15
<> 156:95d6b41a828b 1307 * @retval None
<> 156:95d6b41a828b 1308 */
<> 156:95d6b41a828b 1309 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
<> 156:95d6b41a828b 1310 {
<> 156:95d6b41a828b 1311 MODIFY_REG(DMAx->CSELR,
<> 156:95d6b41a828b 1312 DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
<> 156:95d6b41a828b 1313 }
<> 156:95d6b41a828b 1314
<> 156:95d6b41a828b 1315 /**
<> 156:95d6b41a828b 1316 * @brief Get DMA request for DMA instance on Channel x.
<> 156:95d6b41a828b 1317 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1318 * CSELR C2S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1319 * CSELR C3S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1320 * CSELR C4S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1321 * CSELR C5S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1322 * CSELR C6S LL_DMA_GetPeriphRequest\n
<> 156:95d6b41a828b 1323 * CSELR C7S LL_DMA_GetPeriphRequest
<> 156:95d6b41a828b 1324 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1325 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 1326 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 1327 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 1328 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 1329 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 1330 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 1331 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 1332 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 1333 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 1334 * @arg @ref LL_DMA_REQUEST_0
<> 156:95d6b41a828b 1335 * @arg @ref LL_DMA_REQUEST_1
<> 156:95d6b41a828b 1336 * @arg @ref LL_DMA_REQUEST_2
<> 156:95d6b41a828b 1337 * @arg @ref LL_DMA_REQUEST_3
<> 156:95d6b41a828b 1338 * @arg @ref LL_DMA_REQUEST_4
<> 156:95d6b41a828b 1339 * @arg @ref LL_DMA_REQUEST_5
<> 156:95d6b41a828b 1340 * @arg @ref LL_DMA_REQUEST_6
<> 156:95d6b41a828b 1341 * @arg @ref LL_DMA_REQUEST_7
<> 156:95d6b41a828b 1342 * @arg @ref LL_DMA_REQUEST_8
<> 156:95d6b41a828b 1343 * @arg @ref LL_DMA_REQUEST_9
<> 156:95d6b41a828b 1344 * @arg @ref LL_DMA_REQUEST_10
<> 156:95d6b41a828b 1345 * @arg @ref LL_DMA_REQUEST_11
<> 156:95d6b41a828b 1346 * @arg @ref LL_DMA_REQUEST_12
<> 156:95d6b41a828b 1347 * @arg @ref LL_DMA_REQUEST_13
<> 156:95d6b41a828b 1348 * @arg @ref LL_DMA_REQUEST_14
<> 156:95d6b41a828b 1349 * @arg @ref LL_DMA_REQUEST_15
<> 156:95d6b41a828b 1350 */
<> 156:95d6b41a828b 1351 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 1352 {
<> 156:95d6b41a828b 1353 return (READ_BIT(DMAx->CSELR,
<> 156:95d6b41a828b 1354 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
<> 156:95d6b41a828b 1355 }
<> 156:95d6b41a828b 1356 #endif
<> 156:95d6b41a828b 1357
<> 156:95d6b41a828b 1358 /**
<> 156:95d6b41a828b 1359 * @}
<> 156:95d6b41a828b 1360 */
<> 156:95d6b41a828b 1361
<> 156:95d6b41a828b 1362 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<> 156:95d6b41a828b 1363 * @{
<> 156:95d6b41a828b 1364 */
<> 156:95d6b41a828b 1365
<> 156:95d6b41a828b 1366 /**
<> 156:95d6b41a828b 1367 * @brief Get Channel 1 global interrupt flag.
<> 156:95d6b41a828b 1368 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<> 156:95d6b41a828b 1369 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1370 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1371 */
<> 156:95d6b41a828b 1372 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1373 {
<> 156:95d6b41a828b 1374 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<> 156:95d6b41a828b 1375 }
<> 156:95d6b41a828b 1376
<> 156:95d6b41a828b 1377 /**
<> 156:95d6b41a828b 1378 * @brief Get Channel 2 global interrupt flag.
<> 156:95d6b41a828b 1379 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<> 156:95d6b41a828b 1380 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1381 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1382 */
<> 156:95d6b41a828b 1383 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1384 {
<> 156:95d6b41a828b 1385 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<> 156:95d6b41a828b 1386 }
<> 156:95d6b41a828b 1387
<> 156:95d6b41a828b 1388 /**
<> 156:95d6b41a828b 1389 * @brief Get Channel 3 global interrupt flag.
<> 156:95d6b41a828b 1390 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<> 156:95d6b41a828b 1391 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1392 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1393 */
<> 156:95d6b41a828b 1394 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1395 {
<> 156:95d6b41a828b 1396 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<> 156:95d6b41a828b 1397 }
<> 156:95d6b41a828b 1398
<> 156:95d6b41a828b 1399 /**
<> 156:95d6b41a828b 1400 * @brief Get Channel 4 global interrupt flag.
<> 156:95d6b41a828b 1401 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<> 156:95d6b41a828b 1402 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1403 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1404 */
<> 156:95d6b41a828b 1405 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1406 {
<> 156:95d6b41a828b 1407 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<> 156:95d6b41a828b 1408 }
<> 156:95d6b41a828b 1409
<> 156:95d6b41a828b 1410 /**
<> 156:95d6b41a828b 1411 * @brief Get Channel 5 global interrupt flag.
<> 156:95d6b41a828b 1412 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<> 156:95d6b41a828b 1413 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1414 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1415 */
<> 156:95d6b41a828b 1416 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1417 {
<> 156:95d6b41a828b 1418 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<> 156:95d6b41a828b 1419 }
<> 156:95d6b41a828b 1420
<> 156:95d6b41a828b 1421 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1422 /**
<> 156:95d6b41a828b 1423 * @brief Get Channel 6 global interrupt flag.
<> 156:95d6b41a828b 1424 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<> 156:95d6b41a828b 1425 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1426 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1427 */
<> 156:95d6b41a828b 1428 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1429 {
<> 156:95d6b41a828b 1430 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<> 156:95d6b41a828b 1431 }
<> 156:95d6b41a828b 1432 #endif
<> 156:95d6b41a828b 1433
<> 156:95d6b41a828b 1434 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1435 /**
<> 156:95d6b41a828b 1436 * @brief Get Channel 7 global interrupt flag.
<> 156:95d6b41a828b 1437 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<> 156:95d6b41a828b 1438 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1439 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1440 */
<> 156:95d6b41a828b 1441 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1442 {
<> 156:95d6b41a828b 1443 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<> 156:95d6b41a828b 1444 }
<> 156:95d6b41a828b 1445 #endif
<> 156:95d6b41a828b 1446
<> 156:95d6b41a828b 1447 /**
<> 156:95d6b41a828b 1448 * @brief Get Channel 1 transfer complete flag.
<> 156:95d6b41a828b 1449 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<> 156:95d6b41a828b 1450 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1451 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1452 */
<> 156:95d6b41a828b 1453 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1454 {
<> 156:95d6b41a828b 1455 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<> 156:95d6b41a828b 1456 }
<> 156:95d6b41a828b 1457
<> 156:95d6b41a828b 1458 /**
<> 156:95d6b41a828b 1459 * @brief Get Channel 2 transfer complete flag.
<> 156:95d6b41a828b 1460 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<> 156:95d6b41a828b 1461 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1462 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1463 */
<> 156:95d6b41a828b 1464 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1465 {
<> 156:95d6b41a828b 1466 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<> 156:95d6b41a828b 1467 }
<> 156:95d6b41a828b 1468
<> 156:95d6b41a828b 1469 /**
<> 156:95d6b41a828b 1470 * @brief Get Channel 3 transfer complete flag.
<> 156:95d6b41a828b 1471 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<> 156:95d6b41a828b 1472 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1473 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1474 */
<> 156:95d6b41a828b 1475 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1476 {
<> 156:95d6b41a828b 1477 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<> 156:95d6b41a828b 1478 }
<> 156:95d6b41a828b 1479
<> 156:95d6b41a828b 1480 /**
<> 156:95d6b41a828b 1481 * @brief Get Channel 4 transfer complete flag.
<> 156:95d6b41a828b 1482 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<> 156:95d6b41a828b 1483 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1484 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1485 */
<> 156:95d6b41a828b 1486 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1487 {
<> 156:95d6b41a828b 1488 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<> 156:95d6b41a828b 1489 }
<> 156:95d6b41a828b 1490
<> 156:95d6b41a828b 1491 /**
<> 156:95d6b41a828b 1492 * @brief Get Channel 5 transfer complete flag.
<> 156:95d6b41a828b 1493 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<> 156:95d6b41a828b 1494 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1495 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1496 */
<> 156:95d6b41a828b 1497 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1498 {
<> 156:95d6b41a828b 1499 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<> 156:95d6b41a828b 1500 }
<> 156:95d6b41a828b 1501
<> 156:95d6b41a828b 1502 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1503 /**
<> 156:95d6b41a828b 1504 * @brief Get Channel 6 transfer complete flag.
<> 156:95d6b41a828b 1505 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<> 156:95d6b41a828b 1506 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1507 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1508 */
<> 156:95d6b41a828b 1509 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1510 {
<> 156:95d6b41a828b 1511 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<> 156:95d6b41a828b 1512 }
<> 156:95d6b41a828b 1513 #endif
<> 156:95d6b41a828b 1514
<> 156:95d6b41a828b 1515 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1516 /**
<> 156:95d6b41a828b 1517 * @brief Get Channel 7 transfer complete flag.
<> 156:95d6b41a828b 1518 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<> 156:95d6b41a828b 1519 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1520 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1521 */
<> 156:95d6b41a828b 1522 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1523 {
<> 156:95d6b41a828b 1524 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<> 156:95d6b41a828b 1525 }
<> 156:95d6b41a828b 1526 #endif
<> 156:95d6b41a828b 1527
<> 156:95d6b41a828b 1528 /**
<> 156:95d6b41a828b 1529 * @brief Get Channel 1 half transfer flag.
<> 156:95d6b41a828b 1530 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<> 156:95d6b41a828b 1531 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1532 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1533 */
<> 156:95d6b41a828b 1534 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1535 {
<> 156:95d6b41a828b 1536 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<> 156:95d6b41a828b 1537 }
<> 156:95d6b41a828b 1538
<> 156:95d6b41a828b 1539 /**
<> 156:95d6b41a828b 1540 * @brief Get Channel 2 half transfer flag.
<> 156:95d6b41a828b 1541 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<> 156:95d6b41a828b 1542 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1543 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1544 */
<> 156:95d6b41a828b 1545 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1546 {
<> 156:95d6b41a828b 1547 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<> 156:95d6b41a828b 1548 }
<> 156:95d6b41a828b 1549
<> 156:95d6b41a828b 1550 /**
<> 156:95d6b41a828b 1551 * @brief Get Channel 3 half transfer flag.
<> 156:95d6b41a828b 1552 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<> 156:95d6b41a828b 1553 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1554 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1555 */
<> 156:95d6b41a828b 1556 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1557 {
<> 156:95d6b41a828b 1558 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<> 156:95d6b41a828b 1559 }
<> 156:95d6b41a828b 1560
<> 156:95d6b41a828b 1561 /**
<> 156:95d6b41a828b 1562 * @brief Get Channel 4 half transfer flag.
<> 156:95d6b41a828b 1563 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<> 156:95d6b41a828b 1564 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1565 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1566 */
<> 156:95d6b41a828b 1567 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1568 {
<> 156:95d6b41a828b 1569 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<> 156:95d6b41a828b 1570 }
<> 156:95d6b41a828b 1571
<> 156:95d6b41a828b 1572 /**
<> 156:95d6b41a828b 1573 * @brief Get Channel 5 half transfer flag.
<> 156:95d6b41a828b 1574 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<> 156:95d6b41a828b 1575 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1576 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1577 */
<> 156:95d6b41a828b 1578 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1579 {
<> 156:95d6b41a828b 1580 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<> 156:95d6b41a828b 1581 }
<> 156:95d6b41a828b 1582
<> 156:95d6b41a828b 1583 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1584 /**
<> 156:95d6b41a828b 1585 * @brief Get Channel 6 half transfer flag.
<> 156:95d6b41a828b 1586 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<> 156:95d6b41a828b 1587 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1588 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1589 */
<> 156:95d6b41a828b 1590 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1591 {
<> 156:95d6b41a828b 1592 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<> 156:95d6b41a828b 1593 }
<> 156:95d6b41a828b 1594 #endif
<> 156:95d6b41a828b 1595
<> 156:95d6b41a828b 1596 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1597 /**
<> 156:95d6b41a828b 1598 * @brief Get Channel 7 half transfer flag.
<> 156:95d6b41a828b 1599 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<> 156:95d6b41a828b 1600 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1601 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1602 */
<> 156:95d6b41a828b 1603 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1604 {
<> 156:95d6b41a828b 1605 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<> 156:95d6b41a828b 1606 }
<> 156:95d6b41a828b 1607 #endif
<> 156:95d6b41a828b 1608
<> 156:95d6b41a828b 1609 /**
<> 156:95d6b41a828b 1610 * @brief Get Channel 1 transfer error flag.
<> 156:95d6b41a828b 1611 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<> 156:95d6b41a828b 1612 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1613 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1614 */
<> 156:95d6b41a828b 1615 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1616 {
<> 156:95d6b41a828b 1617 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<> 156:95d6b41a828b 1618 }
<> 156:95d6b41a828b 1619
<> 156:95d6b41a828b 1620 /**
<> 156:95d6b41a828b 1621 * @brief Get Channel 2 transfer error flag.
<> 156:95d6b41a828b 1622 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<> 156:95d6b41a828b 1623 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1624 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1625 */
<> 156:95d6b41a828b 1626 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1627 {
<> 156:95d6b41a828b 1628 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<> 156:95d6b41a828b 1629 }
<> 156:95d6b41a828b 1630
<> 156:95d6b41a828b 1631 /**
<> 156:95d6b41a828b 1632 * @brief Get Channel 3 transfer error flag.
<> 156:95d6b41a828b 1633 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<> 156:95d6b41a828b 1634 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1635 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1636 */
<> 156:95d6b41a828b 1637 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1638 {
<> 156:95d6b41a828b 1639 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<> 156:95d6b41a828b 1640 }
<> 156:95d6b41a828b 1641
<> 156:95d6b41a828b 1642 /**
<> 156:95d6b41a828b 1643 * @brief Get Channel 4 transfer error flag.
<> 156:95d6b41a828b 1644 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<> 156:95d6b41a828b 1645 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1646 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1647 */
<> 156:95d6b41a828b 1648 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1649 {
<> 156:95d6b41a828b 1650 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<> 156:95d6b41a828b 1651 }
<> 156:95d6b41a828b 1652
<> 156:95d6b41a828b 1653 /**
<> 156:95d6b41a828b 1654 * @brief Get Channel 5 transfer error flag.
<> 156:95d6b41a828b 1655 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<> 156:95d6b41a828b 1656 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1657 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1658 */
<> 156:95d6b41a828b 1659 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1660 {
<> 156:95d6b41a828b 1661 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<> 156:95d6b41a828b 1662 }
<> 156:95d6b41a828b 1663
<> 156:95d6b41a828b 1664 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1665 /**
<> 156:95d6b41a828b 1666 * @brief Get Channel 6 transfer error flag.
<> 156:95d6b41a828b 1667 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<> 156:95d6b41a828b 1668 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1669 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1670 */
<> 156:95d6b41a828b 1671 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1672 {
<> 156:95d6b41a828b 1673 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<> 156:95d6b41a828b 1674 }
<> 156:95d6b41a828b 1675 #endif
<> 156:95d6b41a828b 1676
<> 156:95d6b41a828b 1677 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1678 /**
<> 156:95d6b41a828b 1679 * @brief Get Channel 7 transfer error flag.
<> 156:95d6b41a828b 1680 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<> 156:95d6b41a828b 1681 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1682 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 1683 */
<> 156:95d6b41a828b 1684 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1685 {
<> 156:95d6b41a828b 1686 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<> 156:95d6b41a828b 1687 }
<> 156:95d6b41a828b 1688 #endif
<> 156:95d6b41a828b 1689
<> 156:95d6b41a828b 1690 /**
<> 156:95d6b41a828b 1691 * @brief Clear Channel 1 global interrupt flag.
<> 156:95d6b41a828b 1692 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<> 156:95d6b41a828b 1693 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1694 * @retval None
<> 156:95d6b41a828b 1695 */
<> 156:95d6b41a828b 1696 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1697 {
<> 156:95d6b41a828b 1698 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
<> 156:95d6b41a828b 1699 }
<> 156:95d6b41a828b 1700
<> 156:95d6b41a828b 1701 /**
<> 156:95d6b41a828b 1702 * @brief Clear Channel 2 global interrupt flag.
<> 156:95d6b41a828b 1703 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<> 156:95d6b41a828b 1704 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1705 * @retval None
<> 156:95d6b41a828b 1706 */
<> 156:95d6b41a828b 1707 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1708 {
<> 156:95d6b41a828b 1709 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
<> 156:95d6b41a828b 1710 }
<> 156:95d6b41a828b 1711
<> 156:95d6b41a828b 1712 /**
<> 156:95d6b41a828b 1713 * @brief Clear Channel 3 global interrupt flag.
<> 156:95d6b41a828b 1714 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<> 156:95d6b41a828b 1715 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1716 * @retval None
<> 156:95d6b41a828b 1717 */
<> 156:95d6b41a828b 1718 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1719 {
<> 156:95d6b41a828b 1720 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
<> 156:95d6b41a828b 1721 }
<> 156:95d6b41a828b 1722
<> 156:95d6b41a828b 1723 /**
<> 156:95d6b41a828b 1724 * @brief Clear Channel 4 global interrupt flag.
<> 156:95d6b41a828b 1725 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<> 156:95d6b41a828b 1726 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1727 * @retval None
<> 156:95d6b41a828b 1728 */
<> 156:95d6b41a828b 1729 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1730 {
<> 156:95d6b41a828b 1731 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
<> 156:95d6b41a828b 1732 }
<> 156:95d6b41a828b 1733
<> 156:95d6b41a828b 1734 /**
<> 156:95d6b41a828b 1735 * @brief Clear Channel 5 global interrupt flag.
<> 156:95d6b41a828b 1736 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<> 156:95d6b41a828b 1737 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1738 * @retval None
<> 156:95d6b41a828b 1739 */
<> 156:95d6b41a828b 1740 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1741 {
<> 156:95d6b41a828b 1742 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
<> 156:95d6b41a828b 1743 }
<> 156:95d6b41a828b 1744
<> 156:95d6b41a828b 1745 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1746 /**
<> 156:95d6b41a828b 1747 * @brief Clear Channel 6 global interrupt flag.
<> 156:95d6b41a828b 1748 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<> 156:95d6b41a828b 1749 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1750 * @retval None
<> 156:95d6b41a828b 1751 */
<> 156:95d6b41a828b 1752 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1753 {
<> 156:95d6b41a828b 1754 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
<> 156:95d6b41a828b 1755 }
<> 156:95d6b41a828b 1756 #endif
<> 156:95d6b41a828b 1757
<> 156:95d6b41a828b 1758 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1759 /**
<> 156:95d6b41a828b 1760 * @brief Clear Channel 7 global interrupt flag.
<> 156:95d6b41a828b 1761 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<> 156:95d6b41a828b 1762 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1763 * @retval None
<> 156:95d6b41a828b 1764 */
<> 156:95d6b41a828b 1765 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1766 {
<> 156:95d6b41a828b 1767 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
<> 156:95d6b41a828b 1768 }
<> 156:95d6b41a828b 1769 #endif
<> 156:95d6b41a828b 1770
<> 156:95d6b41a828b 1771 /**
<> 156:95d6b41a828b 1772 * @brief Clear Channel 1 transfer complete flag.
<> 156:95d6b41a828b 1773 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<> 156:95d6b41a828b 1774 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1775 * @retval None
<> 156:95d6b41a828b 1776 */
<> 156:95d6b41a828b 1777 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1778 {
<> 156:95d6b41a828b 1779 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
<> 156:95d6b41a828b 1780 }
<> 156:95d6b41a828b 1781
<> 156:95d6b41a828b 1782 /**
<> 156:95d6b41a828b 1783 * @brief Clear Channel 2 transfer complete flag.
<> 156:95d6b41a828b 1784 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<> 156:95d6b41a828b 1785 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1786 * @retval None
<> 156:95d6b41a828b 1787 */
<> 156:95d6b41a828b 1788 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1789 {
<> 156:95d6b41a828b 1790 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
<> 156:95d6b41a828b 1791 }
<> 156:95d6b41a828b 1792
<> 156:95d6b41a828b 1793 /**
<> 156:95d6b41a828b 1794 * @brief Clear Channel 3 transfer complete flag.
<> 156:95d6b41a828b 1795 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<> 156:95d6b41a828b 1796 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1797 * @retval None
<> 156:95d6b41a828b 1798 */
<> 156:95d6b41a828b 1799 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1800 {
<> 156:95d6b41a828b 1801 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
<> 156:95d6b41a828b 1802 }
<> 156:95d6b41a828b 1803
<> 156:95d6b41a828b 1804 /**
<> 156:95d6b41a828b 1805 * @brief Clear Channel 4 transfer complete flag.
<> 156:95d6b41a828b 1806 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<> 156:95d6b41a828b 1807 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1808 * @retval None
<> 156:95d6b41a828b 1809 */
<> 156:95d6b41a828b 1810 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1811 {
<> 156:95d6b41a828b 1812 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
<> 156:95d6b41a828b 1813 }
<> 156:95d6b41a828b 1814
<> 156:95d6b41a828b 1815 /**
<> 156:95d6b41a828b 1816 * @brief Clear Channel 5 transfer complete flag.
<> 156:95d6b41a828b 1817 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<> 156:95d6b41a828b 1818 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1819 * @retval None
<> 156:95d6b41a828b 1820 */
<> 156:95d6b41a828b 1821 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1822 {
<> 156:95d6b41a828b 1823 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
<> 156:95d6b41a828b 1824 }
<> 156:95d6b41a828b 1825
<> 156:95d6b41a828b 1826 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1827 /**
<> 156:95d6b41a828b 1828 * @brief Clear Channel 6 transfer complete flag.
<> 156:95d6b41a828b 1829 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<> 156:95d6b41a828b 1830 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1831 * @retval None
<> 156:95d6b41a828b 1832 */
<> 156:95d6b41a828b 1833 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1834 {
<> 156:95d6b41a828b 1835 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
<> 156:95d6b41a828b 1836 }
<> 156:95d6b41a828b 1837 #endif
<> 156:95d6b41a828b 1838
<> 156:95d6b41a828b 1839 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1840 /**
<> 156:95d6b41a828b 1841 * @brief Clear Channel 7 transfer complete flag.
<> 156:95d6b41a828b 1842 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<> 156:95d6b41a828b 1843 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1844 * @retval None
<> 156:95d6b41a828b 1845 */
<> 156:95d6b41a828b 1846 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1847 {
<> 156:95d6b41a828b 1848 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
<> 156:95d6b41a828b 1849 }
<> 156:95d6b41a828b 1850 #endif
<> 156:95d6b41a828b 1851
<> 156:95d6b41a828b 1852 /**
<> 156:95d6b41a828b 1853 * @brief Clear Channel 1 half transfer flag.
<> 156:95d6b41a828b 1854 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<> 156:95d6b41a828b 1855 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1856 * @retval None
<> 156:95d6b41a828b 1857 */
<> 156:95d6b41a828b 1858 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1859 {
<> 156:95d6b41a828b 1860 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
<> 156:95d6b41a828b 1861 }
<> 156:95d6b41a828b 1862
<> 156:95d6b41a828b 1863 /**
<> 156:95d6b41a828b 1864 * @brief Clear Channel 2 half transfer flag.
<> 156:95d6b41a828b 1865 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<> 156:95d6b41a828b 1866 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1867 * @retval None
<> 156:95d6b41a828b 1868 */
<> 156:95d6b41a828b 1869 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1870 {
<> 156:95d6b41a828b 1871 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
<> 156:95d6b41a828b 1872 }
<> 156:95d6b41a828b 1873
<> 156:95d6b41a828b 1874 /**
<> 156:95d6b41a828b 1875 * @brief Clear Channel 3 half transfer flag.
<> 156:95d6b41a828b 1876 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<> 156:95d6b41a828b 1877 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1878 * @retval None
<> 156:95d6b41a828b 1879 */
<> 156:95d6b41a828b 1880 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1881 {
<> 156:95d6b41a828b 1882 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
<> 156:95d6b41a828b 1883 }
<> 156:95d6b41a828b 1884
<> 156:95d6b41a828b 1885 /**
<> 156:95d6b41a828b 1886 * @brief Clear Channel 4 half transfer flag.
<> 156:95d6b41a828b 1887 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<> 156:95d6b41a828b 1888 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1889 * @retval None
<> 156:95d6b41a828b 1890 */
<> 156:95d6b41a828b 1891 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1892 {
<> 156:95d6b41a828b 1893 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
<> 156:95d6b41a828b 1894 }
<> 156:95d6b41a828b 1895
<> 156:95d6b41a828b 1896 /**
<> 156:95d6b41a828b 1897 * @brief Clear Channel 5 half transfer flag.
<> 156:95d6b41a828b 1898 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<> 156:95d6b41a828b 1899 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1900 * @retval None
<> 156:95d6b41a828b 1901 */
<> 156:95d6b41a828b 1902 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1903 {
<> 156:95d6b41a828b 1904 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
<> 156:95d6b41a828b 1905 }
<> 156:95d6b41a828b 1906
<> 156:95d6b41a828b 1907 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1908 /**
<> 156:95d6b41a828b 1909 * @brief Clear Channel 6 half transfer flag.
<> 156:95d6b41a828b 1910 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<> 156:95d6b41a828b 1911 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1912 * @retval None
<> 156:95d6b41a828b 1913 */
<> 156:95d6b41a828b 1914 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1915 {
<> 156:95d6b41a828b 1916 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
<> 156:95d6b41a828b 1917 }
<> 156:95d6b41a828b 1918 #endif
<> 156:95d6b41a828b 1919
<> 156:95d6b41a828b 1920 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 1921 /**
<> 156:95d6b41a828b 1922 * @brief Clear Channel 7 half transfer flag.
<> 156:95d6b41a828b 1923 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<> 156:95d6b41a828b 1924 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1925 * @retval None
<> 156:95d6b41a828b 1926 */
<> 156:95d6b41a828b 1927 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1928 {
<> 156:95d6b41a828b 1929 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
<> 156:95d6b41a828b 1930 }
<> 156:95d6b41a828b 1931 #endif
<> 156:95d6b41a828b 1932
<> 156:95d6b41a828b 1933 /**
<> 156:95d6b41a828b 1934 * @brief Clear Channel 1 transfer error flag.
<> 156:95d6b41a828b 1935 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<> 156:95d6b41a828b 1936 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1937 * @retval None
<> 156:95d6b41a828b 1938 */
<> 156:95d6b41a828b 1939 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1940 {
<> 156:95d6b41a828b 1941 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
<> 156:95d6b41a828b 1942 }
<> 156:95d6b41a828b 1943
<> 156:95d6b41a828b 1944 /**
<> 156:95d6b41a828b 1945 * @brief Clear Channel 2 transfer error flag.
<> 156:95d6b41a828b 1946 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<> 156:95d6b41a828b 1947 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1948 * @retval None
<> 156:95d6b41a828b 1949 */
<> 156:95d6b41a828b 1950 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1951 {
<> 156:95d6b41a828b 1952 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
<> 156:95d6b41a828b 1953 }
<> 156:95d6b41a828b 1954
<> 156:95d6b41a828b 1955 /**
<> 156:95d6b41a828b 1956 * @brief Clear Channel 3 transfer error flag.
<> 156:95d6b41a828b 1957 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<> 156:95d6b41a828b 1958 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1959 * @retval None
<> 156:95d6b41a828b 1960 */
<> 156:95d6b41a828b 1961 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1962 {
<> 156:95d6b41a828b 1963 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
<> 156:95d6b41a828b 1964 }
<> 156:95d6b41a828b 1965
<> 156:95d6b41a828b 1966 /**
<> 156:95d6b41a828b 1967 * @brief Clear Channel 4 transfer error flag.
<> 156:95d6b41a828b 1968 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<> 156:95d6b41a828b 1969 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1970 * @retval None
<> 156:95d6b41a828b 1971 */
<> 156:95d6b41a828b 1972 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1973 {
<> 156:95d6b41a828b 1974 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
<> 156:95d6b41a828b 1975 }
<> 156:95d6b41a828b 1976
<> 156:95d6b41a828b 1977 /**
<> 156:95d6b41a828b 1978 * @brief Clear Channel 5 transfer error flag.
<> 156:95d6b41a828b 1979 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<> 156:95d6b41a828b 1980 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1981 * @retval None
<> 156:95d6b41a828b 1982 */
<> 156:95d6b41a828b 1983 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1984 {
<> 156:95d6b41a828b 1985 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
<> 156:95d6b41a828b 1986 }
<> 156:95d6b41a828b 1987
<> 156:95d6b41a828b 1988 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 1989 /**
<> 156:95d6b41a828b 1990 * @brief Clear Channel 6 transfer error flag.
<> 156:95d6b41a828b 1991 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<> 156:95d6b41a828b 1992 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 1993 * @retval None
<> 156:95d6b41a828b 1994 */
<> 156:95d6b41a828b 1995 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 1996 {
<> 156:95d6b41a828b 1997 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
<> 156:95d6b41a828b 1998 }
<> 156:95d6b41a828b 1999 #endif
<> 156:95d6b41a828b 2000
<> 156:95d6b41a828b 2001 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 2002 /**
<> 156:95d6b41a828b 2003 * @brief Clear Channel 7 transfer error flag.
<> 156:95d6b41a828b 2004 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<> 156:95d6b41a828b 2005 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2006 * @retval None
<> 156:95d6b41a828b 2007 */
<> 156:95d6b41a828b 2008 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<> 156:95d6b41a828b 2009 {
<> 156:95d6b41a828b 2010 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
<> 156:95d6b41a828b 2011 }
<> 156:95d6b41a828b 2012 #endif
<> 156:95d6b41a828b 2013
<> 156:95d6b41a828b 2014 /**
<> 156:95d6b41a828b 2015 * @}
<> 156:95d6b41a828b 2016 */
<> 156:95d6b41a828b 2017
<> 156:95d6b41a828b 2018 /** @defgroup DMA_LL_EF_IT_Management IT_Management
<> 156:95d6b41a828b 2019 * @{
<> 156:95d6b41a828b 2020 */
<> 156:95d6b41a828b 2021 /**
<> 156:95d6b41a828b 2022 * @brief Enable Transfer complete interrupt.
<> 156:95d6b41a828b 2023 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<> 156:95d6b41a828b 2024 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2025 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2026 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2027 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2028 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2029 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2030 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2031 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2032 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2033 * @retval None
<> 156:95d6b41a828b 2034 */
<> 156:95d6b41a828b 2035 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2036 {
<> 156:95d6b41a828b 2037 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<> 156:95d6b41a828b 2038 }
<> 156:95d6b41a828b 2039
<> 156:95d6b41a828b 2040 /**
<> 156:95d6b41a828b 2041 * @brief Enable Half transfer interrupt.
<> 156:95d6b41a828b 2042 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<> 156:95d6b41a828b 2043 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2044 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2045 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2046 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2047 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2048 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2049 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2050 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2051 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2052 * @retval None
<> 156:95d6b41a828b 2053 */
<> 156:95d6b41a828b 2054 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2055 {
<> 156:95d6b41a828b 2056 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<> 156:95d6b41a828b 2057 }
<> 156:95d6b41a828b 2058
<> 156:95d6b41a828b 2059 /**
<> 156:95d6b41a828b 2060 * @brief Enable Transfer error interrupt.
<> 156:95d6b41a828b 2061 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<> 156:95d6b41a828b 2062 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2063 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2064 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2065 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2066 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2067 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2068 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2069 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2070 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2071 * @retval None
<> 156:95d6b41a828b 2072 */
<> 156:95d6b41a828b 2073 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2074 {
<> 156:95d6b41a828b 2075 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<> 156:95d6b41a828b 2076 }
<> 156:95d6b41a828b 2077
<> 156:95d6b41a828b 2078 /**
<> 156:95d6b41a828b 2079 * @brief Disable Transfer complete interrupt.
<> 156:95d6b41a828b 2080 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<> 156:95d6b41a828b 2081 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2082 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2083 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2084 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2085 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2086 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2087 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2088 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2089 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2090 * @retval None
<> 156:95d6b41a828b 2091 */
<> 156:95d6b41a828b 2092 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2093 {
<> 156:95d6b41a828b 2094 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<> 156:95d6b41a828b 2095 }
<> 156:95d6b41a828b 2096
<> 156:95d6b41a828b 2097 /**
<> 156:95d6b41a828b 2098 * @brief Disable Half transfer interrupt.
<> 156:95d6b41a828b 2099 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<> 156:95d6b41a828b 2100 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2101 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2102 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2103 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2104 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2105 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2106 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2107 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2108 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2109 * @retval None
<> 156:95d6b41a828b 2110 */
<> 156:95d6b41a828b 2111 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2112 {
<> 156:95d6b41a828b 2113 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<> 156:95d6b41a828b 2114 }
<> 156:95d6b41a828b 2115
<> 156:95d6b41a828b 2116 /**
<> 156:95d6b41a828b 2117 * @brief Disable Transfer error interrupt.
<> 156:95d6b41a828b 2118 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<> 156:95d6b41a828b 2119 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2120 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2121 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2122 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2123 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2124 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2125 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2126 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2127 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2128 * @retval None
<> 156:95d6b41a828b 2129 */
<> 156:95d6b41a828b 2130 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2131 {
<> 156:95d6b41a828b 2132 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<> 156:95d6b41a828b 2133 }
<> 156:95d6b41a828b 2134
<> 156:95d6b41a828b 2135 /**
<> 156:95d6b41a828b 2136 * @brief Check if Transfer complete Interrupt is enabled.
<> 156:95d6b41a828b 2137 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<> 156:95d6b41a828b 2138 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2139 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2140 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2141 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2142 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2143 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2144 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2145 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2146 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2147 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 2148 */
<> 156:95d6b41a828b 2149 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2150 {
<> 156:95d6b41a828b 2151 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 2152 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<> 156:95d6b41a828b 2153 }
<> 156:95d6b41a828b 2154
<> 156:95d6b41a828b 2155 /**
<> 156:95d6b41a828b 2156 * @brief Check if Half transfer Interrupt is enabled.
<> 156:95d6b41a828b 2157 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<> 156:95d6b41a828b 2158 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2159 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2160 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2161 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2162 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2163 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2164 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2165 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2166 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2167 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 2168 */
<> 156:95d6b41a828b 2169 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2170 {
<> 156:95d6b41a828b 2171 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 2172 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<> 156:95d6b41a828b 2173 }
<> 156:95d6b41a828b 2174
<> 156:95d6b41a828b 2175 /**
<> 156:95d6b41a828b 2176 * @brief Check if Transfer error Interrupt is enabled.
<> 156:95d6b41a828b 2177 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<> 156:95d6b41a828b 2178 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 2179 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 2180 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 2181 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 2182 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 2183 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 2184 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 2185 * @arg @ref LL_DMA_CHANNEL_6
<> 156:95d6b41a828b 2186 * @arg @ref LL_DMA_CHANNEL_7
<> 156:95d6b41a828b 2187 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 2188 */
<> 156:95d6b41a828b 2189 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 2190 {
<> 156:95d6b41a828b 2191 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 156:95d6b41a828b 2192 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<> 156:95d6b41a828b 2193 }
<> 156:95d6b41a828b 2194
<> 156:95d6b41a828b 2195 /**
<> 156:95d6b41a828b 2196 * @}
<> 156:95d6b41a828b 2197 */
<> 156:95d6b41a828b 2198
<> 156:95d6b41a828b 2199 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 2200 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<> 156:95d6b41a828b 2201 * @{
<> 156:95d6b41a828b 2202 */
<> 156:95d6b41a828b 2203
<> 156:95d6b41a828b 2204 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
<> 156:95d6b41a828b 2205 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<> 156:95d6b41a828b 2206 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<> 156:95d6b41a828b 2207
<> 156:95d6b41a828b 2208 /**
<> 156:95d6b41a828b 2209 * @}
<> 156:95d6b41a828b 2210 */
<> 156:95d6b41a828b 2211 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 2212
<> 156:95d6b41a828b 2213 /**
<> 156:95d6b41a828b 2214 * @}
<> 156:95d6b41a828b 2215 */
<> 156:95d6b41a828b 2216
<> 156:95d6b41a828b 2217 /**
<> 156:95d6b41a828b 2218 * @}
<> 156:95d6b41a828b 2219 */
<> 156:95d6b41a828b 2220
<> 156:95d6b41a828b 2221 #endif /* DMA1 || DMA2 */
<> 156:95d6b41a828b 2222
<> 156:95d6b41a828b 2223 /**
<> 156:95d6b41a828b 2224 * @}
<> 156:95d6b41a828b 2225 */
<> 156:95d6b41a828b 2226
<> 156:95d6b41a828b 2227 #ifdef __cplusplus
<> 156:95d6b41a828b 2228 }
<> 156:95d6b41a828b 2229 #endif
<> 156:95d6b41a828b 2230
<> 156:95d6b41a828b 2231 #endif /* __STM32F0xx_LL_DMA_H */
<> 156:95d6b41a828b 2232
<> 156:95d6b41a828b 2233 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/