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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_usart_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief Header file of USART HAL Extended module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_USART_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_USART_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 156:95d6b41a828b 51 /** @addtogroup USARTEx
<> 144:ef7eb2e8f9f7 52 * @{
<> 156:95d6b41a828b 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** @defgroup USARTEx_Word_Length USARTEx Word Length
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 65 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 66 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 67 #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
<> 156:95d6b41a828b 68 #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
<> 144:ef7eb2e8f9f7 69 #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
<> 144:ef7eb2e8f9f7 70 #else
<> 156:95d6b41a828b 71 #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
<> 144:ef7eb2e8f9f7 72 #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
<> 144:ef7eb2e8f9f7 73 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 74 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 75 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @}
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /** @defgroup USART_Request_Parameters USARTEx Request Parameters
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 156:95d6b41a828b 83 #define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 84 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 85 #define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 86 #else
<> 144:ef7eb2e8f9f7 87 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 88 /**
<> 144:ef7eb2e8f9f7 89 * @}
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /** @defgroup USART_Flags USART Flags
<> 144:ef7eb2e8f9f7 93 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 94 * - 0xXXXX : Flag mask in the ISR register
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 98 #define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */
<> 156:95d6b41a828b 99 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 100 #define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */
<> 156:95d6b41a828b 101 #define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */
<> 156:95d6b41a828b 102 #define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */
<> 156:95d6b41a828b 103 #define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */
<> 156:95d6b41a828b 104 #define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */
<> 156:95d6b41a828b 105 #define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */
<> 156:95d6b41a828b 106 #define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */
<> 156:95d6b41a828b 107 #define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */
<> 156:95d6b41a828b 108 #define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */
<> 156:95d6b41a828b 109 #define USART_FLAG_NE (0x00000004U) /*!< USART noise error */
<> 156:95d6b41a828b 110 #define USART_FLAG_FE (0x00000002U) /*!< USART frame error */
<> 156:95d6b41a828b 111 #define USART_FLAG_PE (0x00000001U) /*!< USART parity error */
<> 144:ef7eb2e8f9f7 112 /**
<> 144:ef7eb2e8f9f7 113 * @}
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @}
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @brief Flush the USART Data registers.
Anna Bridge 180:96ed750bd169 126 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 127 * @retval None
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 130 #define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 131 do{ \
<> 144:ef7eb2e8f9f7 132 SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 133 SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 134 } while(0)
<> 144:ef7eb2e8f9f7 135 #else
<> 144:ef7eb2e8f9f7 136 #define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 137 do{ \
<> 144:ef7eb2e8f9f7 138 SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 139 } while(0)
<> 144:ef7eb2e8f9f7 140 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 147 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 156:95d6b41a828b 151 /** @brief Report the USART clock source.
Anna Bridge 180:96ed750bd169 152 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 180:96ed750bd169 153 * @param __CLOCKSOURCE__ output variable.
<> 144:ef7eb2e8f9f7 154 * @retval the USART clocking source, written in __CLOCKSOURCE__.
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
<> 144:ef7eb2e8f9f7 157 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 158 do { \
<> 144:ef7eb2e8f9f7 159 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 160 { \
<> 144:ef7eb2e8f9f7 161 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 162 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 163 break; \
<> 144:ef7eb2e8f9f7 164 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 165 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 166 break; \
<> 144:ef7eb2e8f9f7 167 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 168 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 169 break; \
<> 144:ef7eb2e8f9f7 170 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 171 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 172 break; \
<> 144:ef7eb2e8f9f7 173 default: \
<> 144:ef7eb2e8f9f7 174 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 175 break; \
<> 144:ef7eb2e8f9f7 176 } \
<> 144:ef7eb2e8f9f7 177 } while(0)
<> 144:ef7eb2e8f9f7 178 #elif defined (STM32F030x8) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 179 defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 180 defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 181 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 182 do { \
<> 144:ef7eb2e8f9f7 183 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 184 { \
<> 144:ef7eb2e8f9f7 185 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 186 { \
<> 144:ef7eb2e8f9f7 187 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 188 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 189 break; \
<> 144:ef7eb2e8f9f7 190 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 191 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 192 break; \
<> 144:ef7eb2e8f9f7 193 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 194 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 195 break; \
<> 144:ef7eb2e8f9f7 196 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 197 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 198 break; \
<> 144:ef7eb2e8f9f7 199 default: \
<> 144:ef7eb2e8f9f7 200 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 201 break; \
<> 144:ef7eb2e8f9f7 202 } \
<> 144:ef7eb2e8f9f7 203 } \
<> 144:ef7eb2e8f9f7 204 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 205 { \
<> 144:ef7eb2e8f9f7 206 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 207 } \
<> 144:ef7eb2e8f9f7 208 else \
<> 144:ef7eb2e8f9f7 209 { \
<> 144:ef7eb2e8f9f7 210 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 211 } \
<> 144:ef7eb2e8f9f7 212 } while(0)
<> 144:ef7eb2e8f9f7 213 #elif defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 214 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 215 do { \
<> 144:ef7eb2e8f9f7 216 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 217 { \
<> 144:ef7eb2e8f9f7 218 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 219 { \
<> 144:ef7eb2e8f9f7 220 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 221 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 222 break; \
<> 144:ef7eb2e8f9f7 223 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 224 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 225 break; \
<> 144:ef7eb2e8f9f7 226 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 227 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 228 break; \
<> 144:ef7eb2e8f9f7 229 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 230 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 231 break; \
<> 144:ef7eb2e8f9f7 232 default: \
<> 144:ef7eb2e8f9f7 233 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 234 break; \
<> 144:ef7eb2e8f9f7 235 } \
<> 144:ef7eb2e8f9f7 236 } \
<> 144:ef7eb2e8f9f7 237 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 238 { \
<> 144:ef7eb2e8f9f7 239 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 240 } \
<> 144:ef7eb2e8f9f7 241 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 242 { \
<> 144:ef7eb2e8f9f7 243 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 244 } \
<> 144:ef7eb2e8f9f7 245 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 246 { \
<> 144:ef7eb2e8f9f7 247 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 248 } \
<> 144:ef7eb2e8f9f7 249 else \
<> 144:ef7eb2e8f9f7 250 { \
<> 144:ef7eb2e8f9f7 251 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 252 } \
<> 144:ef7eb2e8f9f7 253 } while(0)
<> 144:ef7eb2e8f9f7 254 #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 255 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 256 do { \
<> 144:ef7eb2e8f9f7 257 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 258 { \
<> 144:ef7eb2e8f9f7 259 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 260 { \
<> 144:ef7eb2e8f9f7 261 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 262 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 263 break; \
<> 144:ef7eb2e8f9f7 264 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 265 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 266 break; \
<> 144:ef7eb2e8f9f7 267 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 268 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 269 break; \
<> 144:ef7eb2e8f9f7 270 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 271 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 272 break; \
<> 144:ef7eb2e8f9f7 273 default: \
<> 144:ef7eb2e8f9f7 274 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 275 break; \
<> 144:ef7eb2e8f9f7 276 } \
<> 144:ef7eb2e8f9f7 277 } \
<> 144:ef7eb2e8f9f7 278 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 279 { \
<> 144:ef7eb2e8f9f7 280 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 281 { \
<> 144:ef7eb2e8f9f7 282 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 283 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 284 break; \
<> 144:ef7eb2e8f9f7 285 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 286 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 287 break; \
<> 144:ef7eb2e8f9f7 288 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 289 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 290 break; \
<> 144:ef7eb2e8f9f7 291 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 292 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 293 break; \
<> 144:ef7eb2e8f9f7 294 default: \
<> 144:ef7eb2e8f9f7 295 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 296 break; \
<> 144:ef7eb2e8f9f7 297 } \
<> 144:ef7eb2e8f9f7 298 } \
<> 144:ef7eb2e8f9f7 299 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 300 { \
<> 144:ef7eb2e8f9f7 301 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 302 } \
<> 144:ef7eb2e8f9f7 303 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 304 { \
<> 144:ef7eb2e8f9f7 305 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 306 } \
<> 144:ef7eb2e8f9f7 307 else \
<> 144:ef7eb2e8f9f7 308 { \
<> 144:ef7eb2e8f9f7 309 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 310 } \
<> 144:ef7eb2e8f9f7 311 } while(0)
<> 144:ef7eb2e8f9f7 312 #elif defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 313 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 314 do { \
<> 144:ef7eb2e8f9f7 315 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 316 { \
<> 144:ef7eb2e8f9f7 317 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 318 { \
<> 144:ef7eb2e8f9f7 319 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 320 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 321 break; \
<> 144:ef7eb2e8f9f7 322 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 323 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 324 break; \
<> 144:ef7eb2e8f9f7 325 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 326 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 327 break; \
<> 144:ef7eb2e8f9f7 328 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 329 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 330 break; \
<> 144:ef7eb2e8f9f7 331 default: \
<> 144:ef7eb2e8f9f7 332 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 333 break; \
<> 144:ef7eb2e8f9f7 334 } \
<> 144:ef7eb2e8f9f7 335 } \
<> 144:ef7eb2e8f9f7 336 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 337 { \
<> 144:ef7eb2e8f9f7 338 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 339 { \
<> 144:ef7eb2e8f9f7 340 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 341 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 342 break; \
<> 144:ef7eb2e8f9f7 343 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 344 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 345 break; \
<> 144:ef7eb2e8f9f7 346 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 347 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 348 break; \
<> 144:ef7eb2e8f9f7 349 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 350 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 351 break; \
<> 144:ef7eb2e8f9f7 352 default: \
<> 144:ef7eb2e8f9f7 353 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 354 break; \
<> 144:ef7eb2e8f9f7 355 } \
<> 144:ef7eb2e8f9f7 356 } \
<> 144:ef7eb2e8f9f7 357 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 358 { \
<> 144:ef7eb2e8f9f7 359 switch(__HAL_RCC_GET_USART3_SOURCE()) \
<> 144:ef7eb2e8f9f7 360 { \
<> 144:ef7eb2e8f9f7 361 case RCC_USART3CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 362 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 363 break; \
<> 144:ef7eb2e8f9f7 364 case RCC_USART3CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 365 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 366 break; \
<> 144:ef7eb2e8f9f7 367 case RCC_USART3CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 368 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 369 break; \
<> 144:ef7eb2e8f9f7 370 case RCC_USART3CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 371 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 372 break; \
<> 144:ef7eb2e8f9f7 373 default: \
<> 144:ef7eb2e8f9f7 374 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 375 break; \
<> 144:ef7eb2e8f9f7 376 } \
<> 144:ef7eb2e8f9f7 377 } \
<> 144:ef7eb2e8f9f7 378 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 379 { \
<> 144:ef7eb2e8f9f7 380 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 381 } \
<> 144:ef7eb2e8f9f7 382 else if((__HANDLE__)->Instance == USART5) \
<> 144:ef7eb2e8f9f7 383 { \
<> 144:ef7eb2e8f9f7 384 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 385 } \
<> 144:ef7eb2e8f9f7 386 else if((__HANDLE__)->Instance == USART6) \
<> 144:ef7eb2e8f9f7 387 { \
<> 144:ef7eb2e8f9f7 388 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 389 } \
<> 144:ef7eb2e8f9f7 390 else if((__HANDLE__)->Instance == USART7) \
<> 144:ef7eb2e8f9f7 391 { \
<> 144:ef7eb2e8f9f7 392 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 393 } \
<> 144:ef7eb2e8f9f7 394 else if((__HANDLE__)->Instance == USART8) \
<> 144:ef7eb2e8f9f7 395 { \
<> 144:ef7eb2e8f9f7 396 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 397 } \
<> 144:ef7eb2e8f9f7 398 else \
<> 144:ef7eb2e8f9f7 399 { \
<> 144:ef7eb2e8f9f7 400 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 401 } \
<> 144:ef7eb2e8f9f7 402 } while(0)
<> 144:ef7eb2e8f9f7 403 #elif defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 404 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 405 do { \
<> 144:ef7eb2e8f9f7 406 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 407 { \
<> 144:ef7eb2e8f9f7 408 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 409 { \
<> 144:ef7eb2e8f9f7 410 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 411 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 412 break; \
<> 144:ef7eb2e8f9f7 413 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 414 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 415 break; \
<> 144:ef7eb2e8f9f7 416 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 417 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 418 break; \
<> 144:ef7eb2e8f9f7 419 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 420 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 421 break; \
<> 144:ef7eb2e8f9f7 422 default: \
<> 144:ef7eb2e8f9f7 423 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 424 break; \
<> 144:ef7eb2e8f9f7 425 } \
<> 144:ef7eb2e8f9f7 426 } \
<> 144:ef7eb2e8f9f7 427 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 428 { \
<> 144:ef7eb2e8f9f7 429 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 430 } \
<> 144:ef7eb2e8f9f7 431 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 432 { \
<> 144:ef7eb2e8f9f7 433 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 434 } \
<> 144:ef7eb2e8f9f7 435 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 436 { \
<> 144:ef7eb2e8f9f7 437 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 438 } \
<> 144:ef7eb2e8f9f7 439 else if((__HANDLE__)->Instance == USART5) \
<> 144:ef7eb2e8f9f7 440 { \
<> 144:ef7eb2e8f9f7 441 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 442 } \
<> 144:ef7eb2e8f9f7 443 else if((__HANDLE__)->Instance == USART6) \
<> 144:ef7eb2e8f9f7 444 { \
<> 144:ef7eb2e8f9f7 445 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 446 } \
<> 144:ef7eb2e8f9f7 447 else \
<> 144:ef7eb2e8f9f7 448 { \
<> 144:ef7eb2e8f9f7 449 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 450 } \
<> 144:ef7eb2e8f9f7 451 } while(0)
<> 144:ef7eb2e8f9f7 452 #endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /** @brief Compute the USART mask to apply to retrieve the received data
<> 144:ef7eb2e8f9f7 456 * according to the word length and to the parity bits activation.
<> 144:ef7eb2e8f9f7 457 * @note If PCE = 1, the parity bit is not included in the data extracted
<> 144:ef7eb2e8f9f7 458 * by the reception API().
<> 144:ef7eb2e8f9f7 459 * This masking operation is not carried out in the case of
<> 144:ef7eb2e8f9f7 460 * DMA transfers.
Anna Bridge 180:96ed750bd169 461 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 462 * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 465 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 466 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 467 #define USART_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 468 do { \
<> 144:ef7eb2e8f9f7 469 if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 470 { \
<> 144:ef7eb2e8f9f7 471 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 472 { \
<> 156:95d6b41a828b 473 (__HANDLE__)->Mask = 0x01FFU; \
<> 144:ef7eb2e8f9f7 474 } \
<> 144:ef7eb2e8f9f7 475 else \
<> 144:ef7eb2e8f9f7 476 { \
<> 156:95d6b41a828b 477 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 478 } \
<> 144:ef7eb2e8f9f7 479 } \
<> 144:ef7eb2e8f9f7 480 else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 481 { \
<> 144:ef7eb2e8f9f7 482 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 483 { \
<> 156:95d6b41a828b 484 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 485 } \
<> 144:ef7eb2e8f9f7 486 else \
<> 144:ef7eb2e8f9f7 487 { \
<> 156:95d6b41a828b 488 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 489 } \
<> 144:ef7eb2e8f9f7 490 } \
<> 144:ef7eb2e8f9f7 491 else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
<> 144:ef7eb2e8f9f7 492 { \
<> 144:ef7eb2e8f9f7 493 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 494 { \
<> 156:95d6b41a828b 495 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 496 } \
<> 144:ef7eb2e8f9f7 497 else \
<> 144:ef7eb2e8f9f7 498 { \
<> 156:95d6b41a828b 499 (__HANDLE__)->Mask = 0x003FU; \
<> 144:ef7eb2e8f9f7 500 } \
<> 144:ef7eb2e8f9f7 501 } \
<> 144:ef7eb2e8f9f7 502 } while(0)
<> 144:ef7eb2e8f9f7 503 #else
<> 144:ef7eb2e8f9f7 504 #define USART_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 505 do { \
<> 144:ef7eb2e8f9f7 506 if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 507 { \
<> 144:ef7eb2e8f9f7 508 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 509 { \
<> 156:95d6b41a828b 510 (__HANDLE__)->Mask = 0x01FFU; \
<> 144:ef7eb2e8f9f7 511 } \
<> 144:ef7eb2e8f9f7 512 else \
<> 144:ef7eb2e8f9f7 513 { \
<> 156:95d6b41a828b 514 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 515 } \
<> 144:ef7eb2e8f9f7 516 } \
<> 144:ef7eb2e8f9f7 517 else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 518 { \
<> 144:ef7eb2e8f9f7 519 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 520 { \
<> 156:95d6b41a828b 521 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 522 } \
<> 144:ef7eb2e8f9f7 523 else \
<> 144:ef7eb2e8f9f7 524 { \
<> 156:95d6b41a828b 525 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 526 } \
<> 144:ef7eb2e8f9f7 527 } \
<> 144:ef7eb2e8f9f7 528 } while(0)
<> 144:ef7eb2e8f9f7 529 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 530 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 531 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @brief Ensure that USART frame length is valid.
Anna Bridge 180:96ed750bd169 536 * @param __LENGTH__ USART frame length.
<> 144:ef7eb2e8f9f7 537 * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 540 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 541 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 542 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
<> 144:ef7eb2e8f9f7 543 ((__LENGTH__) == USART_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 544 ((__LENGTH__) == USART_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 545 #else
<> 144:ef7eb2e8f9f7 546 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 547 ((__LENGTH__) == USART_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 548 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 549 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 550 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /**
<> 144:ef7eb2e8f9f7 553 * @brief Ensure that USART request parameter is valid.
Anna Bridge 180:96ed750bd169 554 * @param __PARAM__ USART request parameter.
<> 144:ef7eb2e8f9f7 555 * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 558 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
<> 144:ef7eb2e8f9f7 559 ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
<> 144:ef7eb2e8f9f7 560 #else
<> 144:ef7eb2e8f9f7 561 #define IS_USART_REQUEST_PARAMETER(__PARAM__) ((__PARAM__) == USART_RXDATA_FLUSH_REQUEST)
<> 144:ef7eb2e8f9f7 562 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /**
<> 144:ef7eb2e8f9f7 565 * @}
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @}
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /**
<> 144:ef7eb2e8f9f7 575 * @}
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 #endif
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 #endif /* __STM32F0xx_HAL_USART_EX_H */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 585