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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_usart_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 156:95d6b41a828b 7 * @brief Header file of USART HAL Extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_USART_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_USART_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 156:95d6b41a828b 53 /** @addtogroup USARTEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 156:95d6b41a828b 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup USARTEx_Word_Length USARTEx Word Length
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 67 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 68 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 69 #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
<> 156:95d6b41a828b 70 #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
<> 144:ef7eb2e8f9f7 71 #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
<> 144:ef7eb2e8f9f7 72 #else
<> 156:95d6b41a828b 73 #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
<> 144:ef7eb2e8f9f7 74 #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
<> 144:ef7eb2e8f9f7 75 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 76 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 77 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @defgroup USART_Request_Parameters USARTEx Request Parameters
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 156:95d6b41a828b 85 #define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 86 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 87 #define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 88 #else
<> 144:ef7eb2e8f9f7 89 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @}
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /** @defgroup USART_Flags USART Flags
<> 144:ef7eb2e8f9f7 95 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 96 * - 0xXXXX : Flag mask in the ISR register
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 100 #define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */
<> 156:95d6b41a828b 101 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 102 #define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */
<> 156:95d6b41a828b 103 #define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */
<> 156:95d6b41a828b 104 #define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */
<> 156:95d6b41a828b 105 #define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */
<> 156:95d6b41a828b 106 #define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */
<> 156:95d6b41a828b 107 #define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */
<> 156:95d6b41a828b 108 #define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */
<> 156:95d6b41a828b 109 #define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */
<> 156:95d6b41a828b 110 #define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */
<> 156:95d6b41a828b 111 #define USART_FLAG_NE (0x00000004U) /*!< USART noise error */
<> 156:95d6b41a828b 112 #define USART_FLAG_FE (0x00000002U) /*!< USART frame error */
<> 156:95d6b41a828b 113 #define USART_FLAG_PE (0x00000001U) /*!< USART parity error */
<> 144:ef7eb2e8f9f7 114 /**
<> 144:ef7eb2e8f9f7 115 * @}
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @}
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** @brief Flush the USART Data registers.
<> 144:ef7eb2e8f9f7 128 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 129 * @retval None
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 132 #define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 133 do{ \
<> 144:ef7eb2e8f9f7 134 SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 135 SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 136 } while(0)
<> 144:ef7eb2e8f9f7 137 #else
<> 144:ef7eb2e8f9f7 138 #define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 139 do{ \
<> 144:ef7eb2e8f9f7 140 SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 141 } while(0)
<> 144:ef7eb2e8f9f7 142 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 156:95d6b41a828b 153 /** @brief Report the USART clock source.
<> 156:95d6b41a828b 154 * @param __HANDLE__: specifies the USART Handle.
<> 156:95d6b41a828b 155 * @param __CLOCKSOURCE__: output variable.
<> 144:ef7eb2e8f9f7 156 * @retval the USART clocking source, written in __CLOCKSOURCE__.
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
<> 144:ef7eb2e8f9f7 159 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 160 do { \
<> 144:ef7eb2e8f9f7 161 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 162 { \
<> 144:ef7eb2e8f9f7 163 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 164 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 165 break; \
<> 144:ef7eb2e8f9f7 166 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 167 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 168 break; \
<> 144:ef7eb2e8f9f7 169 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 170 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 171 break; \
<> 144:ef7eb2e8f9f7 172 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 173 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 174 break; \
<> 144:ef7eb2e8f9f7 175 default: \
<> 144:ef7eb2e8f9f7 176 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 177 break; \
<> 144:ef7eb2e8f9f7 178 } \
<> 144:ef7eb2e8f9f7 179 } while(0)
<> 144:ef7eb2e8f9f7 180 #elif defined (STM32F030x8) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 181 defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 182 defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 183 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 184 do { \
<> 144:ef7eb2e8f9f7 185 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 186 { \
<> 144:ef7eb2e8f9f7 187 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 188 { \
<> 144:ef7eb2e8f9f7 189 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 190 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 191 break; \
<> 144:ef7eb2e8f9f7 192 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 193 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 194 break; \
<> 144:ef7eb2e8f9f7 195 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 196 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 197 break; \
<> 144:ef7eb2e8f9f7 198 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 199 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 200 break; \
<> 144:ef7eb2e8f9f7 201 default: \
<> 144:ef7eb2e8f9f7 202 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 203 break; \
<> 144:ef7eb2e8f9f7 204 } \
<> 144:ef7eb2e8f9f7 205 } \
<> 144:ef7eb2e8f9f7 206 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 207 { \
<> 144:ef7eb2e8f9f7 208 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 209 } \
<> 144:ef7eb2e8f9f7 210 else \
<> 144:ef7eb2e8f9f7 211 { \
<> 144:ef7eb2e8f9f7 212 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 213 } \
<> 144:ef7eb2e8f9f7 214 } while(0)
<> 144:ef7eb2e8f9f7 215 #elif defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 216 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 217 do { \
<> 144:ef7eb2e8f9f7 218 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 219 { \
<> 144:ef7eb2e8f9f7 220 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 221 { \
<> 144:ef7eb2e8f9f7 222 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 223 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 224 break; \
<> 144:ef7eb2e8f9f7 225 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 226 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 227 break; \
<> 144:ef7eb2e8f9f7 228 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 229 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 230 break; \
<> 144:ef7eb2e8f9f7 231 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 232 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 233 break; \
<> 144:ef7eb2e8f9f7 234 default: \
<> 144:ef7eb2e8f9f7 235 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 236 break; \
<> 144:ef7eb2e8f9f7 237 } \
<> 144:ef7eb2e8f9f7 238 } \
<> 144:ef7eb2e8f9f7 239 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 240 { \
<> 144:ef7eb2e8f9f7 241 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 242 } \
<> 144:ef7eb2e8f9f7 243 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 244 { \
<> 144:ef7eb2e8f9f7 245 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 246 } \
<> 144:ef7eb2e8f9f7 247 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 248 { \
<> 144:ef7eb2e8f9f7 249 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 250 } \
<> 144:ef7eb2e8f9f7 251 else \
<> 144:ef7eb2e8f9f7 252 { \
<> 144:ef7eb2e8f9f7 253 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 254 } \
<> 144:ef7eb2e8f9f7 255 } while(0)
<> 144:ef7eb2e8f9f7 256 #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 257 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 258 do { \
<> 144:ef7eb2e8f9f7 259 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 260 { \
<> 144:ef7eb2e8f9f7 261 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 262 { \
<> 144:ef7eb2e8f9f7 263 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 264 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 265 break; \
<> 144:ef7eb2e8f9f7 266 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 267 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 268 break; \
<> 144:ef7eb2e8f9f7 269 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 270 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 271 break; \
<> 144:ef7eb2e8f9f7 272 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 273 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 274 break; \
<> 144:ef7eb2e8f9f7 275 default: \
<> 144:ef7eb2e8f9f7 276 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 277 break; \
<> 144:ef7eb2e8f9f7 278 } \
<> 144:ef7eb2e8f9f7 279 } \
<> 144:ef7eb2e8f9f7 280 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 281 { \
<> 144:ef7eb2e8f9f7 282 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 283 { \
<> 144:ef7eb2e8f9f7 284 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 285 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 286 break; \
<> 144:ef7eb2e8f9f7 287 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 288 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 289 break; \
<> 144:ef7eb2e8f9f7 290 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 291 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 292 break; \
<> 144:ef7eb2e8f9f7 293 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 294 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 295 break; \
<> 144:ef7eb2e8f9f7 296 default: \
<> 144:ef7eb2e8f9f7 297 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 298 break; \
<> 144:ef7eb2e8f9f7 299 } \
<> 144:ef7eb2e8f9f7 300 } \
<> 144:ef7eb2e8f9f7 301 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 302 { \
<> 144:ef7eb2e8f9f7 303 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 304 } \
<> 144:ef7eb2e8f9f7 305 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 306 { \
<> 144:ef7eb2e8f9f7 307 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 308 } \
<> 144:ef7eb2e8f9f7 309 else \
<> 144:ef7eb2e8f9f7 310 { \
<> 144:ef7eb2e8f9f7 311 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 312 } \
<> 144:ef7eb2e8f9f7 313 } while(0)
<> 144:ef7eb2e8f9f7 314 #elif defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 315 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 316 do { \
<> 144:ef7eb2e8f9f7 317 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 318 { \
<> 144:ef7eb2e8f9f7 319 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 320 { \
<> 144:ef7eb2e8f9f7 321 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 322 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 323 break; \
<> 144:ef7eb2e8f9f7 324 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 325 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 326 break; \
<> 144:ef7eb2e8f9f7 327 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 328 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 329 break; \
<> 144:ef7eb2e8f9f7 330 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 331 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 332 break; \
<> 144:ef7eb2e8f9f7 333 default: \
<> 144:ef7eb2e8f9f7 334 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 335 break; \
<> 144:ef7eb2e8f9f7 336 } \
<> 144:ef7eb2e8f9f7 337 } \
<> 144:ef7eb2e8f9f7 338 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 339 { \
<> 144:ef7eb2e8f9f7 340 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 341 { \
<> 144:ef7eb2e8f9f7 342 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 343 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 344 break; \
<> 144:ef7eb2e8f9f7 345 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 346 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 347 break; \
<> 144:ef7eb2e8f9f7 348 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 349 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 350 break; \
<> 144:ef7eb2e8f9f7 351 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 352 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 353 break; \
<> 144:ef7eb2e8f9f7 354 default: \
<> 144:ef7eb2e8f9f7 355 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 356 break; \
<> 144:ef7eb2e8f9f7 357 } \
<> 144:ef7eb2e8f9f7 358 } \
<> 144:ef7eb2e8f9f7 359 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 360 { \
<> 144:ef7eb2e8f9f7 361 switch(__HAL_RCC_GET_USART3_SOURCE()) \
<> 144:ef7eb2e8f9f7 362 { \
<> 144:ef7eb2e8f9f7 363 case RCC_USART3CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 364 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 365 break; \
<> 144:ef7eb2e8f9f7 366 case RCC_USART3CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 367 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 368 break; \
<> 144:ef7eb2e8f9f7 369 case RCC_USART3CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 370 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 371 break; \
<> 144:ef7eb2e8f9f7 372 case RCC_USART3CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 373 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 374 break; \
<> 144:ef7eb2e8f9f7 375 default: \
<> 144:ef7eb2e8f9f7 376 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 377 break; \
<> 144:ef7eb2e8f9f7 378 } \
<> 144:ef7eb2e8f9f7 379 } \
<> 144:ef7eb2e8f9f7 380 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 381 { \
<> 144:ef7eb2e8f9f7 382 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 383 } \
<> 144:ef7eb2e8f9f7 384 else if((__HANDLE__)->Instance == USART5) \
<> 144:ef7eb2e8f9f7 385 { \
<> 144:ef7eb2e8f9f7 386 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 387 } \
<> 144:ef7eb2e8f9f7 388 else if((__HANDLE__)->Instance == USART6) \
<> 144:ef7eb2e8f9f7 389 { \
<> 144:ef7eb2e8f9f7 390 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 391 } \
<> 144:ef7eb2e8f9f7 392 else if((__HANDLE__)->Instance == USART7) \
<> 144:ef7eb2e8f9f7 393 { \
<> 144:ef7eb2e8f9f7 394 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 395 } \
<> 144:ef7eb2e8f9f7 396 else if((__HANDLE__)->Instance == USART8) \
<> 144:ef7eb2e8f9f7 397 { \
<> 144:ef7eb2e8f9f7 398 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 399 } \
<> 144:ef7eb2e8f9f7 400 else \
<> 144:ef7eb2e8f9f7 401 { \
<> 144:ef7eb2e8f9f7 402 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 403 } \
<> 144:ef7eb2e8f9f7 404 } while(0)
<> 144:ef7eb2e8f9f7 405 #elif defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 406 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 407 do { \
<> 144:ef7eb2e8f9f7 408 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 409 { \
<> 144:ef7eb2e8f9f7 410 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 411 { \
<> 144:ef7eb2e8f9f7 412 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 413 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 414 break; \
<> 144:ef7eb2e8f9f7 415 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 416 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 417 break; \
<> 144:ef7eb2e8f9f7 418 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 419 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 420 break; \
<> 144:ef7eb2e8f9f7 421 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 422 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 423 break; \
<> 144:ef7eb2e8f9f7 424 default: \
<> 144:ef7eb2e8f9f7 425 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 426 break; \
<> 144:ef7eb2e8f9f7 427 } \
<> 144:ef7eb2e8f9f7 428 } \
<> 144:ef7eb2e8f9f7 429 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 430 { \
<> 144:ef7eb2e8f9f7 431 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 432 } \
<> 144:ef7eb2e8f9f7 433 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 434 { \
<> 144:ef7eb2e8f9f7 435 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 436 } \
<> 144:ef7eb2e8f9f7 437 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 438 { \
<> 144:ef7eb2e8f9f7 439 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 440 } \
<> 144:ef7eb2e8f9f7 441 else if((__HANDLE__)->Instance == USART5) \
<> 144:ef7eb2e8f9f7 442 { \
<> 144:ef7eb2e8f9f7 443 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 444 } \
<> 144:ef7eb2e8f9f7 445 else if((__HANDLE__)->Instance == USART6) \
<> 144:ef7eb2e8f9f7 446 { \
<> 144:ef7eb2e8f9f7 447 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 448 } \
<> 144:ef7eb2e8f9f7 449 else \
<> 144:ef7eb2e8f9f7 450 { \
<> 144:ef7eb2e8f9f7 451 (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 452 } \
<> 144:ef7eb2e8f9f7 453 } while(0)
<> 144:ef7eb2e8f9f7 454 #endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /** @brief Compute the USART mask to apply to retrieve the received data
<> 144:ef7eb2e8f9f7 458 * according to the word length and to the parity bits activation.
<> 144:ef7eb2e8f9f7 459 * @note If PCE = 1, the parity bit is not included in the data extracted
<> 144:ef7eb2e8f9f7 460 * by the reception API().
<> 144:ef7eb2e8f9f7 461 * This masking operation is not carried out in the case of
<> 144:ef7eb2e8f9f7 462 * DMA transfers.
<> 144:ef7eb2e8f9f7 463 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 464 * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 467 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 468 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 469 #define USART_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 470 do { \
<> 144:ef7eb2e8f9f7 471 if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 472 { \
<> 144:ef7eb2e8f9f7 473 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 474 { \
<> 156:95d6b41a828b 475 (__HANDLE__)->Mask = 0x01FFU; \
<> 144:ef7eb2e8f9f7 476 } \
<> 144:ef7eb2e8f9f7 477 else \
<> 144:ef7eb2e8f9f7 478 { \
<> 156:95d6b41a828b 479 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 480 } \
<> 144:ef7eb2e8f9f7 481 } \
<> 144:ef7eb2e8f9f7 482 else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 483 { \
<> 144:ef7eb2e8f9f7 484 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 485 { \
<> 156:95d6b41a828b 486 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 487 } \
<> 144:ef7eb2e8f9f7 488 else \
<> 144:ef7eb2e8f9f7 489 { \
<> 156:95d6b41a828b 490 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 491 } \
<> 144:ef7eb2e8f9f7 492 } \
<> 144:ef7eb2e8f9f7 493 else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
<> 144:ef7eb2e8f9f7 494 { \
<> 144:ef7eb2e8f9f7 495 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 496 { \
<> 156:95d6b41a828b 497 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 498 } \
<> 144:ef7eb2e8f9f7 499 else \
<> 144:ef7eb2e8f9f7 500 { \
<> 156:95d6b41a828b 501 (__HANDLE__)->Mask = 0x003FU; \
<> 144:ef7eb2e8f9f7 502 } \
<> 144:ef7eb2e8f9f7 503 } \
<> 144:ef7eb2e8f9f7 504 } while(0)
<> 144:ef7eb2e8f9f7 505 #else
<> 144:ef7eb2e8f9f7 506 #define USART_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 507 do { \
<> 144:ef7eb2e8f9f7 508 if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 509 { \
<> 144:ef7eb2e8f9f7 510 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 511 { \
<> 156:95d6b41a828b 512 (__HANDLE__)->Mask = 0x01FFU; \
<> 144:ef7eb2e8f9f7 513 } \
<> 144:ef7eb2e8f9f7 514 else \
<> 144:ef7eb2e8f9f7 515 { \
<> 156:95d6b41a828b 516 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 517 } \
<> 144:ef7eb2e8f9f7 518 } \
<> 144:ef7eb2e8f9f7 519 else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 520 { \
<> 144:ef7eb2e8f9f7 521 if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 522 { \
<> 156:95d6b41a828b 523 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 524 } \
<> 144:ef7eb2e8f9f7 525 else \
<> 144:ef7eb2e8f9f7 526 { \
<> 156:95d6b41a828b 527 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 528 } \
<> 144:ef7eb2e8f9f7 529 } \
<> 144:ef7eb2e8f9f7 530 } while(0)
<> 144:ef7eb2e8f9f7 531 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 532 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 533 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @brief Ensure that USART frame length is valid.
<> 144:ef7eb2e8f9f7 538 * @param __LENGTH__: USART frame length.
<> 144:ef7eb2e8f9f7 539 * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 542 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 543 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 544 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
<> 144:ef7eb2e8f9f7 545 ((__LENGTH__) == USART_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 546 ((__LENGTH__) == USART_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 547 #else
<> 144:ef7eb2e8f9f7 548 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 549 ((__LENGTH__) == USART_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 550 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 551 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 552 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /**
<> 144:ef7eb2e8f9f7 555 * @brief Ensure that USART request parameter is valid.
<> 144:ef7eb2e8f9f7 556 * @param __PARAM__: USART request parameter.
<> 144:ef7eb2e8f9f7 557 * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 560 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
<> 144:ef7eb2e8f9f7 561 ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
<> 144:ef7eb2e8f9f7 562 #else
<> 144:ef7eb2e8f9f7 563 #define IS_USART_REQUEST_PARAMETER(__PARAM__) ((__PARAM__) == USART_RXDATA_FLUSH_REQUEST)
<> 144:ef7eb2e8f9f7 564 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @}
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /**
<> 144:ef7eb2e8f9f7 573 * @}
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /**
<> 144:ef7eb2e8f9f7 577 * @}
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 #endif
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 #endif /* __STM32F0xx_HAL_USART_EX_H */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 587