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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_tim.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Timer (TIM) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Time Base Initialization
<> 144:ef7eb2e8f9f7 9 * + Time Base Start
<> 144:ef7eb2e8f9f7 10 * + Time Base Start Interruption
<> 144:ef7eb2e8f9f7 11 * + Time Base Start DMA
<> 144:ef7eb2e8f9f7 12 * + Time Output Compare/PWM Initialization
<> 144:ef7eb2e8f9f7 13 * + Time Output Compare/PWM Channel Configuration
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Start
<> 144:ef7eb2e8f9f7 15 * + Time Output Compare/PWM Start Interruption
<> 144:ef7eb2e8f9f7 16 * + Time Output Compare/PWM Start DMA
<> 144:ef7eb2e8f9f7 17 * + Time Input Capture Initialization
<> 144:ef7eb2e8f9f7 18 * + Time Input Capture Channel Configuration
<> 144:ef7eb2e8f9f7 19 * + Time Input Capture Start
<> 144:ef7eb2e8f9f7 20 * + Time Input Capture Start Interruption
<> 144:ef7eb2e8f9f7 21 * + Time Input Capture Start DMA
<> 144:ef7eb2e8f9f7 22 * + Time One Pulse Initialization
<> 144:ef7eb2e8f9f7 23 * + Time One Pulse Channel Configuration
<> 144:ef7eb2e8f9f7 24 * + Time One Pulse Start
<> 144:ef7eb2e8f9f7 25 * + Time Encoder Interface Initialization
<> 144:ef7eb2e8f9f7 26 * + Time Encoder Interface Start
<> 144:ef7eb2e8f9f7 27 * + Time Encoder Interface Start Interruption
<> 144:ef7eb2e8f9f7 28 * + Time Encoder Interface Start DMA
<> 144:ef7eb2e8f9f7 29 * + Commutation Event configuration with Interruption and DMA
<> 144:ef7eb2e8f9f7 30 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 31 * + Time External Clock configuration
<> 144:ef7eb2e8f9f7 32 @verbatim
<> 144:ef7eb2e8f9f7 33 ==============================================================================
<> 144:ef7eb2e8f9f7 34 ##### TIMER Generic features #####
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 [..] The Timer features include:
<> 144:ef7eb2e8f9f7 37 (#) 16-bit up, down, up/down auto-reload counter.
<> 144:ef7eb2e8f9f7 38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<> 144:ef7eb2e8f9f7 39 counter clock frequency either by any factor between 1 and 65536.
<> 144:ef7eb2e8f9f7 40 (#) Up to 4 independent channels for:
<> 144:ef7eb2e8f9f7 41 (++) Input Capture
<> 144:ef7eb2e8f9f7 42 (++) Output Compare
<> 144:ef7eb2e8f9f7 43 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 44 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 47 ==============================================================================
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 50 depending from feature used :
<> 144:ef7eb2e8f9f7 51 (++) Time Base : HAL_TIM_Base_MspInit()
<> 144:ef7eb2e8f9f7 52 (++) Input Capture : HAL_TIM_IC_MspInit()
<> 144:ef7eb2e8f9f7 53 (++) Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 54 (++) PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 55 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 56 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 59 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 60 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 61 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 62 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 63 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 66 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 67 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 68 any start function.
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 71 Initialization function of this driver:
<> 144:ef7eb2e8f9f7 72 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<> 144:ef7eb2e8f9f7 73 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<> 144:ef7eb2e8f9f7 74 Output Compare signal.
<> 144:ef7eb2e8f9f7 75 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<> 144:ef7eb2e8f9f7 76 PWM signal.
<> 144:ef7eb2e8f9f7 77 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<> 144:ef7eb2e8f9f7 78 external signal.
<> 144:ef7eb2e8f9f7 79 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<> 144:ef7eb2e8f9f7 80 in One Pulse Mode.
<> 144:ef7eb2e8f9f7 81 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<> 144:ef7eb2e8f9f7 84 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<> 144:ef7eb2e8f9f7 85 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<> 144:ef7eb2e8f9f7 86 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<> 144:ef7eb2e8f9f7 87 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<> 144:ef7eb2e8f9f7 88 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<> 144:ef7eb2e8f9f7 89 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 (#) The DMA Burst is managed with the two following functions:
<> 144:ef7eb2e8f9f7 92 HAL_TIM_DMABurst_WriteStart()
<> 144:ef7eb2e8f9f7 93 HAL_TIM_DMABurst_ReadStart()
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 @endverbatim
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 * @attention
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 102 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 103 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 104 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 105 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 107 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 108 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 109 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 110 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 ******************************************************************************
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup TIM TIM
<> 144:ef7eb2e8f9f7 134 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @defgroup TIM_Private_Functions TIM_Private_Functions
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 150 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 151 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 152 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 154 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 155 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 156 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 157 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 158 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 159 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 160 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<> 144:ef7eb2e8f9f7 161 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 163 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 164 TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** @defgroup TIM_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 173 * @{
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<> 144:ef7eb2e8f9f7 177 * @brief Time Base functions
<> 144:ef7eb2e8f9f7 178 *
<> 144:ef7eb2e8f9f7 179 @verbatim
<> 144:ef7eb2e8f9f7 180 ==============================================================================
<> 144:ef7eb2e8f9f7 181 ##### Time Base functions #####
<> 144:ef7eb2e8f9f7 182 ==============================================================================
<> 144:ef7eb2e8f9f7 183 [..]
<> 144:ef7eb2e8f9f7 184 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 185 (+) Initialize and configure the TIM base.
<> 144:ef7eb2e8f9f7 186 (+) De-initialize the TIM base.
<> 144:ef7eb2e8f9f7 187 (+) Start the Time Base.
<> 144:ef7eb2e8f9f7 188 (+) Stop the Time Base.
<> 144:ef7eb2e8f9f7 189 (+) Start the Time Base and enable interrupt.
<> 144:ef7eb2e8f9f7 190 (+) Stop the Time Base and disable interrupt.
<> 144:ef7eb2e8f9f7 191 (+) Start the Time Base and enable DMA transfer.
<> 144:ef7eb2e8f9f7 192 (+) Stop the Time Base and disable DMA transfer.
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 @endverbatim
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @brief Initializes the TIM Time base Unit according to the specified
<> 144:ef7eb2e8f9f7 199 * parameters in the TIM_HandleTypeDef and create the associated handle.
Anna Bridge 180:96ed750bd169 200 * @param htim TIM Base handle
<> 144:ef7eb2e8f9f7 201 * @retval HAL status
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 206 if(htim == NULL)
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Check the parameters */
<> 144:ef7eb2e8f9f7 212 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 213 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 214 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 215 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 220 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 223 HAL_TIM_Base_MspInit(htim);
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 227 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Set the Time Base configuration */
<> 144:ef7eb2e8f9f7 230 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 233 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 return HAL_OK;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @brief DeInitializes the TIM Base peripheral
Anna Bridge 180:96ed750bd169 240 * @param htim TIM Base handle
<> 144:ef7eb2e8f9f7 241 * @retval HAL status
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* Check the parameters */
<> 144:ef7eb2e8f9f7 246 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 251 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 254 HAL_TIM_Base_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Change TIM state */
<> 144:ef7eb2e8f9f7 257 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Release Lock */
<> 144:ef7eb2e8f9f7 260 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 return HAL_OK;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @brief Initializes the TIM Base MSP.
Anna Bridge 180:96ed750bd169 267 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 268 * @retval None
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 273 UNUSED(htim);
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 276 the HAL_TIM_Base_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @brief DeInitializes TIM Base MSP.
Anna Bridge 180:96ed750bd169 282 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 283 * @retval None
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 288 UNUSED(htim);
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 291 the HAL_TIM_Base_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @brief Starts the TIM Base generation.
Anna Bridge 180:96ed750bd169 298 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 299 * @retval HAL status
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Check the parameters */
<> 144:ef7eb2e8f9f7 304 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 307 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 310 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 313 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Return function status */
<> 144:ef7eb2e8f9f7 316 return HAL_OK;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @brief Stops the TIM Base generation.
Anna Bridge 180:96ed750bd169 321 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 322 * @retval HAL status
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 /* Check the parameters */
<> 144:ef7eb2e8f9f7 327 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 330 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 333 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 336 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Return function status */
<> 144:ef7eb2e8f9f7 339 return HAL_OK;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @brief Starts the TIM Base generation in interrupt mode.
Anna Bridge 180:96ed750bd169 344 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 345 * @retval HAL status
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 348 {
<> 144:ef7eb2e8f9f7 349 /* Check the parameters */
<> 144:ef7eb2e8f9f7 350 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Enable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 353 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 356 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Return function status */
<> 144:ef7eb2e8f9f7 359 return HAL_OK;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @brief Stops the TIM Base generation in interrupt mode.
Anna Bridge 180:96ed750bd169 364 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 365 * @retval HAL status
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 /* Check the parameters */
<> 144:ef7eb2e8f9f7 370 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 371 /* Disable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 375 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Return function status */
<> 144:ef7eb2e8f9f7 378 return HAL_OK;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @brief Starts the TIM Base generation in DMA mode.
Anna Bridge 180:96ed750bd169 383 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 384 * @param pData The source Buffer address.
Anna Bridge 180:96ed750bd169 385 * @param Length The length of data to be transferred from memory to peripheral.
<> 144:ef7eb2e8f9f7 386 * @retval HAL status
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 /* Check the parameters */
<> 144:ef7eb2e8f9f7 391 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 if((pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 else
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 409 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 412 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 415 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Enable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 418 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 421 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Return function status */
<> 144:ef7eb2e8f9f7 424 return HAL_OK;
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /**
<> 144:ef7eb2e8f9f7 428 * @brief Stops the TIM Base generation in DMA mode.
Anna Bridge 180:96ed750bd169 429 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 430 * @retval HAL status
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 /* Check the parameters */
<> 144:ef7eb2e8f9f7 435 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 438 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 441 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Change the htim state */
<> 144:ef7eb2e8f9f7 444 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Return function status */
<> 144:ef7eb2e8f9f7 447 return HAL_OK;
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /**
<> 144:ef7eb2e8f9f7 451 * @}
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<> 144:ef7eb2e8f9f7 455 * @brief Time Output Compare functions
<> 144:ef7eb2e8f9f7 456 *
<> 144:ef7eb2e8f9f7 457 @verbatim
<> 144:ef7eb2e8f9f7 458 ==============================================================================
<> 144:ef7eb2e8f9f7 459 ##### Time Output Compare functions #####
<> 144:ef7eb2e8f9f7 460 ==============================================================================
<> 144:ef7eb2e8f9f7 461 [..]
<> 144:ef7eb2e8f9f7 462 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 463 (+) Initialize and configure the TIM Output Compare.
<> 144:ef7eb2e8f9f7 464 (+) De-initialize the TIM Output Compare.
<> 144:ef7eb2e8f9f7 465 (+) Start the Time Output Compare.
<> 144:ef7eb2e8f9f7 466 (+) Stop the Time Output Compare.
<> 144:ef7eb2e8f9f7 467 (+) Start the Time Output Compare and enable interrupt.
<> 144:ef7eb2e8f9f7 468 (+) Stop the Time Output Compare and disable interrupt.
<> 144:ef7eb2e8f9f7 469 (+) Start the Time Output Compare and enable DMA transfer.
<> 144:ef7eb2e8f9f7 470 (+) Stop the Time Output Compare and disable DMA transfer.
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 @endverbatim
<> 144:ef7eb2e8f9f7 473 * @{
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 /**
<> 144:ef7eb2e8f9f7 476 * @brief Initializes the TIM Output Compare according to the specified
<> 144:ef7eb2e8f9f7 477 * parameters in the TIM_HandleTypeDef and create the associated handle.
Anna Bridge 180:96ed750bd169 478 * @param htim TIM Output Compare handle
<> 144:ef7eb2e8f9f7 479 * @retval HAL status
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 484 if(htim == NULL)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Check the parameters */
<> 144:ef7eb2e8f9f7 490 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 491 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 492 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 493 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 498 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 501 HAL_TIM_OC_MspInit(htim);
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 505 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Init the base time for the Output Compare */
<> 144:ef7eb2e8f9f7 508 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 511 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 return HAL_OK;
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @brief DeInitializes the TIM peripheral
Anna Bridge 180:96ed750bd169 518 * @param htim TIM Output Compare handle
<> 144:ef7eb2e8f9f7 519 * @retval HAL status
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Check the parameters */
<> 144:ef7eb2e8f9f7 524 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 529 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 532 HAL_TIM_OC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Change TIM state */
<> 144:ef7eb2e8f9f7 535 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Release Lock */
<> 144:ef7eb2e8f9f7 538 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 return HAL_OK;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /**
<> 144:ef7eb2e8f9f7 544 * @brief Initializes the TIM Output Compare MSP.
Anna Bridge 180:96ed750bd169 545 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 546 * @retval None
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 551 UNUSED(htim);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 554 the HAL_TIM_OC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /**
<> 144:ef7eb2e8f9f7 559 * @brief DeInitializes TIM Output Compare MSP.
Anna Bridge 180:96ed750bd169 560 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 561 * @retval None
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 566 UNUSED(htim);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 569 the HAL_TIM_OC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @brief Starts the TIM Output Compare signal generation.
Anna Bridge 180:96ed750bd169 575 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 576 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 577 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 578 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 579 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 580 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 581 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 582 * @retval HAL status
<> 144:ef7eb2e8f9f7 583 */
<> 144:ef7eb2e8f9f7 584 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 /* Check the parameters */
<> 144:ef7eb2e8f9f7 587 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 590 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 /* Enable the main output */
<> 144:ef7eb2e8f9f7 595 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 599 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Return function status */
<> 144:ef7eb2e8f9f7 602 return HAL_OK;
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /**
<> 144:ef7eb2e8f9f7 606 * @brief Stops the TIM Output Compare signal generation.
Anna Bridge 180:96ed750bd169 607 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 608 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 609 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 610 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 611 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 612 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 613 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 614 * @retval HAL status
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 /* Check the parameters */
<> 144:ef7eb2e8f9f7 619 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 622 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 627 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 631 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Return function status */
<> 144:ef7eb2e8f9f7 634 return HAL_OK;
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
Anna Bridge 180:96ed750bd169 639 * @param htim TIM OC handle
Anna Bridge 180:96ed750bd169 640 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 641 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 642 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 643 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 644 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 645 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 646 * @retval HAL status
<> 144:ef7eb2e8f9f7 647 */
<> 144:ef7eb2e8f9f7 648 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Check the parameters */
<> 144:ef7eb2e8f9f7 651 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 switch (Channel)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 658 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660 break;
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 break;
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 672 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 break;
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 679 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681 break;
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 default:
<> 144:ef7eb2e8f9f7 684 break;
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 688 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 /* Enable the main output */
<> 144:ef7eb2e8f9f7 693 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 697 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Return function status */
<> 144:ef7eb2e8f9f7 700 return HAL_OK;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /**
<> 144:ef7eb2e8f9f7 704 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
Anna Bridge 180:96ed750bd169 705 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 706 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 707 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 708 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 709 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 710 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 711 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 712 * @retval HAL status
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 /* Check the parameters */
<> 144:ef7eb2e8f9f7 717 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 switch (Channel)
<> 144:ef7eb2e8f9f7 720 {
<> 144:ef7eb2e8f9f7 721 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 724 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726 break;
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 731 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 break;
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 738 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 739 }
<> 144:ef7eb2e8f9f7 740 break;
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 743 {
<> 144:ef7eb2e8f9f7 744 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 745 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747 break;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 default:
<> 144:ef7eb2e8f9f7 750 break;
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 754 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 757 {
<> 144:ef7eb2e8f9f7 758 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 759 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 763 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Return function status */
<> 144:ef7eb2e8f9f7 766 return HAL_OK;
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @brief Starts the TIM Output Compare signal generation in DMA mode.
Anna Bridge 180:96ed750bd169 771 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 772 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 773 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 774 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 775 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 776 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 777 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
Anna Bridge 180:96ed750bd169 778 * @param pData The source Buffer address.
Anna Bridge 180:96ed750bd169 779 * @param Length The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 780 * @retval HAL status
<> 144:ef7eb2e8f9f7 781 */
<> 144:ef7eb2e8f9f7 782 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 /* Check the parameters */
<> 144:ef7eb2e8f9f7 785 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 792 {
<> 156:95d6b41a828b 793 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797 else
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802 switch (Channel)
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 807 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 810 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 813 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 816 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818 break;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 823 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 826 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 829 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 832 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 break;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 839 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 842 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 845 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 848 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 break;
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 853 {
<> 144:ef7eb2e8f9f7 854 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 855 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 858 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 861 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 864 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 865 }
<> 144:ef7eb2e8f9f7 866 break;
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 default:
<> 144:ef7eb2e8f9f7 869 break;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 873 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 /* Enable the main output */
<> 144:ef7eb2e8f9f7 878 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 879 }
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 882 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Return function status */
<> 144:ef7eb2e8f9f7 885 return HAL_OK;
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * @brief Stops the TIM Output Compare signal generation in DMA mode.
Anna Bridge 180:96ed750bd169 890 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 891 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 892 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 893 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 894 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 895 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 896 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 897 * @retval HAL status
<> 144:ef7eb2e8f9f7 898 */
<> 144:ef7eb2e8f9f7 899 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 /* Check the parameters */
<> 144:ef7eb2e8f9f7 902 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 switch (Channel)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 907 {
<> 144:ef7eb2e8f9f7 908 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 909 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911 break;
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 916 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918 break;
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925 break;
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 928 {
<> 144:ef7eb2e8f9f7 929 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 930 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932 break;
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 default:
<> 144:ef7eb2e8f9f7 935 break;
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 939 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 942 {
<> 144:ef7eb2e8f9f7 943 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 944 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 948 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Change the htim state */
<> 144:ef7eb2e8f9f7 951 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Return function status */
<> 144:ef7eb2e8f9f7 954 return HAL_OK;
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /**
<> 144:ef7eb2e8f9f7 958 * @}
<> 144:ef7eb2e8f9f7 959 */
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<> 144:ef7eb2e8f9f7 962 * @brief Time PWM functions
<> 144:ef7eb2e8f9f7 963 *
<> 144:ef7eb2e8f9f7 964 @verbatim
<> 144:ef7eb2e8f9f7 965 ==============================================================================
<> 144:ef7eb2e8f9f7 966 ##### Time PWM functions #####
<> 144:ef7eb2e8f9f7 967 ==============================================================================
<> 144:ef7eb2e8f9f7 968 [..]
<> 144:ef7eb2e8f9f7 969 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 970 (+) Initialize and configure the TIM OPWM.
<> 144:ef7eb2e8f9f7 971 (+) De-initialize the TIM PWM.
<> 144:ef7eb2e8f9f7 972 (+) Start the Time PWM.
<> 144:ef7eb2e8f9f7 973 (+) Stop the Time PWM.
<> 144:ef7eb2e8f9f7 974 (+) Start the Time PWM and enable interrupt.
<> 144:ef7eb2e8f9f7 975 (+) Stop the Time PWM and disable interrupt.
<> 144:ef7eb2e8f9f7 976 (+) Start the Time PWM and enable DMA transfer.
<> 144:ef7eb2e8f9f7 977 (+) Stop the Time PWM and disable DMA transfer.
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 @endverbatim
<> 144:ef7eb2e8f9f7 980 * @{
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982 /**
<> 144:ef7eb2e8f9f7 983 * @brief Initializes the TIM PWM Time Base according to the specified
<> 144:ef7eb2e8f9f7 984 * parameters in the TIM_HandleTypeDef and create the associated handle.
Anna Bridge 180:96ed750bd169 985 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 986 * @retval HAL status
<> 144:ef7eb2e8f9f7 987 */
<> 144:ef7eb2e8f9f7 988 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 989 {
<> 144:ef7eb2e8f9f7 990 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 991 if(htim == NULL)
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 994 }
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Check the parameters */
<> 144:ef7eb2e8f9f7 997 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 998 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 999 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 1000 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1005 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1008 HAL_TIM_PWM_MspInit(htim);
<> 144:ef7eb2e8f9f7 1009 }
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1012 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Init the base time for the PWM */
<> 144:ef7eb2e8f9f7 1015 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1018 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 return HAL_OK;
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /**
<> 144:ef7eb2e8f9f7 1024 * @brief DeInitializes the TIM peripheral
Anna Bridge 180:96ed750bd169 1025 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 1026 * @retval HAL status
<> 144:ef7eb2e8f9f7 1027 */
<> 144:ef7eb2e8f9f7 1028 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1031 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1036 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1039 HAL_TIM_PWM_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1042 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /* Release Lock */
<> 144:ef7eb2e8f9f7 1045 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 return HAL_OK;
<> 144:ef7eb2e8f9f7 1048 }
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /**
<> 144:ef7eb2e8f9f7 1051 * @brief Initializes the TIM PWM MSP.
Anna Bridge 180:96ed750bd169 1052 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 1053 * @retval None
<> 144:ef7eb2e8f9f7 1054 */
<> 144:ef7eb2e8f9f7 1055 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1056 {
<> 144:ef7eb2e8f9f7 1057 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1058 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1061 the HAL_TIM_PWM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1062 */
<> 144:ef7eb2e8f9f7 1063 }
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 /**
<> 144:ef7eb2e8f9f7 1066 * @brief DeInitializes TIM PWM MSP.
Anna Bridge 180:96ed750bd169 1067 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 1068 * @retval None
<> 144:ef7eb2e8f9f7 1069 */
<> 144:ef7eb2e8f9f7 1070 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1073 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1076 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1077 */
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /**
<> 144:ef7eb2e8f9f7 1081 * @brief Starts the PWM signal generation.
Anna Bridge 180:96ed750bd169 1082 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1083 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1084 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1085 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1086 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1087 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1088 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1089 * @retval HAL status
<> 144:ef7eb2e8f9f7 1090 */
<> 144:ef7eb2e8f9f7 1091 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1092 {
<> 144:ef7eb2e8f9f7 1093 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1094 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1097 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1100 {
<> 144:ef7eb2e8f9f7 1101 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1102 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1103 }
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1106 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /* Return function status */
<> 144:ef7eb2e8f9f7 1109 return HAL_OK;
<> 144:ef7eb2e8f9f7 1110 }
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /**
<> 144:ef7eb2e8f9f7 1113 * @brief Stops the PWM signal generation.
Anna Bridge 180:96ed750bd169 1114 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1115 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1116 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1117 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1118 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1119 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1120 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1121 * @retval HAL status
<> 144:ef7eb2e8f9f7 1122 */
<> 144:ef7eb2e8f9f7 1123 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1124 {
<> 144:ef7eb2e8f9f7 1125 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1126 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1129 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1134 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1135 }
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1138 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1141 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /* Return function status */
<> 144:ef7eb2e8f9f7 1144 return HAL_OK;
<> 144:ef7eb2e8f9f7 1145 }
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /**
<> 144:ef7eb2e8f9f7 1148 * @brief Starts the PWM signal generation in interrupt mode.
Anna Bridge 180:96ed750bd169 1149 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1150 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1151 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1152 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1153 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1154 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1155 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1156 * @retval HAL status
<> 144:ef7eb2e8f9f7 1157 */
<> 144:ef7eb2e8f9f7 1158 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1161 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 switch (Channel)
<> 144:ef7eb2e8f9f7 1164 {
<> 144:ef7eb2e8f9f7 1165 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1166 {
<> 144:ef7eb2e8f9f7 1167 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1168 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170 break;
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1173 {
<> 144:ef7eb2e8f9f7 1174 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1175 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177 break;
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1182 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1183 }
<> 144:ef7eb2e8f9f7 1184 break;
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1187 {
<> 144:ef7eb2e8f9f7 1188 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1189 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1190 }
<> 144:ef7eb2e8f9f7 1191 break;
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 default:
<> 144:ef7eb2e8f9f7 1194 break;
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1198 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1201 {
<> 144:ef7eb2e8f9f7 1202 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1203 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1204 }
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1207 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Return function status */
<> 144:ef7eb2e8f9f7 1210 return HAL_OK;
<> 144:ef7eb2e8f9f7 1211 }
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /**
<> 144:ef7eb2e8f9f7 1214 * @brief Stops the PWM signal generation in interrupt mode.
Anna Bridge 180:96ed750bd169 1215 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1216 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1217 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1218 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1219 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1220 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1221 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1222 * @retval HAL status
<> 144:ef7eb2e8f9f7 1223 */
<> 144:ef7eb2e8f9f7 1224 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1225 {
<> 144:ef7eb2e8f9f7 1226 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1227 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 switch (Channel)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1234 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1235 }
<> 144:ef7eb2e8f9f7 1236 break;
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1239 {
<> 144:ef7eb2e8f9f7 1240 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1241 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243 break;
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1246 {
<> 144:ef7eb2e8f9f7 1247 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1248 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1249 }
<> 144:ef7eb2e8f9f7 1250 break;
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1253 {
<> 144:ef7eb2e8f9f7 1254 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1255 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1256 }
<> 144:ef7eb2e8f9f7 1257 break;
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 default:
<> 144:ef7eb2e8f9f7 1260 break;
<> 144:ef7eb2e8f9f7 1261 }
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1264 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1267 {
<> 144:ef7eb2e8f9f7 1268 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1269 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1270 }
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1273 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* Return function status */
<> 144:ef7eb2e8f9f7 1276 return HAL_OK;
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /**
<> 144:ef7eb2e8f9f7 1280 * @brief Starts the TIM PWM signal generation in DMA mode.
Anna Bridge 180:96ed750bd169 1281 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1282 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1283 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1284 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1285 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1286 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1287 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
Anna Bridge 180:96ed750bd169 1288 * @param pData The source Buffer address.
Anna Bridge 180:96ed750bd169 1289 * @param Length The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1290 * @retval HAL status
<> 144:ef7eb2e8f9f7 1291 */
<> 144:ef7eb2e8f9f7 1292 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1293 {
<> 144:ef7eb2e8f9f7 1294 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1295 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1298 {
<> 144:ef7eb2e8f9f7 1299 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1302 {
<> 156:95d6b41a828b 1303 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1306 }
<> 144:ef7eb2e8f9f7 1307 else
<> 144:ef7eb2e8f9f7 1308 {
<> 144:ef7eb2e8f9f7 1309 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1310 }
<> 144:ef7eb2e8f9f7 1311 }
<> 144:ef7eb2e8f9f7 1312 switch (Channel)
<> 144:ef7eb2e8f9f7 1313 {
<> 144:ef7eb2e8f9f7 1314 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1317 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1320 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1323 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1326 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1327 }
<> 144:ef7eb2e8f9f7 1328 break;
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1331 {
<> 144:ef7eb2e8f9f7 1332 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1333 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1334
<> 144:ef7eb2e8f9f7 1335 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1336 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1337
<> 144:ef7eb2e8f9f7 1338 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1339 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1342 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1343 }
<> 144:ef7eb2e8f9f7 1344 break;
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1347 {
<> 144:ef7eb2e8f9f7 1348 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1349 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1352 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1355 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1356
<> 144:ef7eb2e8f9f7 1357 /* Enable the TIM Output Capture/Compare 3 request */
<> 144:ef7eb2e8f9f7 1358 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1359 }
<> 144:ef7eb2e8f9f7 1360 break;
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1363 {
<> 144:ef7eb2e8f9f7 1364 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1365 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1368 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1371 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1374 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1375 }
<> 144:ef7eb2e8f9f7 1376 break;
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 default:
<> 144:ef7eb2e8f9f7 1379 break;
<> 144:ef7eb2e8f9f7 1380 }
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1383 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1384
<> 144:ef7eb2e8f9f7 1385 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1386 {
<> 144:ef7eb2e8f9f7 1387 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1388 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1389 }
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1392 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* Return function status */
<> 144:ef7eb2e8f9f7 1395 return HAL_OK;
<> 144:ef7eb2e8f9f7 1396 }
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 /**
<> 144:ef7eb2e8f9f7 1399 * @brief Stops the TIM PWM signal generation in DMA mode.
Anna Bridge 180:96ed750bd169 1400 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1401 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1402 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1403 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1404 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1405 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1406 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1407 * @retval HAL status
<> 144:ef7eb2e8f9f7 1408 */
<> 144:ef7eb2e8f9f7 1409 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1412 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 switch (Channel)
<> 144:ef7eb2e8f9f7 1415 {
<> 144:ef7eb2e8f9f7 1416 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1417 {
<> 144:ef7eb2e8f9f7 1418 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1419 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1420 }
<> 144:ef7eb2e8f9f7 1421 break;
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1424 {
<> 144:ef7eb2e8f9f7 1425 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1426 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1427 }
<> 144:ef7eb2e8f9f7 1428 break;
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1431 {
<> 144:ef7eb2e8f9f7 1432 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1433 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435 break;
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1438 {
<> 144:ef7eb2e8f9f7 1439 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1440 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1441 }
<> 144:ef7eb2e8f9f7 1442 break;
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 default:
<> 144:ef7eb2e8f9f7 1445 break;
<> 144:ef7eb2e8f9f7 1446 }
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1449 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1452 {
<> 144:ef7eb2e8f9f7 1453 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1454 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1455 }
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1458 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1459
<> 144:ef7eb2e8f9f7 1460 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1461 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 /* Return function status */
<> 144:ef7eb2e8f9f7 1464 return HAL_OK;
<> 144:ef7eb2e8f9f7 1465 }
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /**
<> 144:ef7eb2e8f9f7 1468 * @}
<> 144:ef7eb2e8f9f7 1469 */
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<> 144:ef7eb2e8f9f7 1472 * @brief Time Input Capture functions
<> 144:ef7eb2e8f9f7 1473 *
<> 144:ef7eb2e8f9f7 1474 @verbatim
<> 144:ef7eb2e8f9f7 1475 ==============================================================================
<> 144:ef7eb2e8f9f7 1476 ##### Time Input Capture functions #####
<> 144:ef7eb2e8f9f7 1477 ==============================================================================
<> 144:ef7eb2e8f9f7 1478 [..]
<> 144:ef7eb2e8f9f7 1479 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1480 (+) Initialize and configure the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1481 (+) De-initialize the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1482 (+) Start the Time Input Capture.
<> 144:ef7eb2e8f9f7 1483 (+) Stop the Time Input Capture.
<> 144:ef7eb2e8f9f7 1484 (+) Start the Time Input Capture and enable interrupt.
<> 144:ef7eb2e8f9f7 1485 (+) Stop the Time Input Capture and disable interrupt.
<> 144:ef7eb2e8f9f7 1486 (+) Start the Time Input Capture and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1487 (+) Stop the Time Input Capture and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 @endverbatim
<> 144:ef7eb2e8f9f7 1490 * @{
<> 144:ef7eb2e8f9f7 1491 */
<> 144:ef7eb2e8f9f7 1492 /**
<> 144:ef7eb2e8f9f7 1493 * @brief Initializes the TIM Input Capture Time base according to the specified
<> 144:ef7eb2e8f9f7 1494 * parameters in the TIM_HandleTypeDef and create the associated handle.
Anna Bridge 180:96ed750bd169 1495 * @param htim TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1496 * @retval HAL status
<> 144:ef7eb2e8f9f7 1497 */
<> 144:ef7eb2e8f9f7 1498 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1499 {
<> 144:ef7eb2e8f9f7 1500 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1501 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1502 {
<> 144:ef7eb2e8f9f7 1503 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1504 }
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1507 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1508 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1509 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 1510 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1513 {
<> 144:ef7eb2e8f9f7 1514 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1515 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1518 HAL_TIM_IC_MspInit(htim);
<> 144:ef7eb2e8f9f7 1519 }
<> 144:ef7eb2e8f9f7 1520
<> 144:ef7eb2e8f9f7 1521 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1522 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1523
<> 144:ef7eb2e8f9f7 1524 /* Init the base time for the input capture */
<> 144:ef7eb2e8f9f7 1525 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1528 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 return HAL_OK;
<> 144:ef7eb2e8f9f7 1531 }
<> 144:ef7eb2e8f9f7 1532
<> 144:ef7eb2e8f9f7 1533 /**
<> 144:ef7eb2e8f9f7 1534 * @brief DeInitializes the TIM peripheral
Anna Bridge 180:96ed750bd169 1535 * @param htim TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1536 * @retval HAL status
<> 144:ef7eb2e8f9f7 1537 */
<> 144:ef7eb2e8f9f7 1538 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1539 {
<> 144:ef7eb2e8f9f7 1540 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1541 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1546 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1549 HAL_TIM_IC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1552 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /* Release Lock */
<> 144:ef7eb2e8f9f7 1555 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1556
<> 144:ef7eb2e8f9f7 1557 return HAL_OK;
<> 144:ef7eb2e8f9f7 1558 }
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /**
<> 144:ef7eb2e8f9f7 1561 * @brief Initializes the TIM Input Capture MSP.
Anna Bridge 180:96ed750bd169 1562 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 1563 * @retval None
<> 144:ef7eb2e8f9f7 1564 */
<> 144:ef7eb2e8f9f7 1565 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1566 {
<> 144:ef7eb2e8f9f7 1567 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1568 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1571 the HAL_TIM_IC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1572 */
<> 144:ef7eb2e8f9f7 1573 }
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575 /**
<> 144:ef7eb2e8f9f7 1576 * @brief DeInitializes TIM Input Capture MSP.
Anna Bridge 180:96ed750bd169 1577 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 1578 * @retval None
<> 144:ef7eb2e8f9f7 1579 */
<> 144:ef7eb2e8f9f7 1580 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1581 {
<> 144:ef7eb2e8f9f7 1582 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1583 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1586 the HAL_TIM_IC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1587 */
<> 144:ef7eb2e8f9f7 1588 }
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /**
<> 144:ef7eb2e8f9f7 1591 * @brief Starts the TIM Input Capture measurement.
Anna Bridge 180:96ed750bd169 1592 * @param htim TIM Input Capture handle
Anna Bridge 180:96ed750bd169 1593 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1594 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1595 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1596 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1597 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1598 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1599 * @retval HAL status
<> 144:ef7eb2e8f9f7 1600 */
<> 144:ef7eb2e8f9f7 1601 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1602 {
<> 144:ef7eb2e8f9f7 1603 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1604 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1607 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1610 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /* Return function status */
<> 144:ef7eb2e8f9f7 1613 return HAL_OK;
<> 144:ef7eb2e8f9f7 1614 }
<> 144:ef7eb2e8f9f7 1615
<> 144:ef7eb2e8f9f7 1616 /**
<> 144:ef7eb2e8f9f7 1617 * @brief Stops the TIM Input Capture measurement.
Anna Bridge 180:96ed750bd169 1618 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1619 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1620 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1621 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1622 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1623 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1624 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1625 * @retval HAL status
<> 144:ef7eb2e8f9f7 1626 */
<> 144:ef7eb2e8f9f7 1627 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1628 {
<> 144:ef7eb2e8f9f7 1629 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1630 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1633 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1634
<> 144:ef7eb2e8f9f7 1635 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1636 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 /* Return function status */
<> 144:ef7eb2e8f9f7 1639 return HAL_OK;
<> 144:ef7eb2e8f9f7 1640 }
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /**
<> 144:ef7eb2e8f9f7 1643 * @brief Starts the TIM Input Capture measurement in interrupt mode.
Anna Bridge 180:96ed750bd169 1644 * @param htim TIM Input Capture handle
Anna Bridge 180:96ed750bd169 1645 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1646 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1647 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1648 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1649 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1650 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1651 * @retval HAL status
<> 144:ef7eb2e8f9f7 1652 */
<> 144:ef7eb2e8f9f7 1653 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1654 {
<> 144:ef7eb2e8f9f7 1655 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1656 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658 switch (Channel)
<> 144:ef7eb2e8f9f7 1659 {
<> 144:ef7eb2e8f9f7 1660 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1661 {
<> 144:ef7eb2e8f9f7 1662 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1663 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1664 }
<> 144:ef7eb2e8f9f7 1665 break;
<> 144:ef7eb2e8f9f7 1666
<> 144:ef7eb2e8f9f7 1667 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1668 {
<> 144:ef7eb2e8f9f7 1669 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1670 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1671 }
<> 144:ef7eb2e8f9f7 1672 break;
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1675 {
<> 144:ef7eb2e8f9f7 1676 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1677 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1678 }
<> 144:ef7eb2e8f9f7 1679 break;
<> 144:ef7eb2e8f9f7 1680
<> 144:ef7eb2e8f9f7 1681 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1682 {
<> 144:ef7eb2e8f9f7 1683 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1685 }
<> 144:ef7eb2e8f9f7 1686 break;
<> 144:ef7eb2e8f9f7 1687
<> 144:ef7eb2e8f9f7 1688 default:
<> 144:ef7eb2e8f9f7 1689 break;
<> 144:ef7eb2e8f9f7 1690 }
<> 144:ef7eb2e8f9f7 1691 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1692 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1695 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 /* Return function status */
<> 144:ef7eb2e8f9f7 1698 return HAL_OK;
<> 144:ef7eb2e8f9f7 1699 }
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 /**
<> 144:ef7eb2e8f9f7 1702 * @brief Stops the TIM Input Capture measurement in interrupt mode.
Anna Bridge 180:96ed750bd169 1703 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1704 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1705 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1706 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1707 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1708 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1709 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1710 * @retval HAL status
<> 144:ef7eb2e8f9f7 1711 */
<> 144:ef7eb2e8f9f7 1712 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1713 {
<> 144:ef7eb2e8f9f7 1714 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1715 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 switch (Channel)
<> 144:ef7eb2e8f9f7 1718 {
<> 144:ef7eb2e8f9f7 1719 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1720 {
<> 144:ef7eb2e8f9f7 1721 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1722 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1723 }
<> 144:ef7eb2e8f9f7 1724 break;
<> 144:ef7eb2e8f9f7 1725
<> 144:ef7eb2e8f9f7 1726 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1727 {
<> 144:ef7eb2e8f9f7 1728 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1729 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1730 }
<> 144:ef7eb2e8f9f7 1731 break;
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1734 {
<> 144:ef7eb2e8f9f7 1735 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1737 }
<> 144:ef7eb2e8f9f7 1738 break;
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1741 {
<> 144:ef7eb2e8f9f7 1742 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1743 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1744 }
<> 144:ef7eb2e8f9f7 1745 break;
<> 144:ef7eb2e8f9f7 1746
<> 144:ef7eb2e8f9f7 1747 default:
<> 144:ef7eb2e8f9f7 1748 break;
<> 144:ef7eb2e8f9f7 1749 }
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1752 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1753
<> 144:ef7eb2e8f9f7 1754 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1755 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 /* Return function status */
<> 144:ef7eb2e8f9f7 1758 return HAL_OK;
<> 144:ef7eb2e8f9f7 1759 }
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /**
<> 144:ef7eb2e8f9f7 1762 * @brief Starts the TIM Input Capture measurement in DMA mode.
Anna Bridge 180:96ed750bd169 1763 * @param htim TIM Input Capture handle
Anna Bridge 180:96ed750bd169 1764 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1765 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1766 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1767 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1768 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1769 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
Anna Bridge 180:96ed750bd169 1770 * @param pData The destination Buffer address.
Anna Bridge 180:96ed750bd169 1771 * @param Length The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 1772 * @retval HAL status
<> 144:ef7eb2e8f9f7 1773 */
<> 144:ef7eb2e8f9f7 1774 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1775 {
<> 144:ef7eb2e8f9f7 1776 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1777 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1778 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1779
<> 144:ef7eb2e8f9f7 1780 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1781 {
<> 144:ef7eb2e8f9f7 1782 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1785 {
<> 156:95d6b41a828b 1786 if((pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1787 {
<> 144:ef7eb2e8f9f7 1788 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1789 }
<> 144:ef7eb2e8f9f7 1790 else
<> 144:ef7eb2e8f9f7 1791 {
<> 144:ef7eb2e8f9f7 1792 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1793 }
<> 144:ef7eb2e8f9f7 1794 }
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 switch (Channel)
<> 144:ef7eb2e8f9f7 1797 {
<> 144:ef7eb2e8f9f7 1798 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1799 {
<> 144:ef7eb2e8f9f7 1800 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1801 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1804 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1805
<> 144:ef7eb2e8f9f7 1806 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1807 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1808
<> 144:ef7eb2e8f9f7 1809 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1810 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1811 }
<> 144:ef7eb2e8f9f7 1812 break;
<> 144:ef7eb2e8f9f7 1813
<> 144:ef7eb2e8f9f7 1814 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1815 {
<> 144:ef7eb2e8f9f7 1816 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1817 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1818
<> 144:ef7eb2e8f9f7 1819 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1820 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1823 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1824
<> 144:ef7eb2e8f9f7 1825 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1826 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1827 }
<> 144:ef7eb2e8f9f7 1828 break;
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1831 {
<> 144:ef7eb2e8f9f7 1832 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1833 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1834
<> 144:ef7eb2e8f9f7 1835 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1836 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1837
<> 144:ef7eb2e8f9f7 1838 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1839 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1842 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1843 }
<> 144:ef7eb2e8f9f7 1844 break;
<> 144:ef7eb2e8f9f7 1845
<> 144:ef7eb2e8f9f7 1846 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1847 {
<> 144:ef7eb2e8f9f7 1848 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1849 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1850
<> 144:ef7eb2e8f9f7 1851 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1852 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1853
<> 144:ef7eb2e8f9f7 1854 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1855 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1858 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860 break;
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 default:
<> 144:ef7eb2e8f9f7 1863 break;
<> 144:ef7eb2e8f9f7 1864 }
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1867 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1868
<> 144:ef7eb2e8f9f7 1869 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1870 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1871
<> 144:ef7eb2e8f9f7 1872 /* Return function status */
<> 144:ef7eb2e8f9f7 1873 return HAL_OK;
<> 144:ef7eb2e8f9f7 1874 }
<> 144:ef7eb2e8f9f7 1875
<> 144:ef7eb2e8f9f7 1876 /**
<> 144:ef7eb2e8f9f7 1877 * @brief Stops the TIM Input Capture measurement in DMA mode.
Anna Bridge 180:96ed750bd169 1878 * @param htim TIM Input Capture handle
Anna Bridge 180:96ed750bd169 1879 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1880 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1881 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1882 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1883 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1884 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1885 * @retval HAL status
<> 144:ef7eb2e8f9f7 1886 */
<> 144:ef7eb2e8f9f7 1887 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1888 {
<> 144:ef7eb2e8f9f7 1889 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1890 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1891 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1892
<> 144:ef7eb2e8f9f7 1893 switch (Channel)
<> 144:ef7eb2e8f9f7 1894 {
<> 144:ef7eb2e8f9f7 1895 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1896 {
<> 144:ef7eb2e8f9f7 1897 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1898 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1899 }
<> 144:ef7eb2e8f9f7 1900 break;
<> 144:ef7eb2e8f9f7 1901
<> 144:ef7eb2e8f9f7 1902 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1903 {
<> 144:ef7eb2e8f9f7 1904 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1905 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1906 }
<> 144:ef7eb2e8f9f7 1907 break;
<> 144:ef7eb2e8f9f7 1908
<> 144:ef7eb2e8f9f7 1909 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1910 {
<> 144:ef7eb2e8f9f7 1911 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1913 }
<> 144:ef7eb2e8f9f7 1914 break;
<> 144:ef7eb2e8f9f7 1915
<> 144:ef7eb2e8f9f7 1916 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1917 {
<> 144:ef7eb2e8f9f7 1918 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1920 }
<> 144:ef7eb2e8f9f7 1921 break;
<> 144:ef7eb2e8f9f7 1922
<> 144:ef7eb2e8f9f7 1923 default:
<> 144:ef7eb2e8f9f7 1924 break;
<> 144:ef7eb2e8f9f7 1925 }
<> 144:ef7eb2e8f9f7 1926
<> 144:ef7eb2e8f9f7 1927 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1928 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1931 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1932
<> 144:ef7eb2e8f9f7 1933 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1934 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1935
<> 144:ef7eb2e8f9f7 1936 /* Return function status */
<> 144:ef7eb2e8f9f7 1937 return HAL_OK;
<> 144:ef7eb2e8f9f7 1938 }
<> 144:ef7eb2e8f9f7 1939 /**
<> 144:ef7eb2e8f9f7 1940 * @}
<> 144:ef7eb2e8f9f7 1941 */
<> 144:ef7eb2e8f9f7 1942
<> 144:ef7eb2e8f9f7 1943 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<> 144:ef7eb2e8f9f7 1944 * @brief Time One Pulse functions
<> 144:ef7eb2e8f9f7 1945 *
<> 144:ef7eb2e8f9f7 1946 @verbatim
<> 144:ef7eb2e8f9f7 1947 ==============================================================================
<> 144:ef7eb2e8f9f7 1948 ##### Time One Pulse functions #####
<> 144:ef7eb2e8f9f7 1949 ==============================================================================
<> 144:ef7eb2e8f9f7 1950 [..]
<> 144:ef7eb2e8f9f7 1951 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1952 (+) Initialize and configure the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1953 (+) De-initialize the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1954 (+) Start the Time One Pulse.
<> 144:ef7eb2e8f9f7 1955 (+) Stop the Time One Pulse.
<> 144:ef7eb2e8f9f7 1956 (+) Start the Time One Pulse and enable interrupt.
<> 144:ef7eb2e8f9f7 1957 (+) Stop the Time One Pulse and disable interrupt.
<> 144:ef7eb2e8f9f7 1958 (+) Start the Time One Pulse and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1959 (+) Stop the Time One Pulse and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961 @endverbatim
<> 144:ef7eb2e8f9f7 1962 * @{
<> 144:ef7eb2e8f9f7 1963 */
<> 144:ef7eb2e8f9f7 1964 /**
<> 144:ef7eb2e8f9f7 1965 * @brief Initializes the TIM One Pulse Time Base according to the specified
<> 144:ef7eb2e8f9f7 1966 * parameters in the TIM_HandleTypeDef and create the associated handle.
Anna Bridge 180:96ed750bd169 1967 * @param htim TIM OnePulse handle
Anna Bridge 180:96ed750bd169 1968 * @param OnePulseMode Select the One pulse mode.
<> 144:ef7eb2e8f9f7 1969 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1970 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<> 144:ef7eb2e8f9f7 1971 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
<> 144:ef7eb2e8f9f7 1972 * @retval HAL status
<> 144:ef7eb2e8f9f7 1973 */
<> 144:ef7eb2e8f9f7 1974 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<> 144:ef7eb2e8f9f7 1975 {
<> 144:ef7eb2e8f9f7 1976 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1977 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1978 {
<> 144:ef7eb2e8f9f7 1979 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1980 }
<> 144:ef7eb2e8f9f7 1981
<> 144:ef7eb2e8f9f7 1982 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1983 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1984 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1985 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1986 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<> 156:95d6b41a828b 1987 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 1988
<> 144:ef7eb2e8f9f7 1989 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1990 {
<> 144:ef7eb2e8f9f7 1991 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1992 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1993
<> 144:ef7eb2e8f9f7 1994 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1995 HAL_TIM_OnePulse_MspInit(htim);
<> 144:ef7eb2e8f9f7 1996 }
<> 144:ef7eb2e8f9f7 1997
<> 144:ef7eb2e8f9f7 1998 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1999 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001 /* Configure the Time base in the One Pulse Mode */
<> 144:ef7eb2e8f9f7 2002 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2003
<> 144:ef7eb2e8f9f7 2004 /* Reset the OPM Bit */
<> 144:ef7eb2e8f9f7 2005 htim->Instance->CR1 &= ~TIM_CR1_OPM;
<> 144:ef7eb2e8f9f7 2006
<> 144:ef7eb2e8f9f7 2007 /* Configure the OPM Mode */
<> 144:ef7eb2e8f9f7 2008 htim->Instance->CR1 |= OnePulseMode;
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2011 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2012
<> 144:ef7eb2e8f9f7 2013 return HAL_OK;
<> 144:ef7eb2e8f9f7 2014 }
<> 144:ef7eb2e8f9f7 2015
<> 144:ef7eb2e8f9f7 2016 /**
<> 144:ef7eb2e8f9f7 2017 * @brief DeInitializes the TIM One Pulse
Anna Bridge 180:96ed750bd169 2018 * @param htim TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2019 * @retval HAL status
<> 144:ef7eb2e8f9f7 2020 */
<> 144:ef7eb2e8f9f7 2021 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2022 {
<> 144:ef7eb2e8f9f7 2023 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2024 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2025
<> 144:ef7eb2e8f9f7 2026 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2027
<> 144:ef7eb2e8f9f7 2028 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2029 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2030
<> 144:ef7eb2e8f9f7 2031 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2032 HAL_TIM_OnePulse_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2033
<> 144:ef7eb2e8f9f7 2034 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2035 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2036
<> 144:ef7eb2e8f9f7 2037 /* Release Lock */
<> 144:ef7eb2e8f9f7 2038 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2039
<> 144:ef7eb2e8f9f7 2040 return HAL_OK;
<> 144:ef7eb2e8f9f7 2041 }
<> 144:ef7eb2e8f9f7 2042
<> 144:ef7eb2e8f9f7 2043 /**
<> 144:ef7eb2e8f9f7 2044 * @brief Initializes the TIM One Pulse MSP.
Anna Bridge 180:96ed750bd169 2045 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 2046 * @retval None
<> 144:ef7eb2e8f9f7 2047 */
<> 144:ef7eb2e8f9f7 2048 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2049 {
<> 144:ef7eb2e8f9f7 2050 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2051 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2054 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2055 */
<> 144:ef7eb2e8f9f7 2056 }
<> 144:ef7eb2e8f9f7 2057
<> 144:ef7eb2e8f9f7 2058 /**
<> 144:ef7eb2e8f9f7 2059 * @brief DeInitializes TIM One Pulse MSP.
Anna Bridge 180:96ed750bd169 2060 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 2061 * @retval None
<> 144:ef7eb2e8f9f7 2062 */
<> 144:ef7eb2e8f9f7 2063 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2064 {
<> 144:ef7eb2e8f9f7 2065 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2066 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2067
<> 144:ef7eb2e8f9f7 2068 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2069 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2070 */
<> 144:ef7eb2e8f9f7 2071 }
<> 144:ef7eb2e8f9f7 2072
<> 144:ef7eb2e8f9f7 2073 /**
<> 144:ef7eb2e8f9f7 2074 * @brief Starts the TIM One Pulse signal generation.
Anna Bridge 180:96ed750bd169 2075 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 2076 * @param OutputChannel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2077 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2078 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2079 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2080 * @retval HAL status
<> 144:ef7eb2e8f9f7 2081 */
<> 144:ef7eb2e8f9f7 2082 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2083 {
<> 144:ef7eb2e8f9f7 2084 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2085 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2086 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2087 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2088 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2089
<> 144:ef7eb2e8f9f7 2090 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2091 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2094 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2097 {
<> 144:ef7eb2e8f9f7 2098 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2099 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2100 }
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 /* Return function status */
<> 144:ef7eb2e8f9f7 2103 return HAL_OK;
<> 144:ef7eb2e8f9f7 2104 }
<> 144:ef7eb2e8f9f7 2105
<> 144:ef7eb2e8f9f7 2106 /**
<> 144:ef7eb2e8f9f7 2107 * @brief Stops the TIM One Pulse signal generation.
Anna Bridge 180:96ed750bd169 2108 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 2109 * @param OutputChannel TIM Channels to be disable
<> 144:ef7eb2e8f9f7 2110 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2111 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2112 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2113 * @retval HAL status
<> 144:ef7eb2e8f9f7 2114 */
<> 144:ef7eb2e8f9f7 2115 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2116 {
<> 144:ef7eb2e8f9f7 2117 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2118 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2119 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2120 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2121 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2122
<> 144:ef7eb2e8f9f7 2123 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2124 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2125
<> 144:ef7eb2e8f9f7 2126 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2127 {
<> 144:ef7eb2e8f9f7 2128 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 2129 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2130 }
<> 144:ef7eb2e8f9f7 2131
<> 144:ef7eb2e8f9f7 2132 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2133 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2134
<> 144:ef7eb2e8f9f7 2135 /* Return function status */
<> 144:ef7eb2e8f9f7 2136 return HAL_OK;
<> 144:ef7eb2e8f9f7 2137 }
<> 144:ef7eb2e8f9f7 2138
<> 144:ef7eb2e8f9f7 2139 /**
<> 144:ef7eb2e8f9f7 2140 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
Anna Bridge 180:96ed750bd169 2141 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 2142 * @param OutputChannel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2143 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2144 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2145 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2146 * @retval HAL status
<> 144:ef7eb2e8f9f7 2147 */
<> 144:ef7eb2e8f9f7 2148 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2149 {
<> 144:ef7eb2e8f9f7 2150 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2151 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2152 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2153 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2154 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2155
<> 144:ef7eb2e8f9f7 2156 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2157 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2158
<> 144:ef7eb2e8f9f7 2159 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2160 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2161
<> 144:ef7eb2e8f9f7 2162 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2163 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2166 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2169 {
<> 144:ef7eb2e8f9f7 2170 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2171 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2172 }
<> 144:ef7eb2e8f9f7 2173
<> 144:ef7eb2e8f9f7 2174 /* Return function status */
<> 144:ef7eb2e8f9f7 2175 return HAL_OK;
<> 144:ef7eb2e8f9f7 2176 }
<> 144:ef7eb2e8f9f7 2177
<> 144:ef7eb2e8f9f7 2178 /**
<> 144:ef7eb2e8f9f7 2179 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
Anna Bridge 180:96ed750bd169 2180 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 2181 * @param OutputChannel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2182 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2183 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2184 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2185 * @retval HAL status
<> 144:ef7eb2e8f9f7 2186 */
<> 144:ef7eb2e8f9f7 2187 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2188 {
<> 144:ef7eb2e8f9f7 2189 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2190 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2191
<> 144:ef7eb2e8f9f7 2192 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2193 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2194
<> 144:ef7eb2e8f9f7 2195 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2196 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2197 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2198 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2199 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2200 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2201 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2202
<> 144:ef7eb2e8f9f7 2203 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2204 {
<> 144:ef7eb2e8f9f7 2205 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 2206 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2207 }
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2210 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2211
<> 144:ef7eb2e8f9f7 2212 /* Return function status */
<> 144:ef7eb2e8f9f7 2213 return HAL_OK;
<> 144:ef7eb2e8f9f7 2214 }
<> 144:ef7eb2e8f9f7 2215
<> 144:ef7eb2e8f9f7 2216 /**
<> 144:ef7eb2e8f9f7 2217 * @}
<> 144:ef7eb2e8f9f7 2218 */
<> 144:ef7eb2e8f9f7 2219
<> 144:ef7eb2e8f9f7 2220 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<> 144:ef7eb2e8f9f7 2221 * @brief Time Encoder functions
<> 144:ef7eb2e8f9f7 2222 *
<> 144:ef7eb2e8f9f7 2223 @verbatim
<> 144:ef7eb2e8f9f7 2224 ==============================================================================
<> 144:ef7eb2e8f9f7 2225 ##### Time Encoder functions #####
<> 144:ef7eb2e8f9f7 2226 ==============================================================================
<> 144:ef7eb2e8f9f7 2227 [..]
<> 144:ef7eb2e8f9f7 2228 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2229 (+) Initialize and configure the TIM Encoder.
<> 144:ef7eb2e8f9f7 2230 (+) De-initialize the TIM Encoder.
<> 144:ef7eb2e8f9f7 2231 (+) Start the Time Encoder.
<> 144:ef7eb2e8f9f7 2232 (+) Stop the Time Encoder.
<> 144:ef7eb2e8f9f7 2233 (+) Start the Time Encoder and enable interrupt.
<> 144:ef7eb2e8f9f7 2234 (+) Stop the Time Encoder and disable interrupt.
<> 144:ef7eb2e8f9f7 2235 (+) Start the Time Encoder and enable DMA transfer.
<> 144:ef7eb2e8f9f7 2236 (+) Stop the Time Encoder and disable DMA transfer.
<> 144:ef7eb2e8f9f7 2237
<> 144:ef7eb2e8f9f7 2238 @endverbatim
<> 144:ef7eb2e8f9f7 2239 * @{
<> 144:ef7eb2e8f9f7 2240 */
<> 144:ef7eb2e8f9f7 2241 /**
<> 144:ef7eb2e8f9f7 2242 * @brief Initializes the TIM Encoder Interface and create the associated handle.
Anna Bridge 180:96ed750bd169 2243 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 2244 * @param sConfig TIM Encoder Interface configuration structure
<> 144:ef7eb2e8f9f7 2245 * @retval HAL status
<> 144:ef7eb2e8f9f7 2246 */
<> 144:ef7eb2e8f9f7 2247 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 2248 {
<> 156:95d6b41a828b 2249 uint32_t tmpsmcr = 0U;
<> 156:95d6b41a828b 2250 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 2251 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 2252
<> 144:ef7eb2e8f9f7 2253 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2254 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2255 {
<> 144:ef7eb2e8f9f7 2256 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2257 }
<> 144:ef7eb2e8f9f7 2258
<> 144:ef7eb2e8f9f7 2259 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2260 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 156:95d6b41a828b 2261 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 156:95d6b41a828b 2262 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 2263 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 2264 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<> 144:ef7eb2e8f9f7 2265 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<> 144:ef7eb2e8f9f7 2266 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<> 144:ef7eb2e8f9f7 2267 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 2268 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<> 144:ef7eb2e8f9f7 2269 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 2270 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<> 144:ef7eb2e8f9f7 2271 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 2272 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<> 144:ef7eb2e8f9f7 2273
<> 144:ef7eb2e8f9f7 2274 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2275 {
<> 144:ef7eb2e8f9f7 2276 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2277 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2278
<> 144:ef7eb2e8f9f7 2279 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2280 HAL_TIM_Encoder_MspInit(htim);
<> 144:ef7eb2e8f9f7 2281 }
<> 144:ef7eb2e8f9f7 2282
<> 144:ef7eb2e8f9f7 2283 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2284 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2285
<> 144:ef7eb2e8f9f7 2286 /* Reset the SMS bits */
<> 144:ef7eb2e8f9f7 2287 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 2288
<> 144:ef7eb2e8f9f7 2289 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 2290 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 2293 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 2294
<> 144:ef7eb2e8f9f7 2295 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2296 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 2297
<> 144:ef7eb2e8f9f7 2298 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2299 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 2300
<> 144:ef7eb2e8f9f7 2301 /* Set the encoder Mode */
<> 144:ef7eb2e8f9f7 2302 tmpsmcr |= sConfig->EncoderMode;
<> 144:ef7eb2e8f9f7 2303
<> 144:ef7eb2e8f9f7 2304 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
<> 144:ef7eb2e8f9f7 2305 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
<> 156:95d6b41a828b 2306 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
<> 144:ef7eb2e8f9f7 2307
<> 144:ef7eb2e8f9f7 2308 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<> 144:ef7eb2e8f9f7 2309 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
<> 144:ef7eb2e8f9f7 2310 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
<> 156:95d6b41a828b 2311 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
<> 156:95d6b41a828b 2312 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
<> 144:ef7eb2e8f9f7 2313
<> 144:ef7eb2e8f9f7 2314 /* Set the TI1 and the TI2 Polarities */
<> 144:ef7eb2e8f9f7 2315 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
<> 144:ef7eb2e8f9f7 2316 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
<> 156:95d6b41a828b 2317 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
<> 144:ef7eb2e8f9f7 2318
<> 144:ef7eb2e8f9f7 2319 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 2320 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 2321
<> 144:ef7eb2e8f9f7 2322 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 2323 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 2324
<> 144:ef7eb2e8f9f7 2325 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2326 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2327
<> 144:ef7eb2e8f9f7 2328 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2329 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2330
<> 144:ef7eb2e8f9f7 2331 return HAL_OK;
<> 144:ef7eb2e8f9f7 2332 }
<> 144:ef7eb2e8f9f7 2333
<> 144:ef7eb2e8f9f7 2334
<> 144:ef7eb2e8f9f7 2335 /**
<> 144:ef7eb2e8f9f7 2336 * @brief DeInitializes the TIM Encoder interface
Anna Bridge 180:96ed750bd169 2337 * @param htim TIM Encoder handle
<> 144:ef7eb2e8f9f7 2338 * @retval HAL status
<> 144:ef7eb2e8f9f7 2339 */
<> 144:ef7eb2e8f9f7 2340 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2341 {
<> 144:ef7eb2e8f9f7 2342 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2343 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2344
<> 144:ef7eb2e8f9f7 2345 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2346
<> 144:ef7eb2e8f9f7 2347 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2348 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2349
<> 144:ef7eb2e8f9f7 2350 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2351 HAL_TIM_Encoder_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2352
<> 144:ef7eb2e8f9f7 2353 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2354 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2355
<> 144:ef7eb2e8f9f7 2356 /* Release Lock */
<> 144:ef7eb2e8f9f7 2357 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2358
<> 144:ef7eb2e8f9f7 2359 return HAL_OK;
<> 144:ef7eb2e8f9f7 2360 }
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 /**
<> 144:ef7eb2e8f9f7 2363 * @brief Initializes the TIM Encoder Interface MSP.
Anna Bridge 180:96ed750bd169 2364 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 2365 * @retval None
<> 144:ef7eb2e8f9f7 2366 */
<> 144:ef7eb2e8f9f7 2367 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2368 {
<> 144:ef7eb2e8f9f7 2369 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2370 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2371
<> 144:ef7eb2e8f9f7 2372 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2373 the HAL_TIM_Encoder_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2374 */
<> 144:ef7eb2e8f9f7 2375 }
<> 144:ef7eb2e8f9f7 2376
<> 144:ef7eb2e8f9f7 2377 /**
<> 144:ef7eb2e8f9f7 2378 * @brief DeInitializes TIM Encoder Interface MSP.
Anna Bridge 180:96ed750bd169 2379 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 2380 * @retval None
<> 144:ef7eb2e8f9f7 2381 */
<> 144:ef7eb2e8f9f7 2382 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2383 {
<> 144:ef7eb2e8f9f7 2384 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2385 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2386
<> 144:ef7eb2e8f9f7 2387 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2388 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2389 */
<> 144:ef7eb2e8f9f7 2390 }
<> 144:ef7eb2e8f9f7 2391
<> 144:ef7eb2e8f9f7 2392 /**
<> 144:ef7eb2e8f9f7 2393 * @brief Starts the TIM Encoder Interface.
Anna Bridge 180:96ed750bd169 2394 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 2395 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2396 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2397 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2398 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2399 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2400 * @retval HAL status
<> 144:ef7eb2e8f9f7 2401 */
<> 144:ef7eb2e8f9f7 2402 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2403 {
<> 144:ef7eb2e8f9f7 2404 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2405 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2406
<> 144:ef7eb2e8f9f7 2407 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2408 switch (Channel)
<> 144:ef7eb2e8f9f7 2409 {
<> 144:ef7eb2e8f9f7 2410 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2411 {
<> 144:ef7eb2e8f9f7 2412 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2413 break;
<> 144:ef7eb2e8f9f7 2414 }
<> 144:ef7eb2e8f9f7 2415 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2416 {
<> 144:ef7eb2e8f9f7 2417 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2418 break;
<> 144:ef7eb2e8f9f7 2419 }
<> 144:ef7eb2e8f9f7 2420 default :
<> 144:ef7eb2e8f9f7 2421 {
<> 144:ef7eb2e8f9f7 2422 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2423 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2424 break;
<> 144:ef7eb2e8f9f7 2425 }
<> 144:ef7eb2e8f9f7 2426 }
<> 144:ef7eb2e8f9f7 2427 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2428 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2429
<> 144:ef7eb2e8f9f7 2430 /* Return function status */
<> 144:ef7eb2e8f9f7 2431 return HAL_OK;
<> 144:ef7eb2e8f9f7 2432 }
<> 144:ef7eb2e8f9f7 2433
<> 144:ef7eb2e8f9f7 2434 /**
<> 144:ef7eb2e8f9f7 2435 * @brief Stops the TIM Encoder Interface.
Anna Bridge 180:96ed750bd169 2436 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 2437 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 2438 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2439 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2440 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2441 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2442 * @retval HAL status
<> 144:ef7eb2e8f9f7 2443 */
<> 144:ef7eb2e8f9f7 2444 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2445 {
<> 144:ef7eb2e8f9f7 2446 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2447 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2448
<> 144:ef7eb2e8f9f7 2449 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2450 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2451 switch (Channel)
<> 144:ef7eb2e8f9f7 2452 {
<> 144:ef7eb2e8f9f7 2453 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2454 {
<> 144:ef7eb2e8f9f7 2455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2456 break;
<> 144:ef7eb2e8f9f7 2457 }
<> 144:ef7eb2e8f9f7 2458 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2459 {
<> 144:ef7eb2e8f9f7 2460 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2461 break;
<> 144:ef7eb2e8f9f7 2462 }
<> 144:ef7eb2e8f9f7 2463 default :
<> 144:ef7eb2e8f9f7 2464 {
<> 144:ef7eb2e8f9f7 2465 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2466 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2467 break;
<> 144:ef7eb2e8f9f7 2468 }
<> 144:ef7eb2e8f9f7 2469 }
<> 144:ef7eb2e8f9f7 2470
<> 144:ef7eb2e8f9f7 2471 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2472 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2473
<> 144:ef7eb2e8f9f7 2474 /* Return function status */
<> 144:ef7eb2e8f9f7 2475 return HAL_OK;
<> 144:ef7eb2e8f9f7 2476 }
<> 144:ef7eb2e8f9f7 2477
<> 144:ef7eb2e8f9f7 2478 /**
<> 144:ef7eb2e8f9f7 2479 * @brief Starts the TIM Encoder Interface in interrupt mode.
Anna Bridge 180:96ed750bd169 2480 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 2481 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2482 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2483 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2484 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2485 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2486 * @retval HAL status
<> 144:ef7eb2e8f9f7 2487 */
<> 144:ef7eb2e8f9f7 2488 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2489 {
<> 144:ef7eb2e8f9f7 2490 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2491 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2492
<> 144:ef7eb2e8f9f7 2493 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2494 /* Enable the capture compare Interrupts 1 and/or 2 */
<> 144:ef7eb2e8f9f7 2495 switch (Channel)
<> 144:ef7eb2e8f9f7 2496 {
<> 144:ef7eb2e8f9f7 2497 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2498 {
<> 144:ef7eb2e8f9f7 2499 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2500 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2501 break;
<> 144:ef7eb2e8f9f7 2502 }
<> 144:ef7eb2e8f9f7 2503 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2504 {
<> 144:ef7eb2e8f9f7 2505 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2506 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2507 break;
<> 144:ef7eb2e8f9f7 2508 }
<> 144:ef7eb2e8f9f7 2509 default :
<> 144:ef7eb2e8f9f7 2510 {
<> 144:ef7eb2e8f9f7 2511 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2512 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2513 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2514 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2515 break;
<> 144:ef7eb2e8f9f7 2516 }
<> 144:ef7eb2e8f9f7 2517 }
<> 144:ef7eb2e8f9f7 2518
<> 144:ef7eb2e8f9f7 2519 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2520 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2521
<> 144:ef7eb2e8f9f7 2522 /* Return function status */
<> 144:ef7eb2e8f9f7 2523 return HAL_OK;
<> 144:ef7eb2e8f9f7 2524 }
<> 144:ef7eb2e8f9f7 2525
<> 144:ef7eb2e8f9f7 2526 /**
<> 144:ef7eb2e8f9f7 2527 * @brief Stops the TIM Encoder Interface in interrupt mode.
Anna Bridge 180:96ed750bd169 2528 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 2529 * @param Channel TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 2530 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2531 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2532 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2533 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2534 * @retval HAL status
<> 144:ef7eb2e8f9f7 2535 */
<> 144:ef7eb2e8f9f7 2536 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2537 {
<> 144:ef7eb2e8f9f7 2538 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2539 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2540
<> 144:ef7eb2e8f9f7 2541 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2542 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2543 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2544 {
<> 144:ef7eb2e8f9f7 2545 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2546
<> 144:ef7eb2e8f9f7 2547 /* Disable the capture compare Interrupts 1 */
<> 144:ef7eb2e8f9f7 2548 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2549 }
<> 144:ef7eb2e8f9f7 2550 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2551 {
<> 144:ef7eb2e8f9f7 2552 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2553
<> 144:ef7eb2e8f9f7 2554 /* Disable the capture compare Interrupts 2 */
<> 144:ef7eb2e8f9f7 2555 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2556 }
<> 144:ef7eb2e8f9f7 2557 else
<> 144:ef7eb2e8f9f7 2558 {
<> 144:ef7eb2e8f9f7 2559 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2560 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2561
<> 144:ef7eb2e8f9f7 2562 /* Disable the capture compare Interrupts 1 and 2 */
<> 144:ef7eb2e8f9f7 2563 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2564 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2565 }
<> 144:ef7eb2e8f9f7 2566
<> 144:ef7eb2e8f9f7 2567 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2568 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2569
<> 144:ef7eb2e8f9f7 2570 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2571 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2572
<> 144:ef7eb2e8f9f7 2573 /* Return function status */
<> 144:ef7eb2e8f9f7 2574 return HAL_OK;
<> 144:ef7eb2e8f9f7 2575 }
<> 144:ef7eb2e8f9f7 2576
<> 144:ef7eb2e8f9f7 2577 /**
<> 144:ef7eb2e8f9f7 2578 * @brief Starts the TIM Encoder Interface in DMA mode.
Anna Bridge 180:96ed750bd169 2579 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 2580 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2581 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2582 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2583 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2584 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Anna Bridge 180:96ed750bd169 2585 * @param pData1 The destination Buffer address for IC1.
Anna Bridge 180:96ed750bd169 2586 * @param pData2 The destination Buffer address for IC2.
Anna Bridge 180:96ed750bd169 2587 * @param Length The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 2588 * @retval HAL status
<> 144:ef7eb2e8f9f7 2589 */
<> 144:ef7eb2e8f9f7 2590 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
<> 144:ef7eb2e8f9f7 2591 {
<> 144:ef7eb2e8f9f7 2592 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2593 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2594
<> 144:ef7eb2e8f9f7 2595 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 2596 {
<> 144:ef7eb2e8f9f7 2597 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2598 }
<> 144:ef7eb2e8f9f7 2599 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 2600 {
<> 156:95d6b41a828b 2601 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
<> 144:ef7eb2e8f9f7 2602 {
<> 144:ef7eb2e8f9f7 2603 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2604 }
<> 144:ef7eb2e8f9f7 2605 else
<> 144:ef7eb2e8f9f7 2606 {
<> 144:ef7eb2e8f9f7 2607 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2608 }
<> 144:ef7eb2e8f9f7 2609 }
<> 144:ef7eb2e8f9f7 2610
<> 144:ef7eb2e8f9f7 2611 switch (Channel)
<> 144:ef7eb2e8f9f7 2612 {
<> 144:ef7eb2e8f9f7 2613 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2614 {
<> 144:ef7eb2e8f9f7 2615 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2616 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2617
<> 144:ef7eb2e8f9f7 2618 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2619 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2620
<> 144:ef7eb2e8f9f7 2621 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2622 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<> 144:ef7eb2e8f9f7 2623
<> 144:ef7eb2e8f9f7 2624 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2625 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2626
<> 144:ef7eb2e8f9f7 2627 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2628 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2629
<> 144:ef7eb2e8f9f7 2630 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2631 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2632 }
<> 144:ef7eb2e8f9f7 2633 break;
<> 144:ef7eb2e8f9f7 2634
<> 144:ef7eb2e8f9f7 2635 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2636 {
<> 144:ef7eb2e8f9f7 2637 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2638 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2639
<> 144:ef7eb2e8f9f7 2640 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2641 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 2642 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2643 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2644
<> 144:ef7eb2e8f9f7 2645 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2647
<> 144:ef7eb2e8f9f7 2648 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2649 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2650
<> 144:ef7eb2e8f9f7 2651 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2652 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2653 }
<> 144:ef7eb2e8f9f7 2654 break;
<> 144:ef7eb2e8f9f7 2655
<> 144:ef7eb2e8f9f7 2656 case TIM_CHANNEL_ALL:
<> 144:ef7eb2e8f9f7 2657 {
<> 144:ef7eb2e8f9f7 2658 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2659 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2660
<> 144:ef7eb2e8f9f7 2661 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2662 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2663
<> 144:ef7eb2e8f9f7 2664 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2665 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<> 144:ef7eb2e8f9f7 2666
<> 144:ef7eb2e8f9f7 2667 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2668 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2669
<> 144:ef7eb2e8f9f7 2670 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2671 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2672
<> 144:ef7eb2e8f9f7 2673 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2674 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2675
<> 144:ef7eb2e8f9f7 2676 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2677 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2678
<> 144:ef7eb2e8f9f7 2679 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2680 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2681 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2682
<> 144:ef7eb2e8f9f7 2683 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2684 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2685 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2686 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2687 }
<> 144:ef7eb2e8f9f7 2688 break;
<> 144:ef7eb2e8f9f7 2689
<> 144:ef7eb2e8f9f7 2690 default:
<> 144:ef7eb2e8f9f7 2691 break;
<> 144:ef7eb2e8f9f7 2692 }
<> 144:ef7eb2e8f9f7 2693 /* Return function status */
<> 144:ef7eb2e8f9f7 2694 return HAL_OK;
<> 144:ef7eb2e8f9f7 2695 }
<> 144:ef7eb2e8f9f7 2696
<> 144:ef7eb2e8f9f7 2697 /**
<> 144:ef7eb2e8f9f7 2698 * @brief Stops the TIM Encoder Interface in DMA mode.
Anna Bridge 180:96ed750bd169 2699 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 2700 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2701 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2702 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2703 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2704 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2705 * @retval HAL status
<> 144:ef7eb2e8f9f7 2706 */
<> 144:ef7eb2e8f9f7 2707 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2708 {
<> 144:ef7eb2e8f9f7 2709 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2710 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2711
<> 144:ef7eb2e8f9f7 2712 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2713 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2714 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2715 {
<> 144:ef7eb2e8f9f7 2716 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2717
<> 144:ef7eb2e8f9f7 2718 /* Disable the capture compare DMA Request 1 */
<> 144:ef7eb2e8f9f7 2719 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2720 }
<> 144:ef7eb2e8f9f7 2721 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2722 {
<> 144:ef7eb2e8f9f7 2723 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2724
<> 144:ef7eb2e8f9f7 2725 /* Disable the capture compare DMA Request 2 */
<> 144:ef7eb2e8f9f7 2726 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2727 }
<> 144:ef7eb2e8f9f7 2728 else
<> 144:ef7eb2e8f9f7 2729 {
<> 144:ef7eb2e8f9f7 2730 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2731 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2732
<> 144:ef7eb2e8f9f7 2733 /* Disable the capture compare DMA Request 1 and 2 */
<> 144:ef7eb2e8f9f7 2734 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2735 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2736 }
<> 144:ef7eb2e8f9f7 2737
<> 144:ef7eb2e8f9f7 2738 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2739 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2740
<> 144:ef7eb2e8f9f7 2741 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2742 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2743
<> 144:ef7eb2e8f9f7 2744 /* Return function status */
<> 144:ef7eb2e8f9f7 2745 return HAL_OK;
<> 144:ef7eb2e8f9f7 2746 }
<> 144:ef7eb2e8f9f7 2747
<> 144:ef7eb2e8f9f7 2748 /**
<> 144:ef7eb2e8f9f7 2749 * @}
<> 144:ef7eb2e8f9f7 2750 */
<> 144:ef7eb2e8f9f7 2751 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<> 144:ef7eb2e8f9f7 2752 * @brief IRQ handler management
<> 144:ef7eb2e8f9f7 2753 *
<> 144:ef7eb2e8f9f7 2754 @verbatim
<> 144:ef7eb2e8f9f7 2755 ==============================================================================
<> 144:ef7eb2e8f9f7 2756 ##### IRQ handler management #####
<> 144:ef7eb2e8f9f7 2757 ==============================================================================
<> 144:ef7eb2e8f9f7 2758 [..]
<> 144:ef7eb2e8f9f7 2759 This section provides Timer IRQ handler function.
<> 144:ef7eb2e8f9f7 2760
<> 144:ef7eb2e8f9f7 2761 @endverbatim
<> 144:ef7eb2e8f9f7 2762 * @{
<> 144:ef7eb2e8f9f7 2763 */
<> 144:ef7eb2e8f9f7 2764 /**
<> 144:ef7eb2e8f9f7 2765 * @brief This function handles TIM interrupts requests.
Anna Bridge 180:96ed750bd169 2766 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 2767 * @retval None
<> 144:ef7eb2e8f9f7 2768 */
<> 144:ef7eb2e8f9f7 2769 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2770 {
<> 144:ef7eb2e8f9f7 2771 /* Capture compare 1 event */
<> 144:ef7eb2e8f9f7 2772 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<> 144:ef7eb2e8f9f7 2773 {
<> 144:ef7eb2e8f9f7 2774 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<> 144:ef7eb2e8f9f7 2775 {
<> 144:ef7eb2e8f9f7 2776 {
<> 144:ef7eb2e8f9f7 2777 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2778 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 2779
<> 144:ef7eb2e8f9f7 2780 /* Input capture event */
<> 156:95d6b41a828b 2781 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
<> 144:ef7eb2e8f9f7 2782 {
<> 144:ef7eb2e8f9f7 2783 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2784 }
<> 144:ef7eb2e8f9f7 2785 /* Output compare event */
<> 144:ef7eb2e8f9f7 2786 else
<> 144:ef7eb2e8f9f7 2787 {
<> 144:ef7eb2e8f9f7 2788 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2789 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2790 }
<> 144:ef7eb2e8f9f7 2791 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2792 }
<> 144:ef7eb2e8f9f7 2793 }
<> 144:ef7eb2e8f9f7 2794 }
<> 144:ef7eb2e8f9f7 2795 /* Capture compare 2 event */
<> 144:ef7eb2e8f9f7 2796 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<> 144:ef7eb2e8f9f7 2797 {
<> 144:ef7eb2e8f9f7 2798 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<> 144:ef7eb2e8f9f7 2799 {
<> 144:ef7eb2e8f9f7 2800 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2801 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 2802 /* Input capture event */
<> 156:95d6b41a828b 2803 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
<> 144:ef7eb2e8f9f7 2804 {
<> 144:ef7eb2e8f9f7 2805 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2806 }
<> 144:ef7eb2e8f9f7 2807 /* Output compare event */
<> 144:ef7eb2e8f9f7 2808 else
<> 144:ef7eb2e8f9f7 2809 {
<> 144:ef7eb2e8f9f7 2810 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2811 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2812 }
<> 144:ef7eb2e8f9f7 2813 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2814 }
<> 144:ef7eb2e8f9f7 2815 }
<> 144:ef7eb2e8f9f7 2816 /* Capture compare 3 event */
<> 144:ef7eb2e8f9f7 2817 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<> 144:ef7eb2e8f9f7 2818 {
<> 144:ef7eb2e8f9f7 2819 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<> 144:ef7eb2e8f9f7 2820 {
<> 144:ef7eb2e8f9f7 2821 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 2822 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 2823 /* Input capture event */
<> 156:95d6b41a828b 2824 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
<> 144:ef7eb2e8f9f7 2825 {
<> 144:ef7eb2e8f9f7 2826 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2827 }
<> 144:ef7eb2e8f9f7 2828 /* Output compare event */
<> 144:ef7eb2e8f9f7 2829 else
<> 144:ef7eb2e8f9f7 2830 {
<> 144:ef7eb2e8f9f7 2831 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2832 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2833 }
<> 144:ef7eb2e8f9f7 2834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2835 }
<> 144:ef7eb2e8f9f7 2836 }
<> 144:ef7eb2e8f9f7 2837 /* Capture compare 4 event */
<> 144:ef7eb2e8f9f7 2838 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<> 144:ef7eb2e8f9f7 2839 {
<> 144:ef7eb2e8f9f7 2840 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<> 144:ef7eb2e8f9f7 2841 {
<> 144:ef7eb2e8f9f7 2842 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 2843 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 2844 /* Input capture event */
<> 156:95d6b41a828b 2845 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
<> 144:ef7eb2e8f9f7 2846 {
<> 144:ef7eb2e8f9f7 2847 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2848 }
<> 144:ef7eb2e8f9f7 2849 /* Output compare event */
<> 144:ef7eb2e8f9f7 2850 else
<> 144:ef7eb2e8f9f7 2851 {
<> 144:ef7eb2e8f9f7 2852 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2853 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2854 }
<> 144:ef7eb2e8f9f7 2855 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2856 }
<> 144:ef7eb2e8f9f7 2857 }
<> 144:ef7eb2e8f9f7 2858 /* TIM Update event */
<> 144:ef7eb2e8f9f7 2859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<> 144:ef7eb2e8f9f7 2860 {
<> 144:ef7eb2e8f9f7 2861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<> 144:ef7eb2e8f9f7 2862 {
<> 144:ef7eb2e8f9f7 2863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 2864 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2865 }
<> 144:ef7eb2e8f9f7 2866 }
<> 144:ef7eb2e8f9f7 2867 /* TIM Break input event */
<> 144:ef7eb2e8f9f7 2868 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<> 144:ef7eb2e8f9f7 2869 {
<> 144:ef7eb2e8f9f7 2870 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<> 144:ef7eb2e8f9f7 2871 {
<> 144:ef7eb2e8f9f7 2872 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 2873 HAL_TIMEx_BreakCallback(htim);
<> 144:ef7eb2e8f9f7 2874 }
<> 144:ef7eb2e8f9f7 2875 }
<> 144:ef7eb2e8f9f7 2876 /* TIM Trigger detection event */
<> 144:ef7eb2e8f9f7 2877 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<> 144:ef7eb2e8f9f7 2878 {
<> 144:ef7eb2e8f9f7 2879 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<> 144:ef7eb2e8f9f7 2880 {
<> 144:ef7eb2e8f9f7 2881 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 2882 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 2883 }
<> 144:ef7eb2e8f9f7 2884 }
<> 144:ef7eb2e8f9f7 2885 /* TIM commutation event */
<> 144:ef7eb2e8f9f7 2886 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<> 144:ef7eb2e8f9f7 2887 {
<> 144:ef7eb2e8f9f7 2888 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<> 144:ef7eb2e8f9f7 2889 {
<> 144:ef7eb2e8f9f7 2890 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<> 144:ef7eb2e8f9f7 2891 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 2892 }
<> 144:ef7eb2e8f9f7 2893 }
<> 144:ef7eb2e8f9f7 2894 }
<> 144:ef7eb2e8f9f7 2895
<> 144:ef7eb2e8f9f7 2896 /**
<> 144:ef7eb2e8f9f7 2897 * @}
<> 144:ef7eb2e8f9f7 2898 */
<> 144:ef7eb2e8f9f7 2899
<> 144:ef7eb2e8f9f7 2900 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<> 144:ef7eb2e8f9f7 2901 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 2902 *
<> 144:ef7eb2e8f9f7 2903 @verbatim
<> 144:ef7eb2e8f9f7 2904 ==============================================================================
<> 144:ef7eb2e8f9f7 2905 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 2906 ==============================================================================
<> 144:ef7eb2e8f9f7 2907 [..]
<> 144:ef7eb2e8f9f7 2908 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2909 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 2910 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 2911 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 2912 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 2913 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 2914
<> 144:ef7eb2e8f9f7 2915 @endverbatim
<> 144:ef7eb2e8f9f7 2916 * @{
<> 144:ef7eb2e8f9f7 2917 */
<> 144:ef7eb2e8f9f7 2918
<> 144:ef7eb2e8f9f7 2919 /**
<> 144:ef7eb2e8f9f7 2920 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 2921 * parameters in the TIM_OC_InitTypeDef.
Anna Bridge 180:96ed750bd169 2922 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 2923 * @param sConfig TIM Output Compare configuration structure
Anna Bridge 180:96ed750bd169 2924 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2925 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2926 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2927 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2928 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2929 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2930 * @retval HAL status
<> 144:ef7eb2e8f9f7 2931 */
<> 144:ef7eb2e8f9f7 2932 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2933 {
<> 144:ef7eb2e8f9f7 2934 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2935 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2936 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2937 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2938
<> 144:ef7eb2e8f9f7 2939 /* Check input state */
<> 144:ef7eb2e8f9f7 2940 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2941
<> 144:ef7eb2e8f9f7 2942 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2943
<> 144:ef7eb2e8f9f7 2944 switch (Channel)
<> 144:ef7eb2e8f9f7 2945 {
<> 144:ef7eb2e8f9f7 2946 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2947 {
<> 144:ef7eb2e8f9f7 2948 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2949 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 2950 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2951 }
<> 144:ef7eb2e8f9f7 2952 break;
<> 144:ef7eb2e8f9f7 2953
<> 144:ef7eb2e8f9f7 2954 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2955 {
<> 144:ef7eb2e8f9f7 2956 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2957 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 2958 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2959 }
<> 144:ef7eb2e8f9f7 2960 break;
<> 144:ef7eb2e8f9f7 2961
<> 144:ef7eb2e8f9f7 2962 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 2963 {
<> 144:ef7eb2e8f9f7 2964 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2965 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 2966 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2967 }
<> 144:ef7eb2e8f9f7 2968 break;
<> 144:ef7eb2e8f9f7 2969
<> 144:ef7eb2e8f9f7 2970 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 2971 {
<> 144:ef7eb2e8f9f7 2972 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2973 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 2974 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2975 }
<> 144:ef7eb2e8f9f7 2976 break;
<> 144:ef7eb2e8f9f7 2977
<> 144:ef7eb2e8f9f7 2978 default:
<> 144:ef7eb2e8f9f7 2979 break;
<> 144:ef7eb2e8f9f7 2980 }
<> 144:ef7eb2e8f9f7 2981 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2982
<> 144:ef7eb2e8f9f7 2983 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2984
<> 144:ef7eb2e8f9f7 2985 return HAL_OK;
<> 144:ef7eb2e8f9f7 2986 }
<> 144:ef7eb2e8f9f7 2987
<> 144:ef7eb2e8f9f7 2988 /**
<> 144:ef7eb2e8f9f7 2989 * @brief Initializes the TIM Input Capture Channels according to the specified
<> 144:ef7eb2e8f9f7 2990 * parameters in the TIM_IC_InitTypeDef.
Anna Bridge 180:96ed750bd169 2991 * @param htim TIM IC handle
Anna Bridge 180:96ed750bd169 2992 * @param sConfig TIM Input Capture configuration structure
Anna Bridge 180:96ed750bd169 2993 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2994 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2995 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2996 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2997 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2998 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2999 * @retval HAL status
<> 144:ef7eb2e8f9f7 3000 */
<> 144:ef7eb2e8f9f7 3001 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3002 {
<> 144:ef7eb2e8f9f7 3003 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3004 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3005 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<> 144:ef7eb2e8f9f7 3006 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<> 144:ef7eb2e8f9f7 3007 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<> 144:ef7eb2e8f9f7 3008 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<> 144:ef7eb2e8f9f7 3009
<> 144:ef7eb2e8f9f7 3010 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3011
<> 144:ef7eb2e8f9f7 3012 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3013
<> 144:ef7eb2e8f9f7 3014 if (Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 3015 {
<> 144:ef7eb2e8f9f7 3016 /* TI1 Configuration */
<> 144:ef7eb2e8f9f7 3017 TIM_TI1_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3018 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3019 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3020 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3021
<> 144:ef7eb2e8f9f7 3022 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3023 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3024
<> 144:ef7eb2e8f9f7 3025 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 3026 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3027 }
<> 144:ef7eb2e8f9f7 3028 else if (Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 3029 {
<> 144:ef7eb2e8f9f7 3030 /* TI2 Configuration */
<> 144:ef7eb2e8f9f7 3031 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3032
<> 144:ef7eb2e8f9f7 3033 TIM_TI2_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3034 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3035 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3036 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3037
<> 144:ef7eb2e8f9f7 3038 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3039 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3040
<> 144:ef7eb2e8f9f7 3041 /* Set the IC2PSC value */
<> 156:95d6b41a828b 3042 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 3043 }
<> 144:ef7eb2e8f9f7 3044 else if (Channel == TIM_CHANNEL_3)
<> 144:ef7eb2e8f9f7 3045 {
<> 144:ef7eb2e8f9f7 3046 /* TI3 Configuration */
<> 144:ef7eb2e8f9f7 3047 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3048
<> 144:ef7eb2e8f9f7 3049 TIM_TI3_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3050 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3051 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3052 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3053
<> 144:ef7eb2e8f9f7 3054 /* Reset the IC3PSC Bits */
<> 144:ef7eb2e8f9f7 3055 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<> 144:ef7eb2e8f9f7 3056
<> 144:ef7eb2e8f9f7 3057 /* Set the IC3PSC value */
<> 144:ef7eb2e8f9f7 3058 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3059 }
<> 144:ef7eb2e8f9f7 3060 else
<> 144:ef7eb2e8f9f7 3061 {
<> 144:ef7eb2e8f9f7 3062 /* TI4 Configuration */
<> 144:ef7eb2e8f9f7 3063 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3064
<> 144:ef7eb2e8f9f7 3065 TIM_TI4_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3066 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3067 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3068 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3069
<> 144:ef7eb2e8f9f7 3070 /* Reset the IC4PSC Bits */
<> 144:ef7eb2e8f9f7 3071 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<> 144:ef7eb2e8f9f7 3072
<> 144:ef7eb2e8f9f7 3073 /* Set the IC4PSC value */
<> 156:95d6b41a828b 3074 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 3075 }
<> 144:ef7eb2e8f9f7 3076
<> 144:ef7eb2e8f9f7 3077 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3078
<> 144:ef7eb2e8f9f7 3079 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3080
<> 144:ef7eb2e8f9f7 3081 return HAL_OK;
<> 144:ef7eb2e8f9f7 3082 }
<> 144:ef7eb2e8f9f7 3083
<> 144:ef7eb2e8f9f7 3084 /**
<> 144:ef7eb2e8f9f7 3085 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 3086 * parameters in the TIM_OC_InitTypeDef.
Anna Bridge 180:96ed750bd169 3087 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3088 * @param sConfig TIM PWM configuration structure
Anna Bridge 180:96ed750bd169 3089 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3090 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3091 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3092 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3093 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3094 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3095 * @retval HAL status
<> 144:ef7eb2e8f9f7 3096 */
<> 144:ef7eb2e8f9f7 3097 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3098 {
<> 144:ef7eb2e8f9f7 3099 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3100
<> 144:ef7eb2e8f9f7 3101 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3102 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3103 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 3104 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 3105 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 3106
<> 144:ef7eb2e8f9f7 3107 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3108
<> 144:ef7eb2e8f9f7 3109 switch (Channel)
<> 144:ef7eb2e8f9f7 3110 {
<> 144:ef7eb2e8f9f7 3111 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3112 {
<> 144:ef7eb2e8f9f7 3113 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3114 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 3115 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3116
<> 144:ef7eb2e8f9f7 3117 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 3118 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 3119
<> 144:ef7eb2e8f9f7 3120 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3121 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 3122 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3123 }
<> 144:ef7eb2e8f9f7 3124 break;
<> 144:ef7eb2e8f9f7 3125
<> 144:ef7eb2e8f9f7 3126 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3127 {
<> 144:ef7eb2e8f9f7 3128 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3129 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 3130 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3131
<> 144:ef7eb2e8f9f7 3132 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 3133 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 3134
<> 144:ef7eb2e8f9f7 3135 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3136 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 156:95d6b41a828b 3137 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3138 }
<> 144:ef7eb2e8f9f7 3139 break;
<> 144:ef7eb2e8f9f7 3140
<> 144:ef7eb2e8f9f7 3141 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3142 {
<> 144:ef7eb2e8f9f7 3143 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3144 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 3145 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3146
<> 144:ef7eb2e8f9f7 3147 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 3148 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 3149
<> 144:ef7eb2e8f9f7 3150 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3151 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 3152 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3153 }
<> 144:ef7eb2e8f9f7 3154 break;
<> 144:ef7eb2e8f9f7 3155
<> 144:ef7eb2e8f9f7 3156 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3157 {
<> 144:ef7eb2e8f9f7 3158 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3159 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 3160 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3161
<> 144:ef7eb2e8f9f7 3162 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 3163 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 3164
<> 144:ef7eb2e8f9f7 3165 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3166 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 156:95d6b41a828b 3167 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3168 }
<> 144:ef7eb2e8f9f7 3169 break;
<> 144:ef7eb2e8f9f7 3170
<> 144:ef7eb2e8f9f7 3171 default:
<> 144:ef7eb2e8f9f7 3172 break;
<> 144:ef7eb2e8f9f7 3173 }
<> 144:ef7eb2e8f9f7 3174
<> 144:ef7eb2e8f9f7 3175 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3176
<> 144:ef7eb2e8f9f7 3177 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3178
<> 144:ef7eb2e8f9f7 3179 return HAL_OK;
<> 144:ef7eb2e8f9f7 3180 }
<> 144:ef7eb2e8f9f7 3181
<> 144:ef7eb2e8f9f7 3182 /**
<> 144:ef7eb2e8f9f7 3183 * @brief Initializes the TIM One Pulse Channels according to the specified
<> 144:ef7eb2e8f9f7 3184 * parameters in the TIM_OnePulse_InitTypeDef.
Anna Bridge 180:96ed750bd169 3185 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 3186 * @param sConfig TIM One Pulse configuration structure
Anna Bridge 180:96ed750bd169 3187 * @param OutputChannel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3188 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3189 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3190 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
Anna Bridge 180:96ed750bd169 3191 * @param InputChannel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3192 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3193 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3194 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3195 * @retval HAL status
<> 144:ef7eb2e8f9f7 3196 */
<> 144:ef7eb2e8f9f7 3197 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<> 144:ef7eb2e8f9f7 3198 {
<> 144:ef7eb2e8f9f7 3199 TIM_OC_InitTypeDef temp1;
<> 144:ef7eb2e8f9f7 3200
<> 144:ef7eb2e8f9f7 3201 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3202 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<> 144:ef7eb2e8f9f7 3203 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<> 144:ef7eb2e8f9f7 3204
<> 144:ef7eb2e8f9f7 3205 if(OutputChannel != InputChannel)
<> 144:ef7eb2e8f9f7 3206 {
<> 144:ef7eb2e8f9f7 3207 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3208
<> 144:ef7eb2e8f9f7 3209 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3210
<> 144:ef7eb2e8f9f7 3211 /* Extract the Ouput compare configuration from sConfig structure */
<> 144:ef7eb2e8f9f7 3212 temp1.OCMode = sConfig->OCMode;
<> 144:ef7eb2e8f9f7 3213 temp1.Pulse = sConfig->Pulse;
<> 144:ef7eb2e8f9f7 3214 temp1.OCPolarity = sConfig->OCPolarity;
<> 144:ef7eb2e8f9f7 3215 temp1.OCNPolarity = sConfig->OCNPolarity;
<> 144:ef7eb2e8f9f7 3216 temp1.OCIdleState = sConfig->OCIdleState;
<> 144:ef7eb2e8f9f7 3217 temp1.OCNIdleState = sConfig->OCNIdleState;
<> 144:ef7eb2e8f9f7 3218
<> 144:ef7eb2e8f9f7 3219 switch (OutputChannel)
<> 144:ef7eb2e8f9f7 3220 {
<> 144:ef7eb2e8f9f7 3221 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3222 {
<> 144:ef7eb2e8f9f7 3223 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3224
<> 144:ef7eb2e8f9f7 3225 TIM_OC1_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3226 }
<> 144:ef7eb2e8f9f7 3227 break;
<> 144:ef7eb2e8f9f7 3228 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3229 {
<> 144:ef7eb2e8f9f7 3230 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3231
<> 144:ef7eb2e8f9f7 3232 TIM_OC2_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3233 }
<> 144:ef7eb2e8f9f7 3234 break;
<> 144:ef7eb2e8f9f7 3235 default:
<> 144:ef7eb2e8f9f7 3236 break;
<> 144:ef7eb2e8f9f7 3237 }
<> 144:ef7eb2e8f9f7 3238 switch (InputChannel)
<> 144:ef7eb2e8f9f7 3239 {
<> 144:ef7eb2e8f9f7 3240 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3241 {
<> 144:ef7eb2e8f9f7 3242 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3243
<> 144:ef7eb2e8f9f7 3244 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3245 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3246
<> 144:ef7eb2e8f9f7 3247 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3248 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3249
<> 144:ef7eb2e8f9f7 3250 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3251 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3252 htim->Instance->SMCR |= TIM_TS_TI1FP1;
<> 144:ef7eb2e8f9f7 3253
<> 144:ef7eb2e8f9f7 3254 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3255 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3256 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3257 }
<> 144:ef7eb2e8f9f7 3258 break;
<> 144:ef7eb2e8f9f7 3259 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3260 {
<> 144:ef7eb2e8f9f7 3261 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3262
<> 144:ef7eb2e8f9f7 3263 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3264 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3265
<> 144:ef7eb2e8f9f7 3266 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3267 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3268
<> 144:ef7eb2e8f9f7 3269 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3270 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3271 htim->Instance->SMCR |= TIM_TS_TI2FP2;
<> 144:ef7eb2e8f9f7 3272
<> 144:ef7eb2e8f9f7 3273 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3274 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3275 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3276 }
<> 144:ef7eb2e8f9f7 3277 break;
<> 144:ef7eb2e8f9f7 3278
<> 144:ef7eb2e8f9f7 3279 default:
<> 144:ef7eb2e8f9f7 3280 break;
<> 144:ef7eb2e8f9f7 3281 }
<> 144:ef7eb2e8f9f7 3282
<> 144:ef7eb2e8f9f7 3283 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3284
<> 144:ef7eb2e8f9f7 3285 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3286
<> 144:ef7eb2e8f9f7 3287 return HAL_OK;
<> 144:ef7eb2e8f9f7 3288 }
<> 144:ef7eb2e8f9f7 3289 else
<> 144:ef7eb2e8f9f7 3290 {
<> 144:ef7eb2e8f9f7 3291 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3292 }
<> 144:ef7eb2e8f9f7 3293 }
<> 144:ef7eb2e8f9f7 3294
<> 144:ef7eb2e8f9f7 3295 /**
<> 144:ef7eb2e8f9f7 3296 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
Anna Bridge 180:96ed750bd169 3297 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3298 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
<> 144:ef7eb2e8f9f7 3299 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3300 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3301 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3302 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3303 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3304 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3305 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3306 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3307 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3308 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3309 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3310 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3311 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3312 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3313 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3314 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3315 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3316 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3317 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3318 * @arg TIM_DMABASE_DCR
Anna Bridge 180:96ed750bd169 3319 * @param BurstRequestSrc TIM DMA Request sources
<> 144:ef7eb2e8f9f7 3320 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3321 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3322 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3323 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3324 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3325 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3326 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3327 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
Anna Bridge 180:96ed750bd169 3328 * @param BurstBuffer The Buffer address.
Anna Bridge 180:96ed750bd169 3329 * @param BurstLength DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3330 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3331 * @retval HAL status
<> 144:ef7eb2e8f9f7 3332 */
<> 144:ef7eb2e8f9f7 3333 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
Anna Bridge 180:96ed750bd169 3334 uint32_t *BurstBuffer, uint32_t BurstLength)
Anna Bridge 180:96ed750bd169 3335 {
Anna Bridge 180:96ed750bd169 3336 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
Anna Bridge 180:96ed750bd169 3337 }
Anna Bridge 180:96ed750bd169 3338
Anna Bridge 180:96ed750bd169 3339 /**
Anna Bridge 180:96ed750bd169 3340 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
Anna Bridge 180:96ed750bd169 3341 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3342 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
Anna Bridge 180:96ed750bd169 3343 * This parameter can be one of the following values:
Anna Bridge 180:96ed750bd169 3344 * @arg TIM_DMABASE_CR1
Anna Bridge 180:96ed750bd169 3345 * @arg TIM_DMABASE_CR2
Anna Bridge 180:96ed750bd169 3346 * @arg TIM_DMABASE_SMCR
Anna Bridge 180:96ed750bd169 3347 * @arg TIM_DMABASE_DIER
Anna Bridge 180:96ed750bd169 3348 * @arg TIM_DMABASE_SR
Anna Bridge 180:96ed750bd169 3349 * @arg TIM_DMABASE_EGR
Anna Bridge 180:96ed750bd169 3350 * @arg TIM_DMABASE_CCMR1
Anna Bridge 180:96ed750bd169 3351 * @arg TIM_DMABASE_CCMR2
Anna Bridge 180:96ed750bd169 3352 * @arg TIM_DMABASE_CCER
Anna Bridge 180:96ed750bd169 3353 * @arg TIM_DMABASE_CNT
Anna Bridge 180:96ed750bd169 3354 * @arg TIM_DMABASE_PSC
Anna Bridge 180:96ed750bd169 3355 * @arg TIM_DMABASE_ARR
Anna Bridge 180:96ed750bd169 3356 * @arg TIM_DMABASE_RCR
Anna Bridge 180:96ed750bd169 3357 * @arg TIM_DMABASE_CCR1
Anna Bridge 180:96ed750bd169 3358 * @arg TIM_DMABASE_CCR2
Anna Bridge 180:96ed750bd169 3359 * @arg TIM_DMABASE_CCR3
Anna Bridge 180:96ed750bd169 3360 * @arg TIM_DMABASE_CCR4
Anna Bridge 180:96ed750bd169 3361 * @arg TIM_DMABASE_BDTR
Anna Bridge 180:96ed750bd169 3362 * @arg TIM_DMABASE_DCR
Anna Bridge 180:96ed750bd169 3363 * @param BurstRequestSrc TIM DMA Request sources
Anna Bridge 180:96ed750bd169 3364 * This parameter can be one of the following values:
Anna Bridge 180:96ed750bd169 3365 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
Anna Bridge 180:96ed750bd169 3366 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
Anna Bridge 180:96ed750bd169 3367 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
Anna Bridge 180:96ed750bd169 3368 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
Anna Bridge 180:96ed750bd169 3369 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
Anna Bridge 180:96ed750bd169 3370 * @arg TIM_DMA_COM: TIM Commutation DMA source
Anna Bridge 180:96ed750bd169 3371 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
Anna Bridge 180:96ed750bd169 3372 * @param BurstBuffer The Buffer address.
Anna Bridge 180:96ed750bd169 3373 * @param BurstLength DMA Burst length. This parameter can be one value
Anna Bridge 180:96ed750bd169 3374 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Anna Bridge 180:96ed750bd169 3375 * @param DataLength Data length. This parameter can be one value
Anna Bridge 180:96ed750bd169 3376 * between 1 and 0xFFFF.
Anna Bridge 180:96ed750bd169 3377 * @retval HAL status
Anna Bridge 180:96ed750bd169 3378 */
Anna Bridge 180:96ed750bd169 3379 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
Anna Bridge 180:96ed750bd169 3380 uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 3381 {
<> 144:ef7eb2e8f9f7 3382 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3383 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3384 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3385 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3386 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
Anna Bridge 180:96ed750bd169 3387 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
<> 144:ef7eb2e8f9f7 3388
<> 144:ef7eb2e8f9f7 3389 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3390 {
<> 144:ef7eb2e8f9f7 3391 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3392 }
<> 144:ef7eb2e8f9f7 3393 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3394 {
<> 156:95d6b41a828b 3395 if((BurstBuffer == 0U ) && (BurstLength > 0U))
<> 144:ef7eb2e8f9f7 3396 {
<> 144:ef7eb2e8f9f7 3397 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3398 }
<> 144:ef7eb2e8f9f7 3399 else
<> 144:ef7eb2e8f9f7 3400 {
<> 144:ef7eb2e8f9f7 3401 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3402 }
<> 144:ef7eb2e8f9f7 3403 }
<> 144:ef7eb2e8f9f7 3404 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3405 {
<> 144:ef7eb2e8f9f7 3406 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3407 {
<> 144:ef7eb2e8f9f7 3408 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3409 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3410
<> 144:ef7eb2e8f9f7 3411 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3412 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3413
<> 144:ef7eb2e8f9f7 3414 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3415 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
<> 144:ef7eb2e8f9f7 3416 }
<> 144:ef7eb2e8f9f7 3417 break;
<> 144:ef7eb2e8f9f7 3418 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3419 {
<> 144:ef7eb2e8f9f7 3420 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3421 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3422
<> 144:ef7eb2e8f9f7 3423 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3424 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3425
<> 144:ef7eb2e8f9f7 3426 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3427 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
<> 144:ef7eb2e8f9f7 3428 }
<> 144:ef7eb2e8f9f7 3429 break;
<> 144:ef7eb2e8f9f7 3430 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3431 {
<> 144:ef7eb2e8f9f7 3432 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3433 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3434
<> 144:ef7eb2e8f9f7 3435 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3436 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3437
<> 144:ef7eb2e8f9f7 3438 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3439 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
<> 144:ef7eb2e8f9f7 3440 }
<> 144:ef7eb2e8f9f7 3441 break;
<> 144:ef7eb2e8f9f7 3442 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3443 {
<> 144:ef7eb2e8f9f7 3444 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3445 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3446
<> 144:ef7eb2e8f9f7 3447 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3448 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3449
<> 144:ef7eb2e8f9f7 3450 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3451 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
<> 144:ef7eb2e8f9f7 3452 }
<> 144:ef7eb2e8f9f7 3453 break;
<> 144:ef7eb2e8f9f7 3454 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3455 {
<> 144:ef7eb2e8f9f7 3456 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3457 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3458
<> 144:ef7eb2e8f9f7 3459 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3460 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3461
<> 144:ef7eb2e8f9f7 3462 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3463 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
<> 144:ef7eb2e8f9f7 3464 }
<> 144:ef7eb2e8f9f7 3465 break;
<> 144:ef7eb2e8f9f7 3466 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3467 {
<> 144:ef7eb2e8f9f7 3468 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3469 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3470
<> 144:ef7eb2e8f9f7 3471 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3472 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3473
<> 144:ef7eb2e8f9f7 3474 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3475 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
<> 144:ef7eb2e8f9f7 3476 }
<> 144:ef7eb2e8f9f7 3477 break;
<> 144:ef7eb2e8f9f7 3478 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3479 {
<> 144:ef7eb2e8f9f7 3480 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3481 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3482
<> 144:ef7eb2e8f9f7 3483 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3484 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3485
<> 144:ef7eb2e8f9f7 3486 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3487 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
<> 144:ef7eb2e8f9f7 3488 }
<> 144:ef7eb2e8f9f7 3489 break;
<> 144:ef7eb2e8f9f7 3490 default:
<> 144:ef7eb2e8f9f7 3491 break;
<> 144:ef7eb2e8f9f7 3492 }
<> 144:ef7eb2e8f9f7 3493 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3494 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3495
<> 144:ef7eb2e8f9f7 3496 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3497 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3498
<> 144:ef7eb2e8f9f7 3499 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3500
<> 144:ef7eb2e8f9f7 3501 /* Return function status */
<> 144:ef7eb2e8f9f7 3502 return HAL_OK;
<> 144:ef7eb2e8f9f7 3503 }
<> 144:ef7eb2e8f9f7 3504
<> 144:ef7eb2e8f9f7 3505 /**
<> 144:ef7eb2e8f9f7 3506 * @brief Stops the TIM DMA Burst mode
Anna Bridge 180:96ed750bd169 3507 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3508 * @param BurstRequestSrc TIM DMA Request sources to disable
<> 144:ef7eb2e8f9f7 3509 * @retval HAL status
<> 144:ef7eb2e8f9f7 3510 */
<> 144:ef7eb2e8f9f7 3511 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3512 {
<> 144:ef7eb2e8f9f7 3513 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3514 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3515
<> 144:ef7eb2e8f9f7 3516 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3517 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3518 {
<> 144:ef7eb2e8f9f7 3519 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3520 {
<> 144:ef7eb2e8f9f7 3521 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3522 }
<> 144:ef7eb2e8f9f7 3523 break;
<> 144:ef7eb2e8f9f7 3524 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3525 {
<> 144:ef7eb2e8f9f7 3526 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3527 }
<> 144:ef7eb2e8f9f7 3528 break;
<> 144:ef7eb2e8f9f7 3529 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3530 {
<> 144:ef7eb2e8f9f7 3531 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3532 }
<> 144:ef7eb2e8f9f7 3533 break;
<> 144:ef7eb2e8f9f7 3534 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3535 {
<> 144:ef7eb2e8f9f7 3536 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3537 }
<> 144:ef7eb2e8f9f7 3538 break;
<> 144:ef7eb2e8f9f7 3539 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3540 {
<> 144:ef7eb2e8f9f7 3541 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3542 }
<> 144:ef7eb2e8f9f7 3543 break;
<> 144:ef7eb2e8f9f7 3544 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3545 {
<> 144:ef7eb2e8f9f7 3546 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3547 }
<> 144:ef7eb2e8f9f7 3548 break;
<> 144:ef7eb2e8f9f7 3549 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3550 {
<> 144:ef7eb2e8f9f7 3551 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3552 }
<> 144:ef7eb2e8f9f7 3553 break;
<> 144:ef7eb2e8f9f7 3554 default:
<> 144:ef7eb2e8f9f7 3555 break;
<> 144:ef7eb2e8f9f7 3556 }
<> 144:ef7eb2e8f9f7 3557
<> 144:ef7eb2e8f9f7 3558 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3559 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3560
<> 144:ef7eb2e8f9f7 3561 /* Return function status */
<> 144:ef7eb2e8f9f7 3562 return HAL_OK;
<> 144:ef7eb2e8f9f7 3563 }
<> 144:ef7eb2e8f9f7 3564
<> 144:ef7eb2e8f9f7 3565 /**
<> 144:ef7eb2e8f9f7 3566 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
Anna Bridge 180:96ed750bd169 3567 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3568 * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
<> 144:ef7eb2e8f9f7 3569 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3570 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3571 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3572 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3573 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3574 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3575 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3576 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3577 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3578 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3579 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3580 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3581 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3582 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3583 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3584 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3585 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3586 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3587 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3588 * @arg TIM_DMABASE_DCR
Anna Bridge 180:96ed750bd169 3589 * @param BurstRequestSrc TIM DMA Request sources
<> 144:ef7eb2e8f9f7 3590 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3591 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3592 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3593 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3594 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3595 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3596 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3597 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
Anna Bridge 180:96ed750bd169 3598 * @param BurstBuffer The Buffer address.
Anna Bridge 180:96ed750bd169 3599 * @param BurstLength DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3600 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3601 * @retval HAL status
<> 144:ef7eb2e8f9f7 3602 */
<> 144:ef7eb2e8f9f7 3603 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3604 uint32_t *BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3605 {
Anna Bridge 180:96ed750bd169 3606 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
Anna Bridge 180:96ed750bd169 3607 }
Anna Bridge 180:96ed750bd169 3608
Anna Bridge 180:96ed750bd169 3609 /**
Anna Bridge 180:96ed750bd169 3610 * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
Anna Bridge 180:96ed750bd169 3611 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3612 * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
Anna Bridge 180:96ed750bd169 3613 * This parameter can be one of the following values:
Anna Bridge 180:96ed750bd169 3614 * @arg TIM_DMABASE_CR1
Anna Bridge 180:96ed750bd169 3615 * @arg TIM_DMABASE_CR2
Anna Bridge 180:96ed750bd169 3616 * @arg TIM_DMABASE_SMCR
Anna Bridge 180:96ed750bd169 3617 * @arg TIM_DMABASE_DIER
Anna Bridge 180:96ed750bd169 3618 * @arg TIM_DMABASE_SR
Anna Bridge 180:96ed750bd169 3619 * @arg TIM_DMABASE_EGR
Anna Bridge 180:96ed750bd169 3620 * @arg TIM_DMABASE_CCMR1
Anna Bridge 180:96ed750bd169 3621 * @arg TIM_DMABASE_CCMR2
Anna Bridge 180:96ed750bd169 3622 * @arg TIM_DMABASE_CCER
Anna Bridge 180:96ed750bd169 3623 * @arg TIM_DMABASE_CNT
Anna Bridge 180:96ed750bd169 3624 * @arg TIM_DMABASE_PSC
Anna Bridge 180:96ed750bd169 3625 * @arg TIM_DMABASE_ARR
Anna Bridge 180:96ed750bd169 3626 * @arg TIM_DMABASE_RCR
Anna Bridge 180:96ed750bd169 3627 * @arg TIM_DMABASE_CCR1
Anna Bridge 180:96ed750bd169 3628 * @arg TIM_DMABASE_CCR2
Anna Bridge 180:96ed750bd169 3629 * @arg TIM_DMABASE_CCR3
Anna Bridge 180:96ed750bd169 3630 * @arg TIM_DMABASE_CCR4
Anna Bridge 180:96ed750bd169 3631 * @arg TIM_DMABASE_BDTR
Anna Bridge 180:96ed750bd169 3632 * @arg TIM_DMABASE_DCR
Anna Bridge 180:96ed750bd169 3633 * @param BurstRequestSrc TIM DMA Request sources
Anna Bridge 180:96ed750bd169 3634 * This parameter can be one of the following values:
Anna Bridge 180:96ed750bd169 3635 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
Anna Bridge 180:96ed750bd169 3636 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
Anna Bridge 180:96ed750bd169 3637 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
Anna Bridge 180:96ed750bd169 3638 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
Anna Bridge 180:96ed750bd169 3639 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
Anna Bridge 180:96ed750bd169 3640 * @arg TIM_DMA_COM: TIM Commutation DMA source
Anna Bridge 180:96ed750bd169 3641 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
Anna Bridge 180:96ed750bd169 3642 * @param BurstBuffer The Buffer address.
Anna Bridge 180:96ed750bd169 3643 * @param BurstLength DMA Burst length. This parameter can be one value
Anna Bridge 180:96ed750bd169 3644 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Anna Bridge 180:96ed750bd169 3645 * @param DataLength Data length. This parameter can be one value
Anna Bridge 180:96ed750bd169 3646 * between 1 and 0xFFFF.
Anna Bridge 180:96ed750bd169 3647 * @retval HAL status
Anna Bridge 180:96ed750bd169 3648 */
Anna Bridge 180:96ed750bd169 3649 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
Anna Bridge 180:96ed750bd169 3650 uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Anna Bridge 180:96ed750bd169 3651 {
<> 144:ef7eb2e8f9f7 3652 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3653 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3654 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3655 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3656 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
Anna Bridge 180:96ed750bd169 3657 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
<> 144:ef7eb2e8f9f7 3658
<> 144:ef7eb2e8f9f7 3659 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3660 {
<> 144:ef7eb2e8f9f7 3661 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3662 }
<> 144:ef7eb2e8f9f7 3663 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3664 {
<> 156:95d6b41a828b 3665 if((BurstBuffer == 0U ) && (BurstLength > 0U))
<> 144:ef7eb2e8f9f7 3666 {
<> 144:ef7eb2e8f9f7 3667 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3668 }
<> 144:ef7eb2e8f9f7 3669 else
<> 144:ef7eb2e8f9f7 3670 {
<> 144:ef7eb2e8f9f7 3671 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3672 }
<> 144:ef7eb2e8f9f7 3673 }
<> 144:ef7eb2e8f9f7 3674 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3675 {
<> 144:ef7eb2e8f9f7 3676 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3677 {
<> 144:ef7eb2e8f9f7 3678 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3679 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3680
<> 144:ef7eb2e8f9f7 3681 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3682 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3683
<> 144:ef7eb2e8f9f7 3684 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3685 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
<> 144:ef7eb2e8f9f7 3686 }
<> 144:ef7eb2e8f9f7 3687 break;
<> 144:ef7eb2e8f9f7 3688 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3689 {
<> 144:ef7eb2e8f9f7 3690 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3691 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3692
<> 144:ef7eb2e8f9f7 3693 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3694 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3695
<> 144:ef7eb2e8f9f7 3696 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3697 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
<> 144:ef7eb2e8f9f7 3698 }
<> 144:ef7eb2e8f9f7 3699 break;
<> 144:ef7eb2e8f9f7 3700 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3701 {
<> 144:ef7eb2e8f9f7 3702 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3703 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3704
<> 144:ef7eb2e8f9f7 3705 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3706 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3707
<> 144:ef7eb2e8f9f7 3708 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3709 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
<> 144:ef7eb2e8f9f7 3710 }
<> 144:ef7eb2e8f9f7 3711 break;
<> 144:ef7eb2e8f9f7 3712 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3713 {
<> 144:ef7eb2e8f9f7 3714 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3715 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3716
<> 144:ef7eb2e8f9f7 3717 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3718 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3719
<> 144:ef7eb2e8f9f7 3720 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3721 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
<> 144:ef7eb2e8f9f7 3722 }
<> 144:ef7eb2e8f9f7 3723 break;
<> 144:ef7eb2e8f9f7 3724 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3725 {
<> 144:ef7eb2e8f9f7 3726 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3727 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3728
<> 144:ef7eb2e8f9f7 3729 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3730 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3731
<> 144:ef7eb2e8f9f7 3732 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3733 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
<> 144:ef7eb2e8f9f7 3734 }
<> 144:ef7eb2e8f9f7 3735 break;
<> 144:ef7eb2e8f9f7 3736 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3737 {
<> 144:ef7eb2e8f9f7 3738 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3739 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3740
<> 144:ef7eb2e8f9f7 3741 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3742 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3743
<> 144:ef7eb2e8f9f7 3744 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3745 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
<> 144:ef7eb2e8f9f7 3746 }
<> 144:ef7eb2e8f9f7 3747 break;
<> 144:ef7eb2e8f9f7 3748 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3749 {
<> 144:ef7eb2e8f9f7 3750 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3751 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3752
<> 144:ef7eb2e8f9f7 3753 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3754 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3755
<> 144:ef7eb2e8f9f7 3756 /* Enable the DMA channel */
Anna Bridge 180:96ed750bd169 3757 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
<> 144:ef7eb2e8f9f7 3758 }
<> 144:ef7eb2e8f9f7 3759 break;
<> 144:ef7eb2e8f9f7 3760 default:
<> 144:ef7eb2e8f9f7 3761 break;
<> 144:ef7eb2e8f9f7 3762 }
<> 144:ef7eb2e8f9f7 3763
<> 144:ef7eb2e8f9f7 3764 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3765 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3766
<> 144:ef7eb2e8f9f7 3767 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3768 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3769
<> 144:ef7eb2e8f9f7 3770 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3771
<> 144:ef7eb2e8f9f7 3772 /* Return function status */
<> 144:ef7eb2e8f9f7 3773 return HAL_OK;
<> 144:ef7eb2e8f9f7 3774 }
<> 144:ef7eb2e8f9f7 3775
<> 144:ef7eb2e8f9f7 3776 /**
<> 144:ef7eb2e8f9f7 3777 * @brief Stop the DMA burst reading
Anna Bridge 180:96ed750bd169 3778 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3779 * @param BurstRequestSrc TIM DMA Request sources to disable.
<> 144:ef7eb2e8f9f7 3780 * @retval HAL status
<> 144:ef7eb2e8f9f7 3781 */
<> 144:ef7eb2e8f9f7 3782 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3783 {
<> 144:ef7eb2e8f9f7 3784 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3785 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3786
<> 144:ef7eb2e8f9f7 3787 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3788 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3789 {
<> 144:ef7eb2e8f9f7 3790 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3791 {
<> 144:ef7eb2e8f9f7 3792 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3793 }
<> 144:ef7eb2e8f9f7 3794 break;
<> 144:ef7eb2e8f9f7 3795 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3796 {
<> 144:ef7eb2e8f9f7 3797 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3798 }
<> 144:ef7eb2e8f9f7 3799 break;
<> 144:ef7eb2e8f9f7 3800 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3801 {
<> 144:ef7eb2e8f9f7 3802 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3803 }
<> 144:ef7eb2e8f9f7 3804 break;
<> 144:ef7eb2e8f9f7 3805 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3806 {
<> 144:ef7eb2e8f9f7 3807 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3808 }
<> 144:ef7eb2e8f9f7 3809 break;
<> 144:ef7eb2e8f9f7 3810 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3811 {
<> 144:ef7eb2e8f9f7 3812 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3813 }
<> 144:ef7eb2e8f9f7 3814 break;
<> 144:ef7eb2e8f9f7 3815 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3816 {
<> 144:ef7eb2e8f9f7 3817 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3818 }
<> 144:ef7eb2e8f9f7 3819 break;
<> 144:ef7eb2e8f9f7 3820 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3821 {
<> 144:ef7eb2e8f9f7 3822 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3823 }
<> 144:ef7eb2e8f9f7 3824 break;
<> 144:ef7eb2e8f9f7 3825 default:
<> 144:ef7eb2e8f9f7 3826 break;
<> 144:ef7eb2e8f9f7 3827 }
<> 144:ef7eb2e8f9f7 3828
<> 144:ef7eb2e8f9f7 3829 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3830 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3831
<> 144:ef7eb2e8f9f7 3832 /* Return function status */
<> 144:ef7eb2e8f9f7 3833 return HAL_OK;
<> 144:ef7eb2e8f9f7 3834 }
<> 144:ef7eb2e8f9f7 3835
<> 144:ef7eb2e8f9f7 3836 /**
<> 144:ef7eb2e8f9f7 3837 * @brief Generate a software event
Anna Bridge 180:96ed750bd169 3838 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3839 * @param EventSource specifies the event source.
<> 144:ef7eb2e8f9f7 3840 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3841 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<> 144:ef7eb2e8f9f7 3842 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<> 144:ef7eb2e8f9f7 3843 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<> 144:ef7eb2e8f9f7 3844 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<> 144:ef7eb2e8f9f7 3845 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<> 144:ef7eb2e8f9f7 3846 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
<> 144:ef7eb2e8f9f7 3847 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<> 144:ef7eb2e8f9f7 3848 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<> 144:ef7eb2e8f9f7 3849 * @note TIM6 and TIM7 can only generate an update event.
<> 144:ef7eb2e8f9f7 3850 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
<> 144:ef7eb2e8f9f7 3851 * @retval HAL status
<> 144:ef7eb2e8f9f7 3852 */
<> 144:ef7eb2e8f9f7 3853
<> 144:ef7eb2e8f9f7 3854 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<> 144:ef7eb2e8f9f7 3855 {
<> 144:ef7eb2e8f9f7 3856 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3857 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3858 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<> 144:ef7eb2e8f9f7 3859
<> 144:ef7eb2e8f9f7 3860 /* Process Locked */
<> 144:ef7eb2e8f9f7 3861 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3862
<> 144:ef7eb2e8f9f7 3863 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3864 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3865
<> 144:ef7eb2e8f9f7 3866 /* Set the event sources */
<> 144:ef7eb2e8f9f7 3867 htim->Instance->EGR = EventSource;
<> 144:ef7eb2e8f9f7 3868
<> 144:ef7eb2e8f9f7 3869 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3870 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3871
<> 144:ef7eb2e8f9f7 3872 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3873
<> 144:ef7eb2e8f9f7 3874 /* Return function status */
<> 144:ef7eb2e8f9f7 3875 return HAL_OK;
<> 144:ef7eb2e8f9f7 3876 }
<> 144:ef7eb2e8f9f7 3877
<> 144:ef7eb2e8f9f7 3878 /**
<> 144:ef7eb2e8f9f7 3879 * @brief Configures the OCRef clear feature
Anna Bridge 180:96ed750bd169 3880 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 3881 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3882 * contains the OCREF clear feature and parameters for the TIM peripheral.
Anna Bridge 180:96ed750bd169 3883 * @param Channel specifies the TIM Channel
<> 144:ef7eb2e8f9f7 3884 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3885 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 3886 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 3887 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 3888 * @arg TIM_CHANNEL_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 3889 * @retval HAL status
<> 144:ef7eb2e8f9f7 3890 */
<> 144:ef7eb2e8f9f7 3891 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3892 {
<> 144:ef7eb2e8f9f7 3893 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 3894
<> 144:ef7eb2e8f9f7 3895 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3896 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3897 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 3898 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 3899 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 3900 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 3901
<> 144:ef7eb2e8f9f7 3902 /* Process Locked */
<> 144:ef7eb2e8f9f7 3903 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3904
<> 144:ef7eb2e8f9f7 3905 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3906
<> 144:ef7eb2e8f9f7 3907 switch (sClearInputConfig->ClearInputSource)
<> 144:ef7eb2e8f9f7 3908 {
<> 144:ef7eb2e8f9f7 3909 case TIM_CLEARINPUTSOURCE_NONE:
<> 144:ef7eb2e8f9f7 3910 {
<> 144:ef7eb2e8f9f7 3911 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 3912 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3913
<> 144:ef7eb2e8f9f7 3914 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 3915 tmpsmcr &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 3916
<> 144:ef7eb2e8f9f7 3917 /* Clear the ETR Bits */
<> 144:ef7eb2e8f9f7 3918 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 3919
<> 144:ef7eb2e8f9f7 3920 /* Set TIMx_SMCR */
<> 144:ef7eb2e8f9f7 3921 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3922 }
<> 144:ef7eb2e8f9f7 3923 break;
<> 144:ef7eb2e8f9f7 3924
<> 144:ef7eb2e8f9f7 3925 case TIM_CLEARINPUTSOURCE_ETR:
<> 144:ef7eb2e8f9f7 3926 {
<> 144:ef7eb2e8f9f7 3927 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3928 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 3929 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 3930 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 3931
<> 144:ef7eb2e8f9f7 3932 /* Set the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 3933 htim->Instance->SMCR |= TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 3934 }
<> 144:ef7eb2e8f9f7 3935 break;
<> 144:ef7eb2e8f9f7 3936 default:
<> 144:ef7eb2e8f9f7 3937 break;
<> 144:ef7eb2e8f9f7 3938 }
<> 144:ef7eb2e8f9f7 3939
<> 144:ef7eb2e8f9f7 3940 switch (Channel)
<> 144:ef7eb2e8f9f7 3941 {
<> 144:ef7eb2e8f9f7 3942 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3943 {
<> 144:ef7eb2e8f9f7 3944 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3945 {
<> 144:ef7eb2e8f9f7 3946 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3947 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3948 }
<> 144:ef7eb2e8f9f7 3949 else
<> 144:ef7eb2e8f9f7 3950 {
<> 144:ef7eb2e8f9f7 3951 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3952 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3953 }
<> 144:ef7eb2e8f9f7 3954 }
<> 144:ef7eb2e8f9f7 3955 break;
<> 144:ef7eb2e8f9f7 3956 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3957 {
<> 144:ef7eb2e8f9f7 3958 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3959 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3960 {
<> 144:ef7eb2e8f9f7 3961 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3962 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3963 }
<> 144:ef7eb2e8f9f7 3964 else
<> 144:ef7eb2e8f9f7 3965 {
<> 144:ef7eb2e8f9f7 3966 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3967 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3968 }
<> 144:ef7eb2e8f9f7 3969 }
<> 144:ef7eb2e8f9f7 3970 break;
<> 144:ef7eb2e8f9f7 3971 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3972 {
<> 144:ef7eb2e8f9f7 3973 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3974 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3975 {
<> 144:ef7eb2e8f9f7 3976 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3977 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3978 }
<> 144:ef7eb2e8f9f7 3979 else
<> 144:ef7eb2e8f9f7 3980 {
<> 144:ef7eb2e8f9f7 3981 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3982 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3983 }
<> 144:ef7eb2e8f9f7 3984 }
<> 144:ef7eb2e8f9f7 3985 break;
<> 144:ef7eb2e8f9f7 3986 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3987 {
<> 144:ef7eb2e8f9f7 3988 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3989 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3990 {
<> 144:ef7eb2e8f9f7 3991 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3992 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3993 }
<> 144:ef7eb2e8f9f7 3994 else
<> 144:ef7eb2e8f9f7 3995 {
<> 144:ef7eb2e8f9f7 3996 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3997 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3998 }
<> 144:ef7eb2e8f9f7 3999 }
<> 144:ef7eb2e8f9f7 4000 break;
<> 144:ef7eb2e8f9f7 4001 default:
<> 144:ef7eb2e8f9f7 4002 break;
<> 144:ef7eb2e8f9f7 4003 }
<> 144:ef7eb2e8f9f7 4004
<> 144:ef7eb2e8f9f7 4005 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4006
<> 144:ef7eb2e8f9f7 4007 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4008
<> 144:ef7eb2e8f9f7 4009 return HAL_OK;
<> 144:ef7eb2e8f9f7 4010 }
<> 144:ef7eb2e8f9f7 4011
<> 144:ef7eb2e8f9f7 4012 /**
<> 144:ef7eb2e8f9f7 4013 * @brief Configures the clock source to be used
Anna Bridge 180:96ed750bd169 4014 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 4015 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4016 * contains the clock source information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 4017 * @retval HAL status
<> 144:ef7eb2e8f9f7 4018 */
<> 144:ef7eb2e8f9f7 4019 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
<> 144:ef7eb2e8f9f7 4020 {
<> 156:95d6b41a828b 4021 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 4022
<> 144:ef7eb2e8f9f7 4023 /* Process Locked */
<> 144:ef7eb2e8f9f7 4024 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4025
<> 144:ef7eb2e8f9f7 4026 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4027
<> 144:ef7eb2e8f9f7 4028 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4029 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<> 144:ef7eb2e8f9f7 4030
<> 144:ef7eb2e8f9f7 4031 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<> 144:ef7eb2e8f9f7 4032 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4033 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 4034 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 4035 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4036
<> 144:ef7eb2e8f9f7 4037 switch (sClockSourceConfig->ClockSource)
<> 144:ef7eb2e8f9f7 4038 {
<> 144:ef7eb2e8f9f7 4039 case TIM_CLOCKSOURCE_INTERNAL:
<> 144:ef7eb2e8f9f7 4040 {
<> 144:ef7eb2e8f9f7 4041 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4042 /* Disable slave mode to clock the prescaler directly with the internal clock */
<> 144:ef7eb2e8f9f7 4043 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 4044 }
<> 144:ef7eb2e8f9f7 4045 break;
<> 144:ef7eb2e8f9f7 4046
<> 144:ef7eb2e8f9f7 4047 case TIM_CLOCKSOURCE_ETRMODE1:
<> 144:ef7eb2e8f9f7 4048 {
<> 144:ef7eb2e8f9f7 4049 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
<> 144:ef7eb2e8f9f7 4050 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4051
<> 144:ef7eb2e8f9f7 4052 /* Check ETR input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4053 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 4054 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4055 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4056
<> 144:ef7eb2e8f9f7 4057 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 4058 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 4059 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 4060 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4061 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4062 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4063 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4064 /* Reset the SMS and TS Bits */
<> 144:ef7eb2e8f9f7 4065 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 4066 /* Select the External clock mode1 and the ETRF trigger */
<> 144:ef7eb2e8f9f7 4067 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
<> 144:ef7eb2e8f9f7 4068 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4069 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4070 }
<> 144:ef7eb2e8f9f7 4071 break;
<> 144:ef7eb2e8f9f7 4072
<> 144:ef7eb2e8f9f7 4073 case TIM_CLOCKSOURCE_ETRMODE2:
<> 144:ef7eb2e8f9f7 4074 {
<> 144:ef7eb2e8f9f7 4075 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
<> 144:ef7eb2e8f9f7 4076 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4077
<> 144:ef7eb2e8f9f7 4078 /* Check ETR input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4079 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 4080 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4081 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4082
<> 144:ef7eb2e8f9f7 4083 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 4084 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 4085 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 4086 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4087 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4088 /* Enable the External clock mode2 */
<> 144:ef7eb2e8f9f7 4089 htim->Instance->SMCR |= TIM_SMCR_ECE;
<> 144:ef7eb2e8f9f7 4090 }
<> 144:ef7eb2e8f9f7 4091 break;
<> 144:ef7eb2e8f9f7 4092
<> 144:ef7eb2e8f9f7 4093 case TIM_CLOCKSOURCE_TI1:
<> 144:ef7eb2e8f9f7 4094 {
<> 144:ef7eb2e8f9f7 4095 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4096 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4097
<> 144:ef7eb2e8f9f7 4098 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4099 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4100 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4101
<> 144:ef7eb2e8f9f7 4102 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4103 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4104 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4105 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<> 144:ef7eb2e8f9f7 4106 }
<> 144:ef7eb2e8f9f7 4107 break;
<> 144:ef7eb2e8f9f7 4108 case TIM_CLOCKSOURCE_TI2:
<> 144:ef7eb2e8f9f7 4109 {
<> 144:ef7eb2e8f9f7 4110 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
<> 144:ef7eb2e8f9f7 4111 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4112
<> 144:ef7eb2e8f9f7 4113 /* Check TI2 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4114 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4115 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4116
<> 144:ef7eb2e8f9f7 4117 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4118 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4119 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4120 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<> 144:ef7eb2e8f9f7 4121 }
<> 144:ef7eb2e8f9f7 4122 break;
<> 144:ef7eb2e8f9f7 4123 case TIM_CLOCKSOURCE_TI1ED:
<> 144:ef7eb2e8f9f7 4124 {
<> 144:ef7eb2e8f9f7 4125 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4126 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4127
<> 144:ef7eb2e8f9f7 4128 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4129 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4130 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4131
<> 144:ef7eb2e8f9f7 4132 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4133 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4134 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4135 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<> 144:ef7eb2e8f9f7 4136 }
<> 144:ef7eb2e8f9f7 4137 break;
<> 144:ef7eb2e8f9f7 4138 case TIM_CLOCKSOURCE_ITR0:
<> 144:ef7eb2e8f9f7 4139 {
<> 144:ef7eb2e8f9f7 4140 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4141 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4142
<> 144:ef7eb2e8f9f7 4143 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<> 144:ef7eb2e8f9f7 4144 }
<> 144:ef7eb2e8f9f7 4145 break;
<> 144:ef7eb2e8f9f7 4146 case TIM_CLOCKSOURCE_ITR1:
<> 144:ef7eb2e8f9f7 4147 {
<> 144:ef7eb2e8f9f7 4148 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4149 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4150
<> 144:ef7eb2e8f9f7 4151 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<> 144:ef7eb2e8f9f7 4152 }
<> 144:ef7eb2e8f9f7 4153 break;
<> 144:ef7eb2e8f9f7 4154 case TIM_CLOCKSOURCE_ITR2:
<> 144:ef7eb2e8f9f7 4155 {
<> 144:ef7eb2e8f9f7 4156 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4157 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4158
<> 144:ef7eb2e8f9f7 4159 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<> 144:ef7eb2e8f9f7 4160 }
<> 144:ef7eb2e8f9f7 4161 break;
<> 144:ef7eb2e8f9f7 4162 case TIM_CLOCKSOURCE_ITR3:
<> 144:ef7eb2e8f9f7 4163 {
<> 144:ef7eb2e8f9f7 4164 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4165 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4166
<> 144:ef7eb2e8f9f7 4167 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<> 144:ef7eb2e8f9f7 4168 }
<> 144:ef7eb2e8f9f7 4169 break;
<> 144:ef7eb2e8f9f7 4170
<> 144:ef7eb2e8f9f7 4171 default:
<> 144:ef7eb2e8f9f7 4172 break;
<> 144:ef7eb2e8f9f7 4173 }
<> 144:ef7eb2e8f9f7 4174 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4175
<> 144:ef7eb2e8f9f7 4176 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4177
<> 144:ef7eb2e8f9f7 4178 return HAL_OK;
<> 144:ef7eb2e8f9f7 4179 }
<> 144:ef7eb2e8f9f7 4180
<> 144:ef7eb2e8f9f7 4181 /**
<> 144:ef7eb2e8f9f7 4182 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
<> 144:ef7eb2e8f9f7 4183 * or a XOR combination between CH1_input, CH2_input & CH3_input
Anna Bridge 180:96ed750bd169 4184 * @param htim TIM handle.
Anna Bridge 180:96ed750bd169 4185 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
<> 144:ef7eb2e8f9f7 4186 * output of a XOR gate.
<> 144:ef7eb2e8f9f7 4187 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4188 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<> 144:ef7eb2e8f9f7 4189 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<> 144:ef7eb2e8f9f7 4190 * pins are connected to the TI1 input (XOR combination)
<> 144:ef7eb2e8f9f7 4191 * @retval HAL status
<> 144:ef7eb2e8f9f7 4192 */
<> 144:ef7eb2e8f9f7 4193 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<> 144:ef7eb2e8f9f7 4194 {
<> 156:95d6b41a828b 4195 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4196
<> 144:ef7eb2e8f9f7 4197 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4198 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4199 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<> 144:ef7eb2e8f9f7 4200
<> 144:ef7eb2e8f9f7 4201 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4202 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 4203
<> 144:ef7eb2e8f9f7 4204 /* Reset the TI1 selection */
<> 144:ef7eb2e8f9f7 4205 tmpcr2 &= ~TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 4206
<> 144:ef7eb2e8f9f7 4207 /* Set the the TI1 selection */
<> 144:ef7eb2e8f9f7 4208 tmpcr2 |= TI1_Selection;
<> 144:ef7eb2e8f9f7 4209
<> 144:ef7eb2e8f9f7 4210 /* Write to TIMxCR2 */
<> 144:ef7eb2e8f9f7 4211 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4212
<> 144:ef7eb2e8f9f7 4213 return HAL_OK;
<> 144:ef7eb2e8f9f7 4214 }
<> 144:ef7eb2e8f9f7 4215
<> 144:ef7eb2e8f9f7 4216 /**
<> 144:ef7eb2e8f9f7 4217 * @brief Configures the TIM in Slave mode
Anna Bridge 180:96ed750bd169 4218 * @param htim TIM handle.
Anna Bridge 180:96ed750bd169 4219 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4220 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4221 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4222 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4223 * @retval HAL status
<> 144:ef7eb2e8f9f7 4224 */
<> 144:ef7eb2e8f9f7 4225 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4226 {
<> 144:ef7eb2e8f9f7 4227 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4228 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4229 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4230 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4231
<> 144:ef7eb2e8f9f7 4232 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4233
<> 144:ef7eb2e8f9f7 4234 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4235
<> 144:ef7eb2e8f9f7 4236 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4237
<> 144:ef7eb2e8f9f7 4238 /* Disable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4239 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4240
<> 144:ef7eb2e8f9f7 4241 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4242 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4243
<> 144:ef7eb2e8f9f7 4244 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4245
<> 144:ef7eb2e8f9f7 4246 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4247
<> 144:ef7eb2e8f9f7 4248 return HAL_OK;
<> 144:ef7eb2e8f9f7 4249 }
<> 144:ef7eb2e8f9f7 4250
<> 144:ef7eb2e8f9f7 4251 /**
<> 144:ef7eb2e8f9f7 4252 * @brief Configures the TIM in Slave mode in interrupt mode
Anna Bridge 180:96ed750bd169 4253 * @param htim TIM handle.
Anna Bridge 180:96ed750bd169 4254 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4255 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4256 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4257 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4258 * @retval HAL status
<> 144:ef7eb2e8f9f7 4259 */
<> 144:ef7eb2e8f9f7 4260 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4261 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4262 {
<> 144:ef7eb2e8f9f7 4263 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4264 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4265 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4266 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4267
<> 144:ef7eb2e8f9f7 4268 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4269
<> 144:ef7eb2e8f9f7 4270 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4271
<> 144:ef7eb2e8f9f7 4272 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4273
<> 144:ef7eb2e8f9f7 4274 /* Enable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4275 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4276
<> 144:ef7eb2e8f9f7 4277 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4278 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4279
<> 144:ef7eb2e8f9f7 4280 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4281
<> 144:ef7eb2e8f9f7 4282 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4283
<> 144:ef7eb2e8f9f7 4284 return HAL_OK;
<> 144:ef7eb2e8f9f7 4285 }
<> 144:ef7eb2e8f9f7 4286
<> 144:ef7eb2e8f9f7 4287 /**
<> 144:ef7eb2e8f9f7 4288 * @brief Read the captured value from Capture Compare unit
Anna Bridge 180:96ed750bd169 4289 * @param htim TIM handle.
Anna Bridge 180:96ed750bd169 4290 * @param Channel TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 4291 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4292 * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 4293 * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 4294 * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 4295 * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 4296 * @retval Captured value
<> 144:ef7eb2e8f9f7 4297 */
<> 144:ef7eb2e8f9f7 4298 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 4299 {
<> 156:95d6b41a828b 4300 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 4301
<> 144:ef7eb2e8f9f7 4302 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4303
<> 144:ef7eb2e8f9f7 4304 switch (Channel)
<> 144:ef7eb2e8f9f7 4305 {
<> 144:ef7eb2e8f9f7 4306 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 4307 {
<> 144:ef7eb2e8f9f7 4308 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4309 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4310
<> 144:ef7eb2e8f9f7 4311 /* Return the capture 1 value */
<> 144:ef7eb2e8f9f7 4312 tmpreg = htim->Instance->CCR1;
<> 144:ef7eb2e8f9f7 4313
<> 144:ef7eb2e8f9f7 4314 break;
<> 144:ef7eb2e8f9f7 4315 }
<> 144:ef7eb2e8f9f7 4316 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 4317 {
<> 144:ef7eb2e8f9f7 4318 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4319 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4320
<> 144:ef7eb2e8f9f7 4321 /* Return the capture 2 value */
<> 144:ef7eb2e8f9f7 4322 tmpreg = htim->Instance->CCR2;
<> 144:ef7eb2e8f9f7 4323
<> 144:ef7eb2e8f9f7 4324 break;
<> 144:ef7eb2e8f9f7 4325 }
<> 144:ef7eb2e8f9f7 4326
<> 144:ef7eb2e8f9f7 4327 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 4328 {
<> 144:ef7eb2e8f9f7 4329 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4330 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4331
<> 144:ef7eb2e8f9f7 4332 /* Return the capture 3 value */
<> 144:ef7eb2e8f9f7 4333 tmpreg = htim->Instance->CCR3;
<> 144:ef7eb2e8f9f7 4334
<> 144:ef7eb2e8f9f7 4335 break;
<> 144:ef7eb2e8f9f7 4336 }
<> 144:ef7eb2e8f9f7 4337
<> 144:ef7eb2e8f9f7 4338 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 4339 {
<> 144:ef7eb2e8f9f7 4340 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4341 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4342
<> 144:ef7eb2e8f9f7 4343 /* Return the capture 4 value */
<> 144:ef7eb2e8f9f7 4344 tmpreg = htim->Instance->CCR4;
<> 144:ef7eb2e8f9f7 4345
<> 144:ef7eb2e8f9f7 4346 break;
<> 144:ef7eb2e8f9f7 4347 }
<> 144:ef7eb2e8f9f7 4348
<> 144:ef7eb2e8f9f7 4349 default:
<> 144:ef7eb2e8f9f7 4350 break;
<> 144:ef7eb2e8f9f7 4351 }
<> 144:ef7eb2e8f9f7 4352
<> 144:ef7eb2e8f9f7 4353 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4354 return tmpreg;
<> 144:ef7eb2e8f9f7 4355 }
<> 144:ef7eb2e8f9f7 4356
<> 144:ef7eb2e8f9f7 4357 /**
<> 144:ef7eb2e8f9f7 4358 * @}
<> 144:ef7eb2e8f9f7 4359 */
<> 144:ef7eb2e8f9f7 4360
<> 144:ef7eb2e8f9f7 4361 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4362 * @brief TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4363 *
<> 144:ef7eb2e8f9f7 4364 @verbatim
<> 144:ef7eb2e8f9f7 4365 ==============================================================================
<> 144:ef7eb2e8f9f7 4366 ##### TIM Callbacks functions #####
<> 144:ef7eb2e8f9f7 4367 ==============================================================================
<> 144:ef7eb2e8f9f7 4368 [..]
<> 144:ef7eb2e8f9f7 4369 This section provides TIM callback functions:
<> 144:ef7eb2e8f9f7 4370 (+) Timer Period elapsed callback
<> 144:ef7eb2e8f9f7 4371 (+) Timer Output Compare callback
<> 144:ef7eb2e8f9f7 4372 (+) Timer Input capture callback
<> 144:ef7eb2e8f9f7 4373 (+) Timer Trigger callback
<> 144:ef7eb2e8f9f7 4374 (+) Timer Error callback
<> 144:ef7eb2e8f9f7 4375
<> 144:ef7eb2e8f9f7 4376 @endverbatim
<> 144:ef7eb2e8f9f7 4377 * @{
<> 144:ef7eb2e8f9f7 4378 */
<> 144:ef7eb2e8f9f7 4379
<> 144:ef7eb2e8f9f7 4380 /**
<> 144:ef7eb2e8f9f7 4381 * @brief Period elapsed callback in non blocking mode
Anna Bridge 180:96ed750bd169 4382 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 4383 * @retval None
<> 144:ef7eb2e8f9f7 4384 */
<> 144:ef7eb2e8f9f7 4385 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4386 {
<> 144:ef7eb2e8f9f7 4387 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4388 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4389
<> 144:ef7eb2e8f9f7 4390 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4391 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4392 */
<> 144:ef7eb2e8f9f7 4393
<> 144:ef7eb2e8f9f7 4394 }
<> 144:ef7eb2e8f9f7 4395 /**
<> 144:ef7eb2e8f9f7 4396 * @brief Output Compare callback in non blocking mode
Anna Bridge 180:96ed750bd169 4397 * @param htim TIM OC handle
<> 144:ef7eb2e8f9f7 4398 * @retval None
<> 144:ef7eb2e8f9f7 4399 */
<> 144:ef7eb2e8f9f7 4400 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4401 {
<> 144:ef7eb2e8f9f7 4402 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4403 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4404
<> 144:ef7eb2e8f9f7 4405 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4406 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4407 */
<> 144:ef7eb2e8f9f7 4408 }
<> 144:ef7eb2e8f9f7 4409 /**
<> 144:ef7eb2e8f9f7 4410 * @brief Input Capture callback in non blocking mode
Anna Bridge 180:96ed750bd169 4411 * @param htim TIM IC handle
<> 144:ef7eb2e8f9f7 4412 * @retval None
<> 144:ef7eb2e8f9f7 4413 */
<> 144:ef7eb2e8f9f7 4414 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4415 {
<> 144:ef7eb2e8f9f7 4416 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4417 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4418
<> 144:ef7eb2e8f9f7 4419 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4420 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4421 */
<> 144:ef7eb2e8f9f7 4422 }
<> 144:ef7eb2e8f9f7 4423
<> 144:ef7eb2e8f9f7 4424 /**
<> 144:ef7eb2e8f9f7 4425 * @brief PWM Pulse finished callback in non blocking mode
Anna Bridge 180:96ed750bd169 4426 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 4427 * @retval None
<> 144:ef7eb2e8f9f7 4428 */
<> 144:ef7eb2e8f9f7 4429 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4430 {
<> 144:ef7eb2e8f9f7 4431 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4432 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4433
<> 144:ef7eb2e8f9f7 4434 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4435 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4436 */
<> 144:ef7eb2e8f9f7 4437 }
<> 144:ef7eb2e8f9f7 4438
<> 144:ef7eb2e8f9f7 4439 /**
<> 144:ef7eb2e8f9f7 4440 * @brief Hall Trigger detection callback in non blocking mode
Anna Bridge 180:96ed750bd169 4441 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 4442 * @retval None
<> 144:ef7eb2e8f9f7 4443 */
<> 144:ef7eb2e8f9f7 4444 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4445 {
<> 144:ef7eb2e8f9f7 4446 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4447 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4448
<> 144:ef7eb2e8f9f7 4449 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4450 the HAL_TIM_TriggerCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4451 */
<> 144:ef7eb2e8f9f7 4452 }
<> 144:ef7eb2e8f9f7 4453
<> 144:ef7eb2e8f9f7 4454 /**
<> 144:ef7eb2e8f9f7 4455 * @brief Timer error callback in non blocking mode
Anna Bridge 180:96ed750bd169 4456 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 4457 * @retval None
<> 144:ef7eb2e8f9f7 4458 */
<> 144:ef7eb2e8f9f7 4459 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4460 {
<> 144:ef7eb2e8f9f7 4461 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4462 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4463
<> 144:ef7eb2e8f9f7 4464 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4465 the HAL_TIM_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4466 */
<> 144:ef7eb2e8f9f7 4467 }
<> 144:ef7eb2e8f9f7 4468
<> 144:ef7eb2e8f9f7 4469 /**
<> 144:ef7eb2e8f9f7 4470 * @}
<> 144:ef7eb2e8f9f7 4471 */
<> 144:ef7eb2e8f9f7 4472
<> 144:ef7eb2e8f9f7 4473 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<> 144:ef7eb2e8f9f7 4474 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 4475 *
<> 144:ef7eb2e8f9f7 4476 @verbatim
<> 144:ef7eb2e8f9f7 4477 ==============================================================================
<> 144:ef7eb2e8f9f7 4478 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 4479 ==============================================================================
<> 144:ef7eb2e8f9f7 4480 [..]
<> 144:ef7eb2e8f9f7 4481 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 4482 and the data flow.
<> 144:ef7eb2e8f9f7 4483
<> 144:ef7eb2e8f9f7 4484 @endverbatim
<> 144:ef7eb2e8f9f7 4485 * @{
<> 144:ef7eb2e8f9f7 4486 */
<> 144:ef7eb2e8f9f7 4487
<> 144:ef7eb2e8f9f7 4488 /**
<> 144:ef7eb2e8f9f7 4489 * @brief Return the TIM Base state
Anna Bridge 180:96ed750bd169 4490 * @param htim TIM Base handle
<> 144:ef7eb2e8f9f7 4491 * @retval HAL state
<> 144:ef7eb2e8f9f7 4492 */
<> 144:ef7eb2e8f9f7 4493 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4494 {
<> 144:ef7eb2e8f9f7 4495 return htim->State;
<> 144:ef7eb2e8f9f7 4496 }
<> 144:ef7eb2e8f9f7 4497
<> 144:ef7eb2e8f9f7 4498 /**
<> 144:ef7eb2e8f9f7 4499 * @brief Return the TIM OC state
Anna Bridge 180:96ed750bd169 4500 * @param htim TIM Ouput Compare handle
<> 144:ef7eb2e8f9f7 4501 * @retval HAL state
<> 144:ef7eb2e8f9f7 4502 */
<> 144:ef7eb2e8f9f7 4503 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4504 {
<> 144:ef7eb2e8f9f7 4505 return htim->State;
<> 144:ef7eb2e8f9f7 4506 }
<> 144:ef7eb2e8f9f7 4507
<> 144:ef7eb2e8f9f7 4508 /**
<> 144:ef7eb2e8f9f7 4509 * @brief Return the TIM PWM state
Anna Bridge 180:96ed750bd169 4510 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 4511 * @retval HAL state
<> 144:ef7eb2e8f9f7 4512 */
<> 144:ef7eb2e8f9f7 4513 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4514 {
<> 144:ef7eb2e8f9f7 4515 return htim->State;
<> 144:ef7eb2e8f9f7 4516 }
<> 144:ef7eb2e8f9f7 4517
<> 144:ef7eb2e8f9f7 4518 /**
<> 144:ef7eb2e8f9f7 4519 * @brief Return the TIM Input Capture state
Anna Bridge 180:96ed750bd169 4520 * @param htim TIM IC handle
<> 144:ef7eb2e8f9f7 4521 * @retval HAL state
<> 144:ef7eb2e8f9f7 4522 */
<> 144:ef7eb2e8f9f7 4523 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4524 {
<> 144:ef7eb2e8f9f7 4525 return htim->State;
<> 144:ef7eb2e8f9f7 4526 }
<> 144:ef7eb2e8f9f7 4527
<> 144:ef7eb2e8f9f7 4528 /**
<> 144:ef7eb2e8f9f7 4529 * @brief Return the TIM One Pulse Mode state
Anna Bridge 180:96ed750bd169 4530 * @param htim TIM OPM handle
<> 144:ef7eb2e8f9f7 4531 * @retval HAL state
<> 144:ef7eb2e8f9f7 4532 */
<> 144:ef7eb2e8f9f7 4533 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4534 {
<> 144:ef7eb2e8f9f7 4535 return htim->State;
<> 144:ef7eb2e8f9f7 4536 }
<> 144:ef7eb2e8f9f7 4537
<> 144:ef7eb2e8f9f7 4538 /**
<> 144:ef7eb2e8f9f7 4539 * @brief Return the TIM Encoder Mode state
Anna Bridge 180:96ed750bd169 4540 * @param htim TIM Encoder handle
<> 144:ef7eb2e8f9f7 4541 * @retval HAL state
<> 144:ef7eb2e8f9f7 4542 */
<> 144:ef7eb2e8f9f7 4543 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4544 {
<> 144:ef7eb2e8f9f7 4545 return htim->State;
<> 144:ef7eb2e8f9f7 4546 }
<> 144:ef7eb2e8f9f7 4547
<> 144:ef7eb2e8f9f7 4548 /**
<> 144:ef7eb2e8f9f7 4549 * @}
<> 144:ef7eb2e8f9f7 4550 */
<> 144:ef7eb2e8f9f7 4551
<> 144:ef7eb2e8f9f7 4552 /**
<> 144:ef7eb2e8f9f7 4553 * @}
<> 144:ef7eb2e8f9f7 4554 */
<> 144:ef7eb2e8f9f7 4555
<> 144:ef7eb2e8f9f7 4556 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
<> 144:ef7eb2e8f9f7 4557 * @{
<> 144:ef7eb2e8f9f7 4558 */
<> 144:ef7eb2e8f9f7 4559
<> 144:ef7eb2e8f9f7 4560 /**
<> 144:ef7eb2e8f9f7 4561 * @brief TIM DMA error callback
Anna Bridge 180:96ed750bd169 4562 * @param hdma pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4563 * @retval None
<> 144:ef7eb2e8f9f7 4564 */
<> 144:ef7eb2e8f9f7 4565 void TIM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4566 {
<> 144:ef7eb2e8f9f7 4567 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4568
<> 144:ef7eb2e8f9f7 4569 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4570
<> 144:ef7eb2e8f9f7 4571 HAL_TIM_ErrorCallback(htim);
<> 144:ef7eb2e8f9f7 4572 }
<> 144:ef7eb2e8f9f7 4573
<> 144:ef7eb2e8f9f7 4574 /**
<> 144:ef7eb2e8f9f7 4575 * @brief TIM DMA Delay Pulse complete callback.
Anna Bridge 180:96ed750bd169 4576 * @param hdma pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4577 * @retval None
<> 144:ef7eb2e8f9f7 4578 */
<> 144:ef7eb2e8f9f7 4579 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4580 {
<> 144:ef7eb2e8f9f7 4581 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4582
<> 144:ef7eb2e8f9f7 4583 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4584
<> 144:ef7eb2e8f9f7 4585 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4586 {
<> 144:ef7eb2e8f9f7 4587 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4588 }
<> 144:ef7eb2e8f9f7 4589 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4590 {
<> 144:ef7eb2e8f9f7 4591 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4592 }
<> 144:ef7eb2e8f9f7 4593 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4594 {
<> 144:ef7eb2e8f9f7 4595 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4596 }
<> 144:ef7eb2e8f9f7 4597 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4598 {
<> 144:ef7eb2e8f9f7 4599 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4600 }
<> 144:ef7eb2e8f9f7 4601
<> 144:ef7eb2e8f9f7 4602 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 4603
<> 144:ef7eb2e8f9f7 4604 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4605 }
<> 144:ef7eb2e8f9f7 4606 /**
<> 144:ef7eb2e8f9f7 4607 * @brief TIM DMA Capture complete callback.
Anna Bridge 180:96ed750bd169 4608 * @param hdma pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4609 * @retval None
<> 144:ef7eb2e8f9f7 4610 */
<> 144:ef7eb2e8f9f7 4611 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4612 {
<> 144:ef7eb2e8f9f7 4613 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4614
<> 144:ef7eb2e8f9f7 4615 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4616
<> 144:ef7eb2e8f9f7 4617 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4618 {
<> 144:ef7eb2e8f9f7 4619 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4620 }
<> 144:ef7eb2e8f9f7 4621 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4622 {
<> 144:ef7eb2e8f9f7 4623 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4624 }
<> 144:ef7eb2e8f9f7 4625 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4626 {
<> 144:ef7eb2e8f9f7 4627 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4628 }
<> 144:ef7eb2e8f9f7 4629 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4630 {
<> 144:ef7eb2e8f9f7 4631 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4632 }
<> 144:ef7eb2e8f9f7 4633
<> 144:ef7eb2e8f9f7 4634 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 4635
<> 144:ef7eb2e8f9f7 4636 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4637 }
<> 144:ef7eb2e8f9f7 4638
<> 144:ef7eb2e8f9f7 4639 /**
<> 144:ef7eb2e8f9f7 4640 * @brief TIM DMA Period Elapse complete callback.
Anna Bridge 180:96ed750bd169 4641 * @param hdma pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4642 * @retval None
<> 144:ef7eb2e8f9f7 4643 */
<> 144:ef7eb2e8f9f7 4644 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4645 {
<> 144:ef7eb2e8f9f7 4646 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4647
<> 144:ef7eb2e8f9f7 4648 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4649
<> 144:ef7eb2e8f9f7 4650 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 4651 }
<> 144:ef7eb2e8f9f7 4652
<> 144:ef7eb2e8f9f7 4653 /**
<> 144:ef7eb2e8f9f7 4654 * @brief TIM DMA Trigger callback.
Anna Bridge 180:96ed750bd169 4655 * @param hdma pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4656 * @retval None
<> 144:ef7eb2e8f9f7 4657 */
<> 144:ef7eb2e8f9f7 4658 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4659 {
<> 144:ef7eb2e8f9f7 4660 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4661
<> 144:ef7eb2e8f9f7 4662 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4663
<> 144:ef7eb2e8f9f7 4664 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 4665 }
<> 144:ef7eb2e8f9f7 4666
<> 144:ef7eb2e8f9f7 4667 /**
<> 144:ef7eb2e8f9f7 4668 * @brief Time Base configuration
Anna Bridge 180:96ed750bd169 4669 * @param TIMx TIM periheral
Anna Bridge 180:96ed750bd169 4670 * @param Structure TIM Base configuration structure
<> 144:ef7eb2e8f9f7 4671 * @retval None
<> 144:ef7eb2e8f9f7 4672 */
<> 144:ef7eb2e8f9f7 4673 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
<> 144:ef7eb2e8f9f7 4674 {
<> 156:95d6b41a828b 4675 uint32_t tmpcr1 = 0U;
<> 144:ef7eb2e8f9f7 4676 tmpcr1 = TIMx->CR1;
<> 144:ef7eb2e8f9f7 4677
<> 144:ef7eb2e8f9f7 4678 /* Set TIM Time Base Unit parameters ---------------------------------------*/
<> 144:ef7eb2e8f9f7 4679 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4680 {
<> 144:ef7eb2e8f9f7 4681 /* Select the Counter Mode */
<> 144:ef7eb2e8f9f7 4682 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
<> 144:ef7eb2e8f9f7 4683 tmpcr1 |= Structure->CounterMode;
<> 144:ef7eb2e8f9f7 4684 }
<> 144:ef7eb2e8f9f7 4685
<> 144:ef7eb2e8f9f7 4686 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4687 {
<> 144:ef7eb2e8f9f7 4688 /* Set the clock division */
<> 144:ef7eb2e8f9f7 4689 tmpcr1 &= ~TIM_CR1_CKD;
<> 144:ef7eb2e8f9f7 4690 tmpcr1 |= (uint32_t)Structure->ClockDivision;
<> 144:ef7eb2e8f9f7 4691 }
<> 144:ef7eb2e8f9f7 4692
<> 156:95d6b41a828b 4693 /* Set the auto-reload preload */
<> 156:95d6b41a828b 4694 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
<> 156:95d6b41a828b 4695
<> 144:ef7eb2e8f9f7 4696 TIMx->CR1 = tmpcr1;
<> 144:ef7eb2e8f9f7 4697
<> 144:ef7eb2e8f9f7 4698 /* Set the Autoreload value */
<> 144:ef7eb2e8f9f7 4699 TIMx->ARR = (uint32_t)Structure->Period ;
<> 144:ef7eb2e8f9f7 4700
<> 144:ef7eb2e8f9f7 4701 /* Set the Prescaler value */
<> 144:ef7eb2e8f9f7 4702 TIMx->PSC = (uint32_t)Structure->Prescaler;
<> 144:ef7eb2e8f9f7 4703
<> 144:ef7eb2e8f9f7 4704 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4705 {
<> 144:ef7eb2e8f9f7 4706 /* Set the Repetition Counter value */
<> 144:ef7eb2e8f9f7 4707 TIMx->RCR = Structure->RepetitionCounter;
<> 144:ef7eb2e8f9f7 4708 }
<> 144:ef7eb2e8f9f7 4709
<> 144:ef7eb2e8f9f7 4710 /* Generate an update event to reload the Prescaler
<> 144:ef7eb2e8f9f7 4711 and the repetition counter(only for TIM1 and TIM8) value immediatly */
<> 144:ef7eb2e8f9f7 4712 TIMx->EGR = TIM_EGR_UG;
<> 144:ef7eb2e8f9f7 4713 }
<> 144:ef7eb2e8f9f7 4714
<> 144:ef7eb2e8f9f7 4715 /**
<> 144:ef7eb2e8f9f7 4716 * @brief Time Ouput Compare 1 configuration
<> 144:ef7eb2e8f9f7 4717 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 4718 * @param OC_Config The ouput configuration structure
<> 144:ef7eb2e8f9f7 4719 * @retval None
<> 144:ef7eb2e8f9f7 4720 */
<> 144:ef7eb2e8f9f7 4721 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4722 {
<> 156:95d6b41a828b 4723 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4724 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4725 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4726
<> 144:ef7eb2e8f9f7 4727 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4728 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4729
<> 144:ef7eb2e8f9f7 4730 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4731 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4732 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4733 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4734
<> 144:ef7eb2e8f9f7 4735 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4736 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4737
<> 144:ef7eb2e8f9f7 4738 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 4739 tmpccmrx &= ~TIM_CCMR1_OC1M;
<> 144:ef7eb2e8f9f7 4740 tmpccmrx &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4741 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4742 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4743
<> 144:ef7eb2e8f9f7 4744 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4745 tmpccer &= ~TIM_CCER_CC1P;
<> 144:ef7eb2e8f9f7 4746 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4747 tmpccer |= OC_Config->OCPolarity;
<> 144:ef7eb2e8f9f7 4748
<> 144:ef7eb2e8f9f7 4749 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
<> 144:ef7eb2e8f9f7 4750 {
<> 144:ef7eb2e8f9f7 4751 /* Check parameters */
<> 144:ef7eb2e8f9f7 4752 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4753
<> 144:ef7eb2e8f9f7 4754 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4755 tmpccer &= ~TIM_CCER_CC1NP;
<> 144:ef7eb2e8f9f7 4756 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4757 tmpccer |= OC_Config->OCNPolarity;
<> 144:ef7eb2e8f9f7 4758 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4759 tmpccer &= ~TIM_CCER_CC1NE;
<> 144:ef7eb2e8f9f7 4760 }
<> 144:ef7eb2e8f9f7 4761
<> 144:ef7eb2e8f9f7 4762 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4763 {
<> 144:ef7eb2e8f9f7 4764 /* Check parameters */
<> 144:ef7eb2e8f9f7 4765 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4766 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4767
<> 144:ef7eb2e8f9f7 4768 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4769 tmpcr2 &= ~TIM_CR2_OIS1;
<> 144:ef7eb2e8f9f7 4770 tmpcr2 &= ~TIM_CR2_OIS1N;
<> 144:ef7eb2e8f9f7 4771 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4772 tmpcr2 |= OC_Config->OCIdleState;
<> 144:ef7eb2e8f9f7 4773 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4774 tmpcr2 |= OC_Config->OCNIdleState;
<> 144:ef7eb2e8f9f7 4775 }
<> 144:ef7eb2e8f9f7 4776 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4777 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4778
<> 144:ef7eb2e8f9f7 4779 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4780 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4781
<> 144:ef7eb2e8f9f7 4782 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4783 TIMx->CCR1 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4784
<> 144:ef7eb2e8f9f7 4785 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4786 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4787 }
<> 144:ef7eb2e8f9f7 4788
<> 144:ef7eb2e8f9f7 4789 /**
<> 144:ef7eb2e8f9f7 4790 * @brief Time Ouput Compare 2 configuration
<> 144:ef7eb2e8f9f7 4791 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 4792 * @param OC_Config The ouput configuration structure
<> 144:ef7eb2e8f9f7 4793 * @retval None
<> 144:ef7eb2e8f9f7 4794 */
<> 144:ef7eb2e8f9f7 4795 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4796 {
<> 156:95d6b41a828b 4797 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4798 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4799 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4800
<> 144:ef7eb2e8f9f7 4801 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4802 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4803
<> 144:ef7eb2e8f9f7 4804 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4805 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4806 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4807 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4808
<> 144:ef7eb2e8f9f7 4809 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4810 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4811
<> 144:ef7eb2e8f9f7 4812 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4813 tmpccmrx &= ~TIM_CCMR1_OC2M;
<> 144:ef7eb2e8f9f7 4814 tmpccmrx &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 4815
<> 144:ef7eb2e8f9f7 4816 /* Select the Output Compare Mode */
<> 156:95d6b41a828b 4817 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4818
<> 144:ef7eb2e8f9f7 4819 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4820 tmpccer &= ~TIM_CCER_CC2P;
<> 144:ef7eb2e8f9f7 4821 /* Set the Output Compare Polarity */
<> 156:95d6b41a828b 4822 tmpccer |= (OC_Config->OCPolarity << 4U);
<> 144:ef7eb2e8f9f7 4823
<> 144:ef7eb2e8f9f7 4824 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 4825 {
<> 144:ef7eb2e8f9f7 4826 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4827
<> 144:ef7eb2e8f9f7 4828 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4829 tmpccer &= ~TIM_CCER_CC2NP;
<> 144:ef7eb2e8f9f7 4830 /* Set the Output N Polarity */
<> 156:95d6b41a828b 4831 tmpccer |= (OC_Config->OCNPolarity << 4U);
<> 144:ef7eb2e8f9f7 4832 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4833 tmpccer &= ~TIM_CCER_CC2NE;
<> 144:ef7eb2e8f9f7 4834
<> 144:ef7eb2e8f9f7 4835 }
<> 144:ef7eb2e8f9f7 4836
<> 144:ef7eb2e8f9f7 4837 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4838 {
<> 144:ef7eb2e8f9f7 4839 /* Check parameters */
<> 144:ef7eb2e8f9f7 4840 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4841 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4842
<> 144:ef7eb2e8f9f7 4843 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4844 tmpcr2 &= ~TIM_CR2_OIS2;
<> 144:ef7eb2e8f9f7 4845 tmpcr2 &= ~TIM_CR2_OIS2N;
<> 144:ef7eb2e8f9f7 4846 /* Set the Output Idle state */
<> 156:95d6b41a828b 4847 tmpcr2 |= (OC_Config->OCIdleState << 2U);
<> 144:ef7eb2e8f9f7 4848 /* Set the Output N Idle state */
<> 156:95d6b41a828b 4849 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
<> 144:ef7eb2e8f9f7 4850 }
<> 144:ef7eb2e8f9f7 4851
<> 144:ef7eb2e8f9f7 4852 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4853 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4854
<> 144:ef7eb2e8f9f7 4855 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4856 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4857
<> 144:ef7eb2e8f9f7 4858 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4859 TIMx->CCR2 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4860
<> 144:ef7eb2e8f9f7 4861 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4862 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4863 }
<> 144:ef7eb2e8f9f7 4864
<> 144:ef7eb2e8f9f7 4865 /**
<> 144:ef7eb2e8f9f7 4866 * @brief Time Ouput Compare 3 configuration
<> 144:ef7eb2e8f9f7 4867 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 4868 * @param OC_Config The ouput configuration structure
<> 144:ef7eb2e8f9f7 4869 * @retval None
<> 144:ef7eb2e8f9f7 4870 */
<> 144:ef7eb2e8f9f7 4871 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4872 {
<> 156:95d6b41a828b 4873 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4874 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4875 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4876
<> 144:ef7eb2e8f9f7 4877 /* Disable the Channel 3: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4878 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 4879
<> 144:ef7eb2e8f9f7 4880 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4881 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4882 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4883 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4884
<> 144:ef7eb2e8f9f7 4885 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4886 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4887
<> 144:ef7eb2e8f9f7 4888 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4889 tmpccmrx &= ~TIM_CCMR2_OC3M;
<> 144:ef7eb2e8f9f7 4890 tmpccmrx &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 4891 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4892 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4893
<> 144:ef7eb2e8f9f7 4894 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4895 tmpccer &= ~TIM_CCER_CC3P;
<> 144:ef7eb2e8f9f7 4896 /* Set the Output Compare Polarity */
<> 156:95d6b41a828b 4897 tmpccer |= (OC_Config->OCPolarity << 8U);
<> 144:ef7eb2e8f9f7 4898
<> 144:ef7eb2e8f9f7 4899 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 4900 {
<> 144:ef7eb2e8f9f7 4901 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4902
<> 144:ef7eb2e8f9f7 4903 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4904 tmpccer &= ~TIM_CCER_CC3NP;
<> 144:ef7eb2e8f9f7 4905 /* Set the Output N Polarity */
<> 156:95d6b41a828b 4906 tmpccer |= (OC_Config->OCNPolarity << 8U);
<> 144:ef7eb2e8f9f7 4907 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4908 tmpccer &= ~TIM_CCER_CC3NE;
<> 144:ef7eb2e8f9f7 4909 }
<> 144:ef7eb2e8f9f7 4910
<> 144:ef7eb2e8f9f7 4911 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4912 {
<> 144:ef7eb2e8f9f7 4913 /* Check parameters */
<> 144:ef7eb2e8f9f7 4914 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4915 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4916
<> 144:ef7eb2e8f9f7 4917 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4918 tmpcr2 &= ~TIM_CR2_OIS3;
<> 144:ef7eb2e8f9f7 4919 tmpcr2 &= ~TIM_CR2_OIS3N;
<> 144:ef7eb2e8f9f7 4920 /* Set the Output Idle state */
<> 156:95d6b41a828b 4921 tmpcr2 |= (OC_Config->OCIdleState << 4U);
<> 144:ef7eb2e8f9f7 4922 /* Set the Output N Idle state */
<> 156:95d6b41a828b 4923 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
<> 144:ef7eb2e8f9f7 4924 }
<> 144:ef7eb2e8f9f7 4925
<> 144:ef7eb2e8f9f7 4926 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4927 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4928
<> 144:ef7eb2e8f9f7 4929 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4930 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4931
<> 144:ef7eb2e8f9f7 4932 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4933 TIMx->CCR3 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4934
<> 144:ef7eb2e8f9f7 4935 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4936 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4937 }
<> 144:ef7eb2e8f9f7 4938
<> 144:ef7eb2e8f9f7 4939 /**
<> 144:ef7eb2e8f9f7 4940 * @brief Time Ouput Compare 4 configuration
<> 144:ef7eb2e8f9f7 4941 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 4942 * @param OC_Config The ouput configuration structure
<> 144:ef7eb2e8f9f7 4943 * @retval None
<> 144:ef7eb2e8f9f7 4944 */
<> 144:ef7eb2e8f9f7 4945 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4946 {
<> 156:95d6b41a828b 4947 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4948 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4949 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4950
<> 144:ef7eb2e8f9f7 4951 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 4952 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 4953
<> 144:ef7eb2e8f9f7 4954 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4955 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4956 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4957 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4958
<> 144:ef7eb2e8f9f7 4959 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4960 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4961
<> 144:ef7eb2e8f9f7 4962 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4963 tmpccmrx &= ~TIM_CCMR2_OC4M;
<> 144:ef7eb2e8f9f7 4964 tmpccmrx &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 4965
<> 144:ef7eb2e8f9f7 4966 /* Select the Output Compare Mode */
<> 156:95d6b41a828b 4967 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4968
<> 144:ef7eb2e8f9f7 4969 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4970 tmpccer &= ~TIM_CCER_CC4P;
<> 144:ef7eb2e8f9f7 4971 /* Set the Output Compare Polarity */
<> 156:95d6b41a828b 4972 tmpccer |= (OC_Config->OCPolarity << 12U);
<> 144:ef7eb2e8f9f7 4973
<> 144:ef7eb2e8f9f7 4974 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4975 {
<> 144:ef7eb2e8f9f7 4976 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4977
<> 144:ef7eb2e8f9f7 4978 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 4979 tmpcr2 &= ~TIM_CR2_OIS4;
<> 144:ef7eb2e8f9f7 4980 /* Set the Output Idle state */
<> 156:95d6b41a828b 4981 tmpcr2 |= (OC_Config->OCIdleState << 6U);
<> 144:ef7eb2e8f9f7 4982 }
<> 144:ef7eb2e8f9f7 4983
<> 144:ef7eb2e8f9f7 4984 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4985 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4986
<> 144:ef7eb2e8f9f7 4987 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4988 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4989
<> 144:ef7eb2e8f9f7 4990 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4991 TIMx->CCR4 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4992
<> 144:ef7eb2e8f9f7 4993 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4994 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4995 }
<> 144:ef7eb2e8f9f7 4996
<> 144:ef7eb2e8f9f7 4997 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4998 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4999 {
<> 156:95d6b41a828b 5000 uint32_t tmpsmcr = 0U;
<> 156:95d6b41a828b 5001 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5002 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5003
<> 144:ef7eb2e8f9f7 5004 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 5005 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 5006
<> 144:ef7eb2e8f9f7 5007 /* Reset the Trigger Selection Bits */
<> 144:ef7eb2e8f9f7 5008 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 5009 /* Set the Input Trigger source */
<> 144:ef7eb2e8f9f7 5010 tmpsmcr |= sSlaveConfig->InputTrigger;
<> 144:ef7eb2e8f9f7 5011
<> 144:ef7eb2e8f9f7 5012 /* Reset the slave mode Bits */
<> 144:ef7eb2e8f9f7 5013 tmpsmcr &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 5014 /* Set the slave mode */
<> 144:ef7eb2e8f9f7 5015 tmpsmcr |= sSlaveConfig->SlaveMode;
<> 144:ef7eb2e8f9f7 5016
<> 144:ef7eb2e8f9f7 5017 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5018 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5019
<> 144:ef7eb2e8f9f7 5020 /* Configure the trigger prescaler, filter, and polarity */
<> 144:ef7eb2e8f9f7 5021 switch (sSlaveConfig->InputTrigger)
<> 144:ef7eb2e8f9f7 5022 {
<> 144:ef7eb2e8f9f7 5023 case TIM_TS_ETRF:
<> 144:ef7eb2e8f9f7 5024 {
<> 144:ef7eb2e8f9f7 5025 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5026 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5027 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<> 144:ef7eb2e8f9f7 5028 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5029 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5030 /* Configure the ETR Trigger source */
<> 144:ef7eb2e8f9f7 5031 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 5032 sSlaveConfig->TriggerPrescaler,
<> 144:ef7eb2e8f9f7 5033 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5034 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5035 }
<> 144:ef7eb2e8f9f7 5036 break;
<> 144:ef7eb2e8f9f7 5037
<> 144:ef7eb2e8f9f7 5038 case TIM_TS_TI1F_ED:
<> 144:ef7eb2e8f9f7 5039 {
<> 144:ef7eb2e8f9f7 5040 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5041 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5042 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5043
<> 144:ef7eb2e8f9f7 5044 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5045 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 5046 htim->Instance->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5047 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 5048
<> 144:ef7eb2e8f9f7 5049 /* Set the filter */
<> 144:ef7eb2e8f9f7 5050 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 156:95d6b41a828b 5051 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
<> 144:ef7eb2e8f9f7 5052
<> 144:ef7eb2e8f9f7 5053 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5054 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5055 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5056
<> 144:ef7eb2e8f9f7 5057 }
<> 144:ef7eb2e8f9f7 5058 break;
<> 144:ef7eb2e8f9f7 5059
<> 144:ef7eb2e8f9f7 5060 case TIM_TS_TI1FP1:
<> 144:ef7eb2e8f9f7 5061 {
<> 144:ef7eb2e8f9f7 5062 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5063 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5064 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5065 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5066
<> 144:ef7eb2e8f9f7 5067 /* Configure TI1 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5068 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5069 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5070 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5071 }
<> 144:ef7eb2e8f9f7 5072 break;
<> 144:ef7eb2e8f9f7 5073
<> 144:ef7eb2e8f9f7 5074 case TIM_TS_TI2FP2:
<> 144:ef7eb2e8f9f7 5075 {
<> 144:ef7eb2e8f9f7 5076 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5077 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5078 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5079 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5080
<> 144:ef7eb2e8f9f7 5081 /* Configure TI2 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5082 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5083 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5084 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5085 }
<> 144:ef7eb2e8f9f7 5086 break;
<> 144:ef7eb2e8f9f7 5087
<> 144:ef7eb2e8f9f7 5088 case TIM_TS_ITR0:
<> 144:ef7eb2e8f9f7 5089 {
<> 144:ef7eb2e8f9f7 5090 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5091 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5092 }
<> 144:ef7eb2e8f9f7 5093 break;
<> 144:ef7eb2e8f9f7 5094
<> 144:ef7eb2e8f9f7 5095 case TIM_TS_ITR1:
<> 144:ef7eb2e8f9f7 5096 {
<> 144:ef7eb2e8f9f7 5097 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5098 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5099 }
<> 144:ef7eb2e8f9f7 5100 break;
<> 144:ef7eb2e8f9f7 5101
<> 144:ef7eb2e8f9f7 5102 case TIM_TS_ITR2:
<> 144:ef7eb2e8f9f7 5103 {
<> 144:ef7eb2e8f9f7 5104 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5105 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5106 }
<> 144:ef7eb2e8f9f7 5107 break;
<> 144:ef7eb2e8f9f7 5108
<> 144:ef7eb2e8f9f7 5109 case TIM_TS_ITR3:
<> 144:ef7eb2e8f9f7 5110 {
<> 144:ef7eb2e8f9f7 5111 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5112 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5113 }
<> 144:ef7eb2e8f9f7 5114 break;
<> 144:ef7eb2e8f9f7 5115
<> 144:ef7eb2e8f9f7 5116 default:
<> 144:ef7eb2e8f9f7 5117 break;
<> 144:ef7eb2e8f9f7 5118 }
<> 144:ef7eb2e8f9f7 5119 }
<> 144:ef7eb2e8f9f7 5120
<> 144:ef7eb2e8f9f7 5121 /**
<> 144:ef7eb2e8f9f7 5122 * @brief Configure the TI1 as Input.
<> 144:ef7eb2e8f9f7 5123 * @param TIMx to select the TIM peripheral.
Anna Bridge 180:96ed750bd169 5124 * @param TIM_ICPolarity The Input Polarity.
<> 144:ef7eb2e8f9f7 5125 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5126 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5127 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5128 * @arg TIM_ICPOLARITY_BOTHEDGE
Anna Bridge 180:96ed750bd169 5129 * @param TIM_ICSelection specifies the input to be used.
<> 144:ef7eb2e8f9f7 5130 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5131 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5132 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5133 * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
Anna Bridge 180:96ed750bd169 5134 * @param TIM_ICFilter Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5135 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5136 * @retval None
<> 144:ef7eb2e8f9f7 5137 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<> 144:ef7eb2e8f9f7 5138 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5139 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5140 */
<> 144:ef7eb2e8f9f7 5141 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5142 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5143 {
<> 156:95d6b41a828b 5144 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5145 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5146
<> 144:ef7eb2e8f9f7 5147 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5148 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5149 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5150 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5151
<> 144:ef7eb2e8f9f7 5152 /* Select the Input */
<> 144:ef7eb2e8f9f7 5153 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 5154 {
<> 144:ef7eb2e8f9f7 5155 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 5156 tmpccmr1 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5157 }
<> 144:ef7eb2e8f9f7 5158 else
<> 144:ef7eb2e8f9f7 5159 {
<> 144:ef7eb2e8f9f7 5160 tmpccmr1 |= TIM_CCMR1_CC1S_0;
<> 144:ef7eb2e8f9f7 5161 }
<> 144:ef7eb2e8f9f7 5162
<> 144:ef7eb2e8f9f7 5163 /* Set the filter */
<> 144:ef7eb2e8f9f7 5164 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 156:95d6b41a828b 5165 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
<> 144:ef7eb2e8f9f7 5166
<> 144:ef7eb2e8f9f7 5167 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5168 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5169 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
<> 144:ef7eb2e8f9f7 5170
<> 144:ef7eb2e8f9f7 5171 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5172 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5173 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5174 }
<> 144:ef7eb2e8f9f7 5175
<> 144:ef7eb2e8f9f7 5176 /**
<> 144:ef7eb2e8f9f7 5177 * @brief Configure the Polarity and Filter for TI1.
<> 144:ef7eb2e8f9f7 5178 * @param TIMx to select the TIM peripheral.
Anna Bridge 180:96ed750bd169 5179 * @param TIM_ICPolarity The Input Polarity.
<> 144:ef7eb2e8f9f7 5180 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5181 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5182 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5183 * @arg TIM_ICPOLARITY_BOTHEDGE
Anna Bridge 180:96ed750bd169 5184 * @param TIM_ICFilter Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5185 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5186 * @retval None
<> 144:ef7eb2e8f9f7 5187 */
<> 144:ef7eb2e8f9f7 5188 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5189 {
<> 156:95d6b41a828b 5190 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5191 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5192
<> 144:ef7eb2e8f9f7 5193 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5194 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5195 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5196 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5197
<> 144:ef7eb2e8f9f7 5198 /* Set the filter */
<> 144:ef7eb2e8f9f7 5199 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 156:95d6b41a828b 5200 tmpccmr1 |= (TIM_ICFilter << 4U);
<> 144:ef7eb2e8f9f7 5201
<> 144:ef7eb2e8f9f7 5202 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5203 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5204 tmpccer |= TIM_ICPolarity;
<> 144:ef7eb2e8f9f7 5205
<> 144:ef7eb2e8f9f7 5206 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5207 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5208 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5209 }
<> 144:ef7eb2e8f9f7 5210
<> 144:ef7eb2e8f9f7 5211 /**
<> 144:ef7eb2e8f9f7 5212 * @brief Configure the TI2 as Input.
<> 144:ef7eb2e8f9f7 5213 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 5214 * @param TIM_ICPolarity The Input Polarity.
<> 144:ef7eb2e8f9f7 5215 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5216 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5217 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5218 * @arg TIM_ICPOLARITY_BOTHEDGE
Anna Bridge 180:96ed750bd169 5219 * @param TIM_ICSelection specifies the input to be used.
<> 144:ef7eb2e8f9f7 5220 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5221 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5222 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5223 * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
Anna Bridge 180:96ed750bd169 5224 * @param TIM_ICFilter Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5225 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5226 * @retval None
<> 144:ef7eb2e8f9f7 5227 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<> 144:ef7eb2e8f9f7 5228 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5229 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5230 */
<> 144:ef7eb2e8f9f7 5231 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5232 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5233 {
<> 156:95d6b41a828b 5234 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5235 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5236
<> 144:ef7eb2e8f9f7 5237 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5238 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5239 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5240 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5241
<> 144:ef7eb2e8f9f7 5242 /* Select the Input */
<> 144:ef7eb2e8f9f7 5243 tmpccmr1 &= ~TIM_CCMR1_CC2S;
<> 156:95d6b41a828b 5244 tmpccmr1 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 5245
<> 144:ef7eb2e8f9f7 5246 /* Set the filter */
<> 144:ef7eb2e8f9f7 5247 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 156:95d6b41a828b 5248 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 5249
<> 144:ef7eb2e8f9f7 5250 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5251 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 156:95d6b41a828b 5252 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
<> 144:ef7eb2e8f9f7 5253
<> 144:ef7eb2e8f9f7 5254 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5255 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5256 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5257 }
<> 144:ef7eb2e8f9f7 5258
<> 144:ef7eb2e8f9f7 5259 /**
<> 144:ef7eb2e8f9f7 5260 * @brief Configure the Polarity and Filter for TI2.
<> 144:ef7eb2e8f9f7 5261 * @param TIMx to select the TIM peripheral.
Anna Bridge 180:96ed750bd169 5262 * @param TIM_ICPolarity The Input Polarity.
<> 144:ef7eb2e8f9f7 5263 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5264 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5265 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5266 * @arg TIM_ICPOLARITY_BOTHEDGE
Anna Bridge 180:96ed750bd169 5267 * @param TIM_ICFilter Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5268 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5269 * @retval None
<> 144:ef7eb2e8f9f7 5270 */
<> 144:ef7eb2e8f9f7 5271 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5272 {
<> 156:95d6b41a828b 5273 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5274 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5275
<> 144:ef7eb2e8f9f7 5276 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5277 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5278 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5279 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5280
<> 144:ef7eb2e8f9f7 5281 /* Set the filter */
<> 144:ef7eb2e8f9f7 5282 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 156:95d6b41a828b 5283 tmpccmr1 |= (TIM_ICFilter << 12U);
<> 144:ef7eb2e8f9f7 5284
<> 144:ef7eb2e8f9f7 5285 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5286 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 156:95d6b41a828b 5287 tmpccer |= (TIM_ICPolarity << 4U);
<> 144:ef7eb2e8f9f7 5288
<> 144:ef7eb2e8f9f7 5289 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5290 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5291 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5292 }
<> 144:ef7eb2e8f9f7 5293
<> 144:ef7eb2e8f9f7 5294 /**
<> 144:ef7eb2e8f9f7 5295 * @brief Configure the TI3 as Input.
<> 144:ef7eb2e8f9f7 5296 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 5297 * @param TIM_ICPolarity The Input Polarity.
<> 144:ef7eb2e8f9f7 5298 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5299 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5300 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5301 * @arg TIM_ICPOLARITY_BOTHEDGE
Anna Bridge 180:96ed750bd169 5302 * @param TIM_ICSelection specifies the input to be used.
<> 144:ef7eb2e8f9f7 5303 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5304 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5305 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5306 * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
Anna Bridge 180:96ed750bd169 5307 * @param TIM_ICFilter Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5308 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5309 * @retval None
<> 144:ef7eb2e8f9f7 5310 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<> 144:ef7eb2e8f9f7 5311 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5312 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5313 */
<> 144:ef7eb2e8f9f7 5314 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5315 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5316 {
<> 156:95d6b41a828b 5317 uint32_t tmpccmr2 = 0U;
<> 156:95d6b41a828b 5318 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5319
<> 144:ef7eb2e8f9f7 5320 /* Disable the Channel 3: Reset the CC3E Bit */
<> 144:ef7eb2e8f9f7 5321 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 5322 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5323 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5324
<> 144:ef7eb2e8f9f7 5325 /* Select the Input */
<> 144:ef7eb2e8f9f7 5326 tmpccmr2 &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 5327 tmpccmr2 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5328
<> 144:ef7eb2e8f9f7 5329 /* Set the filter */
<> 144:ef7eb2e8f9f7 5330 tmpccmr2 &= ~TIM_CCMR2_IC3F;
<> 156:95d6b41a828b 5331 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
<> 144:ef7eb2e8f9f7 5332
<> 144:ef7eb2e8f9f7 5333 /* Select the Polarity and set the CC3E Bit */
<> 144:ef7eb2e8f9f7 5334 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
<> 156:95d6b41a828b 5335 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
<> 144:ef7eb2e8f9f7 5336
<> 144:ef7eb2e8f9f7 5337 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5338 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5339 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5340 }
<> 144:ef7eb2e8f9f7 5341
<> 144:ef7eb2e8f9f7 5342 /**
<> 144:ef7eb2e8f9f7 5343 * @brief Configure the TI4 as Input.
<> 144:ef7eb2e8f9f7 5344 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 5345 * @param TIM_ICPolarity The Input Polarity.
<> 144:ef7eb2e8f9f7 5346 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5347 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5348 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5349 * @arg TIM_ICPOLARITY_BOTHEDGE
Anna Bridge 180:96ed750bd169 5350 * @param TIM_ICSelection specifies the input to be used.
<> 144:ef7eb2e8f9f7 5351 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5352 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5353 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5354 * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
Anna Bridge 180:96ed750bd169 5355 * @param TIM_ICFilter Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5356 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5357 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<> 144:ef7eb2e8f9f7 5358 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5359 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5360 * @retval None
<> 144:ef7eb2e8f9f7 5361 */
<> 144:ef7eb2e8f9f7 5362 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5363 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5364 {
<> 156:95d6b41a828b 5365 uint32_t tmpccmr2 = 0U;
<> 156:95d6b41a828b 5366 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5367
<> 144:ef7eb2e8f9f7 5368 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 5369 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 5370 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5371 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5372
<> 144:ef7eb2e8f9f7 5373 /* Select the Input */
<> 144:ef7eb2e8f9f7 5374 tmpccmr2 &= ~TIM_CCMR2_CC4S;
<> 156:95d6b41a828b 5375 tmpccmr2 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 5376
<> 144:ef7eb2e8f9f7 5377 /* Set the filter */
<> 144:ef7eb2e8f9f7 5378 tmpccmr2 &= ~TIM_CCMR2_IC4F;
<> 156:95d6b41a828b 5379 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
<> 144:ef7eb2e8f9f7 5380
<> 144:ef7eb2e8f9f7 5381 /* Select the Polarity and set the CC4E Bit */
<> 144:ef7eb2e8f9f7 5382 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
<> 156:95d6b41a828b 5383 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
<> 144:ef7eb2e8f9f7 5384
<> 144:ef7eb2e8f9f7 5385 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5386 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5387 TIMx->CCER = tmpccer ;
<> 144:ef7eb2e8f9f7 5388 }
<> 144:ef7eb2e8f9f7 5389
<> 144:ef7eb2e8f9f7 5390 /**
<> 144:ef7eb2e8f9f7 5391 * @brief Selects the Input Trigger source
<> 144:ef7eb2e8f9f7 5392 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 5393 * @param InputTriggerSource The Input Trigger source.
<> 144:ef7eb2e8f9f7 5394 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5395 * @arg TIM_TS_ITR0 : Internal Trigger 0
<> 144:ef7eb2e8f9f7 5396 * @arg TIM_TS_ITR1 : Internal Trigger 1
<> 144:ef7eb2e8f9f7 5397 * @arg TIM_TS_ITR2 : Internal Trigger 2
<> 144:ef7eb2e8f9f7 5398 * @arg TIM_TS_ITR3 : Internal Trigger 3
<> 144:ef7eb2e8f9f7 5399 * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
<> 144:ef7eb2e8f9f7 5400 * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
<> 144:ef7eb2e8f9f7 5401 * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
<> 144:ef7eb2e8f9f7 5402 * @arg TIM_TS_ETRF : External Trigger input
<> 144:ef7eb2e8f9f7 5403 * @retval None
<> 144:ef7eb2e8f9f7 5404 */
<> 144:ef7eb2e8f9f7 5405 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<> 144:ef7eb2e8f9f7 5406 {
<> 156:95d6b41a828b 5407 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 5408
<> 144:ef7eb2e8f9f7 5409 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 5410 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5411 /* Reset the TS Bits */
<> 144:ef7eb2e8f9f7 5412 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 5413 /* Set the Input Trigger source and the slave mode*/
<> 144:ef7eb2e8f9f7 5414 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
<> 144:ef7eb2e8f9f7 5415 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5416 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5417 }
<> 144:ef7eb2e8f9f7 5418 /**
<> 144:ef7eb2e8f9f7 5419 * @brief Configures the TIMx External Trigger (ETR).
<> 144:ef7eb2e8f9f7 5420 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 5421 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
<> 144:ef7eb2e8f9f7 5422 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5423 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
<> 144:ef7eb2e8f9f7 5424 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
<> 144:ef7eb2e8f9f7 5425 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
<> 144:ef7eb2e8f9f7 5426 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
Anna Bridge 180:96ed750bd169 5427 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
<> 144:ef7eb2e8f9f7 5428 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5429 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
<> 144:ef7eb2e8f9f7 5430 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
Anna Bridge 180:96ed750bd169 5431 * @param ExtTRGFilter External Trigger Filter.
<> 144:ef7eb2e8f9f7 5432 * This parameter must be a value between 0x00 and 0x0F
<> 144:ef7eb2e8f9f7 5433 * @retval None
<> 144:ef7eb2e8f9f7 5434 */
<> 144:ef7eb2e8f9f7 5435 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 5436 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<> 144:ef7eb2e8f9f7 5437 {
<> 156:95d6b41a828b 5438 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 5439
<> 144:ef7eb2e8f9f7 5440 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5441
<> 144:ef7eb2e8f9f7 5442 /* Reset the ETR Bits */
<> 144:ef7eb2e8f9f7 5443 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 5444
<> 144:ef7eb2e8f9f7 5445 /* Set the Prescaler, the Filter value and the Polarity */
<> 156:95d6b41a828b 5446 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
<> 144:ef7eb2e8f9f7 5447
<> 144:ef7eb2e8f9f7 5448 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5449 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5450 }
<> 144:ef7eb2e8f9f7 5451
<> 144:ef7eb2e8f9f7 5452 /**
<> 144:ef7eb2e8f9f7 5453 * @brief Enables or disables the TIM Capture Compare Channel x.
<> 144:ef7eb2e8f9f7 5454 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 5455 * @param Channel specifies the TIM Channel
<> 144:ef7eb2e8f9f7 5456 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5457 * @arg TIM_CHANNEL_1 : TIM Channel 1
<> 144:ef7eb2e8f9f7 5458 * @arg TIM_CHANNEL_2 : TIM Channel 2
<> 144:ef7eb2e8f9f7 5459 * @arg TIM_CHANNEL_3 : TIM Channel 3
<> 144:ef7eb2e8f9f7 5460 * @arg TIM_CHANNEL_4 : TIM Channel 4
Anna Bridge 180:96ed750bd169 5461 * @param ChannelState specifies the TIM Channel CCxE bit new state.
<> 144:ef7eb2e8f9f7 5462 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<> 144:ef7eb2e8f9f7 5463 * @retval None
<> 144:ef7eb2e8f9f7 5464 */
<> 144:ef7eb2e8f9f7 5465 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<> 144:ef7eb2e8f9f7 5466 {
<> 156:95d6b41a828b 5467 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 5468
<> 144:ef7eb2e8f9f7 5469 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5470 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 5471 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 5472
<> 144:ef7eb2e8f9f7 5473 tmp = TIM_CCER_CC1E << Channel;
<> 144:ef7eb2e8f9f7 5474
<> 144:ef7eb2e8f9f7 5475 /* Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5476 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 5477
<> 144:ef7eb2e8f9f7 5478 /* Set or reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5479 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
<> 144:ef7eb2e8f9f7 5480 }
<> 144:ef7eb2e8f9f7 5481
<> 144:ef7eb2e8f9f7 5482
<> 144:ef7eb2e8f9f7 5483 /**
<> 144:ef7eb2e8f9f7 5484 * @}
<> 144:ef7eb2e8f9f7 5485 */
<> 144:ef7eb2e8f9f7 5486
<> 144:ef7eb2e8f9f7 5487 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 5488 /**
<> 144:ef7eb2e8f9f7 5489 * @}
<> 144:ef7eb2e8f9f7 5490 */
<> 144:ef7eb2e8f9f7 5491
<> 144:ef7eb2e8f9f7 5492 /**
<> 144:ef7eb2e8f9f7 5493 * @}
<> 144:ef7eb2e8f9f7 5494 */
<> 144:ef7eb2e8f9f7 5495 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/