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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_tim.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer (TIM) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Base Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Base Start
<> 144:ef7eb2e8f9f7 12 * + Time Base Start Interruption
<> 144:ef7eb2e8f9f7 13 * + Time Base Start DMA
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Initialization
<> 144:ef7eb2e8f9f7 15 * + Time Output Compare/PWM Channel Configuration
<> 144:ef7eb2e8f9f7 16 * + Time Output Compare/PWM Start
<> 144:ef7eb2e8f9f7 17 * + Time Output Compare/PWM Start Interruption
<> 144:ef7eb2e8f9f7 18 * + Time Output Compare/PWM Start DMA
<> 144:ef7eb2e8f9f7 19 * + Time Input Capture Initialization
<> 144:ef7eb2e8f9f7 20 * + Time Input Capture Channel Configuration
<> 144:ef7eb2e8f9f7 21 * + Time Input Capture Start
<> 144:ef7eb2e8f9f7 22 * + Time Input Capture Start Interruption
<> 144:ef7eb2e8f9f7 23 * + Time Input Capture Start DMA
<> 144:ef7eb2e8f9f7 24 * + Time One Pulse Initialization
<> 144:ef7eb2e8f9f7 25 * + Time One Pulse Channel Configuration
<> 144:ef7eb2e8f9f7 26 * + Time One Pulse Start
<> 144:ef7eb2e8f9f7 27 * + Time Encoder Interface Initialization
<> 144:ef7eb2e8f9f7 28 * + Time Encoder Interface Start
<> 144:ef7eb2e8f9f7 29 * + Time Encoder Interface Start Interruption
<> 144:ef7eb2e8f9f7 30 * + Time Encoder Interface Start DMA
<> 144:ef7eb2e8f9f7 31 * + Commutation Event configuration with Interruption and DMA
<> 144:ef7eb2e8f9f7 32 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 33 * + Time External Clock configuration
<> 144:ef7eb2e8f9f7 34 @verbatim
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 ##### TIMER Generic features #####
<> 144:ef7eb2e8f9f7 37 ==============================================================================
<> 144:ef7eb2e8f9f7 38 [..] The Timer features include:
<> 144:ef7eb2e8f9f7 39 (#) 16-bit up, down, up/down auto-reload counter.
<> 144:ef7eb2e8f9f7 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<> 144:ef7eb2e8f9f7 41 counter clock frequency either by any factor between 1 and 65536.
<> 144:ef7eb2e8f9f7 42 (#) Up to 4 independent channels for:
<> 144:ef7eb2e8f9f7 43 (++) Input Capture
<> 144:ef7eb2e8f9f7 44 (++) Output Compare
<> 144:ef7eb2e8f9f7 45 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 46 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 49 ==============================================================================
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 52 depending from feature used :
<> 144:ef7eb2e8f9f7 53 (++) Time Base : HAL_TIM_Base_MspInit()
<> 144:ef7eb2e8f9f7 54 (++) Input Capture : HAL_TIM_IC_MspInit()
<> 144:ef7eb2e8f9f7 55 (++) Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 62 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 63 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 64 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 68 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 70 any start function.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 73 Initialization function of this driver:
<> 144:ef7eb2e8f9f7 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<> 144:ef7eb2e8f9f7 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<> 144:ef7eb2e8f9f7 76 Output Compare signal.
<> 144:ef7eb2e8f9f7 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<> 144:ef7eb2e8f9f7 78 PWM signal.
<> 144:ef7eb2e8f9f7 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<> 144:ef7eb2e8f9f7 80 external signal.
<> 144:ef7eb2e8f9f7 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<> 144:ef7eb2e8f9f7 82 in One Pulse Mode.
<> 144:ef7eb2e8f9f7 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<> 144:ef7eb2e8f9f7 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<> 144:ef7eb2e8f9f7 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<> 144:ef7eb2e8f9f7 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<> 144:ef7eb2e8f9f7 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<> 144:ef7eb2e8f9f7 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<> 144:ef7eb2e8f9f7 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (#) The DMA Burst is managed with the two following functions:
<> 144:ef7eb2e8f9f7 94 HAL_TIM_DMABurst_WriteStart()
<> 144:ef7eb2e8f9f7 95 HAL_TIM_DMABurst_ReadStart()
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup TIM TIM
<> 144:ef7eb2e8f9f7 136 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @defgroup TIM_Private_Functions TIM_Private_Functions
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 152 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 153 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 156 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 159 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 161 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 162 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<> 144:ef7eb2e8f9f7 163 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 164 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 165 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 166 TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /** @defgroup TIM_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<> 144:ef7eb2e8f9f7 179 * @brief Time Base functions
<> 144:ef7eb2e8f9f7 180 *
<> 144:ef7eb2e8f9f7 181 @verbatim
<> 144:ef7eb2e8f9f7 182 ==============================================================================
<> 144:ef7eb2e8f9f7 183 ##### Time Base functions #####
<> 144:ef7eb2e8f9f7 184 ==============================================================================
<> 144:ef7eb2e8f9f7 185 [..]
<> 144:ef7eb2e8f9f7 186 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 187 (+) Initialize and configure the TIM base.
<> 144:ef7eb2e8f9f7 188 (+) De-initialize the TIM base.
<> 144:ef7eb2e8f9f7 189 (+) Start the Time Base.
<> 144:ef7eb2e8f9f7 190 (+) Stop the Time Base.
<> 144:ef7eb2e8f9f7 191 (+) Start the Time Base and enable interrupt.
<> 144:ef7eb2e8f9f7 192 (+) Stop the Time Base and disable interrupt.
<> 144:ef7eb2e8f9f7 193 (+) Start the Time Base and enable DMA transfer.
<> 144:ef7eb2e8f9f7 194 (+) Stop the Time Base and disable DMA transfer.
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 @endverbatim
<> 144:ef7eb2e8f9f7 197 * @{
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @brief Initializes the TIM Time base Unit according to the specified
<> 144:ef7eb2e8f9f7 201 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 202 * @param htim : TIM Base handle
<> 144:ef7eb2e8f9f7 203 * @retval HAL status
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 208 if(htim == NULL)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Check the parameters */
<> 144:ef7eb2e8f9f7 214 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 215 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 216 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 217 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 222 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 225 HAL_TIM_Base_MspInit(htim);
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 229 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Set the Time Base configuration */
<> 144:ef7eb2e8f9f7 232 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 235 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 return HAL_OK;
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief DeInitializes the TIM Base peripheral
<> 144:ef7eb2e8f9f7 242 * @param htim : TIM Base handle
<> 144:ef7eb2e8f9f7 243 * @retval HAL status
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 /* Check the parameters */
<> 144:ef7eb2e8f9f7 248 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 253 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 256 HAL_TIM_Base_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Change TIM state */
<> 144:ef7eb2e8f9f7 259 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Release Lock */
<> 144:ef7eb2e8f9f7 262 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 return HAL_OK;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @brief Initializes the TIM Base MSP.
<> 144:ef7eb2e8f9f7 269 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 270 * @retval None
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 275 UNUSED(htim);
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 278 the HAL_TIM_Base_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @brief DeInitializes TIM Base MSP.
<> 144:ef7eb2e8f9f7 284 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 285 * @retval None
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 290 UNUSED(htim);
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 293 the HAL_TIM_Base_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief Starts the TIM Base generation.
<> 144:ef7eb2e8f9f7 300 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 301 * @retval HAL status
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* Check the parameters */
<> 144:ef7eb2e8f9f7 306 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 309 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 312 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 315 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Return function status */
<> 144:ef7eb2e8f9f7 318 return HAL_OK;
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @brief Stops the TIM Base generation.
<> 144:ef7eb2e8f9f7 323 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 324 * @retval HAL status
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Check the parameters */
<> 144:ef7eb2e8f9f7 329 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 332 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 335 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 338 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Return function status */
<> 144:ef7eb2e8f9f7 341 return HAL_OK;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Starts the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 346 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 347 * @retval HAL status
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 /* Check the parameters */
<> 144:ef7eb2e8f9f7 352 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Enable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 355 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 358 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Return function status */
<> 144:ef7eb2e8f9f7 361 return HAL_OK;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @brief Stops the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 366 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 367 * @retval HAL status
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 /* Check the parameters */
<> 144:ef7eb2e8f9f7 372 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 373 /* Disable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 374 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 377 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Return function status */
<> 144:ef7eb2e8f9f7 380 return HAL_OK;
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief Starts the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 385 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 386 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 387 * @param Length : The length of data to be transferred from memory to peripheral.
<> 144:ef7eb2e8f9f7 388 * @retval HAL status
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 /* Check the parameters */
<> 144:ef7eb2e8f9f7 393 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 if((pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 else
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 411 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 414 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 417 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Enable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 420 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 423 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Return function status */
<> 144:ef7eb2e8f9f7 426 return HAL_OK;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Stops the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 431 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 432 * @retval HAL status
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 /* Check the parameters */
<> 144:ef7eb2e8f9f7 437 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 440 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 443 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Change the htim state */
<> 144:ef7eb2e8f9f7 446 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Return function status */
<> 144:ef7eb2e8f9f7 449 return HAL_OK;
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @}
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<> 144:ef7eb2e8f9f7 457 * @brief Time Output Compare functions
<> 144:ef7eb2e8f9f7 458 *
<> 144:ef7eb2e8f9f7 459 @verbatim
<> 144:ef7eb2e8f9f7 460 ==============================================================================
<> 144:ef7eb2e8f9f7 461 ##### Time Output Compare functions #####
<> 144:ef7eb2e8f9f7 462 ==============================================================================
<> 144:ef7eb2e8f9f7 463 [..]
<> 144:ef7eb2e8f9f7 464 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 465 (+) Initialize and configure the TIM Output Compare.
<> 144:ef7eb2e8f9f7 466 (+) De-initialize the TIM Output Compare.
<> 144:ef7eb2e8f9f7 467 (+) Start the Time Output Compare.
<> 144:ef7eb2e8f9f7 468 (+) Stop the Time Output Compare.
<> 144:ef7eb2e8f9f7 469 (+) Start the Time Output Compare and enable interrupt.
<> 144:ef7eb2e8f9f7 470 (+) Stop the Time Output Compare and disable interrupt.
<> 144:ef7eb2e8f9f7 471 (+) Start the Time Output Compare and enable DMA transfer.
<> 144:ef7eb2e8f9f7 472 (+) Stop the Time Output Compare and disable DMA transfer.
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 @endverbatim
<> 144:ef7eb2e8f9f7 475 * @{
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Initializes the TIM Output Compare according to the specified
<> 144:ef7eb2e8f9f7 479 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 480 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 481 * @retval HAL status
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 486 if(htim == NULL)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Check the parameters */
<> 144:ef7eb2e8f9f7 492 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 493 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 494 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 495 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 500 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 503 HAL_TIM_OC_MspInit(htim);
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 507 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Init the base time for the Output Compare */
<> 144:ef7eb2e8f9f7 510 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 513 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 return HAL_OK;
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 520 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 521 * @retval HAL status
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 /* Check the parameters */
<> 144:ef7eb2e8f9f7 526 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 531 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 534 HAL_TIM_OC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Change TIM state */
<> 144:ef7eb2e8f9f7 537 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Release Lock */
<> 144:ef7eb2e8f9f7 540 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 return HAL_OK;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @brief Initializes the TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 547 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 548 * @retval None
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 553 UNUSED(htim);
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 556 the HAL_TIM_OC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @brief DeInitializes TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 562 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 563 * @retval None
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 568 UNUSED(htim);
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 571 the HAL_TIM_OC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /**
<> 144:ef7eb2e8f9f7 576 * @brief Starts the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 577 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 578 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 579 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 580 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 581 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 582 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 583 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 584 * @retval HAL status
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 /* Check the parameters */
<> 144:ef7eb2e8f9f7 589 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 592 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 /* Enable the main output */
<> 144:ef7eb2e8f9f7 597 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 601 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Return function status */
<> 144:ef7eb2e8f9f7 604 return HAL_OK;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @brief Stops the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 609 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 610 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 611 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 616 * @retval HAL status
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 /* Check the parameters */
<> 144:ef7eb2e8f9f7 621 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 624 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 629 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 633 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Return function status */
<> 144:ef7eb2e8f9f7 636 return HAL_OK;
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 641 * @param htim : TIM OC handle
<> 144:ef7eb2e8f9f7 642 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 643 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 644 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 645 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 646 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 647 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 648 * @retval HAL status
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 /* Check the parameters */
<> 144:ef7eb2e8f9f7 653 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 switch (Channel)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 660 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662 break;
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 667 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669 break;
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 674 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 break;
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 681 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683 break;
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 default:
<> 144:ef7eb2e8f9f7 686 break;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 690 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 /* Enable the main output */
<> 144:ef7eb2e8f9f7 695 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 699 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Return function status */
<> 144:ef7eb2e8f9f7 702 return HAL_OK;
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 707 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 708 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 709 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 710 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 711 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 712 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 713 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 714 * @retval HAL status
<> 144:ef7eb2e8f9f7 715 */
<> 144:ef7eb2e8f9f7 716 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 /* Check the parameters */
<> 144:ef7eb2e8f9f7 719 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 switch (Channel)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 726 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 break;
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 733 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735 break;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 740 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742 break;
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 745 {
<> 144:ef7eb2e8f9f7 746 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 747 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749 break;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 default:
<> 144:ef7eb2e8f9f7 752 break;
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 756 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 761 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 765 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Return function status */
<> 144:ef7eb2e8f9f7 768 return HAL_OK;
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /**
<> 144:ef7eb2e8f9f7 772 * @brief Starts the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 773 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 774 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 775 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 776 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 777 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 778 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 779 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 780 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 781 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 782 * @retval HAL status
<> 144:ef7eb2e8f9f7 783 */
<> 144:ef7eb2e8f9f7 784 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 /* Check the parameters */
<> 144:ef7eb2e8f9f7 787 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 794 {
<> 156:95d6b41a828b 795 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799 else
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804 switch (Channel)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 809 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 812 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 815 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 818 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 break;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 825 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 828 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 831 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 834 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836 break;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 841 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 844 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 847 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 850 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 851 }
<> 144:ef7eb2e8f9f7 852 break;
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 855 {
<> 144:ef7eb2e8f9f7 856 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 857 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 860 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 863 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 866 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868 break;
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 default:
<> 144:ef7eb2e8f9f7 871 break;
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 875 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Enable the main output */
<> 144:ef7eb2e8f9f7 880 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 884 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Return function status */
<> 144:ef7eb2e8f9f7 887 return HAL_OK;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /**
<> 144:ef7eb2e8f9f7 891 * @brief Stops the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 892 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 893 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 894 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 895 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 896 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 897 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 898 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 899 * @retval HAL status
<> 144:ef7eb2e8f9f7 900 */
<> 144:ef7eb2e8f9f7 901 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 /* Check the parameters */
<> 144:ef7eb2e8f9f7 904 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 switch (Channel)
<> 144:ef7eb2e8f9f7 907 {
<> 144:ef7eb2e8f9f7 908 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913 break;
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 918 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920 break;
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 923 {
<> 144:ef7eb2e8f9f7 924 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 925 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927 break;
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 932 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934 break;
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 default:
<> 144:ef7eb2e8f9f7 937 break;
<> 144:ef7eb2e8f9f7 938 }
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 941 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 944 {
<> 144:ef7eb2e8f9f7 945 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 946 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 950 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Change the htim state */
<> 144:ef7eb2e8f9f7 953 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /* Return function status */
<> 144:ef7eb2e8f9f7 956 return HAL_OK;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /**
<> 144:ef7eb2e8f9f7 960 * @}
<> 144:ef7eb2e8f9f7 961 */
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<> 144:ef7eb2e8f9f7 964 * @brief Time PWM functions
<> 144:ef7eb2e8f9f7 965 *
<> 144:ef7eb2e8f9f7 966 @verbatim
<> 144:ef7eb2e8f9f7 967 ==============================================================================
<> 144:ef7eb2e8f9f7 968 ##### Time PWM functions #####
<> 144:ef7eb2e8f9f7 969 ==============================================================================
<> 144:ef7eb2e8f9f7 970 [..]
<> 144:ef7eb2e8f9f7 971 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 972 (+) Initialize and configure the TIM OPWM.
<> 144:ef7eb2e8f9f7 973 (+) De-initialize the TIM PWM.
<> 144:ef7eb2e8f9f7 974 (+) Start the Time PWM.
<> 144:ef7eb2e8f9f7 975 (+) Stop the Time PWM.
<> 144:ef7eb2e8f9f7 976 (+) Start the Time PWM and enable interrupt.
<> 144:ef7eb2e8f9f7 977 (+) Stop the Time PWM and disable interrupt.
<> 144:ef7eb2e8f9f7 978 (+) Start the Time PWM and enable DMA transfer.
<> 144:ef7eb2e8f9f7 979 (+) Stop the Time PWM and disable DMA transfer.
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 @endverbatim
<> 144:ef7eb2e8f9f7 982 * @{
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 /**
<> 144:ef7eb2e8f9f7 985 * @brief Initializes the TIM PWM Time Base according to the specified
<> 144:ef7eb2e8f9f7 986 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 987 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 988 * @retval HAL status
<> 144:ef7eb2e8f9f7 989 */
<> 144:ef7eb2e8f9f7 990 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 993 if(htim == NULL)
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* Check the parameters */
<> 144:ef7eb2e8f9f7 999 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1000 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1001 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 1002 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1005 {
<> 144:ef7eb2e8f9f7 1006 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1007 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1010 HAL_TIM_PWM_MspInit(htim);
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1014 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Init the base time for the PWM */
<> 144:ef7eb2e8f9f7 1017 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1020 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 return HAL_OK;
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /**
<> 144:ef7eb2e8f9f7 1026 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1027 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1028 * @retval HAL status
<> 144:ef7eb2e8f9f7 1029 */
<> 144:ef7eb2e8f9f7 1030 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1033 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1038 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1041 HAL_TIM_PWM_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1044 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* Release Lock */
<> 144:ef7eb2e8f9f7 1047 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 return HAL_OK;
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /**
<> 144:ef7eb2e8f9f7 1053 * @brief Initializes the TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1054 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1055 * @retval None
<> 144:ef7eb2e8f9f7 1056 */
<> 144:ef7eb2e8f9f7 1057 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1058 {
<> 144:ef7eb2e8f9f7 1059 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1060 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1063 the HAL_TIM_PWM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1064 */
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /**
<> 144:ef7eb2e8f9f7 1068 * @brief DeInitializes TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1069 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1070 * @retval None
<> 144:ef7eb2e8f9f7 1071 */
<> 144:ef7eb2e8f9f7 1072 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1075 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1078 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1079 */
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /**
<> 144:ef7eb2e8f9f7 1083 * @brief Starts the PWM signal generation.
<> 144:ef7eb2e8f9f7 1084 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1085 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1086 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1087 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1088 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1089 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1090 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1091 * @retval HAL status
<> 144:ef7eb2e8f9f7 1092 */
<> 144:ef7eb2e8f9f7 1093 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1094 {
<> 144:ef7eb2e8f9f7 1095 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1096 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1099 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1102 {
<> 144:ef7eb2e8f9f7 1103 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1104 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1108 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Return function status */
<> 144:ef7eb2e8f9f7 1111 return HAL_OK;
<> 144:ef7eb2e8f9f7 1112 }
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 /**
<> 144:ef7eb2e8f9f7 1115 * @brief Stops the PWM signal generation.
<> 144:ef7eb2e8f9f7 1116 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1117 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1118 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1119 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1120 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1121 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1122 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1123 * @retval HAL status
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1128 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1131 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1134 {
<> 144:ef7eb2e8f9f7 1135 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1136 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1137 }
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1140 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1143 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 /* Return function status */
<> 144:ef7eb2e8f9f7 1146 return HAL_OK;
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /**
<> 144:ef7eb2e8f9f7 1150 * @brief Starts the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1151 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1152 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1153 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1154 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1155 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1156 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1157 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1158 * @retval HAL status
<> 144:ef7eb2e8f9f7 1159 */
<> 144:ef7eb2e8f9f7 1160 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1161 {
<> 144:ef7eb2e8f9f7 1162 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1163 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 switch (Channel)
<> 144:ef7eb2e8f9f7 1166 {
<> 144:ef7eb2e8f9f7 1167 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1168 {
<> 144:ef7eb2e8f9f7 1169 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1170 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172 break;
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1175 {
<> 144:ef7eb2e8f9f7 1176 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1177 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1178 }
<> 144:ef7eb2e8f9f7 1179 break;
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1182 {
<> 144:ef7eb2e8f9f7 1183 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1184 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1185 }
<> 144:ef7eb2e8f9f7 1186 break;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1191 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1192 }
<> 144:ef7eb2e8f9f7 1193 break;
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 default:
<> 144:ef7eb2e8f9f7 1196 break;
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1200 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1203 {
<> 144:ef7eb2e8f9f7 1204 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1205 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1206 }
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1209 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Return function status */
<> 144:ef7eb2e8f9f7 1212 return HAL_OK;
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /**
<> 144:ef7eb2e8f9f7 1216 * @brief Stops the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1217 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1218 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1219 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1220 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1221 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1222 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1223 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1224 * @retval HAL status
<> 144:ef7eb2e8f9f7 1225 */
<> 144:ef7eb2e8f9f7 1226 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1227 {
<> 144:ef7eb2e8f9f7 1228 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1229 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 switch (Channel)
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1234 {
<> 144:ef7eb2e8f9f7 1235 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1236 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1237 }
<> 144:ef7eb2e8f9f7 1238 break;
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1243 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1244 }
<> 144:ef7eb2e8f9f7 1245 break;
<> 144:ef7eb2e8f9f7 1246
<> 144:ef7eb2e8f9f7 1247 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1250 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252 break;
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1255 {
<> 144:ef7eb2e8f9f7 1256 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1257 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1258 }
<> 144:ef7eb2e8f9f7 1259 break;
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 default:
<> 144:ef7eb2e8f9f7 1262 break;
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1266 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1269 {
<> 144:ef7eb2e8f9f7 1270 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1271 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1272 }
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1275 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /* Return function status */
<> 144:ef7eb2e8f9f7 1278 return HAL_OK;
<> 144:ef7eb2e8f9f7 1279 }
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /**
<> 144:ef7eb2e8f9f7 1282 * @brief Starts the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1283 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1284 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1285 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1286 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1287 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1288 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1289 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1290 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 1291 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1292 * @retval HAL status
<> 144:ef7eb2e8f9f7 1293 */
<> 144:ef7eb2e8f9f7 1294 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1297 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1300 {
<> 144:ef7eb2e8f9f7 1301 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1302 }
<> 144:ef7eb2e8f9f7 1303 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1304 {
<> 156:95d6b41a828b 1305 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1306 {
<> 144:ef7eb2e8f9f7 1307 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1308 }
<> 144:ef7eb2e8f9f7 1309 else
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1312 }
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314 switch (Channel)
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1319 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1322 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1325 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1328 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1329 }
<> 144:ef7eb2e8f9f7 1330 break;
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1333 {
<> 144:ef7eb2e8f9f7 1334 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1335 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1338 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1341 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1344 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1345 }
<> 144:ef7eb2e8f9f7 1346 break;
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1349 {
<> 144:ef7eb2e8f9f7 1350 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1351 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1354 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1357 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /* Enable the TIM Output Capture/Compare 3 request */
<> 144:ef7eb2e8f9f7 1360 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362 break;
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1365 {
<> 144:ef7eb2e8f9f7 1366 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1367 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1370 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1373 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1376 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378 break;
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 default:
<> 144:ef7eb2e8f9f7 1381 break;
<> 144:ef7eb2e8f9f7 1382 }
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1385 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1388 {
<> 144:ef7eb2e8f9f7 1389 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1390 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1391 }
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1394 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Return function status */
<> 144:ef7eb2e8f9f7 1397 return HAL_OK;
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /**
<> 144:ef7eb2e8f9f7 1401 * @brief Stops the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1402 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1403 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1404 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1405 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1406 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1407 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1408 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1409 * @retval HAL status
<> 144:ef7eb2e8f9f7 1410 */
<> 144:ef7eb2e8f9f7 1411 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1412 {
<> 144:ef7eb2e8f9f7 1413 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1414 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 switch (Channel)
<> 144:ef7eb2e8f9f7 1417 {
<> 144:ef7eb2e8f9f7 1418 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1419 {
<> 144:ef7eb2e8f9f7 1420 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1421 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1422 }
<> 144:ef7eb2e8f9f7 1423 break;
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1426 {
<> 144:ef7eb2e8f9f7 1427 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1428 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1429 }
<> 144:ef7eb2e8f9f7 1430 break;
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1433 {
<> 144:ef7eb2e8f9f7 1434 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1435 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1436 }
<> 144:ef7eb2e8f9f7 1437 break;
<> 144:ef7eb2e8f9f7 1438
<> 144:ef7eb2e8f9f7 1439 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1440 {
<> 144:ef7eb2e8f9f7 1441 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1442 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1443 }
<> 144:ef7eb2e8f9f7 1444 break;
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 default:
<> 144:ef7eb2e8f9f7 1447 break;
<> 144:ef7eb2e8f9f7 1448 }
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1451 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1452
<> 144:ef7eb2e8f9f7 1453 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1454 {
<> 144:ef7eb2e8f9f7 1455 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1456 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1457 }
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1460 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1463 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 /* Return function status */
<> 144:ef7eb2e8f9f7 1466 return HAL_OK;
<> 144:ef7eb2e8f9f7 1467 }
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 /**
<> 144:ef7eb2e8f9f7 1470 * @}
<> 144:ef7eb2e8f9f7 1471 */
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<> 144:ef7eb2e8f9f7 1474 * @brief Time Input Capture functions
<> 144:ef7eb2e8f9f7 1475 *
<> 144:ef7eb2e8f9f7 1476 @verbatim
<> 144:ef7eb2e8f9f7 1477 ==============================================================================
<> 144:ef7eb2e8f9f7 1478 ##### Time Input Capture functions #####
<> 144:ef7eb2e8f9f7 1479 ==============================================================================
<> 144:ef7eb2e8f9f7 1480 [..]
<> 144:ef7eb2e8f9f7 1481 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1482 (+) Initialize and configure the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1483 (+) De-initialize the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1484 (+) Start the Time Input Capture.
<> 144:ef7eb2e8f9f7 1485 (+) Stop the Time Input Capture.
<> 144:ef7eb2e8f9f7 1486 (+) Start the Time Input Capture and enable interrupt.
<> 144:ef7eb2e8f9f7 1487 (+) Stop the Time Input Capture and disable interrupt.
<> 144:ef7eb2e8f9f7 1488 (+) Start the Time Input Capture and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1489 (+) Stop the Time Input Capture and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 @endverbatim
<> 144:ef7eb2e8f9f7 1492 * @{
<> 144:ef7eb2e8f9f7 1493 */
<> 144:ef7eb2e8f9f7 1494 /**
<> 144:ef7eb2e8f9f7 1495 * @brief Initializes the TIM Input Capture Time base according to the specified
<> 144:ef7eb2e8f9f7 1496 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1497 * @param htim : TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1498 * @retval HAL status
<> 144:ef7eb2e8f9f7 1499 */
<> 144:ef7eb2e8f9f7 1500 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1501 {
<> 144:ef7eb2e8f9f7 1502 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1503 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1504 {
<> 144:ef7eb2e8f9f7 1505 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1506 }
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1509 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1510 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1511 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 1512 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1515 {
<> 144:ef7eb2e8f9f7 1516 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1517 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1520 HAL_TIM_IC_MspInit(htim);
<> 144:ef7eb2e8f9f7 1521 }
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1524 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1525
<> 144:ef7eb2e8f9f7 1526 /* Init the base time for the input capture */
<> 144:ef7eb2e8f9f7 1527 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1530 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 return HAL_OK;
<> 144:ef7eb2e8f9f7 1533 }
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 /**
<> 144:ef7eb2e8f9f7 1536 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1537 * @param htim : TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1538 * @retval HAL status
<> 144:ef7eb2e8f9f7 1539 */
<> 144:ef7eb2e8f9f7 1540 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1541 {
<> 144:ef7eb2e8f9f7 1542 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1543 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1548 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1551 HAL_TIM_IC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1554 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /* Release Lock */
<> 144:ef7eb2e8f9f7 1557 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1558
<> 144:ef7eb2e8f9f7 1559 return HAL_OK;
<> 144:ef7eb2e8f9f7 1560 }
<> 144:ef7eb2e8f9f7 1561
<> 144:ef7eb2e8f9f7 1562 /**
<> 144:ef7eb2e8f9f7 1563 * @brief Initializes the TIM Input Capture MSP.
<> 144:ef7eb2e8f9f7 1564 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1565 * @retval None
<> 144:ef7eb2e8f9f7 1566 */
<> 144:ef7eb2e8f9f7 1567 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1568 {
<> 144:ef7eb2e8f9f7 1569 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1570 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1573 the HAL_TIM_IC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1574 */
<> 144:ef7eb2e8f9f7 1575 }
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 /**
<> 144:ef7eb2e8f9f7 1578 * @brief DeInitializes TIM Input Capture MSP.
<> 144:ef7eb2e8f9f7 1579 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1580 * @retval None
<> 144:ef7eb2e8f9f7 1581 */
<> 144:ef7eb2e8f9f7 1582 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1583 {
<> 144:ef7eb2e8f9f7 1584 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1585 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1588 the HAL_TIM_IC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1589 */
<> 144:ef7eb2e8f9f7 1590 }
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 /**
<> 144:ef7eb2e8f9f7 1593 * @brief Starts the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1594 * @param htim : TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1595 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1596 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1597 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1598 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1599 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1600 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1601 * @retval HAL status
<> 144:ef7eb2e8f9f7 1602 */
<> 144:ef7eb2e8f9f7 1603 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1604 {
<> 144:ef7eb2e8f9f7 1605 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1606 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1609 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1610
<> 144:ef7eb2e8f9f7 1611 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1612 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /* Return function status */
<> 144:ef7eb2e8f9f7 1615 return HAL_OK;
<> 144:ef7eb2e8f9f7 1616 }
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 /**
<> 144:ef7eb2e8f9f7 1619 * @brief Stops the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1620 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1621 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1622 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1623 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1624 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1625 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1626 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1627 * @retval HAL status
<> 144:ef7eb2e8f9f7 1628 */
<> 144:ef7eb2e8f9f7 1629 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1630 {
<> 144:ef7eb2e8f9f7 1631 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1632 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1633
<> 144:ef7eb2e8f9f7 1634 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1635 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1638 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1639
<> 144:ef7eb2e8f9f7 1640 /* Return function status */
<> 144:ef7eb2e8f9f7 1641 return HAL_OK;
<> 144:ef7eb2e8f9f7 1642 }
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 /**
<> 144:ef7eb2e8f9f7 1645 * @brief Starts the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1646 * @param htim : TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1647 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1648 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1653 * @retval HAL status
<> 144:ef7eb2e8f9f7 1654 */
<> 144:ef7eb2e8f9f7 1655 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1656 {
<> 144:ef7eb2e8f9f7 1657 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1658 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 switch (Channel)
<> 144:ef7eb2e8f9f7 1661 {
<> 144:ef7eb2e8f9f7 1662 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1663 {
<> 144:ef7eb2e8f9f7 1664 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1666 }
<> 144:ef7eb2e8f9f7 1667 break;
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1670 {
<> 144:ef7eb2e8f9f7 1671 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1672 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1673 }
<> 144:ef7eb2e8f9f7 1674 break;
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1677 {
<> 144:ef7eb2e8f9f7 1678 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1679 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1680 }
<> 144:ef7eb2e8f9f7 1681 break;
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1684 {
<> 144:ef7eb2e8f9f7 1685 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1686 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1687 }
<> 144:ef7eb2e8f9f7 1688 break;
<> 144:ef7eb2e8f9f7 1689
<> 144:ef7eb2e8f9f7 1690 default:
<> 144:ef7eb2e8f9f7 1691 break;
<> 144:ef7eb2e8f9f7 1692 }
<> 144:ef7eb2e8f9f7 1693 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1694 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1697 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 /* Return function status */
<> 144:ef7eb2e8f9f7 1700 return HAL_OK;
<> 144:ef7eb2e8f9f7 1701 }
<> 144:ef7eb2e8f9f7 1702
<> 144:ef7eb2e8f9f7 1703 /**
<> 144:ef7eb2e8f9f7 1704 * @brief Stops the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1705 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1706 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1707 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1708 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1709 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1710 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1711 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1712 * @retval HAL status
<> 144:ef7eb2e8f9f7 1713 */
<> 144:ef7eb2e8f9f7 1714 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1715 {
<> 144:ef7eb2e8f9f7 1716 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1717 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 switch (Channel)
<> 144:ef7eb2e8f9f7 1720 {
<> 144:ef7eb2e8f9f7 1721 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1722 {
<> 144:ef7eb2e8f9f7 1723 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1724 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1725 }
<> 144:ef7eb2e8f9f7 1726 break;
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1729 {
<> 144:ef7eb2e8f9f7 1730 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1731 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1732 }
<> 144:ef7eb2e8f9f7 1733 break;
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1736 {
<> 144:ef7eb2e8f9f7 1737 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1738 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1739 }
<> 144:ef7eb2e8f9f7 1740 break;
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1743 {
<> 144:ef7eb2e8f9f7 1744 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1745 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1746 }
<> 144:ef7eb2e8f9f7 1747 break;
<> 144:ef7eb2e8f9f7 1748
<> 144:ef7eb2e8f9f7 1749 default:
<> 144:ef7eb2e8f9f7 1750 break;
<> 144:ef7eb2e8f9f7 1751 }
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1754 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1755
<> 144:ef7eb2e8f9f7 1756 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1757 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1758
<> 144:ef7eb2e8f9f7 1759 /* Return function status */
<> 144:ef7eb2e8f9f7 1760 return HAL_OK;
<> 144:ef7eb2e8f9f7 1761 }
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /**
<> 144:ef7eb2e8f9f7 1764 * @brief Starts the TIM Input Capture measurement in DMA mode.
<> 144:ef7eb2e8f9f7 1765 * @param htim : TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1766 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1767 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1768 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1769 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1770 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1771 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1772 * @param pData : The destination Buffer address.
<> 144:ef7eb2e8f9f7 1773 * @param Length : The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 1774 * @retval HAL status
<> 144:ef7eb2e8f9f7 1775 */
<> 144:ef7eb2e8f9f7 1776 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1777 {
<> 144:ef7eb2e8f9f7 1778 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1779 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1780 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1781
<> 144:ef7eb2e8f9f7 1782 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1783 {
<> 144:ef7eb2e8f9f7 1784 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1785 }
<> 144:ef7eb2e8f9f7 1786 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1787 {
<> 156:95d6b41a828b 1788 if((pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1789 {
<> 144:ef7eb2e8f9f7 1790 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1791 }
<> 144:ef7eb2e8f9f7 1792 else
<> 144:ef7eb2e8f9f7 1793 {
<> 144:ef7eb2e8f9f7 1794 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1795 }
<> 144:ef7eb2e8f9f7 1796 }
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 switch (Channel)
<> 144:ef7eb2e8f9f7 1799 {
<> 144:ef7eb2e8f9f7 1800 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1801 {
<> 144:ef7eb2e8f9f7 1802 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1803 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1804
<> 144:ef7eb2e8f9f7 1805 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1806 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1809 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1812 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1813 }
<> 144:ef7eb2e8f9f7 1814 break;
<> 144:ef7eb2e8f9f7 1815
<> 144:ef7eb2e8f9f7 1816 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1817 {
<> 144:ef7eb2e8f9f7 1818 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1819 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1822 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1825 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1826
<> 144:ef7eb2e8f9f7 1827 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1828 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1829 }
<> 144:ef7eb2e8f9f7 1830 break;
<> 144:ef7eb2e8f9f7 1831
<> 144:ef7eb2e8f9f7 1832 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1833 {
<> 144:ef7eb2e8f9f7 1834 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1835 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1836
<> 144:ef7eb2e8f9f7 1837 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1838 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1839
<> 144:ef7eb2e8f9f7 1840 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1841 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1842
<> 144:ef7eb2e8f9f7 1843 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1844 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1845 }
<> 144:ef7eb2e8f9f7 1846 break;
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1849 {
<> 144:ef7eb2e8f9f7 1850 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1851 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1852
<> 144:ef7eb2e8f9f7 1853 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1854 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1857 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1858
<> 144:ef7eb2e8f9f7 1859 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1860 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1861 }
<> 144:ef7eb2e8f9f7 1862 break;
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 default:
<> 144:ef7eb2e8f9f7 1865 break;
<> 144:ef7eb2e8f9f7 1866 }
<> 144:ef7eb2e8f9f7 1867
<> 144:ef7eb2e8f9f7 1868 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1869 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1872 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1873
<> 144:ef7eb2e8f9f7 1874 /* Return function status */
<> 144:ef7eb2e8f9f7 1875 return HAL_OK;
<> 144:ef7eb2e8f9f7 1876 }
<> 144:ef7eb2e8f9f7 1877
<> 144:ef7eb2e8f9f7 1878 /**
<> 144:ef7eb2e8f9f7 1879 * @brief Stops the TIM Input Capture measurement in DMA mode.
<> 144:ef7eb2e8f9f7 1880 * @param htim : TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1881 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1882 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1883 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1884 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1885 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1886 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1887 * @retval HAL status
<> 144:ef7eb2e8f9f7 1888 */
<> 144:ef7eb2e8f9f7 1889 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1890 {
<> 144:ef7eb2e8f9f7 1891 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1892 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1893 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1894
<> 144:ef7eb2e8f9f7 1895 switch (Channel)
<> 144:ef7eb2e8f9f7 1896 {
<> 144:ef7eb2e8f9f7 1897 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1898 {
<> 144:ef7eb2e8f9f7 1899 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1900 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1901 }
<> 144:ef7eb2e8f9f7 1902 break;
<> 144:ef7eb2e8f9f7 1903
<> 144:ef7eb2e8f9f7 1904 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1905 {
<> 144:ef7eb2e8f9f7 1906 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1908 }
<> 144:ef7eb2e8f9f7 1909 break;
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1912 {
<> 144:ef7eb2e8f9f7 1913 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1915 }
<> 144:ef7eb2e8f9f7 1916 break;
<> 144:ef7eb2e8f9f7 1917
<> 144:ef7eb2e8f9f7 1918 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1919 {
<> 144:ef7eb2e8f9f7 1920 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1921 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1922 }
<> 144:ef7eb2e8f9f7 1923 break;
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 default:
<> 144:ef7eb2e8f9f7 1926 break;
<> 144:ef7eb2e8f9f7 1927 }
<> 144:ef7eb2e8f9f7 1928
<> 144:ef7eb2e8f9f7 1929 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1930 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1931
<> 144:ef7eb2e8f9f7 1932 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1933 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1936 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1937
<> 144:ef7eb2e8f9f7 1938 /* Return function status */
<> 144:ef7eb2e8f9f7 1939 return HAL_OK;
<> 144:ef7eb2e8f9f7 1940 }
<> 144:ef7eb2e8f9f7 1941 /**
<> 144:ef7eb2e8f9f7 1942 * @}
<> 144:ef7eb2e8f9f7 1943 */
<> 144:ef7eb2e8f9f7 1944
<> 144:ef7eb2e8f9f7 1945 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<> 144:ef7eb2e8f9f7 1946 * @brief Time One Pulse functions
<> 144:ef7eb2e8f9f7 1947 *
<> 144:ef7eb2e8f9f7 1948 @verbatim
<> 144:ef7eb2e8f9f7 1949 ==============================================================================
<> 144:ef7eb2e8f9f7 1950 ##### Time One Pulse functions #####
<> 144:ef7eb2e8f9f7 1951 ==============================================================================
<> 144:ef7eb2e8f9f7 1952 [..]
<> 144:ef7eb2e8f9f7 1953 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1954 (+) Initialize and configure the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1955 (+) De-initialize the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1956 (+) Start the Time One Pulse.
<> 144:ef7eb2e8f9f7 1957 (+) Stop the Time One Pulse.
<> 144:ef7eb2e8f9f7 1958 (+) Start the Time One Pulse and enable interrupt.
<> 144:ef7eb2e8f9f7 1959 (+) Stop the Time One Pulse and disable interrupt.
<> 144:ef7eb2e8f9f7 1960 (+) Start the Time One Pulse and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1961 (+) Stop the Time One Pulse and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1962
<> 144:ef7eb2e8f9f7 1963 @endverbatim
<> 144:ef7eb2e8f9f7 1964 * @{
<> 144:ef7eb2e8f9f7 1965 */
<> 144:ef7eb2e8f9f7 1966 /**
<> 144:ef7eb2e8f9f7 1967 * @brief Initializes the TIM One Pulse Time Base according to the specified
<> 144:ef7eb2e8f9f7 1968 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1969 * @param htim : TIM OnePulse handle
<> 144:ef7eb2e8f9f7 1970 * @param OnePulseMode : Select the One pulse mode.
<> 144:ef7eb2e8f9f7 1971 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1972 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<> 144:ef7eb2e8f9f7 1973 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
<> 144:ef7eb2e8f9f7 1974 * @retval HAL status
<> 144:ef7eb2e8f9f7 1975 */
<> 144:ef7eb2e8f9f7 1976 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<> 144:ef7eb2e8f9f7 1977 {
<> 144:ef7eb2e8f9f7 1978 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1979 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1980 {
<> 144:ef7eb2e8f9f7 1981 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1982 }
<> 144:ef7eb2e8f9f7 1983
<> 144:ef7eb2e8f9f7 1984 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1985 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1986 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1987 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1988 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<> 156:95d6b41a828b 1989 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 1990
<> 144:ef7eb2e8f9f7 1991 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1992 {
<> 144:ef7eb2e8f9f7 1993 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1994 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1995
<> 144:ef7eb2e8f9f7 1996 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1997 HAL_TIM_OnePulse_MspInit(htim);
<> 144:ef7eb2e8f9f7 1998 }
<> 144:ef7eb2e8f9f7 1999
<> 144:ef7eb2e8f9f7 2000 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2001 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2002
<> 144:ef7eb2e8f9f7 2003 /* Configure the Time base in the One Pulse Mode */
<> 144:ef7eb2e8f9f7 2004 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2005
<> 144:ef7eb2e8f9f7 2006 /* Reset the OPM Bit */
<> 144:ef7eb2e8f9f7 2007 htim->Instance->CR1 &= ~TIM_CR1_OPM;
<> 144:ef7eb2e8f9f7 2008
<> 144:ef7eb2e8f9f7 2009 /* Configure the OPM Mode */
<> 144:ef7eb2e8f9f7 2010 htim->Instance->CR1 |= OnePulseMode;
<> 144:ef7eb2e8f9f7 2011
<> 144:ef7eb2e8f9f7 2012 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2013 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2014
<> 144:ef7eb2e8f9f7 2015 return HAL_OK;
<> 144:ef7eb2e8f9f7 2016 }
<> 144:ef7eb2e8f9f7 2017
<> 144:ef7eb2e8f9f7 2018 /**
<> 144:ef7eb2e8f9f7 2019 * @brief DeInitializes the TIM One Pulse
<> 144:ef7eb2e8f9f7 2020 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2021 * @retval HAL status
<> 144:ef7eb2e8f9f7 2022 */
<> 144:ef7eb2e8f9f7 2023 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2024 {
<> 144:ef7eb2e8f9f7 2025 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2026 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2027
<> 144:ef7eb2e8f9f7 2028 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2031 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2034 HAL_TIM_OnePulse_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2037 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2038
<> 144:ef7eb2e8f9f7 2039 /* Release Lock */
<> 144:ef7eb2e8f9f7 2040 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2041
<> 144:ef7eb2e8f9f7 2042 return HAL_OK;
<> 144:ef7eb2e8f9f7 2043 }
<> 144:ef7eb2e8f9f7 2044
<> 144:ef7eb2e8f9f7 2045 /**
<> 144:ef7eb2e8f9f7 2046 * @brief Initializes the TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2047 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2048 * @retval None
<> 144:ef7eb2e8f9f7 2049 */
<> 144:ef7eb2e8f9f7 2050 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2051 {
<> 144:ef7eb2e8f9f7 2052 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2053 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2054
<> 144:ef7eb2e8f9f7 2055 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2056 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2057 */
<> 144:ef7eb2e8f9f7 2058 }
<> 144:ef7eb2e8f9f7 2059
<> 144:ef7eb2e8f9f7 2060 /**
<> 144:ef7eb2e8f9f7 2061 * @brief DeInitializes TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2062 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2063 * @retval None
<> 144:ef7eb2e8f9f7 2064 */
<> 144:ef7eb2e8f9f7 2065 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2066 {
<> 144:ef7eb2e8f9f7 2067 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2068 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2069
<> 144:ef7eb2e8f9f7 2070 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2071 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2072 */
<> 144:ef7eb2e8f9f7 2073 }
<> 144:ef7eb2e8f9f7 2074
<> 144:ef7eb2e8f9f7 2075 /**
<> 144:ef7eb2e8f9f7 2076 * @brief Starts the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2077 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2078 * @param OutputChannel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2079 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2080 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2081 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2082 * @retval HAL status
<> 144:ef7eb2e8f9f7 2083 */
<> 144:ef7eb2e8f9f7 2084 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2085 {
<> 144:ef7eb2e8f9f7 2086 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2087 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2088 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2089 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2090 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2091
<> 144:ef7eb2e8f9f7 2092 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2093 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2094
<> 144:ef7eb2e8f9f7 2095 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2096 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2097
<> 144:ef7eb2e8f9f7 2098 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2099 {
<> 144:ef7eb2e8f9f7 2100 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2101 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2102 }
<> 144:ef7eb2e8f9f7 2103
<> 144:ef7eb2e8f9f7 2104 /* Return function status */
<> 144:ef7eb2e8f9f7 2105 return HAL_OK;
<> 144:ef7eb2e8f9f7 2106 }
<> 144:ef7eb2e8f9f7 2107
<> 144:ef7eb2e8f9f7 2108 /**
<> 144:ef7eb2e8f9f7 2109 * @brief Stops the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2110 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2111 * @param OutputChannel : TIM Channels to be disable
<> 144:ef7eb2e8f9f7 2112 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2115 * @retval HAL status
<> 144:ef7eb2e8f9f7 2116 */
<> 144:ef7eb2e8f9f7 2117 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2118 {
<> 144:ef7eb2e8f9f7 2119 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2120 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2121 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2122 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2123 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2124
<> 144:ef7eb2e8f9f7 2125 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2126 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2127
<> 144:ef7eb2e8f9f7 2128 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2129 {
<> 144:ef7eb2e8f9f7 2130 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 2131 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2132 }
<> 144:ef7eb2e8f9f7 2133
<> 144:ef7eb2e8f9f7 2134 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2135 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2136
<> 144:ef7eb2e8f9f7 2137 /* Return function status */
<> 144:ef7eb2e8f9f7 2138 return HAL_OK;
<> 144:ef7eb2e8f9f7 2139 }
<> 144:ef7eb2e8f9f7 2140
<> 144:ef7eb2e8f9f7 2141 /**
<> 144:ef7eb2e8f9f7 2142 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2143 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2144 * @param OutputChannel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2145 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2146 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2147 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2148 * @retval HAL status
<> 144:ef7eb2e8f9f7 2149 */
<> 144:ef7eb2e8f9f7 2150 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2151 {
<> 144:ef7eb2e8f9f7 2152 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2153 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2154 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2155 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2156 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2157
<> 144:ef7eb2e8f9f7 2158 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2159 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2160
<> 144:ef7eb2e8f9f7 2161 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2162 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2165 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2168 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2169
<> 144:ef7eb2e8f9f7 2170 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2171 {
<> 144:ef7eb2e8f9f7 2172 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2173 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2174 }
<> 144:ef7eb2e8f9f7 2175
<> 144:ef7eb2e8f9f7 2176 /* Return function status */
<> 144:ef7eb2e8f9f7 2177 return HAL_OK;
<> 144:ef7eb2e8f9f7 2178 }
<> 144:ef7eb2e8f9f7 2179
<> 144:ef7eb2e8f9f7 2180 /**
<> 144:ef7eb2e8f9f7 2181 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2182 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2183 * @param OutputChannel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2184 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2185 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2186 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2187 * @retval HAL status
<> 144:ef7eb2e8f9f7 2188 */
<> 144:ef7eb2e8f9f7 2189 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2190 {
<> 144:ef7eb2e8f9f7 2191 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2192 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2193
<> 144:ef7eb2e8f9f7 2194 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2195 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2196
<> 144:ef7eb2e8f9f7 2197 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2198 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2199 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2200 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2201 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2202 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2203 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2204
<> 144:ef7eb2e8f9f7 2205 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2206 {
<> 144:ef7eb2e8f9f7 2207 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 2208 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2209 }
<> 144:ef7eb2e8f9f7 2210
<> 144:ef7eb2e8f9f7 2211 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2212 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2213
<> 144:ef7eb2e8f9f7 2214 /* Return function status */
<> 144:ef7eb2e8f9f7 2215 return HAL_OK;
<> 144:ef7eb2e8f9f7 2216 }
<> 144:ef7eb2e8f9f7 2217
<> 144:ef7eb2e8f9f7 2218 /**
<> 144:ef7eb2e8f9f7 2219 * @}
<> 144:ef7eb2e8f9f7 2220 */
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<> 144:ef7eb2e8f9f7 2223 * @brief Time Encoder functions
<> 144:ef7eb2e8f9f7 2224 *
<> 144:ef7eb2e8f9f7 2225 @verbatim
<> 144:ef7eb2e8f9f7 2226 ==============================================================================
<> 144:ef7eb2e8f9f7 2227 ##### Time Encoder functions #####
<> 144:ef7eb2e8f9f7 2228 ==============================================================================
<> 144:ef7eb2e8f9f7 2229 [..]
<> 144:ef7eb2e8f9f7 2230 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2231 (+) Initialize and configure the TIM Encoder.
<> 144:ef7eb2e8f9f7 2232 (+) De-initialize the TIM Encoder.
<> 144:ef7eb2e8f9f7 2233 (+) Start the Time Encoder.
<> 144:ef7eb2e8f9f7 2234 (+) Stop the Time Encoder.
<> 144:ef7eb2e8f9f7 2235 (+) Start the Time Encoder and enable interrupt.
<> 144:ef7eb2e8f9f7 2236 (+) Stop the Time Encoder and disable interrupt.
<> 144:ef7eb2e8f9f7 2237 (+) Start the Time Encoder and enable DMA transfer.
<> 144:ef7eb2e8f9f7 2238 (+) Stop the Time Encoder and disable DMA transfer.
<> 144:ef7eb2e8f9f7 2239
<> 144:ef7eb2e8f9f7 2240 @endverbatim
<> 144:ef7eb2e8f9f7 2241 * @{
<> 144:ef7eb2e8f9f7 2242 */
<> 144:ef7eb2e8f9f7 2243 /**
<> 144:ef7eb2e8f9f7 2244 * @brief Initializes the TIM Encoder Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 2245 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2246 * @param sConfig : TIM Encoder Interface configuration structure
<> 144:ef7eb2e8f9f7 2247 * @retval HAL status
<> 144:ef7eb2e8f9f7 2248 */
<> 144:ef7eb2e8f9f7 2249 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 2250 {
<> 156:95d6b41a828b 2251 uint32_t tmpsmcr = 0U;
<> 156:95d6b41a828b 2252 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 2253 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 2254
<> 144:ef7eb2e8f9f7 2255 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2256 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2257 {
<> 144:ef7eb2e8f9f7 2258 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2259 }
<> 144:ef7eb2e8f9f7 2260
<> 144:ef7eb2e8f9f7 2261 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2262 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 156:95d6b41a828b 2263 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 156:95d6b41a828b 2264 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 156:95d6b41a828b 2265 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 2266 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<> 144:ef7eb2e8f9f7 2267 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<> 144:ef7eb2e8f9f7 2268 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<> 144:ef7eb2e8f9f7 2269 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 2270 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<> 144:ef7eb2e8f9f7 2271 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 2272 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<> 144:ef7eb2e8f9f7 2273 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 2274 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<> 144:ef7eb2e8f9f7 2275
<> 144:ef7eb2e8f9f7 2276 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2277 {
<> 144:ef7eb2e8f9f7 2278 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2279 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2280
<> 144:ef7eb2e8f9f7 2281 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2282 HAL_TIM_Encoder_MspInit(htim);
<> 144:ef7eb2e8f9f7 2283 }
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2286 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2287
<> 144:ef7eb2e8f9f7 2288 /* Reset the SMS bits */
<> 144:ef7eb2e8f9f7 2289 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 2290
<> 144:ef7eb2e8f9f7 2291 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 2292 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2293
<> 144:ef7eb2e8f9f7 2294 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 2295 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 2296
<> 144:ef7eb2e8f9f7 2297 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2298 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 2299
<> 144:ef7eb2e8f9f7 2300 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2301 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 2302
<> 144:ef7eb2e8f9f7 2303 /* Set the encoder Mode */
<> 144:ef7eb2e8f9f7 2304 tmpsmcr |= sConfig->EncoderMode;
<> 144:ef7eb2e8f9f7 2305
<> 144:ef7eb2e8f9f7 2306 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
<> 144:ef7eb2e8f9f7 2307 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
<> 156:95d6b41a828b 2308 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
<> 144:ef7eb2e8f9f7 2309
<> 144:ef7eb2e8f9f7 2310 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<> 144:ef7eb2e8f9f7 2311 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
<> 144:ef7eb2e8f9f7 2312 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
<> 156:95d6b41a828b 2313 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
<> 156:95d6b41a828b 2314 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
<> 144:ef7eb2e8f9f7 2315
<> 144:ef7eb2e8f9f7 2316 /* Set the TI1 and the TI2 Polarities */
<> 144:ef7eb2e8f9f7 2317 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
<> 144:ef7eb2e8f9f7 2318 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
<> 156:95d6b41a828b 2319 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
<> 144:ef7eb2e8f9f7 2320
<> 144:ef7eb2e8f9f7 2321 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 2322 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 2325 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2328 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2329
<> 144:ef7eb2e8f9f7 2330 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2331 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2332
<> 144:ef7eb2e8f9f7 2333 return HAL_OK;
<> 144:ef7eb2e8f9f7 2334 }
<> 144:ef7eb2e8f9f7 2335
<> 144:ef7eb2e8f9f7 2336
<> 144:ef7eb2e8f9f7 2337 /**
<> 144:ef7eb2e8f9f7 2338 * @brief DeInitializes the TIM Encoder interface
<> 144:ef7eb2e8f9f7 2339 * @param htim : TIM Encoder handle
<> 144:ef7eb2e8f9f7 2340 * @retval HAL status
<> 144:ef7eb2e8f9f7 2341 */
<> 144:ef7eb2e8f9f7 2342 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2343 {
<> 144:ef7eb2e8f9f7 2344 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2345 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2346
<> 144:ef7eb2e8f9f7 2347 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2348
<> 144:ef7eb2e8f9f7 2349 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2350 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2351
<> 144:ef7eb2e8f9f7 2352 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2353 HAL_TIM_Encoder_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2354
<> 144:ef7eb2e8f9f7 2355 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2356 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /* Release Lock */
<> 144:ef7eb2e8f9f7 2359 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2360
<> 144:ef7eb2e8f9f7 2361 return HAL_OK;
<> 144:ef7eb2e8f9f7 2362 }
<> 144:ef7eb2e8f9f7 2363
<> 144:ef7eb2e8f9f7 2364 /**
<> 144:ef7eb2e8f9f7 2365 * @brief Initializes the TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2366 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2367 * @retval None
<> 144:ef7eb2e8f9f7 2368 */
<> 144:ef7eb2e8f9f7 2369 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2370 {
<> 144:ef7eb2e8f9f7 2371 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2372 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2373
<> 144:ef7eb2e8f9f7 2374 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2375 the HAL_TIM_Encoder_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2376 */
<> 144:ef7eb2e8f9f7 2377 }
<> 144:ef7eb2e8f9f7 2378
<> 144:ef7eb2e8f9f7 2379 /**
<> 144:ef7eb2e8f9f7 2380 * @brief DeInitializes TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2381 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2382 * @retval None
<> 144:ef7eb2e8f9f7 2383 */
<> 144:ef7eb2e8f9f7 2384 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2385 {
<> 144:ef7eb2e8f9f7 2386 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2387 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2388
<> 144:ef7eb2e8f9f7 2389 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2390 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2391 */
<> 144:ef7eb2e8f9f7 2392 }
<> 144:ef7eb2e8f9f7 2393
<> 144:ef7eb2e8f9f7 2394 /**
<> 144:ef7eb2e8f9f7 2395 * @brief Starts the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2396 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2397 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2398 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2399 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2400 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2401 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2402 * @retval HAL status
<> 144:ef7eb2e8f9f7 2403 */
<> 144:ef7eb2e8f9f7 2404 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2405 {
<> 144:ef7eb2e8f9f7 2406 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2407 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2408
<> 144:ef7eb2e8f9f7 2409 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2410 switch (Channel)
<> 144:ef7eb2e8f9f7 2411 {
<> 144:ef7eb2e8f9f7 2412 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2413 {
<> 144:ef7eb2e8f9f7 2414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2415 break;
<> 144:ef7eb2e8f9f7 2416 }
<> 144:ef7eb2e8f9f7 2417 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2418 {
<> 144:ef7eb2e8f9f7 2419 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2420 break;
<> 144:ef7eb2e8f9f7 2421 }
<> 144:ef7eb2e8f9f7 2422 default :
<> 144:ef7eb2e8f9f7 2423 {
<> 144:ef7eb2e8f9f7 2424 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2425 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2426 break;
<> 144:ef7eb2e8f9f7 2427 }
<> 144:ef7eb2e8f9f7 2428 }
<> 144:ef7eb2e8f9f7 2429 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2430 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2431
<> 144:ef7eb2e8f9f7 2432 /* Return function status */
<> 144:ef7eb2e8f9f7 2433 return HAL_OK;
<> 144:ef7eb2e8f9f7 2434 }
<> 144:ef7eb2e8f9f7 2435
<> 144:ef7eb2e8f9f7 2436 /**
<> 144:ef7eb2e8f9f7 2437 * @brief Stops the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2438 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2439 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 2440 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2441 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2442 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2443 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2444 * @retval HAL status
<> 144:ef7eb2e8f9f7 2445 */
<> 144:ef7eb2e8f9f7 2446 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2447 {
<> 144:ef7eb2e8f9f7 2448 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2449 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2450
<> 144:ef7eb2e8f9f7 2451 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2452 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2453 switch (Channel)
<> 144:ef7eb2e8f9f7 2454 {
<> 144:ef7eb2e8f9f7 2455 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2456 {
<> 144:ef7eb2e8f9f7 2457 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2458 break;
<> 144:ef7eb2e8f9f7 2459 }
<> 144:ef7eb2e8f9f7 2460 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2461 {
<> 144:ef7eb2e8f9f7 2462 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2463 break;
<> 144:ef7eb2e8f9f7 2464 }
<> 144:ef7eb2e8f9f7 2465 default :
<> 144:ef7eb2e8f9f7 2466 {
<> 144:ef7eb2e8f9f7 2467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2468 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2469 break;
<> 144:ef7eb2e8f9f7 2470 }
<> 144:ef7eb2e8f9f7 2471 }
<> 144:ef7eb2e8f9f7 2472
<> 144:ef7eb2e8f9f7 2473 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2474 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2475
<> 144:ef7eb2e8f9f7 2476 /* Return function status */
<> 144:ef7eb2e8f9f7 2477 return HAL_OK;
<> 144:ef7eb2e8f9f7 2478 }
<> 144:ef7eb2e8f9f7 2479
<> 144:ef7eb2e8f9f7 2480 /**
<> 144:ef7eb2e8f9f7 2481 * @brief Starts the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2482 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2483 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2484 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2485 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2486 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2487 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2488 * @retval HAL status
<> 144:ef7eb2e8f9f7 2489 */
<> 144:ef7eb2e8f9f7 2490 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2491 {
<> 144:ef7eb2e8f9f7 2492 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2493 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2494
<> 144:ef7eb2e8f9f7 2495 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2496 /* Enable the capture compare Interrupts 1 and/or 2 */
<> 144:ef7eb2e8f9f7 2497 switch (Channel)
<> 144:ef7eb2e8f9f7 2498 {
<> 144:ef7eb2e8f9f7 2499 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2500 {
<> 144:ef7eb2e8f9f7 2501 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2502 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2503 break;
<> 144:ef7eb2e8f9f7 2504 }
<> 144:ef7eb2e8f9f7 2505 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2506 {
<> 144:ef7eb2e8f9f7 2507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2508 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2509 break;
<> 144:ef7eb2e8f9f7 2510 }
<> 144:ef7eb2e8f9f7 2511 default :
<> 144:ef7eb2e8f9f7 2512 {
<> 144:ef7eb2e8f9f7 2513 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2514 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2515 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2516 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2517 break;
<> 144:ef7eb2e8f9f7 2518 }
<> 144:ef7eb2e8f9f7 2519 }
<> 144:ef7eb2e8f9f7 2520
<> 144:ef7eb2e8f9f7 2521 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2522 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /* Return function status */
<> 144:ef7eb2e8f9f7 2525 return HAL_OK;
<> 144:ef7eb2e8f9f7 2526 }
<> 144:ef7eb2e8f9f7 2527
<> 144:ef7eb2e8f9f7 2528 /**
<> 144:ef7eb2e8f9f7 2529 * @brief Stops the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2530 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2531 * @param Channel : TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 2532 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2533 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2534 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2535 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2536 * @retval HAL status
<> 144:ef7eb2e8f9f7 2537 */
<> 144:ef7eb2e8f9f7 2538 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2539 {
<> 144:ef7eb2e8f9f7 2540 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2541 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2542
<> 144:ef7eb2e8f9f7 2543 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2544 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2545 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2546 {
<> 144:ef7eb2e8f9f7 2547 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2548
<> 144:ef7eb2e8f9f7 2549 /* Disable the capture compare Interrupts 1 */
<> 144:ef7eb2e8f9f7 2550 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2551 }
<> 144:ef7eb2e8f9f7 2552 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2553 {
<> 144:ef7eb2e8f9f7 2554 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2555
<> 144:ef7eb2e8f9f7 2556 /* Disable the capture compare Interrupts 2 */
<> 144:ef7eb2e8f9f7 2557 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2558 }
<> 144:ef7eb2e8f9f7 2559 else
<> 144:ef7eb2e8f9f7 2560 {
<> 144:ef7eb2e8f9f7 2561 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2562 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2563
<> 144:ef7eb2e8f9f7 2564 /* Disable the capture compare Interrupts 1 and 2 */
<> 144:ef7eb2e8f9f7 2565 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2566 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2567 }
<> 144:ef7eb2e8f9f7 2568
<> 144:ef7eb2e8f9f7 2569 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2570 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2571
<> 144:ef7eb2e8f9f7 2572 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2573 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2574
<> 144:ef7eb2e8f9f7 2575 /* Return function status */
<> 144:ef7eb2e8f9f7 2576 return HAL_OK;
<> 144:ef7eb2e8f9f7 2577 }
<> 144:ef7eb2e8f9f7 2578
<> 144:ef7eb2e8f9f7 2579 /**
<> 144:ef7eb2e8f9f7 2580 * @brief Starts the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2581 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2582 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2583 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2584 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2585 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2586 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2587 * @param pData1 : The destination Buffer address for IC1.
<> 144:ef7eb2e8f9f7 2588 * @param pData2 : The destination Buffer address for IC2.
<> 144:ef7eb2e8f9f7 2589 * @param Length : The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 2590 * @retval HAL status
<> 144:ef7eb2e8f9f7 2591 */
<> 144:ef7eb2e8f9f7 2592 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
<> 144:ef7eb2e8f9f7 2593 {
<> 144:ef7eb2e8f9f7 2594 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2595 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2596
<> 144:ef7eb2e8f9f7 2597 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 2598 {
<> 144:ef7eb2e8f9f7 2599 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2600 }
<> 144:ef7eb2e8f9f7 2601 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 2602 {
<> 156:95d6b41a828b 2603 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
<> 144:ef7eb2e8f9f7 2604 {
<> 144:ef7eb2e8f9f7 2605 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2606 }
<> 144:ef7eb2e8f9f7 2607 else
<> 144:ef7eb2e8f9f7 2608 {
<> 144:ef7eb2e8f9f7 2609 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2610 }
<> 144:ef7eb2e8f9f7 2611 }
<> 144:ef7eb2e8f9f7 2612
<> 144:ef7eb2e8f9f7 2613 switch (Channel)
<> 144:ef7eb2e8f9f7 2614 {
<> 144:ef7eb2e8f9f7 2615 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2616 {
<> 144:ef7eb2e8f9f7 2617 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2618 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2619
<> 144:ef7eb2e8f9f7 2620 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2621 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2622
<> 144:ef7eb2e8f9f7 2623 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2624 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<> 144:ef7eb2e8f9f7 2625
<> 144:ef7eb2e8f9f7 2626 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2627 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2628
<> 144:ef7eb2e8f9f7 2629 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2630 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2631
<> 144:ef7eb2e8f9f7 2632 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2633 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2634 }
<> 144:ef7eb2e8f9f7 2635 break;
<> 144:ef7eb2e8f9f7 2636
<> 144:ef7eb2e8f9f7 2637 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2638 {
<> 144:ef7eb2e8f9f7 2639 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2640 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2641
<> 144:ef7eb2e8f9f7 2642 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2643 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 2644 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2645 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2646
<> 144:ef7eb2e8f9f7 2647 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2648 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2649
<> 144:ef7eb2e8f9f7 2650 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2651 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2652
<> 144:ef7eb2e8f9f7 2653 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2654 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2655 }
<> 144:ef7eb2e8f9f7 2656 break;
<> 144:ef7eb2e8f9f7 2657
<> 144:ef7eb2e8f9f7 2658 case TIM_CHANNEL_ALL:
<> 144:ef7eb2e8f9f7 2659 {
<> 144:ef7eb2e8f9f7 2660 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2661 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2662
<> 144:ef7eb2e8f9f7 2663 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2664 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2665
<> 144:ef7eb2e8f9f7 2666 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2667 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<> 144:ef7eb2e8f9f7 2668
<> 144:ef7eb2e8f9f7 2669 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2670 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2671
<> 144:ef7eb2e8f9f7 2672 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2673 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2676 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2677
<> 144:ef7eb2e8f9f7 2678 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2679 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2680
<> 144:ef7eb2e8f9f7 2681 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2682 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2683 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2684
<> 144:ef7eb2e8f9f7 2685 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2686 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2687 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2688 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2689 }
<> 144:ef7eb2e8f9f7 2690 break;
<> 144:ef7eb2e8f9f7 2691
<> 144:ef7eb2e8f9f7 2692 default:
<> 144:ef7eb2e8f9f7 2693 break;
<> 144:ef7eb2e8f9f7 2694 }
<> 144:ef7eb2e8f9f7 2695 /* Return function status */
<> 144:ef7eb2e8f9f7 2696 return HAL_OK;
<> 144:ef7eb2e8f9f7 2697 }
<> 144:ef7eb2e8f9f7 2698
<> 144:ef7eb2e8f9f7 2699 /**
<> 144:ef7eb2e8f9f7 2700 * @brief Stops the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2701 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2702 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2703 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2704 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2705 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2706 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2707 * @retval HAL status
<> 144:ef7eb2e8f9f7 2708 */
<> 144:ef7eb2e8f9f7 2709 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2710 {
<> 144:ef7eb2e8f9f7 2711 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2712 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2713
<> 144:ef7eb2e8f9f7 2714 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2715 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2716 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2717 {
<> 144:ef7eb2e8f9f7 2718 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2719
<> 144:ef7eb2e8f9f7 2720 /* Disable the capture compare DMA Request 1 */
<> 144:ef7eb2e8f9f7 2721 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2722 }
<> 144:ef7eb2e8f9f7 2723 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2724 {
<> 144:ef7eb2e8f9f7 2725 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2726
<> 144:ef7eb2e8f9f7 2727 /* Disable the capture compare DMA Request 2 */
<> 144:ef7eb2e8f9f7 2728 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2729 }
<> 144:ef7eb2e8f9f7 2730 else
<> 144:ef7eb2e8f9f7 2731 {
<> 144:ef7eb2e8f9f7 2732 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2733 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2734
<> 144:ef7eb2e8f9f7 2735 /* Disable the capture compare DMA Request 1 and 2 */
<> 144:ef7eb2e8f9f7 2736 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2737 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2738 }
<> 144:ef7eb2e8f9f7 2739
<> 144:ef7eb2e8f9f7 2740 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2741 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2742
<> 144:ef7eb2e8f9f7 2743 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2744 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2745
<> 144:ef7eb2e8f9f7 2746 /* Return function status */
<> 144:ef7eb2e8f9f7 2747 return HAL_OK;
<> 144:ef7eb2e8f9f7 2748 }
<> 144:ef7eb2e8f9f7 2749
<> 144:ef7eb2e8f9f7 2750 /**
<> 144:ef7eb2e8f9f7 2751 * @}
<> 144:ef7eb2e8f9f7 2752 */
<> 144:ef7eb2e8f9f7 2753 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<> 144:ef7eb2e8f9f7 2754 * @brief IRQ handler management
<> 144:ef7eb2e8f9f7 2755 *
<> 144:ef7eb2e8f9f7 2756 @verbatim
<> 144:ef7eb2e8f9f7 2757 ==============================================================================
<> 144:ef7eb2e8f9f7 2758 ##### IRQ handler management #####
<> 144:ef7eb2e8f9f7 2759 ==============================================================================
<> 144:ef7eb2e8f9f7 2760 [..]
<> 144:ef7eb2e8f9f7 2761 This section provides Timer IRQ handler function.
<> 144:ef7eb2e8f9f7 2762
<> 144:ef7eb2e8f9f7 2763 @endverbatim
<> 144:ef7eb2e8f9f7 2764 * @{
<> 144:ef7eb2e8f9f7 2765 */
<> 144:ef7eb2e8f9f7 2766 /**
<> 144:ef7eb2e8f9f7 2767 * @brief This function handles TIM interrupts requests.
<> 144:ef7eb2e8f9f7 2768 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2769 * @retval None
<> 144:ef7eb2e8f9f7 2770 */
<> 144:ef7eb2e8f9f7 2771 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2772 {
<> 144:ef7eb2e8f9f7 2773 /* Capture compare 1 event */
<> 144:ef7eb2e8f9f7 2774 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<> 144:ef7eb2e8f9f7 2775 {
<> 144:ef7eb2e8f9f7 2776 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<> 144:ef7eb2e8f9f7 2777 {
<> 144:ef7eb2e8f9f7 2778 {
<> 144:ef7eb2e8f9f7 2779 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2780 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 2781
<> 144:ef7eb2e8f9f7 2782 /* Input capture event */
<> 156:95d6b41a828b 2783 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
<> 144:ef7eb2e8f9f7 2784 {
<> 144:ef7eb2e8f9f7 2785 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2786 }
<> 144:ef7eb2e8f9f7 2787 /* Output compare event */
<> 144:ef7eb2e8f9f7 2788 else
<> 144:ef7eb2e8f9f7 2789 {
<> 144:ef7eb2e8f9f7 2790 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2791 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2792 }
<> 144:ef7eb2e8f9f7 2793 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2794 }
<> 144:ef7eb2e8f9f7 2795 }
<> 144:ef7eb2e8f9f7 2796 }
<> 144:ef7eb2e8f9f7 2797 /* Capture compare 2 event */
<> 144:ef7eb2e8f9f7 2798 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<> 144:ef7eb2e8f9f7 2799 {
<> 144:ef7eb2e8f9f7 2800 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<> 144:ef7eb2e8f9f7 2801 {
<> 144:ef7eb2e8f9f7 2802 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2803 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 2804 /* Input capture event */
<> 156:95d6b41a828b 2805 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
<> 144:ef7eb2e8f9f7 2806 {
<> 144:ef7eb2e8f9f7 2807 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2808 }
<> 144:ef7eb2e8f9f7 2809 /* Output compare event */
<> 144:ef7eb2e8f9f7 2810 else
<> 144:ef7eb2e8f9f7 2811 {
<> 144:ef7eb2e8f9f7 2812 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2813 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2814 }
<> 144:ef7eb2e8f9f7 2815 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2816 }
<> 144:ef7eb2e8f9f7 2817 }
<> 144:ef7eb2e8f9f7 2818 /* Capture compare 3 event */
<> 144:ef7eb2e8f9f7 2819 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<> 144:ef7eb2e8f9f7 2820 {
<> 144:ef7eb2e8f9f7 2821 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<> 144:ef7eb2e8f9f7 2822 {
<> 144:ef7eb2e8f9f7 2823 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 2824 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 2825 /* Input capture event */
<> 156:95d6b41a828b 2826 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
<> 144:ef7eb2e8f9f7 2827 {
<> 144:ef7eb2e8f9f7 2828 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2829 }
<> 144:ef7eb2e8f9f7 2830 /* Output compare event */
<> 144:ef7eb2e8f9f7 2831 else
<> 144:ef7eb2e8f9f7 2832 {
<> 144:ef7eb2e8f9f7 2833 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2834 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2835 }
<> 144:ef7eb2e8f9f7 2836 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2837 }
<> 144:ef7eb2e8f9f7 2838 }
<> 144:ef7eb2e8f9f7 2839 /* Capture compare 4 event */
<> 144:ef7eb2e8f9f7 2840 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<> 144:ef7eb2e8f9f7 2841 {
<> 144:ef7eb2e8f9f7 2842 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<> 144:ef7eb2e8f9f7 2843 {
<> 144:ef7eb2e8f9f7 2844 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 2845 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 2846 /* Input capture event */
<> 156:95d6b41a828b 2847 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
<> 144:ef7eb2e8f9f7 2848 {
<> 144:ef7eb2e8f9f7 2849 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2850 }
<> 144:ef7eb2e8f9f7 2851 /* Output compare event */
<> 144:ef7eb2e8f9f7 2852 else
<> 144:ef7eb2e8f9f7 2853 {
<> 144:ef7eb2e8f9f7 2854 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2855 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2856 }
<> 144:ef7eb2e8f9f7 2857 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2858 }
<> 144:ef7eb2e8f9f7 2859 }
<> 144:ef7eb2e8f9f7 2860 /* TIM Update event */
<> 144:ef7eb2e8f9f7 2861 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<> 144:ef7eb2e8f9f7 2862 {
<> 144:ef7eb2e8f9f7 2863 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<> 144:ef7eb2e8f9f7 2864 {
<> 144:ef7eb2e8f9f7 2865 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 2866 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2867 }
<> 144:ef7eb2e8f9f7 2868 }
<> 144:ef7eb2e8f9f7 2869 /* TIM Break input event */
<> 144:ef7eb2e8f9f7 2870 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<> 144:ef7eb2e8f9f7 2871 {
<> 144:ef7eb2e8f9f7 2872 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<> 144:ef7eb2e8f9f7 2873 {
<> 144:ef7eb2e8f9f7 2874 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 2875 HAL_TIMEx_BreakCallback(htim);
<> 144:ef7eb2e8f9f7 2876 }
<> 144:ef7eb2e8f9f7 2877 }
<> 144:ef7eb2e8f9f7 2878 /* TIM Trigger detection event */
<> 144:ef7eb2e8f9f7 2879 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<> 144:ef7eb2e8f9f7 2880 {
<> 144:ef7eb2e8f9f7 2881 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<> 144:ef7eb2e8f9f7 2882 {
<> 144:ef7eb2e8f9f7 2883 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 2884 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 2885 }
<> 144:ef7eb2e8f9f7 2886 }
<> 144:ef7eb2e8f9f7 2887 /* TIM commutation event */
<> 144:ef7eb2e8f9f7 2888 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<> 144:ef7eb2e8f9f7 2889 {
<> 144:ef7eb2e8f9f7 2890 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<> 144:ef7eb2e8f9f7 2891 {
<> 144:ef7eb2e8f9f7 2892 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<> 144:ef7eb2e8f9f7 2893 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 2894 }
<> 144:ef7eb2e8f9f7 2895 }
<> 144:ef7eb2e8f9f7 2896 }
<> 144:ef7eb2e8f9f7 2897
<> 144:ef7eb2e8f9f7 2898 /**
<> 144:ef7eb2e8f9f7 2899 * @}
<> 144:ef7eb2e8f9f7 2900 */
<> 144:ef7eb2e8f9f7 2901
<> 144:ef7eb2e8f9f7 2902 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<> 144:ef7eb2e8f9f7 2903 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 2904 *
<> 144:ef7eb2e8f9f7 2905 @verbatim
<> 144:ef7eb2e8f9f7 2906 ==============================================================================
<> 144:ef7eb2e8f9f7 2907 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 2908 ==============================================================================
<> 144:ef7eb2e8f9f7 2909 [..]
<> 144:ef7eb2e8f9f7 2910 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2911 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 2912 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 2913 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 2914 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 2915 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 2916
<> 144:ef7eb2e8f9f7 2917 @endverbatim
<> 144:ef7eb2e8f9f7 2918 * @{
<> 144:ef7eb2e8f9f7 2919 */
<> 144:ef7eb2e8f9f7 2920
<> 144:ef7eb2e8f9f7 2921 /**
<> 144:ef7eb2e8f9f7 2922 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 2923 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2924 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 2925 * @param sConfig : TIM Output Compare configuration structure
<> 144:ef7eb2e8f9f7 2926 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2927 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2928 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2929 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2930 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2931 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2932 * @retval HAL status
<> 144:ef7eb2e8f9f7 2933 */
<> 144:ef7eb2e8f9f7 2934 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2935 {
<> 144:ef7eb2e8f9f7 2936 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2937 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2938 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2939 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2940
<> 144:ef7eb2e8f9f7 2941 /* Check input state */
<> 144:ef7eb2e8f9f7 2942 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2943
<> 144:ef7eb2e8f9f7 2944 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2945
<> 144:ef7eb2e8f9f7 2946 switch (Channel)
<> 144:ef7eb2e8f9f7 2947 {
<> 144:ef7eb2e8f9f7 2948 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2949 {
<> 144:ef7eb2e8f9f7 2950 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2951 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 2952 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2953 }
<> 144:ef7eb2e8f9f7 2954 break;
<> 144:ef7eb2e8f9f7 2955
<> 144:ef7eb2e8f9f7 2956 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2957 {
<> 144:ef7eb2e8f9f7 2958 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2959 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 2960 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2961 }
<> 144:ef7eb2e8f9f7 2962 break;
<> 144:ef7eb2e8f9f7 2963
<> 144:ef7eb2e8f9f7 2964 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 2965 {
<> 144:ef7eb2e8f9f7 2966 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2967 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 2968 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2969 }
<> 144:ef7eb2e8f9f7 2970 break;
<> 144:ef7eb2e8f9f7 2971
<> 144:ef7eb2e8f9f7 2972 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 2973 {
<> 144:ef7eb2e8f9f7 2974 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2975 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 2976 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2977 }
<> 144:ef7eb2e8f9f7 2978 break;
<> 144:ef7eb2e8f9f7 2979
<> 144:ef7eb2e8f9f7 2980 default:
<> 144:ef7eb2e8f9f7 2981 break;
<> 144:ef7eb2e8f9f7 2982 }
<> 144:ef7eb2e8f9f7 2983 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2984
<> 144:ef7eb2e8f9f7 2985 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2986
<> 144:ef7eb2e8f9f7 2987 return HAL_OK;
<> 144:ef7eb2e8f9f7 2988 }
<> 144:ef7eb2e8f9f7 2989
<> 144:ef7eb2e8f9f7 2990 /**
<> 144:ef7eb2e8f9f7 2991 * @brief Initializes the TIM Input Capture Channels according to the specified
<> 144:ef7eb2e8f9f7 2992 * parameters in the TIM_IC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2993 * @param htim : TIM IC handle
<> 144:ef7eb2e8f9f7 2994 * @param sConfig : TIM Input Capture configuration structure
<> 144:ef7eb2e8f9f7 2995 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2996 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2997 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2998 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2999 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3000 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3001 * @retval HAL status
<> 144:ef7eb2e8f9f7 3002 */
<> 144:ef7eb2e8f9f7 3003 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3004 {
<> 144:ef7eb2e8f9f7 3005 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3006 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3007 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<> 144:ef7eb2e8f9f7 3008 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<> 144:ef7eb2e8f9f7 3009 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<> 144:ef7eb2e8f9f7 3010 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<> 144:ef7eb2e8f9f7 3011
<> 144:ef7eb2e8f9f7 3012 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3013
<> 144:ef7eb2e8f9f7 3014 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3015
<> 144:ef7eb2e8f9f7 3016 if (Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 3017 {
<> 144:ef7eb2e8f9f7 3018 /* TI1 Configuration */
<> 144:ef7eb2e8f9f7 3019 TIM_TI1_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3020 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3021 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3022 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3023
<> 144:ef7eb2e8f9f7 3024 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3025 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3026
<> 144:ef7eb2e8f9f7 3027 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 3028 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3029 }
<> 144:ef7eb2e8f9f7 3030 else if (Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 3031 {
<> 144:ef7eb2e8f9f7 3032 /* TI2 Configuration */
<> 144:ef7eb2e8f9f7 3033 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3034
<> 144:ef7eb2e8f9f7 3035 TIM_TI2_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3036 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3037 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3038 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3039
<> 144:ef7eb2e8f9f7 3040 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3041 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3042
<> 144:ef7eb2e8f9f7 3043 /* Set the IC2PSC value */
<> 156:95d6b41a828b 3044 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 3045 }
<> 144:ef7eb2e8f9f7 3046 else if (Channel == TIM_CHANNEL_3)
<> 144:ef7eb2e8f9f7 3047 {
<> 144:ef7eb2e8f9f7 3048 /* TI3 Configuration */
<> 144:ef7eb2e8f9f7 3049 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3050
<> 144:ef7eb2e8f9f7 3051 TIM_TI3_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3052 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3053 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3054 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3055
<> 144:ef7eb2e8f9f7 3056 /* Reset the IC3PSC Bits */
<> 144:ef7eb2e8f9f7 3057 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<> 144:ef7eb2e8f9f7 3058
<> 144:ef7eb2e8f9f7 3059 /* Set the IC3PSC value */
<> 144:ef7eb2e8f9f7 3060 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3061 }
<> 144:ef7eb2e8f9f7 3062 else
<> 144:ef7eb2e8f9f7 3063 {
<> 144:ef7eb2e8f9f7 3064 /* TI4 Configuration */
<> 144:ef7eb2e8f9f7 3065 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3066
<> 144:ef7eb2e8f9f7 3067 TIM_TI4_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3068 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3069 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3070 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3071
<> 144:ef7eb2e8f9f7 3072 /* Reset the IC4PSC Bits */
<> 144:ef7eb2e8f9f7 3073 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<> 144:ef7eb2e8f9f7 3074
<> 144:ef7eb2e8f9f7 3075 /* Set the IC4PSC value */
<> 156:95d6b41a828b 3076 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
<> 144:ef7eb2e8f9f7 3077 }
<> 144:ef7eb2e8f9f7 3078
<> 144:ef7eb2e8f9f7 3079 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3080
<> 144:ef7eb2e8f9f7 3081 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3082
<> 144:ef7eb2e8f9f7 3083 return HAL_OK;
<> 144:ef7eb2e8f9f7 3084 }
<> 144:ef7eb2e8f9f7 3085
<> 144:ef7eb2e8f9f7 3086 /**
<> 144:ef7eb2e8f9f7 3087 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 3088 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 3089 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3090 * @param sConfig : TIM PWM configuration structure
<> 144:ef7eb2e8f9f7 3091 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3092 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3093 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3094 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3095 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3096 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3097 * @retval HAL status
<> 144:ef7eb2e8f9f7 3098 */
<> 144:ef7eb2e8f9f7 3099 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3100 {
<> 144:ef7eb2e8f9f7 3101 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3102
<> 144:ef7eb2e8f9f7 3103 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3104 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3105 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 3106 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 3107 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 3108
<> 144:ef7eb2e8f9f7 3109 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3110
<> 144:ef7eb2e8f9f7 3111 switch (Channel)
<> 144:ef7eb2e8f9f7 3112 {
<> 144:ef7eb2e8f9f7 3113 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3114 {
<> 144:ef7eb2e8f9f7 3115 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3116 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 3117 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3118
<> 144:ef7eb2e8f9f7 3119 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 3120 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 3121
<> 144:ef7eb2e8f9f7 3122 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3123 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 3124 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3125 }
<> 144:ef7eb2e8f9f7 3126 break;
<> 144:ef7eb2e8f9f7 3127
<> 144:ef7eb2e8f9f7 3128 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3129 {
<> 144:ef7eb2e8f9f7 3130 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3131 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 3132 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3133
<> 144:ef7eb2e8f9f7 3134 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 3135 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 3136
<> 144:ef7eb2e8f9f7 3137 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3138 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 156:95d6b41a828b 3139 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3140 }
<> 144:ef7eb2e8f9f7 3141 break;
<> 144:ef7eb2e8f9f7 3142
<> 144:ef7eb2e8f9f7 3143 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3144 {
<> 144:ef7eb2e8f9f7 3145 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3146 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 3147 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3148
<> 144:ef7eb2e8f9f7 3149 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 3150 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 3151
<> 144:ef7eb2e8f9f7 3152 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3153 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 3154 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3155 }
<> 144:ef7eb2e8f9f7 3156 break;
<> 144:ef7eb2e8f9f7 3157
<> 144:ef7eb2e8f9f7 3158 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3159 {
<> 144:ef7eb2e8f9f7 3160 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3161 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 3162 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3163
<> 144:ef7eb2e8f9f7 3164 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 3165 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 3166
<> 144:ef7eb2e8f9f7 3167 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3168 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 156:95d6b41a828b 3169 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
<> 144:ef7eb2e8f9f7 3170 }
<> 144:ef7eb2e8f9f7 3171 break;
<> 144:ef7eb2e8f9f7 3172
<> 144:ef7eb2e8f9f7 3173 default:
<> 144:ef7eb2e8f9f7 3174 break;
<> 144:ef7eb2e8f9f7 3175 }
<> 144:ef7eb2e8f9f7 3176
<> 144:ef7eb2e8f9f7 3177 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3178
<> 144:ef7eb2e8f9f7 3179 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3180
<> 144:ef7eb2e8f9f7 3181 return HAL_OK;
<> 144:ef7eb2e8f9f7 3182 }
<> 144:ef7eb2e8f9f7 3183
<> 144:ef7eb2e8f9f7 3184 /**
<> 144:ef7eb2e8f9f7 3185 * @brief Initializes the TIM One Pulse Channels according to the specified
<> 144:ef7eb2e8f9f7 3186 * parameters in the TIM_OnePulse_InitTypeDef.
<> 144:ef7eb2e8f9f7 3187 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 3188 * @param sConfig : TIM One Pulse configuration structure
<> 144:ef7eb2e8f9f7 3189 * @param OutputChannel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3190 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3191 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3192 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3193 * @param InputChannel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3194 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3195 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3196 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3197 * @retval HAL status
<> 144:ef7eb2e8f9f7 3198 */
<> 144:ef7eb2e8f9f7 3199 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<> 144:ef7eb2e8f9f7 3200 {
<> 144:ef7eb2e8f9f7 3201 TIM_OC_InitTypeDef temp1;
<> 144:ef7eb2e8f9f7 3202
<> 144:ef7eb2e8f9f7 3203 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3204 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<> 144:ef7eb2e8f9f7 3205 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<> 144:ef7eb2e8f9f7 3206
<> 144:ef7eb2e8f9f7 3207 if(OutputChannel != InputChannel)
<> 144:ef7eb2e8f9f7 3208 {
<> 144:ef7eb2e8f9f7 3209 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3210
<> 144:ef7eb2e8f9f7 3211 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3212
<> 144:ef7eb2e8f9f7 3213 /* Extract the Ouput compare configuration from sConfig structure */
<> 144:ef7eb2e8f9f7 3214 temp1.OCMode = sConfig->OCMode;
<> 144:ef7eb2e8f9f7 3215 temp1.Pulse = sConfig->Pulse;
<> 144:ef7eb2e8f9f7 3216 temp1.OCPolarity = sConfig->OCPolarity;
<> 144:ef7eb2e8f9f7 3217 temp1.OCNPolarity = sConfig->OCNPolarity;
<> 144:ef7eb2e8f9f7 3218 temp1.OCIdleState = sConfig->OCIdleState;
<> 144:ef7eb2e8f9f7 3219 temp1.OCNIdleState = sConfig->OCNIdleState;
<> 144:ef7eb2e8f9f7 3220
<> 144:ef7eb2e8f9f7 3221 switch (OutputChannel)
<> 144:ef7eb2e8f9f7 3222 {
<> 144:ef7eb2e8f9f7 3223 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3224 {
<> 144:ef7eb2e8f9f7 3225 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3226
<> 144:ef7eb2e8f9f7 3227 TIM_OC1_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3228 }
<> 144:ef7eb2e8f9f7 3229 break;
<> 144:ef7eb2e8f9f7 3230 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3231 {
<> 144:ef7eb2e8f9f7 3232 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3233
<> 144:ef7eb2e8f9f7 3234 TIM_OC2_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3235 }
<> 144:ef7eb2e8f9f7 3236 break;
<> 144:ef7eb2e8f9f7 3237 default:
<> 144:ef7eb2e8f9f7 3238 break;
<> 144:ef7eb2e8f9f7 3239 }
<> 144:ef7eb2e8f9f7 3240 switch (InputChannel)
<> 144:ef7eb2e8f9f7 3241 {
<> 144:ef7eb2e8f9f7 3242 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3243 {
<> 144:ef7eb2e8f9f7 3244 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3245
<> 144:ef7eb2e8f9f7 3246 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3247 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3248
<> 144:ef7eb2e8f9f7 3249 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3250 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3251
<> 144:ef7eb2e8f9f7 3252 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3253 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3254 htim->Instance->SMCR |= TIM_TS_TI1FP1;
<> 144:ef7eb2e8f9f7 3255
<> 144:ef7eb2e8f9f7 3256 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3257 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3258 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3259 }
<> 144:ef7eb2e8f9f7 3260 break;
<> 144:ef7eb2e8f9f7 3261 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3262 {
<> 144:ef7eb2e8f9f7 3263 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3264
<> 144:ef7eb2e8f9f7 3265 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3266 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3267
<> 144:ef7eb2e8f9f7 3268 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3269 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3270
<> 144:ef7eb2e8f9f7 3271 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3272 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3273 htim->Instance->SMCR |= TIM_TS_TI2FP2;
<> 144:ef7eb2e8f9f7 3274
<> 144:ef7eb2e8f9f7 3275 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3276 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3277 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3278 }
<> 144:ef7eb2e8f9f7 3279 break;
<> 144:ef7eb2e8f9f7 3280
<> 144:ef7eb2e8f9f7 3281 default:
<> 144:ef7eb2e8f9f7 3282 break;
<> 144:ef7eb2e8f9f7 3283 }
<> 144:ef7eb2e8f9f7 3284
<> 144:ef7eb2e8f9f7 3285 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3286
<> 144:ef7eb2e8f9f7 3287 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3288
<> 144:ef7eb2e8f9f7 3289 return HAL_OK;
<> 144:ef7eb2e8f9f7 3290 }
<> 144:ef7eb2e8f9f7 3291 else
<> 144:ef7eb2e8f9f7 3292 {
<> 144:ef7eb2e8f9f7 3293 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3294 }
<> 144:ef7eb2e8f9f7 3295 }
<> 144:ef7eb2e8f9f7 3296
<> 144:ef7eb2e8f9f7 3297 /**
<> 144:ef7eb2e8f9f7 3298 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<> 144:ef7eb2e8f9f7 3299 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3300 * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
<> 144:ef7eb2e8f9f7 3301 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3302 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3303 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3304 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3305 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3306 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3307 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3308 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3309 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3310 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3311 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3312 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3313 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3314 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3315 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3316 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3317 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3318 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3319 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3320 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3321 * @param BurstRequestSrc : TIM DMA Request sources
<> 144:ef7eb2e8f9f7 3322 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3323 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3324 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3325 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3326 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3327 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3328 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3329 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3330 * @param BurstBuffer : The Buffer address.
<> 144:ef7eb2e8f9f7 3331 * @param BurstLength : DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3332 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3333 * @retval HAL status
<> 144:ef7eb2e8f9f7 3334 */
<> 144:ef7eb2e8f9f7 3335 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3336 uint32_t* BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3337 {
<> 144:ef7eb2e8f9f7 3338 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3339 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3340 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3341 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3342 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3343
<> 144:ef7eb2e8f9f7 3344 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3345 {
<> 144:ef7eb2e8f9f7 3346 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3347 }
<> 144:ef7eb2e8f9f7 3348 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3349 {
<> 156:95d6b41a828b 3350 if((BurstBuffer == 0U ) && (BurstLength > 0U))
<> 144:ef7eb2e8f9f7 3351 {
<> 144:ef7eb2e8f9f7 3352 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3353 }
<> 144:ef7eb2e8f9f7 3354 else
<> 144:ef7eb2e8f9f7 3355 {
<> 144:ef7eb2e8f9f7 3356 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3357 }
<> 144:ef7eb2e8f9f7 3358 }
<> 144:ef7eb2e8f9f7 3359 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3360 {
<> 144:ef7eb2e8f9f7 3361 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3362 {
<> 144:ef7eb2e8f9f7 3363 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3364 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3365
<> 144:ef7eb2e8f9f7 3366 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3367 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3368
<> 144:ef7eb2e8f9f7 3369 /* Enable the DMA channel */
<> 156:95d6b41a828b 3370 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3371 }
<> 144:ef7eb2e8f9f7 3372 break;
<> 144:ef7eb2e8f9f7 3373 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3374 {
<> 144:ef7eb2e8f9f7 3375 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3376 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3377
<> 144:ef7eb2e8f9f7 3378 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3379 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3380
<> 144:ef7eb2e8f9f7 3381 /* Enable the DMA channel */
<> 156:95d6b41a828b 3382 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3383 }
<> 144:ef7eb2e8f9f7 3384 break;
<> 144:ef7eb2e8f9f7 3385 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3386 {
<> 144:ef7eb2e8f9f7 3387 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3388 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3389
<> 144:ef7eb2e8f9f7 3390 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3391 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3392
<> 144:ef7eb2e8f9f7 3393 /* Enable the DMA channel */
<> 156:95d6b41a828b 3394 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3395 }
<> 144:ef7eb2e8f9f7 3396 break;
<> 144:ef7eb2e8f9f7 3397 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3398 {
<> 144:ef7eb2e8f9f7 3399 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3400 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3401
<> 144:ef7eb2e8f9f7 3402 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3403 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3404
<> 144:ef7eb2e8f9f7 3405 /* Enable the DMA channel */
<> 156:95d6b41a828b 3406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3407 }
<> 144:ef7eb2e8f9f7 3408 break;
<> 144:ef7eb2e8f9f7 3409 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3410 {
<> 144:ef7eb2e8f9f7 3411 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3412 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3413
<> 144:ef7eb2e8f9f7 3414 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3415 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3416
<> 144:ef7eb2e8f9f7 3417 /* Enable the DMA channel */
<> 156:95d6b41a828b 3418 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3419 }
<> 144:ef7eb2e8f9f7 3420 break;
<> 144:ef7eb2e8f9f7 3421 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3422 {
<> 144:ef7eb2e8f9f7 3423 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3424 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3425
<> 144:ef7eb2e8f9f7 3426 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3427 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3428
<> 144:ef7eb2e8f9f7 3429 /* Enable the DMA channel */
<> 156:95d6b41a828b 3430 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3431 }
<> 144:ef7eb2e8f9f7 3432 break;
<> 144:ef7eb2e8f9f7 3433 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3434 {
<> 144:ef7eb2e8f9f7 3435 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3436 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3437
<> 144:ef7eb2e8f9f7 3438 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3439 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3440
<> 144:ef7eb2e8f9f7 3441 /* Enable the DMA channel */
<> 156:95d6b41a828b 3442 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3443 }
<> 144:ef7eb2e8f9f7 3444 break;
<> 144:ef7eb2e8f9f7 3445 default:
<> 144:ef7eb2e8f9f7 3446 break;
<> 144:ef7eb2e8f9f7 3447 }
<> 144:ef7eb2e8f9f7 3448 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3449 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3450
<> 144:ef7eb2e8f9f7 3451 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3452 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3453
<> 144:ef7eb2e8f9f7 3454 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3455
<> 144:ef7eb2e8f9f7 3456 /* Return function status */
<> 144:ef7eb2e8f9f7 3457 return HAL_OK;
<> 144:ef7eb2e8f9f7 3458 }
<> 144:ef7eb2e8f9f7 3459
<> 144:ef7eb2e8f9f7 3460 /**
<> 144:ef7eb2e8f9f7 3461 * @brief Stops the TIM DMA Burst mode
<> 144:ef7eb2e8f9f7 3462 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3463 * @param BurstRequestSrc : TIM DMA Request sources to disable
<> 144:ef7eb2e8f9f7 3464 * @retval HAL status
<> 144:ef7eb2e8f9f7 3465 */
<> 144:ef7eb2e8f9f7 3466 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3467 {
<> 144:ef7eb2e8f9f7 3468 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3469 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3470
<> 144:ef7eb2e8f9f7 3471 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3472 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3473 {
<> 144:ef7eb2e8f9f7 3474 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3475 {
<> 144:ef7eb2e8f9f7 3476 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3477 }
<> 144:ef7eb2e8f9f7 3478 break;
<> 144:ef7eb2e8f9f7 3479 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3480 {
<> 144:ef7eb2e8f9f7 3481 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3482 }
<> 144:ef7eb2e8f9f7 3483 break;
<> 144:ef7eb2e8f9f7 3484 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3485 {
<> 144:ef7eb2e8f9f7 3486 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3487 }
<> 144:ef7eb2e8f9f7 3488 break;
<> 144:ef7eb2e8f9f7 3489 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3490 {
<> 144:ef7eb2e8f9f7 3491 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3492 }
<> 144:ef7eb2e8f9f7 3493 break;
<> 144:ef7eb2e8f9f7 3494 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3495 {
<> 144:ef7eb2e8f9f7 3496 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3497 }
<> 144:ef7eb2e8f9f7 3498 break;
<> 144:ef7eb2e8f9f7 3499 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3500 {
<> 144:ef7eb2e8f9f7 3501 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3502 }
<> 144:ef7eb2e8f9f7 3503 break;
<> 144:ef7eb2e8f9f7 3504 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3505 {
<> 144:ef7eb2e8f9f7 3506 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3507 }
<> 144:ef7eb2e8f9f7 3508 break;
<> 144:ef7eb2e8f9f7 3509 default:
<> 144:ef7eb2e8f9f7 3510 break;
<> 144:ef7eb2e8f9f7 3511 }
<> 144:ef7eb2e8f9f7 3512
<> 144:ef7eb2e8f9f7 3513 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3514 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3515
<> 144:ef7eb2e8f9f7 3516 /* Return function status */
<> 144:ef7eb2e8f9f7 3517 return HAL_OK;
<> 144:ef7eb2e8f9f7 3518 }
<> 144:ef7eb2e8f9f7 3519
<> 144:ef7eb2e8f9f7 3520 /**
<> 144:ef7eb2e8f9f7 3521 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<> 144:ef7eb2e8f9f7 3522 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3523 * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
<> 144:ef7eb2e8f9f7 3524 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3525 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3526 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3527 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3528 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3529 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3530 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3531 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3532 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3533 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3534 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3535 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3536 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3537 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3538 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3539 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3540 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3541 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3542 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3543 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3544 * @param BurstRequestSrc : TIM DMA Request sources
<> 144:ef7eb2e8f9f7 3545 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3546 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3547 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3548 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3549 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3550 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3551 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3552 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3553 * @param BurstBuffer : The Buffer address.
<> 144:ef7eb2e8f9f7 3554 * @param BurstLength : DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3555 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3556 * @retval HAL status
<> 144:ef7eb2e8f9f7 3557 */
<> 144:ef7eb2e8f9f7 3558 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3559 uint32_t *BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3560 {
<> 144:ef7eb2e8f9f7 3561 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3562 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3563 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3564 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3565 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3566
<> 144:ef7eb2e8f9f7 3567 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3568 {
<> 144:ef7eb2e8f9f7 3569 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3570 }
<> 144:ef7eb2e8f9f7 3571 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3572 {
<> 156:95d6b41a828b 3573 if((BurstBuffer == 0U ) && (BurstLength > 0U))
<> 144:ef7eb2e8f9f7 3574 {
<> 144:ef7eb2e8f9f7 3575 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3576 }
<> 144:ef7eb2e8f9f7 3577 else
<> 144:ef7eb2e8f9f7 3578 {
<> 144:ef7eb2e8f9f7 3579 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3580 }
<> 144:ef7eb2e8f9f7 3581 }
<> 144:ef7eb2e8f9f7 3582 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3583 {
<> 144:ef7eb2e8f9f7 3584 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3585 {
<> 144:ef7eb2e8f9f7 3586 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3587 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3588
<> 144:ef7eb2e8f9f7 3589 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3590 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3591
<> 144:ef7eb2e8f9f7 3592 /* Enable the DMA channel */
<> 156:95d6b41a828b 3593 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3594 }
<> 144:ef7eb2e8f9f7 3595 break;
<> 144:ef7eb2e8f9f7 3596 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3597 {
<> 144:ef7eb2e8f9f7 3598 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3599 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3600
<> 144:ef7eb2e8f9f7 3601 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3602 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3603
<> 144:ef7eb2e8f9f7 3604 /* Enable the DMA channel */
<> 156:95d6b41a828b 3605 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3606 }
<> 144:ef7eb2e8f9f7 3607 break;
<> 144:ef7eb2e8f9f7 3608 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3609 {
<> 144:ef7eb2e8f9f7 3610 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3611 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3612
<> 144:ef7eb2e8f9f7 3613 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3614 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3615
<> 144:ef7eb2e8f9f7 3616 /* Enable the DMA channel */
<> 156:95d6b41a828b 3617 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3618 }
<> 144:ef7eb2e8f9f7 3619 break;
<> 144:ef7eb2e8f9f7 3620 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3621 {
<> 144:ef7eb2e8f9f7 3622 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3623 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3624
<> 144:ef7eb2e8f9f7 3625 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3626 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3627
<> 144:ef7eb2e8f9f7 3628 /* Enable the DMA channel */
<> 156:95d6b41a828b 3629 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3630 }
<> 144:ef7eb2e8f9f7 3631 break;
<> 144:ef7eb2e8f9f7 3632 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3633 {
<> 144:ef7eb2e8f9f7 3634 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3635 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3636
<> 144:ef7eb2e8f9f7 3637 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3638 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3639
<> 144:ef7eb2e8f9f7 3640 /* Enable the DMA channel */
<> 156:95d6b41a828b 3641 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3642 }
<> 144:ef7eb2e8f9f7 3643 break;
<> 144:ef7eb2e8f9f7 3644 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3645 {
<> 144:ef7eb2e8f9f7 3646 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3647 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3648
<> 144:ef7eb2e8f9f7 3649 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3650 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3651
<> 144:ef7eb2e8f9f7 3652 /* Enable the DMA channel */
<> 156:95d6b41a828b 3653 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3654 }
<> 144:ef7eb2e8f9f7 3655 break;
<> 144:ef7eb2e8f9f7 3656 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3657 {
<> 144:ef7eb2e8f9f7 3658 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3659 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3660
<> 144:ef7eb2e8f9f7 3661 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3662 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3663
<> 144:ef7eb2e8f9f7 3664 /* Enable the DMA channel */
<> 156:95d6b41a828b 3665 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
<> 144:ef7eb2e8f9f7 3666 }
<> 144:ef7eb2e8f9f7 3667 break;
<> 144:ef7eb2e8f9f7 3668 default:
<> 144:ef7eb2e8f9f7 3669 break;
<> 144:ef7eb2e8f9f7 3670 }
<> 144:ef7eb2e8f9f7 3671
<> 144:ef7eb2e8f9f7 3672 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3673 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3674
<> 144:ef7eb2e8f9f7 3675 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3676 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3677
<> 144:ef7eb2e8f9f7 3678 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3679
<> 144:ef7eb2e8f9f7 3680 /* Return function status */
<> 144:ef7eb2e8f9f7 3681 return HAL_OK;
<> 144:ef7eb2e8f9f7 3682 }
<> 144:ef7eb2e8f9f7 3683
<> 144:ef7eb2e8f9f7 3684 /**
<> 144:ef7eb2e8f9f7 3685 * @brief Stop the DMA burst reading
<> 144:ef7eb2e8f9f7 3686 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3687 * @param BurstRequestSrc : TIM DMA Request sources to disable.
<> 144:ef7eb2e8f9f7 3688 * @retval HAL status
<> 144:ef7eb2e8f9f7 3689 */
<> 144:ef7eb2e8f9f7 3690 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3691 {
<> 144:ef7eb2e8f9f7 3692 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3693 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3694
<> 144:ef7eb2e8f9f7 3695 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3696 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3697 {
<> 144:ef7eb2e8f9f7 3698 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3699 {
<> 144:ef7eb2e8f9f7 3700 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3701 }
<> 144:ef7eb2e8f9f7 3702 break;
<> 144:ef7eb2e8f9f7 3703 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3704 {
<> 144:ef7eb2e8f9f7 3705 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3706 }
<> 144:ef7eb2e8f9f7 3707 break;
<> 144:ef7eb2e8f9f7 3708 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3709 {
<> 144:ef7eb2e8f9f7 3710 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3711 }
<> 144:ef7eb2e8f9f7 3712 break;
<> 144:ef7eb2e8f9f7 3713 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3714 {
<> 144:ef7eb2e8f9f7 3715 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3716 }
<> 144:ef7eb2e8f9f7 3717 break;
<> 144:ef7eb2e8f9f7 3718 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3719 {
<> 144:ef7eb2e8f9f7 3720 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3721 }
<> 144:ef7eb2e8f9f7 3722 break;
<> 144:ef7eb2e8f9f7 3723 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3724 {
<> 144:ef7eb2e8f9f7 3725 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3726 }
<> 144:ef7eb2e8f9f7 3727 break;
<> 144:ef7eb2e8f9f7 3728 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3729 {
<> 144:ef7eb2e8f9f7 3730 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3731 }
<> 144:ef7eb2e8f9f7 3732 break;
<> 144:ef7eb2e8f9f7 3733 default:
<> 144:ef7eb2e8f9f7 3734 break;
<> 144:ef7eb2e8f9f7 3735 }
<> 144:ef7eb2e8f9f7 3736
<> 144:ef7eb2e8f9f7 3737 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3738 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3739
<> 144:ef7eb2e8f9f7 3740 /* Return function status */
<> 144:ef7eb2e8f9f7 3741 return HAL_OK;
<> 144:ef7eb2e8f9f7 3742 }
<> 144:ef7eb2e8f9f7 3743
<> 144:ef7eb2e8f9f7 3744 /**
<> 144:ef7eb2e8f9f7 3745 * @brief Generate a software event
<> 144:ef7eb2e8f9f7 3746 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3747 * @param EventSource : specifies the event source.
<> 144:ef7eb2e8f9f7 3748 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3749 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<> 144:ef7eb2e8f9f7 3750 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<> 144:ef7eb2e8f9f7 3751 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<> 144:ef7eb2e8f9f7 3752 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<> 144:ef7eb2e8f9f7 3753 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<> 144:ef7eb2e8f9f7 3754 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
<> 144:ef7eb2e8f9f7 3755 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<> 144:ef7eb2e8f9f7 3756 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<> 144:ef7eb2e8f9f7 3757 * @note TIM6 and TIM7 can only generate an update event.
<> 144:ef7eb2e8f9f7 3758 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
<> 144:ef7eb2e8f9f7 3759 * @retval HAL status
<> 144:ef7eb2e8f9f7 3760 */
<> 144:ef7eb2e8f9f7 3761
<> 144:ef7eb2e8f9f7 3762 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<> 144:ef7eb2e8f9f7 3763 {
<> 144:ef7eb2e8f9f7 3764 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3765 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3766 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<> 144:ef7eb2e8f9f7 3767
<> 144:ef7eb2e8f9f7 3768 /* Process Locked */
<> 144:ef7eb2e8f9f7 3769 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3770
<> 144:ef7eb2e8f9f7 3771 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3772 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3773
<> 144:ef7eb2e8f9f7 3774 /* Set the event sources */
<> 144:ef7eb2e8f9f7 3775 htim->Instance->EGR = EventSource;
<> 144:ef7eb2e8f9f7 3776
<> 144:ef7eb2e8f9f7 3777 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3778 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3779
<> 144:ef7eb2e8f9f7 3780 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3781
<> 144:ef7eb2e8f9f7 3782 /* Return function status */
<> 144:ef7eb2e8f9f7 3783 return HAL_OK;
<> 144:ef7eb2e8f9f7 3784 }
<> 144:ef7eb2e8f9f7 3785
<> 144:ef7eb2e8f9f7 3786 /**
<> 144:ef7eb2e8f9f7 3787 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 3788 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3789 * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3790 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3791 * @param Channel : specifies the TIM Channel
<> 144:ef7eb2e8f9f7 3792 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3793 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 3794 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 3795 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 3796 * @arg TIM_CHANNEL_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 3797 * @retval HAL status
<> 144:ef7eb2e8f9f7 3798 */
<> 144:ef7eb2e8f9f7 3799 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3800 {
<> 144:ef7eb2e8f9f7 3801 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 3802
<> 144:ef7eb2e8f9f7 3803 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3804 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3805 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 3806 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 3807 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 3808 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 3809
<> 144:ef7eb2e8f9f7 3810 /* Process Locked */
<> 144:ef7eb2e8f9f7 3811 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3812
<> 144:ef7eb2e8f9f7 3813 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3814
<> 144:ef7eb2e8f9f7 3815 switch (sClearInputConfig->ClearInputSource)
<> 144:ef7eb2e8f9f7 3816 {
<> 144:ef7eb2e8f9f7 3817 case TIM_CLEARINPUTSOURCE_NONE:
<> 144:ef7eb2e8f9f7 3818 {
<> 144:ef7eb2e8f9f7 3819 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 3820 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3821
<> 144:ef7eb2e8f9f7 3822 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 3823 tmpsmcr &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 3824
<> 144:ef7eb2e8f9f7 3825 /* Clear the ETR Bits */
<> 144:ef7eb2e8f9f7 3826 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 3827
<> 144:ef7eb2e8f9f7 3828 /* Set TIMx_SMCR */
<> 144:ef7eb2e8f9f7 3829 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3830 }
<> 144:ef7eb2e8f9f7 3831 break;
<> 144:ef7eb2e8f9f7 3832
<> 144:ef7eb2e8f9f7 3833 case TIM_CLEARINPUTSOURCE_ETR:
<> 144:ef7eb2e8f9f7 3834 {
<> 144:ef7eb2e8f9f7 3835 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3836 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 3837 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 3838 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 3839
<> 144:ef7eb2e8f9f7 3840 /* Set the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 3841 htim->Instance->SMCR |= TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 3842 }
<> 144:ef7eb2e8f9f7 3843 break;
<> 144:ef7eb2e8f9f7 3844 default:
<> 144:ef7eb2e8f9f7 3845 break;
<> 144:ef7eb2e8f9f7 3846 }
<> 144:ef7eb2e8f9f7 3847
<> 144:ef7eb2e8f9f7 3848 switch (Channel)
<> 144:ef7eb2e8f9f7 3849 {
<> 144:ef7eb2e8f9f7 3850 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3851 {
<> 144:ef7eb2e8f9f7 3852 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3853 {
<> 144:ef7eb2e8f9f7 3854 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3855 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3856 }
<> 144:ef7eb2e8f9f7 3857 else
<> 144:ef7eb2e8f9f7 3858 {
<> 144:ef7eb2e8f9f7 3859 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3860 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3861 }
<> 144:ef7eb2e8f9f7 3862 }
<> 144:ef7eb2e8f9f7 3863 break;
<> 144:ef7eb2e8f9f7 3864 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3865 {
<> 144:ef7eb2e8f9f7 3866 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3867 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3868 {
<> 144:ef7eb2e8f9f7 3869 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3870 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3871 }
<> 144:ef7eb2e8f9f7 3872 else
<> 144:ef7eb2e8f9f7 3873 {
<> 144:ef7eb2e8f9f7 3874 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3875 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3876 }
<> 144:ef7eb2e8f9f7 3877 }
<> 144:ef7eb2e8f9f7 3878 break;
<> 144:ef7eb2e8f9f7 3879 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3880 {
<> 144:ef7eb2e8f9f7 3881 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3882 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3883 {
<> 144:ef7eb2e8f9f7 3884 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3885 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3886 }
<> 144:ef7eb2e8f9f7 3887 else
<> 144:ef7eb2e8f9f7 3888 {
<> 144:ef7eb2e8f9f7 3889 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3890 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3891 }
<> 144:ef7eb2e8f9f7 3892 }
<> 144:ef7eb2e8f9f7 3893 break;
<> 144:ef7eb2e8f9f7 3894 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3895 {
<> 144:ef7eb2e8f9f7 3896 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3897 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3898 {
<> 144:ef7eb2e8f9f7 3899 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3900 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3901 }
<> 144:ef7eb2e8f9f7 3902 else
<> 144:ef7eb2e8f9f7 3903 {
<> 144:ef7eb2e8f9f7 3904 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3905 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3906 }
<> 144:ef7eb2e8f9f7 3907 }
<> 144:ef7eb2e8f9f7 3908 break;
<> 144:ef7eb2e8f9f7 3909 default:
<> 144:ef7eb2e8f9f7 3910 break;
<> 144:ef7eb2e8f9f7 3911 }
<> 144:ef7eb2e8f9f7 3912
<> 144:ef7eb2e8f9f7 3913 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3914
<> 144:ef7eb2e8f9f7 3915 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3916
<> 144:ef7eb2e8f9f7 3917 return HAL_OK;
<> 144:ef7eb2e8f9f7 3918 }
<> 144:ef7eb2e8f9f7 3919
<> 144:ef7eb2e8f9f7 3920 /**
<> 144:ef7eb2e8f9f7 3921 * @brief Configures the clock source to be used
<> 144:ef7eb2e8f9f7 3922 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 3923 * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3924 * contains the clock source information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3925 * @retval HAL status
<> 144:ef7eb2e8f9f7 3926 */
<> 144:ef7eb2e8f9f7 3927 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
<> 144:ef7eb2e8f9f7 3928 {
<> 156:95d6b41a828b 3929 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 3930
<> 144:ef7eb2e8f9f7 3931 /* Process Locked */
<> 144:ef7eb2e8f9f7 3932 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3933
<> 144:ef7eb2e8f9f7 3934 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3935
<> 144:ef7eb2e8f9f7 3936 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3937 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<> 144:ef7eb2e8f9f7 3938
<> 144:ef7eb2e8f9f7 3939 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<> 144:ef7eb2e8f9f7 3940 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3941 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3942 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 3943 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3944
<> 144:ef7eb2e8f9f7 3945 switch (sClockSourceConfig->ClockSource)
<> 144:ef7eb2e8f9f7 3946 {
<> 144:ef7eb2e8f9f7 3947 case TIM_CLOCKSOURCE_INTERNAL:
<> 144:ef7eb2e8f9f7 3948 {
<> 144:ef7eb2e8f9f7 3949 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3950 /* Disable slave mode to clock the prescaler directly with the internal clock */
<> 144:ef7eb2e8f9f7 3951 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3952 }
<> 144:ef7eb2e8f9f7 3953 break;
<> 144:ef7eb2e8f9f7 3954
<> 144:ef7eb2e8f9f7 3955 case TIM_CLOCKSOURCE_ETRMODE1:
<> 144:ef7eb2e8f9f7 3956 {
<> 144:ef7eb2e8f9f7 3957 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
<> 144:ef7eb2e8f9f7 3958 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3959
<> 144:ef7eb2e8f9f7 3960 /* Check ETR input conditioning related parameters */
<> 144:ef7eb2e8f9f7 3961 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3962 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3963 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3964
<> 144:ef7eb2e8f9f7 3965 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3966 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3967 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3968 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3969 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3970 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 3971 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3972 /* Reset the SMS and TS Bits */
<> 144:ef7eb2e8f9f7 3973 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3974 /* Select the External clock mode1 and the ETRF trigger */
<> 144:ef7eb2e8f9f7 3975 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
<> 144:ef7eb2e8f9f7 3976 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 3977 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3978 }
<> 144:ef7eb2e8f9f7 3979 break;
<> 144:ef7eb2e8f9f7 3980
<> 144:ef7eb2e8f9f7 3981 case TIM_CLOCKSOURCE_ETRMODE2:
<> 144:ef7eb2e8f9f7 3982 {
<> 144:ef7eb2e8f9f7 3983 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
<> 144:ef7eb2e8f9f7 3984 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3985
<> 144:ef7eb2e8f9f7 3986 /* Check ETR input conditioning related parameters */
<> 144:ef7eb2e8f9f7 3987 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3988 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3989 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3990
<> 144:ef7eb2e8f9f7 3991 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3992 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3993 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3994 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3995 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3996 /* Enable the External clock mode2 */
<> 144:ef7eb2e8f9f7 3997 htim->Instance->SMCR |= TIM_SMCR_ECE;
<> 144:ef7eb2e8f9f7 3998 }
<> 144:ef7eb2e8f9f7 3999 break;
<> 144:ef7eb2e8f9f7 4000
<> 144:ef7eb2e8f9f7 4001 case TIM_CLOCKSOURCE_TI1:
<> 144:ef7eb2e8f9f7 4002 {
<> 144:ef7eb2e8f9f7 4003 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4004 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4005
<> 144:ef7eb2e8f9f7 4006 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4007 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4008 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4009
<> 144:ef7eb2e8f9f7 4010 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4011 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4012 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4013 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<> 144:ef7eb2e8f9f7 4014 }
<> 144:ef7eb2e8f9f7 4015 break;
<> 144:ef7eb2e8f9f7 4016 case TIM_CLOCKSOURCE_TI2:
<> 144:ef7eb2e8f9f7 4017 {
<> 144:ef7eb2e8f9f7 4018 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
<> 144:ef7eb2e8f9f7 4019 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4020
<> 144:ef7eb2e8f9f7 4021 /* Check TI2 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4022 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4023 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4024
<> 144:ef7eb2e8f9f7 4025 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4026 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4027 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4028 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<> 144:ef7eb2e8f9f7 4029 }
<> 144:ef7eb2e8f9f7 4030 break;
<> 144:ef7eb2e8f9f7 4031 case TIM_CLOCKSOURCE_TI1ED:
<> 144:ef7eb2e8f9f7 4032 {
<> 144:ef7eb2e8f9f7 4033 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4034 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4035
<> 144:ef7eb2e8f9f7 4036 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4037 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4038 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4039
<> 144:ef7eb2e8f9f7 4040 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4041 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4042 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4043 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<> 144:ef7eb2e8f9f7 4044 }
<> 144:ef7eb2e8f9f7 4045 break;
<> 144:ef7eb2e8f9f7 4046 case TIM_CLOCKSOURCE_ITR0:
<> 144:ef7eb2e8f9f7 4047 {
<> 144:ef7eb2e8f9f7 4048 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4049 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4050
<> 144:ef7eb2e8f9f7 4051 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<> 144:ef7eb2e8f9f7 4052 }
<> 144:ef7eb2e8f9f7 4053 break;
<> 144:ef7eb2e8f9f7 4054 case TIM_CLOCKSOURCE_ITR1:
<> 144:ef7eb2e8f9f7 4055 {
<> 144:ef7eb2e8f9f7 4056 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4057 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4058
<> 144:ef7eb2e8f9f7 4059 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<> 144:ef7eb2e8f9f7 4060 }
<> 144:ef7eb2e8f9f7 4061 break;
<> 144:ef7eb2e8f9f7 4062 case TIM_CLOCKSOURCE_ITR2:
<> 144:ef7eb2e8f9f7 4063 {
<> 144:ef7eb2e8f9f7 4064 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4065 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4066
<> 144:ef7eb2e8f9f7 4067 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<> 144:ef7eb2e8f9f7 4068 }
<> 144:ef7eb2e8f9f7 4069 break;
<> 144:ef7eb2e8f9f7 4070 case TIM_CLOCKSOURCE_ITR3:
<> 144:ef7eb2e8f9f7 4071 {
<> 144:ef7eb2e8f9f7 4072 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4073 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4074
<> 144:ef7eb2e8f9f7 4075 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<> 144:ef7eb2e8f9f7 4076 }
<> 144:ef7eb2e8f9f7 4077 break;
<> 144:ef7eb2e8f9f7 4078
<> 144:ef7eb2e8f9f7 4079 default:
<> 144:ef7eb2e8f9f7 4080 break;
<> 144:ef7eb2e8f9f7 4081 }
<> 144:ef7eb2e8f9f7 4082 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4083
<> 144:ef7eb2e8f9f7 4084 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4085
<> 144:ef7eb2e8f9f7 4086 return HAL_OK;
<> 144:ef7eb2e8f9f7 4087 }
<> 144:ef7eb2e8f9f7 4088
<> 144:ef7eb2e8f9f7 4089 /**
<> 144:ef7eb2e8f9f7 4090 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
<> 144:ef7eb2e8f9f7 4091 * or a XOR combination between CH1_input, CH2_input & CH3_input
<> 144:ef7eb2e8f9f7 4092 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 4093 * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
<> 144:ef7eb2e8f9f7 4094 * output of a XOR gate.
<> 144:ef7eb2e8f9f7 4095 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4096 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<> 144:ef7eb2e8f9f7 4097 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<> 144:ef7eb2e8f9f7 4098 * pins are connected to the TI1 input (XOR combination)
<> 144:ef7eb2e8f9f7 4099 * @retval HAL status
<> 144:ef7eb2e8f9f7 4100 */
<> 144:ef7eb2e8f9f7 4101 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<> 144:ef7eb2e8f9f7 4102 {
<> 156:95d6b41a828b 4103 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4104
<> 144:ef7eb2e8f9f7 4105 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4106 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4107 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<> 144:ef7eb2e8f9f7 4108
<> 144:ef7eb2e8f9f7 4109 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4110 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 4111
<> 144:ef7eb2e8f9f7 4112 /* Reset the TI1 selection */
<> 144:ef7eb2e8f9f7 4113 tmpcr2 &= ~TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 4114
<> 144:ef7eb2e8f9f7 4115 /* Set the the TI1 selection */
<> 144:ef7eb2e8f9f7 4116 tmpcr2 |= TI1_Selection;
<> 144:ef7eb2e8f9f7 4117
<> 144:ef7eb2e8f9f7 4118 /* Write to TIMxCR2 */
<> 144:ef7eb2e8f9f7 4119 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4120
<> 144:ef7eb2e8f9f7 4121 return HAL_OK;
<> 144:ef7eb2e8f9f7 4122 }
<> 144:ef7eb2e8f9f7 4123
<> 144:ef7eb2e8f9f7 4124 /**
<> 144:ef7eb2e8f9f7 4125 * @brief Configures the TIM in Slave mode
<> 144:ef7eb2e8f9f7 4126 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 4127 * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4128 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4129 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4130 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4131 * @retval HAL status
<> 144:ef7eb2e8f9f7 4132 */
<> 144:ef7eb2e8f9f7 4133 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4134 {
<> 144:ef7eb2e8f9f7 4135 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4136 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4137 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4138 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4139
<> 144:ef7eb2e8f9f7 4140 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4141
<> 144:ef7eb2e8f9f7 4142 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4143
<> 144:ef7eb2e8f9f7 4144 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4145
<> 144:ef7eb2e8f9f7 4146 /* Disable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4147 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4148
<> 144:ef7eb2e8f9f7 4149 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4150 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4151
<> 144:ef7eb2e8f9f7 4152 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4153
<> 144:ef7eb2e8f9f7 4154 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4155
<> 144:ef7eb2e8f9f7 4156 return HAL_OK;
<> 144:ef7eb2e8f9f7 4157 }
<> 144:ef7eb2e8f9f7 4158
<> 144:ef7eb2e8f9f7 4159 /**
<> 144:ef7eb2e8f9f7 4160 * @brief Configures the TIM in Slave mode in interrupt mode
<> 144:ef7eb2e8f9f7 4161 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 4162 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4163 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4164 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4165 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4166 * @retval HAL status
<> 144:ef7eb2e8f9f7 4167 */
<> 144:ef7eb2e8f9f7 4168 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4169 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4170 {
<> 144:ef7eb2e8f9f7 4171 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4172 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4173 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4174 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4175
<> 144:ef7eb2e8f9f7 4176 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4177
<> 144:ef7eb2e8f9f7 4178 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4179
<> 144:ef7eb2e8f9f7 4180 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4181
<> 144:ef7eb2e8f9f7 4182 /* Enable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4183 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4184
<> 144:ef7eb2e8f9f7 4185 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4186 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4187
<> 144:ef7eb2e8f9f7 4188 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4189
<> 144:ef7eb2e8f9f7 4190 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4191
<> 144:ef7eb2e8f9f7 4192 return HAL_OK;
<> 144:ef7eb2e8f9f7 4193 }
<> 144:ef7eb2e8f9f7 4194
<> 144:ef7eb2e8f9f7 4195 /**
<> 144:ef7eb2e8f9f7 4196 * @brief Read the captured value from Capture Compare unit
<> 144:ef7eb2e8f9f7 4197 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 4198 * @param Channel : TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 4199 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4200 * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 4201 * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 4202 * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 4203 * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 4204 * @retval Captured value
<> 144:ef7eb2e8f9f7 4205 */
<> 144:ef7eb2e8f9f7 4206 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 4207 {
<> 156:95d6b41a828b 4208 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 4209
<> 144:ef7eb2e8f9f7 4210 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4211
<> 144:ef7eb2e8f9f7 4212 switch (Channel)
<> 144:ef7eb2e8f9f7 4213 {
<> 144:ef7eb2e8f9f7 4214 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 4215 {
<> 144:ef7eb2e8f9f7 4216 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4217 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4218
<> 144:ef7eb2e8f9f7 4219 /* Return the capture 1 value */
<> 144:ef7eb2e8f9f7 4220 tmpreg = htim->Instance->CCR1;
<> 144:ef7eb2e8f9f7 4221
<> 144:ef7eb2e8f9f7 4222 break;
<> 144:ef7eb2e8f9f7 4223 }
<> 144:ef7eb2e8f9f7 4224 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 4225 {
<> 144:ef7eb2e8f9f7 4226 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4227 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4228
<> 144:ef7eb2e8f9f7 4229 /* Return the capture 2 value */
<> 144:ef7eb2e8f9f7 4230 tmpreg = htim->Instance->CCR2;
<> 144:ef7eb2e8f9f7 4231
<> 144:ef7eb2e8f9f7 4232 break;
<> 144:ef7eb2e8f9f7 4233 }
<> 144:ef7eb2e8f9f7 4234
<> 144:ef7eb2e8f9f7 4235 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 4236 {
<> 144:ef7eb2e8f9f7 4237 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4238 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4239
<> 144:ef7eb2e8f9f7 4240 /* Return the capture 3 value */
<> 144:ef7eb2e8f9f7 4241 tmpreg = htim->Instance->CCR3;
<> 144:ef7eb2e8f9f7 4242
<> 144:ef7eb2e8f9f7 4243 break;
<> 144:ef7eb2e8f9f7 4244 }
<> 144:ef7eb2e8f9f7 4245
<> 144:ef7eb2e8f9f7 4246 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 4247 {
<> 144:ef7eb2e8f9f7 4248 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4249 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4250
<> 144:ef7eb2e8f9f7 4251 /* Return the capture 4 value */
<> 144:ef7eb2e8f9f7 4252 tmpreg = htim->Instance->CCR4;
<> 144:ef7eb2e8f9f7 4253
<> 144:ef7eb2e8f9f7 4254 break;
<> 144:ef7eb2e8f9f7 4255 }
<> 144:ef7eb2e8f9f7 4256
<> 144:ef7eb2e8f9f7 4257 default:
<> 144:ef7eb2e8f9f7 4258 break;
<> 144:ef7eb2e8f9f7 4259 }
<> 144:ef7eb2e8f9f7 4260
<> 144:ef7eb2e8f9f7 4261 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4262 return tmpreg;
<> 144:ef7eb2e8f9f7 4263 }
<> 144:ef7eb2e8f9f7 4264
<> 144:ef7eb2e8f9f7 4265 /**
<> 144:ef7eb2e8f9f7 4266 * @}
<> 144:ef7eb2e8f9f7 4267 */
<> 144:ef7eb2e8f9f7 4268
<> 144:ef7eb2e8f9f7 4269 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4270 * @brief TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4271 *
<> 144:ef7eb2e8f9f7 4272 @verbatim
<> 144:ef7eb2e8f9f7 4273 ==============================================================================
<> 144:ef7eb2e8f9f7 4274 ##### TIM Callbacks functions #####
<> 144:ef7eb2e8f9f7 4275 ==============================================================================
<> 144:ef7eb2e8f9f7 4276 [..]
<> 144:ef7eb2e8f9f7 4277 This section provides TIM callback functions:
<> 144:ef7eb2e8f9f7 4278 (+) Timer Period elapsed callback
<> 144:ef7eb2e8f9f7 4279 (+) Timer Output Compare callback
<> 144:ef7eb2e8f9f7 4280 (+) Timer Input capture callback
<> 144:ef7eb2e8f9f7 4281 (+) Timer Trigger callback
<> 144:ef7eb2e8f9f7 4282 (+) Timer Error callback
<> 144:ef7eb2e8f9f7 4283
<> 144:ef7eb2e8f9f7 4284 @endverbatim
<> 144:ef7eb2e8f9f7 4285 * @{
<> 144:ef7eb2e8f9f7 4286 */
<> 144:ef7eb2e8f9f7 4287
<> 144:ef7eb2e8f9f7 4288 /**
<> 144:ef7eb2e8f9f7 4289 * @brief Period elapsed callback in non blocking mode
<> 144:ef7eb2e8f9f7 4290 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4291 * @retval None
<> 144:ef7eb2e8f9f7 4292 */
<> 144:ef7eb2e8f9f7 4293 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4294 {
<> 144:ef7eb2e8f9f7 4295 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4296 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4297
<> 144:ef7eb2e8f9f7 4298 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4299 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4300 */
<> 144:ef7eb2e8f9f7 4301
<> 144:ef7eb2e8f9f7 4302 }
<> 144:ef7eb2e8f9f7 4303 /**
<> 144:ef7eb2e8f9f7 4304 * @brief Output Compare callback in non blocking mode
<> 144:ef7eb2e8f9f7 4305 * @param htim : TIM OC handle
<> 144:ef7eb2e8f9f7 4306 * @retval None
<> 144:ef7eb2e8f9f7 4307 */
<> 144:ef7eb2e8f9f7 4308 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4309 {
<> 144:ef7eb2e8f9f7 4310 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4311 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4312
<> 144:ef7eb2e8f9f7 4313 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4314 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4315 */
<> 144:ef7eb2e8f9f7 4316 }
<> 144:ef7eb2e8f9f7 4317 /**
<> 144:ef7eb2e8f9f7 4318 * @brief Input Capture callback in non blocking mode
<> 144:ef7eb2e8f9f7 4319 * @param htim : TIM IC handle
<> 144:ef7eb2e8f9f7 4320 * @retval None
<> 144:ef7eb2e8f9f7 4321 */
<> 144:ef7eb2e8f9f7 4322 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4323 {
<> 144:ef7eb2e8f9f7 4324 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4325 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4326
<> 144:ef7eb2e8f9f7 4327 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4328 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4329 */
<> 144:ef7eb2e8f9f7 4330 }
<> 144:ef7eb2e8f9f7 4331
<> 144:ef7eb2e8f9f7 4332 /**
<> 144:ef7eb2e8f9f7 4333 * @brief PWM Pulse finished callback in non blocking mode
<> 144:ef7eb2e8f9f7 4334 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4335 * @retval None
<> 144:ef7eb2e8f9f7 4336 */
<> 144:ef7eb2e8f9f7 4337 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4338 {
<> 144:ef7eb2e8f9f7 4339 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4340 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4341
<> 144:ef7eb2e8f9f7 4342 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4343 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4344 */
<> 144:ef7eb2e8f9f7 4345 }
<> 144:ef7eb2e8f9f7 4346
<> 144:ef7eb2e8f9f7 4347 /**
<> 144:ef7eb2e8f9f7 4348 * @brief Hall Trigger detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 4349 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4350 * @retval None
<> 144:ef7eb2e8f9f7 4351 */
<> 144:ef7eb2e8f9f7 4352 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4353 {
<> 144:ef7eb2e8f9f7 4354 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4355 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4356
<> 144:ef7eb2e8f9f7 4357 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4358 the HAL_TIM_TriggerCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4359 */
<> 144:ef7eb2e8f9f7 4360 }
<> 144:ef7eb2e8f9f7 4361
<> 144:ef7eb2e8f9f7 4362 /**
<> 144:ef7eb2e8f9f7 4363 * @brief Timer error callback in non blocking mode
<> 144:ef7eb2e8f9f7 4364 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4365 * @retval None
<> 144:ef7eb2e8f9f7 4366 */
<> 144:ef7eb2e8f9f7 4367 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4368 {
<> 144:ef7eb2e8f9f7 4369 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4370 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4371
<> 144:ef7eb2e8f9f7 4372 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4373 the HAL_TIM_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4374 */
<> 144:ef7eb2e8f9f7 4375 }
<> 144:ef7eb2e8f9f7 4376
<> 144:ef7eb2e8f9f7 4377 /**
<> 144:ef7eb2e8f9f7 4378 * @}
<> 144:ef7eb2e8f9f7 4379 */
<> 144:ef7eb2e8f9f7 4380
<> 144:ef7eb2e8f9f7 4381 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<> 144:ef7eb2e8f9f7 4382 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 4383 *
<> 144:ef7eb2e8f9f7 4384 @verbatim
<> 144:ef7eb2e8f9f7 4385 ==============================================================================
<> 144:ef7eb2e8f9f7 4386 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 4387 ==============================================================================
<> 144:ef7eb2e8f9f7 4388 [..]
<> 144:ef7eb2e8f9f7 4389 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 4390 and the data flow.
<> 144:ef7eb2e8f9f7 4391
<> 144:ef7eb2e8f9f7 4392 @endverbatim
<> 144:ef7eb2e8f9f7 4393 * @{
<> 144:ef7eb2e8f9f7 4394 */
<> 144:ef7eb2e8f9f7 4395
<> 144:ef7eb2e8f9f7 4396 /**
<> 144:ef7eb2e8f9f7 4397 * @brief Return the TIM Base state
<> 144:ef7eb2e8f9f7 4398 * @param htim : TIM Base handle
<> 144:ef7eb2e8f9f7 4399 * @retval HAL state
<> 144:ef7eb2e8f9f7 4400 */
<> 144:ef7eb2e8f9f7 4401 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4402 {
<> 144:ef7eb2e8f9f7 4403 return htim->State;
<> 144:ef7eb2e8f9f7 4404 }
<> 144:ef7eb2e8f9f7 4405
<> 144:ef7eb2e8f9f7 4406 /**
<> 144:ef7eb2e8f9f7 4407 * @brief Return the TIM OC state
<> 144:ef7eb2e8f9f7 4408 * @param htim : TIM Ouput Compare handle
<> 144:ef7eb2e8f9f7 4409 * @retval HAL state
<> 144:ef7eb2e8f9f7 4410 */
<> 144:ef7eb2e8f9f7 4411 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4412 {
<> 144:ef7eb2e8f9f7 4413 return htim->State;
<> 144:ef7eb2e8f9f7 4414 }
<> 144:ef7eb2e8f9f7 4415
<> 144:ef7eb2e8f9f7 4416 /**
<> 144:ef7eb2e8f9f7 4417 * @brief Return the TIM PWM state
<> 144:ef7eb2e8f9f7 4418 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 4419 * @retval HAL state
<> 144:ef7eb2e8f9f7 4420 */
<> 144:ef7eb2e8f9f7 4421 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4422 {
<> 144:ef7eb2e8f9f7 4423 return htim->State;
<> 144:ef7eb2e8f9f7 4424 }
<> 144:ef7eb2e8f9f7 4425
<> 144:ef7eb2e8f9f7 4426 /**
<> 144:ef7eb2e8f9f7 4427 * @brief Return the TIM Input Capture state
<> 144:ef7eb2e8f9f7 4428 * @param htim : TIM IC handle
<> 144:ef7eb2e8f9f7 4429 * @retval HAL state
<> 144:ef7eb2e8f9f7 4430 */
<> 144:ef7eb2e8f9f7 4431 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4432 {
<> 144:ef7eb2e8f9f7 4433 return htim->State;
<> 144:ef7eb2e8f9f7 4434 }
<> 144:ef7eb2e8f9f7 4435
<> 144:ef7eb2e8f9f7 4436 /**
<> 144:ef7eb2e8f9f7 4437 * @brief Return the TIM One Pulse Mode state
<> 144:ef7eb2e8f9f7 4438 * @param htim : TIM OPM handle
<> 144:ef7eb2e8f9f7 4439 * @retval HAL state
<> 144:ef7eb2e8f9f7 4440 */
<> 144:ef7eb2e8f9f7 4441 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4442 {
<> 144:ef7eb2e8f9f7 4443 return htim->State;
<> 144:ef7eb2e8f9f7 4444 }
<> 144:ef7eb2e8f9f7 4445
<> 144:ef7eb2e8f9f7 4446 /**
<> 144:ef7eb2e8f9f7 4447 * @brief Return the TIM Encoder Mode state
<> 144:ef7eb2e8f9f7 4448 * @param htim : TIM Encoder handle
<> 144:ef7eb2e8f9f7 4449 * @retval HAL state
<> 144:ef7eb2e8f9f7 4450 */
<> 144:ef7eb2e8f9f7 4451 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4452 {
<> 144:ef7eb2e8f9f7 4453 return htim->State;
<> 144:ef7eb2e8f9f7 4454 }
<> 144:ef7eb2e8f9f7 4455
<> 144:ef7eb2e8f9f7 4456 /**
<> 144:ef7eb2e8f9f7 4457 * @}
<> 144:ef7eb2e8f9f7 4458 */
<> 144:ef7eb2e8f9f7 4459
<> 144:ef7eb2e8f9f7 4460 /**
<> 144:ef7eb2e8f9f7 4461 * @}
<> 144:ef7eb2e8f9f7 4462 */
<> 144:ef7eb2e8f9f7 4463
<> 144:ef7eb2e8f9f7 4464 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
<> 144:ef7eb2e8f9f7 4465 * @{
<> 144:ef7eb2e8f9f7 4466 */
<> 144:ef7eb2e8f9f7 4467
<> 144:ef7eb2e8f9f7 4468 /**
<> 144:ef7eb2e8f9f7 4469 * @brief TIM DMA error callback
<> 144:ef7eb2e8f9f7 4470 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4471 * @retval None
<> 144:ef7eb2e8f9f7 4472 */
<> 144:ef7eb2e8f9f7 4473 void TIM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4474 {
<> 144:ef7eb2e8f9f7 4475 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4476
<> 144:ef7eb2e8f9f7 4477 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4478
<> 144:ef7eb2e8f9f7 4479 HAL_TIM_ErrorCallback(htim);
<> 144:ef7eb2e8f9f7 4480 }
<> 144:ef7eb2e8f9f7 4481
<> 144:ef7eb2e8f9f7 4482 /**
<> 144:ef7eb2e8f9f7 4483 * @brief TIM DMA Delay Pulse complete callback.
<> 144:ef7eb2e8f9f7 4484 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4485 * @retval None
<> 144:ef7eb2e8f9f7 4486 */
<> 144:ef7eb2e8f9f7 4487 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4488 {
<> 144:ef7eb2e8f9f7 4489 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4490
<> 144:ef7eb2e8f9f7 4491 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4492
<> 144:ef7eb2e8f9f7 4493 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4494 {
<> 144:ef7eb2e8f9f7 4495 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4496 }
<> 144:ef7eb2e8f9f7 4497 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4498 {
<> 144:ef7eb2e8f9f7 4499 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4500 }
<> 144:ef7eb2e8f9f7 4501 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4502 {
<> 144:ef7eb2e8f9f7 4503 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4504 }
<> 144:ef7eb2e8f9f7 4505 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4506 {
<> 144:ef7eb2e8f9f7 4507 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4508 }
<> 144:ef7eb2e8f9f7 4509
<> 144:ef7eb2e8f9f7 4510 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 4511
<> 144:ef7eb2e8f9f7 4512 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4513 }
<> 144:ef7eb2e8f9f7 4514 /**
<> 144:ef7eb2e8f9f7 4515 * @brief TIM DMA Capture complete callback.
<> 144:ef7eb2e8f9f7 4516 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4517 * @retval None
<> 144:ef7eb2e8f9f7 4518 */
<> 144:ef7eb2e8f9f7 4519 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4520 {
<> 144:ef7eb2e8f9f7 4521 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4522
<> 144:ef7eb2e8f9f7 4523 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4524
<> 144:ef7eb2e8f9f7 4525 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4526 {
<> 144:ef7eb2e8f9f7 4527 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4528 }
<> 144:ef7eb2e8f9f7 4529 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4530 {
<> 144:ef7eb2e8f9f7 4531 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4532 }
<> 144:ef7eb2e8f9f7 4533 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4534 {
<> 144:ef7eb2e8f9f7 4535 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4536 }
<> 144:ef7eb2e8f9f7 4537 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4538 {
<> 144:ef7eb2e8f9f7 4539 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4540 }
<> 144:ef7eb2e8f9f7 4541
<> 144:ef7eb2e8f9f7 4542 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 4543
<> 144:ef7eb2e8f9f7 4544 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4545 }
<> 144:ef7eb2e8f9f7 4546
<> 144:ef7eb2e8f9f7 4547 /**
<> 144:ef7eb2e8f9f7 4548 * @brief TIM DMA Period Elapse complete callback.
<> 144:ef7eb2e8f9f7 4549 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4550 * @retval None
<> 144:ef7eb2e8f9f7 4551 */
<> 144:ef7eb2e8f9f7 4552 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4553 {
<> 144:ef7eb2e8f9f7 4554 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4555
<> 144:ef7eb2e8f9f7 4556 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4557
<> 144:ef7eb2e8f9f7 4558 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 4559 }
<> 144:ef7eb2e8f9f7 4560
<> 144:ef7eb2e8f9f7 4561 /**
<> 144:ef7eb2e8f9f7 4562 * @brief TIM DMA Trigger callback.
<> 144:ef7eb2e8f9f7 4563 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4564 * @retval None
<> 144:ef7eb2e8f9f7 4565 */
<> 144:ef7eb2e8f9f7 4566 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4567 {
<> 144:ef7eb2e8f9f7 4568 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4569
<> 144:ef7eb2e8f9f7 4570 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4571
<> 144:ef7eb2e8f9f7 4572 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 4573 }
<> 144:ef7eb2e8f9f7 4574
<> 144:ef7eb2e8f9f7 4575 /**
<> 144:ef7eb2e8f9f7 4576 * @brief Time Base configuration
<> 144:ef7eb2e8f9f7 4577 * @param TIMx : TIM periheral
<> 144:ef7eb2e8f9f7 4578 * @param Structure : TIM Base configuration structure
<> 144:ef7eb2e8f9f7 4579 * @retval None
<> 144:ef7eb2e8f9f7 4580 */
<> 144:ef7eb2e8f9f7 4581 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
<> 144:ef7eb2e8f9f7 4582 {
<> 156:95d6b41a828b 4583 uint32_t tmpcr1 = 0U;
<> 144:ef7eb2e8f9f7 4584 tmpcr1 = TIMx->CR1;
<> 144:ef7eb2e8f9f7 4585
<> 144:ef7eb2e8f9f7 4586 /* Set TIM Time Base Unit parameters ---------------------------------------*/
<> 144:ef7eb2e8f9f7 4587 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4588 {
<> 144:ef7eb2e8f9f7 4589 /* Select the Counter Mode */
<> 144:ef7eb2e8f9f7 4590 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
<> 144:ef7eb2e8f9f7 4591 tmpcr1 |= Structure->CounterMode;
<> 144:ef7eb2e8f9f7 4592 }
<> 144:ef7eb2e8f9f7 4593
<> 144:ef7eb2e8f9f7 4594 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4595 {
<> 144:ef7eb2e8f9f7 4596 /* Set the clock division */
<> 144:ef7eb2e8f9f7 4597 tmpcr1 &= ~TIM_CR1_CKD;
<> 144:ef7eb2e8f9f7 4598 tmpcr1 |= (uint32_t)Structure->ClockDivision;
<> 144:ef7eb2e8f9f7 4599 }
<> 144:ef7eb2e8f9f7 4600
<> 156:95d6b41a828b 4601 /* Set the auto-reload preload */
<> 156:95d6b41a828b 4602 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
<> 156:95d6b41a828b 4603
<> 144:ef7eb2e8f9f7 4604 TIMx->CR1 = tmpcr1;
<> 144:ef7eb2e8f9f7 4605
<> 144:ef7eb2e8f9f7 4606 /* Set the Autoreload value */
<> 144:ef7eb2e8f9f7 4607 TIMx->ARR = (uint32_t)Structure->Period ;
<> 144:ef7eb2e8f9f7 4608
<> 144:ef7eb2e8f9f7 4609 /* Set the Prescaler value */
<> 144:ef7eb2e8f9f7 4610 TIMx->PSC = (uint32_t)Structure->Prescaler;
<> 144:ef7eb2e8f9f7 4611
<> 144:ef7eb2e8f9f7 4612 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4613 {
<> 144:ef7eb2e8f9f7 4614 /* Set the Repetition Counter value */
<> 144:ef7eb2e8f9f7 4615 TIMx->RCR = Structure->RepetitionCounter;
<> 144:ef7eb2e8f9f7 4616 }
<> 144:ef7eb2e8f9f7 4617
<> 144:ef7eb2e8f9f7 4618 /* Generate an update event to reload the Prescaler
<> 144:ef7eb2e8f9f7 4619 and the repetition counter(only for TIM1 and TIM8) value immediatly */
<> 144:ef7eb2e8f9f7 4620 TIMx->EGR = TIM_EGR_UG;
<> 144:ef7eb2e8f9f7 4621 }
<> 144:ef7eb2e8f9f7 4622
<> 144:ef7eb2e8f9f7 4623 /**
<> 144:ef7eb2e8f9f7 4624 * @brief Time Ouput Compare 1 configuration
<> 144:ef7eb2e8f9f7 4625 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4626 * @param OC_Config : The ouput configuration structure
<> 144:ef7eb2e8f9f7 4627 * @retval None
<> 144:ef7eb2e8f9f7 4628 */
<> 144:ef7eb2e8f9f7 4629 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4630 {
<> 156:95d6b41a828b 4631 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4632 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4633 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4634
<> 144:ef7eb2e8f9f7 4635 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4636 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4637
<> 144:ef7eb2e8f9f7 4638 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4639 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4640 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4641 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4642
<> 144:ef7eb2e8f9f7 4643 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4644 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4645
<> 144:ef7eb2e8f9f7 4646 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 4647 tmpccmrx &= ~TIM_CCMR1_OC1M;
<> 144:ef7eb2e8f9f7 4648 tmpccmrx &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4649 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4650 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4651
<> 144:ef7eb2e8f9f7 4652 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4653 tmpccer &= ~TIM_CCER_CC1P;
<> 144:ef7eb2e8f9f7 4654 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4655 tmpccer |= OC_Config->OCPolarity;
<> 144:ef7eb2e8f9f7 4656
<> 144:ef7eb2e8f9f7 4657 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
<> 144:ef7eb2e8f9f7 4658 {
<> 144:ef7eb2e8f9f7 4659 /* Check parameters */
<> 144:ef7eb2e8f9f7 4660 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4661
<> 144:ef7eb2e8f9f7 4662 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4663 tmpccer &= ~TIM_CCER_CC1NP;
<> 144:ef7eb2e8f9f7 4664 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4665 tmpccer |= OC_Config->OCNPolarity;
<> 144:ef7eb2e8f9f7 4666 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4667 tmpccer &= ~TIM_CCER_CC1NE;
<> 144:ef7eb2e8f9f7 4668 }
<> 144:ef7eb2e8f9f7 4669
<> 144:ef7eb2e8f9f7 4670 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4671 {
<> 144:ef7eb2e8f9f7 4672 /* Check parameters */
<> 144:ef7eb2e8f9f7 4673 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4674 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4675
<> 144:ef7eb2e8f9f7 4676 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4677 tmpcr2 &= ~TIM_CR2_OIS1;
<> 144:ef7eb2e8f9f7 4678 tmpcr2 &= ~TIM_CR2_OIS1N;
<> 144:ef7eb2e8f9f7 4679 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4680 tmpcr2 |= OC_Config->OCIdleState;
<> 144:ef7eb2e8f9f7 4681 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4682 tmpcr2 |= OC_Config->OCNIdleState;
<> 144:ef7eb2e8f9f7 4683 }
<> 144:ef7eb2e8f9f7 4684 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4685 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4686
<> 144:ef7eb2e8f9f7 4687 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4688 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4689
<> 144:ef7eb2e8f9f7 4690 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4691 TIMx->CCR1 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4692
<> 144:ef7eb2e8f9f7 4693 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4694 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4695 }
<> 144:ef7eb2e8f9f7 4696
<> 144:ef7eb2e8f9f7 4697 /**
<> 144:ef7eb2e8f9f7 4698 * @brief Time Ouput Compare 2 configuration
<> 144:ef7eb2e8f9f7 4699 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4700 * @param OC_Config : The ouput configuration structure
<> 144:ef7eb2e8f9f7 4701 * @retval None
<> 144:ef7eb2e8f9f7 4702 */
<> 144:ef7eb2e8f9f7 4703 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4704 {
<> 156:95d6b41a828b 4705 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4706 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4707 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4708
<> 144:ef7eb2e8f9f7 4709 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4710 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4711
<> 144:ef7eb2e8f9f7 4712 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4713 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4714 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4715 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4716
<> 144:ef7eb2e8f9f7 4717 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4718 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4719
<> 144:ef7eb2e8f9f7 4720 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4721 tmpccmrx &= ~TIM_CCMR1_OC2M;
<> 144:ef7eb2e8f9f7 4722 tmpccmrx &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 4723
<> 144:ef7eb2e8f9f7 4724 /* Select the Output Compare Mode */
<> 156:95d6b41a828b 4725 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4726
<> 144:ef7eb2e8f9f7 4727 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4728 tmpccer &= ~TIM_CCER_CC2P;
<> 144:ef7eb2e8f9f7 4729 /* Set the Output Compare Polarity */
<> 156:95d6b41a828b 4730 tmpccer |= (OC_Config->OCPolarity << 4U);
<> 144:ef7eb2e8f9f7 4731
<> 144:ef7eb2e8f9f7 4732 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 4733 {
<> 144:ef7eb2e8f9f7 4734 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4735
<> 144:ef7eb2e8f9f7 4736 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4737 tmpccer &= ~TIM_CCER_CC2NP;
<> 144:ef7eb2e8f9f7 4738 /* Set the Output N Polarity */
<> 156:95d6b41a828b 4739 tmpccer |= (OC_Config->OCNPolarity << 4U);
<> 144:ef7eb2e8f9f7 4740 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4741 tmpccer &= ~TIM_CCER_CC2NE;
<> 144:ef7eb2e8f9f7 4742
<> 144:ef7eb2e8f9f7 4743 }
<> 144:ef7eb2e8f9f7 4744
<> 144:ef7eb2e8f9f7 4745 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4746 {
<> 144:ef7eb2e8f9f7 4747 /* Check parameters */
<> 144:ef7eb2e8f9f7 4748 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4749 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4750
<> 144:ef7eb2e8f9f7 4751 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4752 tmpcr2 &= ~TIM_CR2_OIS2;
<> 144:ef7eb2e8f9f7 4753 tmpcr2 &= ~TIM_CR2_OIS2N;
<> 144:ef7eb2e8f9f7 4754 /* Set the Output Idle state */
<> 156:95d6b41a828b 4755 tmpcr2 |= (OC_Config->OCIdleState << 2U);
<> 144:ef7eb2e8f9f7 4756 /* Set the Output N Idle state */
<> 156:95d6b41a828b 4757 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
<> 144:ef7eb2e8f9f7 4758 }
<> 144:ef7eb2e8f9f7 4759
<> 144:ef7eb2e8f9f7 4760 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4761 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4762
<> 144:ef7eb2e8f9f7 4763 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4764 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4765
<> 144:ef7eb2e8f9f7 4766 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4767 TIMx->CCR2 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4768
<> 144:ef7eb2e8f9f7 4769 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4770 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4771 }
<> 144:ef7eb2e8f9f7 4772
<> 144:ef7eb2e8f9f7 4773 /**
<> 144:ef7eb2e8f9f7 4774 * @brief Time Ouput Compare 3 configuration
<> 144:ef7eb2e8f9f7 4775 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4776 * @param OC_Config : The ouput configuration structure
<> 144:ef7eb2e8f9f7 4777 * @retval None
<> 144:ef7eb2e8f9f7 4778 */
<> 144:ef7eb2e8f9f7 4779 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4780 {
<> 156:95d6b41a828b 4781 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4782 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4783 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4784
<> 144:ef7eb2e8f9f7 4785 /* Disable the Channel 3: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4786 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 4787
<> 144:ef7eb2e8f9f7 4788 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4789 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4790 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4791 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4792
<> 144:ef7eb2e8f9f7 4793 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4794 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4795
<> 144:ef7eb2e8f9f7 4796 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4797 tmpccmrx &= ~TIM_CCMR2_OC3M;
<> 144:ef7eb2e8f9f7 4798 tmpccmrx &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 4799 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4800 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4801
<> 144:ef7eb2e8f9f7 4802 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4803 tmpccer &= ~TIM_CCER_CC3P;
<> 144:ef7eb2e8f9f7 4804 /* Set the Output Compare Polarity */
<> 156:95d6b41a828b 4805 tmpccer |= (OC_Config->OCPolarity << 8U);
<> 144:ef7eb2e8f9f7 4806
<> 144:ef7eb2e8f9f7 4807 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 4808 {
<> 144:ef7eb2e8f9f7 4809 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4810
<> 144:ef7eb2e8f9f7 4811 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4812 tmpccer &= ~TIM_CCER_CC3NP;
<> 144:ef7eb2e8f9f7 4813 /* Set the Output N Polarity */
<> 156:95d6b41a828b 4814 tmpccer |= (OC_Config->OCNPolarity << 8U);
<> 144:ef7eb2e8f9f7 4815 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4816 tmpccer &= ~TIM_CCER_CC3NE;
<> 144:ef7eb2e8f9f7 4817 }
<> 144:ef7eb2e8f9f7 4818
<> 144:ef7eb2e8f9f7 4819 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4820 {
<> 144:ef7eb2e8f9f7 4821 /* Check parameters */
<> 144:ef7eb2e8f9f7 4822 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4823 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4824
<> 144:ef7eb2e8f9f7 4825 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4826 tmpcr2 &= ~TIM_CR2_OIS3;
<> 144:ef7eb2e8f9f7 4827 tmpcr2 &= ~TIM_CR2_OIS3N;
<> 144:ef7eb2e8f9f7 4828 /* Set the Output Idle state */
<> 156:95d6b41a828b 4829 tmpcr2 |= (OC_Config->OCIdleState << 4U);
<> 144:ef7eb2e8f9f7 4830 /* Set the Output N Idle state */
<> 156:95d6b41a828b 4831 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
<> 144:ef7eb2e8f9f7 4832 }
<> 144:ef7eb2e8f9f7 4833
<> 144:ef7eb2e8f9f7 4834 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4835 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4836
<> 144:ef7eb2e8f9f7 4837 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4838 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4839
<> 144:ef7eb2e8f9f7 4840 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4841 TIMx->CCR3 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4842
<> 144:ef7eb2e8f9f7 4843 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4844 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4845 }
<> 144:ef7eb2e8f9f7 4846
<> 144:ef7eb2e8f9f7 4847 /**
<> 144:ef7eb2e8f9f7 4848 * @brief Time Ouput Compare 4 configuration
<> 144:ef7eb2e8f9f7 4849 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4850 * @param OC_Config : The ouput configuration structure
<> 144:ef7eb2e8f9f7 4851 * @retval None
<> 144:ef7eb2e8f9f7 4852 */
<> 144:ef7eb2e8f9f7 4853 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4854 {
<> 156:95d6b41a828b 4855 uint32_t tmpccmrx = 0U;
<> 156:95d6b41a828b 4856 uint32_t tmpccer = 0U;
<> 156:95d6b41a828b 4857 uint32_t tmpcr2 = 0U;
<> 144:ef7eb2e8f9f7 4858
<> 144:ef7eb2e8f9f7 4859 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 4860 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 4861
<> 144:ef7eb2e8f9f7 4862 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4863 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4864 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4865 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4866
<> 144:ef7eb2e8f9f7 4867 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4868 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4869
<> 144:ef7eb2e8f9f7 4870 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4871 tmpccmrx &= ~TIM_CCMR2_OC4M;
<> 144:ef7eb2e8f9f7 4872 tmpccmrx &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 4873
<> 144:ef7eb2e8f9f7 4874 /* Select the Output Compare Mode */
<> 156:95d6b41a828b 4875 tmpccmrx |= (OC_Config->OCMode << 8U);
<> 144:ef7eb2e8f9f7 4876
<> 144:ef7eb2e8f9f7 4877 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4878 tmpccer &= ~TIM_CCER_CC4P;
<> 144:ef7eb2e8f9f7 4879 /* Set the Output Compare Polarity */
<> 156:95d6b41a828b 4880 tmpccer |= (OC_Config->OCPolarity << 12U);
<> 144:ef7eb2e8f9f7 4881
<> 144:ef7eb2e8f9f7 4882 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4883 {
<> 144:ef7eb2e8f9f7 4884 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4885
<> 144:ef7eb2e8f9f7 4886 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 4887 tmpcr2 &= ~TIM_CR2_OIS4;
<> 144:ef7eb2e8f9f7 4888 /* Set the Output Idle state */
<> 156:95d6b41a828b 4889 tmpcr2 |= (OC_Config->OCIdleState << 6U);
<> 144:ef7eb2e8f9f7 4890 }
<> 144:ef7eb2e8f9f7 4891
<> 144:ef7eb2e8f9f7 4892 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4893 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4894
<> 144:ef7eb2e8f9f7 4895 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4896 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4897
<> 144:ef7eb2e8f9f7 4898 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4899 TIMx->CCR4 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4900
<> 144:ef7eb2e8f9f7 4901 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4902 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4903 }
<> 144:ef7eb2e8f9f7 4904
<> 144:ef7eb2e8f9f7 4905 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4906 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4907 {
<> 156:95d6b41a828b 4908 uint32_t tmpsmcr = 0U;
<> 156:95d6b41a828b 4909 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 4910 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 4911
<> 144:ef7eb2e8f9f7 4912 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4913 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4914
<> 144:ef7eb2e8f9f7 4915 /* Reset the Trigger Selection Bits */
<> 144:ef7eb2e8f9f7 4916 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 4917 /* Set the Input Trigger source */
<> 144:ef7eb2e8f9f7 4918 tmpsmcr |= sSlaveConfig->InputTrigger;
<> 144:ef7eb2e8f9f7 4919
<> 144:ef7eb2e8f9f7 4920 /* Reset the slave mode Bits */
<> 144:ef7eb2e8f9f7 4921 tmpsmcr &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 4922 /* Set the slave mode */
<> 144:ef7eb2e8f9f7 4923 tmpsmcr |= sSlaveConfig->SlaveMode;
<> 144:ef7eb2e8f9f7 4924
<> 144:ef7eb2e8f9f7 4925 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4926 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4927
<> 144:ef7eb2e8f9f7 4928 /* Configure the trigger prescaler, filter, and polarity */
<> 144:ef7eb2e8f9f7 4929 switch (sSlaveConfig->InputTrigger)
<> 144:ef7eb2e8f9f7 4930 {
<> 144:ef7eb2e8f9f7 4931 case TIM_TS_ETRF:
<> 144:ef7eb2e8f9f7 4932 {
<> 144:ef7eb2e8f9f7 4933 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4934 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4935 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<> 144:ef7eb2e8f9f7 4936 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4937 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4938 /* Configure the ETR Trigger source */
<> 144:ef7eb2e8f9f7 4939 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 4940 sSlaveConfig->TriggerPrescaler,
<> 144:ef7eb2e8f9f7 4941 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4942 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4943 }
<> 144:ef7eb2e8f9f7 4944 break;
<> 144:ef7eb2e8f9f7 4945
<> 144:ef7eb2e8f9f7 4946 case TIM_TS_TI1F_ED:
<> 144:ef7eb2e8f9f7 4947 {
<> 144:ef7eb2e8f9f7 4948 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4949 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4950 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4951
<> 144:ef7eb2e8f9f7 4952 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4953 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 4954 htim->Instance->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4955 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 4956
<> 144:ef7eb2e8f9f7 4957 /* Set the filter */
<> 144:ef7eb2e8f9f7 4958 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 156:95d6b41a828b 4959 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
<> 144:ef7eb2e8f9f7 4960
<> 144:ef7eb2e8f9f7 4961 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4962 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 4963 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4964
<> 144:ef7eb2e8f9f7 4965 }
<> 144:ef7eb2e8f9f7 4966 break;
<> 144:ef7eb2e8f9f7 4967
<> 144:ef7eb2e8f9f7 4968 case TIM_TS_TI1FP1:
<> 144:ef7eb2e8f9f7 4969 {
<> 144:ef7eb2e8f9f7 4970 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4971 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4972 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4973 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4974
<> 144:ef7eb2e8f9f7 4975 /* Configure TI1 Filter and Polarity */
<> 144:ef7eb2e8f9f7 4976 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4977 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4978 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4979 }
<> 144:ef7eb2e8f9f7 4980 break;
<> 144:ef7eb2e8f9f7 4981
<> 144:ef7eb2e8f9f7 4982 case TIM_TS_TI2FP2:
<> 144:ef7eb2e8f9f7 4983 {
<> 144:ef7eb2e8f9f7 4984 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4985 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4986 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4987 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4988
<> 144:ef7eb2e8f9f7 4989 /* Configure TI2 Filter and Polarity */
<> 144:ef7eb2e8f9f7 4990 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4991 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4992 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4993 }
<> 144:ef7eb2e8f9f7 4994 break;
<> 144:ef7eb2e8f9f7 4995
<> 144:ef7eb2e8f9f7 4996 case TIM_TS_ITR0:
<> 144:ef7eb2e8f9f7 4997 {
<> 144:ef7eb2e8f9f7 4998 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4999 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5000 }
<> 144:ef7eb2e8f9f7 5001 break;
<> 144:ef7eb2e8f9f7 5002
<> 144:ef7eb2e8f9f7 5003 case TIM_TS_ITR1:
<> 144:ef7eb2e8f9f7 5004 {
<> 144:ef7eb2e8f9f7 5005 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5006 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5007 }
<> 144:ef7eb2e8f9f7 5008 break;
<> 144:ef7eb2e8f9f7 5009
<> 144:ef7eb2e8f9f7 5010 case TIM_TS_ITR2:
<> 144:ef7eb2e8f9f7 5011 {
<> 144:ef7eb2e8f9f7 5012 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5013 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5014 }
<> 144:ef7eb2e8f9f7 5015 break;
<> 144:ef7eb2e8f9f7 5016
<> 144:ef7eb2e8f9f7 5017 case TIM_TS_ITR3:
<> 144:ef7eb2e8f9f7 5018 {
<> 144:ef7eb2e8f9f7 5019 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5020 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5021 }
<> 144:ef7eb2e8f9f7 5022 break;
<> 144:ef7eb2e8f9f7 5023
<> 144:ef7eb2e8f9f7 5024 default:
<> 144:ef7eb2e8f9f7 5025 break;
<> 144:ef7eb2e8f9f7 5026 }
<> 144:ef7eb2e8f9f7 5027 }
<> 144:ef7eb2e8f9f7 5028
<> 144:ef7eb2e8f9f7 5029 /**
<> 144:ef7eb2e8f9f7 5030 * @brief Configure the TI1 as Input.
<> 144:ef7eb2e8f9f7 5031 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5032 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5033 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5034 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5035 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5036 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5037 * @param TIM_ICSelection : specifies the input to be used.
<> 144:ef7eb2e8f9f7 5038 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5039 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5040 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5041 * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5042 * @param TIM_ICFilter : Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5043 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5044 * @retval None
<> 144:ef7eb2e8f9f7 5045 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<> 144:ef7eb2e8f9f7 5046 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5047 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5048 */
<> 144:ef7eb2e8f9f7 5049 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5050 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5051 {
<> 156:95d6b41a828b 5052 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5053 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5054
<> 144:ef7eb2e8f9f7 5055 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5056 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5057 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5058 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5059
<> 144:ef7eb2e8f9f7 5060 /* Select the Input */
<> 144:ef7eb2e8f9f7 5061 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 5062 {
<> 144:ef7eb2e8f9f7 5063 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 5064 tmpccmr1 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5065 }
<> 144:ef7eb2e8f9f7 5066 else
<> 144:ef7eb2e8f9f7 5067 {
<> 144:ef7eb2e8f9f7 5068 tmpccmr1 |= TIM_CCMR1_CC1S_0;
<> 144:ef7eb2e8f9f7 5069 }
<> 144:ef7eb2e8f9f7 5070
<> 144:ef7eb2e8f9f7 5071 /* Set the filter */
<> 144:ef7eb2e8f9f7 5072 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 156:95d6b41a828b 5073 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
<> 144:ef7eb2e8f9f7 5074
<> 144:ef7eb2e8f9f7 5075 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5076 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5077 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
<> 144:ef7eb2e8f9f7 5078
<> 144:ef7eb2e8f9f7 5079 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5080 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5081 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5082 }
<> 144:ef7eb2e8f9f7 5083
<> 144:ef7eb2e8f9f7 5084 /**
<> 144:ef7eb2e8f9f7 5085 * @brief Configure the Polarity and Filter for TI1.
<> 144:ef7eb2e8f9f7 5086 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5087 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5088 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5089 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5090 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5091 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5092 * @param TIM_ICFilter : Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5093 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5094 * @retval None
<> 144:ef7eb2e8f9f7 5095 */
<> 144:ef7eb2e8f9f7 5096 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5097 {
<> 156:95d6b41a828b 5098 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5099 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5100
<> 144:ef7eb2e8f9f7 5101 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5102 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5103 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5104 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5105
<> 144:ef7eb2e8f9f7 5106 /* Set the filter */
<> 144:ef7eb2e8f9f7 5107 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 156:95d6b41a828b 5108 tmpccmr1 |= (TIM_ICFilter << 4U);
<> 144:ef7eb2e8f9f7 5109
<> 144:ef7eb2e8f9f7 5110 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5111 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5112 tmpccer |= TIM_ICPolarity;
<> 144:ef7eb2e8f9f7 5113
<> 144:ef7eb2e8f9f7 5114 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5115 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5116 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5117 }
<> 144:ef7eb2e8f9f7 5118
<> 144:ef7eb2e8f9f7 5119 /**
<> 144:ef7eb2e8f9f7 5120 * @brief Configure the TI2 as Input.
<> 144:ef7eb2e8f9f7 5121 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5122 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5123 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5124 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5125 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5126 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5127 * @param TIM_ICSelection : specifies the input to be used.
<> 144:ef7eb2e8f9f7 5128 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5129 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5130 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5131 * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5132 * @param TIM_ICFilter : Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5133 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5134 * @retval None
<> 144:ef7eb2e8f9f7 5135 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<> 144:ef7eb2e8f9f7 5136 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5137 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5138 */
<> 144:ef7eb2e8f9f7 5139 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5140 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5141 {
<> 156:95d6b41a828b 5142 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5143 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5144
<> 144:ef7eb2e8f9f7 5145 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5146 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5147 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5148 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5149
<> 144:ef7eb2e8f9f7 5150 /* Select the Input */
<> 144:ef7eb2e8f9f7 5151 tmpccmr1 &= ~TIM_CCMR1_CC2S;
<> 156:95d6b41a828b 5152 tmpccmr1 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 5153
<> 144:ef7eb2e8f9f7 5154 /* Set the filter */
<> 144:ef7eb2e8f9f7 5155 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 156:95d6b41a828b 5156 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 5157
<> 144:ef7eb2e8f9f7 5158 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5159 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 156:95d6b41a828b 5160 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
<> 144:ef7eb2e8f9f7 5161
<> 144:ef7eb2e8f9f7 5162 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5163 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5164 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5165 }
<> 144:ef7eb2e8f9f7 5166
<> 144:ef7eb2e8f9f7 5167 /**
<> 144:ef7eb2e8f9f7 5168 * @brief Configure the Polarity and Filter for TI2.
<> 144:ef7eb2e8f9f7 5169 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5170 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5171 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5172 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5173 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5174 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5175 * @param TIM_ICFilter : Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5176 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5177 * @retval None
<> 144:ef7eb2e8f9f7 5178 */
<> 144:ef7eb2e8f9f7 5179 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5180 {
<> 156:95d6b41a828b 5181 uint32_t tmpccmr1 = 0U;
<> 156:95d6b41a828b 5182 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5183
<> 144:ef7eb2e8f9f7 5184 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5185 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5186 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5187 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5188
<> 144:ef7eb2e8f9f7 5189 /* Set the filter */
<> 144:ef7eb2e8f9f7 5190 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 156:95d6b41a828b 5191 tmpccmr1 |= (TIM_ICFilter << 12U);
<> 144:ef7eb2e8f9f7 5192
<> 144:ef7eb2e8f9f7 5193 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5194 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 156:95d6b41a828b 5195 tmpccer |= (TIM_ICPolarity << 4U);
<> 144:ef7eb2e8f9f7 5196
<> 144:ef7eb2e8f9f7 5197 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5198 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5199 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5200 }
<> 144:ef7eb2e8f9f7 5201
<> 144:ef7eb2e8f9f7 5202 /**
<> 144:ef7eb2e8f9f7 5203 * @brief Configure the TI3 as Input.
<> 144:ef7eb2e8f9f7 5204 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5205 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5206 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5207 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5208 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5209 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5210 * @param TIM_ICSelection : specifies the input to be used.
<> 144:ef7eb2e8f9f7 5211 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5212 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5213 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5214 * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5215 * @param TIM_ICFilter : Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5216 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5217 * @retval None
<> 144:ef7eb2e8f9f7 5218 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<> 144:ef7eb2e8f9f7 5219 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5220 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5221 */
<> 144:ef7eb2e8f9f7 5222 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5223 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5224 {
<> 156:95d6b41a828b 5225 uint32_t tmpccmr2 = 0U;
<> 156:95d6b41a828b 5226 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5227
<> 144:ef7eb2e8f9f7 5228 /* Disable the Channel 3: Reset the CC3E Bit */
<> 144:ef7eb2e8f9f7 5229 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 5230 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5231 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5232
<> 144:ef7eb2e8f9f7 5233 /* Select the Input */
<> 144:ef7eb2e8f9f7 5234 tmpccmr2 &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 5235 tmpccmr2 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5236
<> 144:ef7eb2e8f9f7 5237 /* Set the filter */
<> 144:ef7eb2e8f9f7 5238 tmpccmr2 &= ~TIM_CCMR2_IC3F;
<> 156:95d6b41a828b 5239 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
<> 144:ef7eb2e8f9f7 5240
<> 144:ef7eb2e8f9f7 5241 /* Select the Polarity and set the CC3E Bit */
<> 144:ef7eb2e8f9f7 5242 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
<> 156:95d6b41a828b 5243 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
<> 144:ef7eb2e8f9f7 5244
<> 144:ef7eb2e8f9f7 5245 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5246 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5247 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5248 }
<> 144:ef7eb2e8f9f7 5249
<> 144:ef7eb2e8f9f7 5250 /**
<> 144:ef7eb2e8f9f7 5251 * @brief Configure the TI4 as Input.
<> 144:ef7eb2e8f9f7 5252 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5253 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5254 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5255 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5256 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5257 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5258 * @param TIM_ICSelection : specifies the input to be used.
<> 144:ef7eb2e8f9f7 5259 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5260 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5261 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5262 * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5263 * @param TIM_ICFilter : Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5264 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5265 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<> 144:ef7eb2e8f9f7 5266 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5267 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5268 * @retval None
<> 144:ef7eb2e8f9f7 5269 */
<> 144:ef7eb2e8f9f7 5270 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5271 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5272 {
<> 156:95d6b41a828b 5273 uint32_t tmpccmr2 = 0U;
<> 156:95d6b41a828b 5274 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 5275
<> 144:ef7eb2e8f9f7 5276 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 5277 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 5278 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5279 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5280
<> 144:ef7eb2e8f9f7 5281 /* Select the Input */
<> 144:ef7eb2e8f9f7 5282 tmpccmr2 &= ~TIM_CCMR2_CC4S;
<> 156:95d6b41a828b 5283 tmpccmr2 |= (TIM_ICSelection << 8U);
<> 144:ef7eb2e8f9f7 5284
<> 144:ef7eb2e8f9f7 5285 /* Set the filter */
<> 144:ef7eb2e8f9f7 5286 tmpccmr2 &= ~TIM_CCMR2_IC4F;
<> 156:95d6b41a828b 5287 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
<> 144:ef7eb2e8f9f7 5288
<> 144:ef7eb2e8f9f7 5289 /* Select the Polarity and set the CC4E Bit */
<> 144:ef7eb2e8f9f7 5290 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
<> 156:95d6b41a828b 5291 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
<> 144:ef7eb2e8f9f7 5292
<> 144:ef7eb2e8f9f7 5293 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5294 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5295 TIMx->CCER = tmpccer ;
<> 144:ef7eb2e8f9f7 5296 }
<> 144:ef7eb2e8f9f7 5297
<> 144:ef7eb2e8f9f7 5298 /**
<> 144:ef7eb2e8f9f7 5299 * @brief Selects the Input Trigger source
<> 144:ef7eb2e8f9f7 5300 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5301 * @param InputTriggerSource : The Input Trigger source.
<> 144:ef7eb2e8f9f7 5302 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5303 * @arg TIM_TS_ITR0 : Internal Trigger 0
<> 144:ef7eb2e8f9f7 5304 * @arg TIM_TS_ITR1 : Internal Trigger 1
<> 144:ef7eb2e8f9f7 5305 * @arg TIM_TS_ITR2 : Internal Trigger 2
<> 144:ef7eb2e8f9f7 5306 * @arg TIM_TS_ITR3 : Internal Trigger 3
<> 144:ef7eb2e8f9f7 5307 * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
<> 144:ef7eb2e8f9f7 5308 * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
<> 144:ef7eb2e8f9f7 5309 * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
<> 144:ef7eb2e8f9f7 5310 * @arg TIM_TS_ETRF : External Trigger input
<> 144:ef7eb2e8f9f7 5311 * @retval None
<> 144:ef7eb2e8f9f7 5312 */
<> 144:ef7eb2e8f9f7 5313 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<> 144:ef7eb2e8f9f7 5314 {
<> 156:95d6b41a828b 5315 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 5316
<> 144:ef7eb2e8f9f7 5317 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 5318 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5319 /* Reset the TS Bits */
<> 144:ef7eb2e8f9f7 5320 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 5321 /* Set the Input Trigger source and the slave mode*/
<> 144:ef7eb2e8f9f7 5322 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
<> 144:ef7eb2e8f9f7 5323 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5324 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5325 }
<> 144:ef7eb2e8f9f7 5326 /**
<> 144:ef7eb2e8f9f7 5327 * @brief Configures the TIMx External Trigger (ETR).
<> 144:ef7eb2e8f9f7 5328 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5329 * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
<> 144:ef7eb2e8f9f7 5330 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5331 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
<> 144:ef7eb2e8f9f7 5332 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
<> 144:ef7eb2e8f9f7 5333 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
<> 144:ef7eb2e8f9f7 5334 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
<> 144:ef7eb2e8f9f7 5335 * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
<> 144:ef7eb2e8f9f7 5336 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5337 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
<> 144:ef7eb2e8f9f7 5338 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
<> 144:ef7eb2e8f9f7 5339 * @param ExtTRGFilter : External Trigger Filter.
<> 144:ef7eb2e8f9f7 5340 * This parameter must be a value between 0x00 and 0x0F
<> 144:ef7eb2e8f9f7 5341 * @retval None
<> 144:ef7eb2e8f9f7 5342 */
<> 144:ef7eb2e8f9f7 5343 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 5344 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<> 144:ef7eb2e8f9f7 5345 {
<> 156:95d6b41a828b 5346 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 5347
<> 144:ef7eb2e8f9f7 5348 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5349
<> 144:ef7eb2e8f9f7 5350 /* Reset the ETR Bits */
<> 144:ef7eb2e8f9f7 5351 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 5352
<> 144:ef7eb2e8f9f7 5353 /* Set the Prescaler, the Filter value and the Polarity */
<> 156:95d6b41a828b 5354 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
<> 144:ef7eb2e8f9f7 5355
<> 144:ef7eb2e8f9f7 5356 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5357 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5358 }
<> 144:ef7eb2e8f9f7 5359
<> 144:ef7eb2e8f9f7 5360 /**
<> 144:ef7eb2e8f9f7 5361 * @brief Enables or disables the TIM Capture Compare Channel x.
<> 144:ef7eb2e8f9f7 5362 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5363 * @param Channel : specifies the TIM Channel
<> 144:ef7eb2e8f9f7 5364 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5365 * @arg TIM_CHANNEL_1 : TIM Channel 1
<> 144:ef7eb2e8f9f7 5366 * @arg TIM_CHANNEL_2 : TIM Channel 2
<> 144:ef7eb2e8f9f7 5367 * @arg TIM_CHANNEL_3 : TIM Channel 3
<> 144:ef7eb2e8f9f7 5368 * @arg TIM_CHANNEL_4 : TIM Channel 4
<> 144:ef7eb2e8f9f7 5369 * @param ChannelState : specifies the TIM Channel CCxE bit new state.
<> 144:ef7eb2e8f9f7 5370 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<> 144:ef7eb2e8f9f7 5371 * @retval None
<> 144:ef7eb2e8f9f7 5372 */
<> 144:ef7eb2e8f9f7 5373 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<> 144:ef7eb2e8f9f7 5374 {
<> 156:95d6b41a828b 5375 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 5376
<> 144:ef7eb2e8f9f7 5377 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5378 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 5379 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 5380
<> 144:ef7eb2e8f9f7 5381 tmp = TIM_CCER_CC1E << Channel;
<> 144:ef7eb2e8f9f7 5382
<> 144:ef7eb2e8f9f7 5383 /* Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5384 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 5385
<> 144:ef7eb2e8f9f7 5386 /* Set or reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5387 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
<> 144:ef7eb2e8f9f7 5388 }
<> 144:ef7eb2e8f9f7 5389
<> 144:ef7eb2e8f9f7 5390
<> 144:ef7eb2e8f9f7 5391 /**
<> 144:ef7eb2e8f9f7 5392 * @}
<> 144:ef7eb2e8f9f7 5393 */
<> 144:ef7eb2e8f9f7 5394
<> 144:ef7eb2e8f9f7 5395 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 5396 /**
<> 144:ef7eb2e8f9f7 5397 * @}
<> 144:ef7eb2e8f9f7 5398 */
<> 144:ef7eb2e8f9f7 5399
<> 144:ef7eb2e8f9f7 5400 /**
<> 144:ef7eb2e8f9f7 5401 * @}
<> 144:ef7eb2e8f9f7 5402 */
<> 144:ef7eb2e8f9f7 5403 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/