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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_smbus.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of SMBUS HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_SMBUS_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_SMBUS_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
Anna Bridge 180:96ed750bd169 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup SMBUS
<> 144:ef7eb2e8f9f7 52 * @{
Anna Bridge 180:96ed750bd169 53 */
<> 144:ef7eb2e8f9f7 54
Anna Bridge 180:96ed750bd169 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
Anna Bridge 180:96ed750bd169 58 */
Anna Bridge 180:96ed750bd169 59
<> 144:ef7eb2e8f9f7 60 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
Anna Bridge 180:96ed750bd169 61 * @brief SMBUS Configuration Structure definition
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
Anna Bridge 180:96ed750bd169 67 This parameter calculated by referring to SMBUS initialization
<> 144:ef7eb2e8f9f7 68 section in Reference manual */
<> 144:ef7eb2e8f9f7 69 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref SMBUS_Analog_Filter */
Anna Bridge 180:96ed750bd169 71
<> 144:ef7eb2e8f9f7 72 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 144:ef7eb2e8f9f7 73 This parameter can be a 7-bit or 10-bit address. */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref SMBUS_addressing_mode */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref SMBUS_dual_addressing_mode */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 82 This parameter can be a 7-bit address. */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 85 This parameter can be a value of @ref SMBUS_own_address2_masks. */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref SMBUS_nostretch_mode */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
<> 144:ef7eb2e8f9f7 94 This parameter can be a value of @ref SMBUS_packet_error_check_mode */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
<> 144:ef7eb2e8f9f7 97 This parameter can be a value of @ref SMBUS_peripheral_mode */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
Anna Bridge 180:96ed750bd169 100 (Enable bits and different timeout values)
Anna Bridge 180:96ed750bd169 101 This parameter calculated by referring to SMBUS initialization
<> 144:ef7eb2e8f9f7 102 section in Reference manual */
<> 144:ef7eb2e8f9f7 103 } SMBUS_InitTypeDef;
Anna Bridge 180:96ed750bd169 104 /**
<> 144:ef7eb2e8f9f7 105 * @}
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @defgroup HAL_state_definition HAL state definition
Anna Bridge 180:96ed750bd169 109 * @brief HAL State definition
<> 144:ef7eb2e8f9f7 110 * @{
Anna Bridge 180:96ed750bd169 111 */
<> 156:95d6b41a828b 112 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
<> 156:95d6b41a828b 113 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
<> 156:95d6b41a828b 114 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
Anna Bridge 180:96ed750bd169 115 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
<> 156:95d6b41a828b 116 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
Anna Bridge 180:96ed750bd169 117 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
<> 156:95d6b41a828b 118 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
Anna Bridge 180:96ed750bd169 119 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
Anna Bridge 180:96ed750bd169 120 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
<> 156:95d6b41a828b 121 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
Anna Bridge 180:96ed750bd169 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
Anna Bridge 180:96ed750bd169 127 * @brief SMBUS Error Code definition
<> 144:ef7eb2e8f9f7 128 * @{
Anna Bridge 180:96ed750bd169 129 */
<> 156:95d6b41a828b 130 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 131 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
Anna Bridge 180:96ed750bd169 132 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
<> 156:95d6b41a828b 133 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
<> 156:95d6b41a828b 134 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
<> 156:95d6b41a828b 135 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
<> 156:95d6b41a828b 136 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
<> 156:95d6b41a828b 137 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
<> 156:95d6b41a828b 138 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
Anna Bridge 180:96ed750bd169 139 /**
<> 144:ef7eb2e8f9f7 140 * @}
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
Anna Bridge 180:96ed750bd169 143 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
Anna Bridge 180:96ed750bd169 144 * @brief SMBUS handle Structure definition
<> 144:ef7eb2e8f9f7 145 * @{
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 typedef struct
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 I2C_TypeDef *Instance; /*!< SMBUS registers base address */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint16_t XferSize; /*!< SMBUS transfer size */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 __IO uint16_t XferCount; /*!< SMBUS transfer counter */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 __IO uint32_t XferOptions; /*!< SMBUS transfer options */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 HAL_LockTypeDef Lock; /*!< SMBUS locking object */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 __IO uint32_t State; /*!< SMBUS communication state */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 __IO uint32_t ErrorCode; /*!< SMBUS Error code */
<> 144:ef7eb2e8f9f7 168
Anna Bridge 180:96ed750bd169 169 } SMBUS_HandleTypeDef;
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
Anna Bridge 180:96ed750bd169 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
<> 144:ef7eb2e8f9f7 184 * @{
<> 144:ef7eb2e8f9f7 185 */
<> 156:95d6b41a828b 186 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
<> 156:95d6b41a828b 187 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
<> 144:ef7eb2e8f9f7 193 * @{
<> 144:ef7eb2e8f9f7 194 */
<> 156:95d6b41a828b 195 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
<> 156:95d6b41a828b 196 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 156:95d6b41a828b 205 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
<> 156:95d6b41a828b 206 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @}
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 156:95d6b41a828b 215 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
<> 156:95d6b41a828b 216 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
<> 156:95d6b41a828b 217 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
<> 156:95d6b41a828b 218 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
<> 156:95d6b41a828b 219 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
<> 156:95d6b41a828b 220 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
<> 156:95d6b41a828b 221 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
<> 156:95d6b41a828b 222 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
<> 144:ef7eb2e8f9f7 229 * @{
<> 144:ef7eb2e8f9f7 230 */
<> 156:95d6b41a828b 231 #define SMBUS_GENERALCALL_DISABLE (0x00000000U)
<> 156:95d6b41a828b 232 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @}
<> 144:ef7eb2e8f9f7 235 */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
<> 144:ef7eb2e8f9f7 238 * @{
<> 144:ef7eb2e8f9f7 239 */
<> 156:95d6b41a828b 240 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
<> 156:95d6b41a828b 241 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
<> 156:95d6b41a828b 249 #define SMBUS_PEC_DISABLE (0x00000000U)
<> 156:95d6b41a828b 250 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 156:95d6b41a828b 258 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
<> 156:95d6b41a828b 259 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
<> 156:95d6b41a828b 260 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @}
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 156:95d6b41a828b 269 #define SMBUS_SOFTEND_MODE (0x00000000U)
<> 144:ef7eb2e8f9f7 270 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
<> 144:ef7eb2e8f9f7 271 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
<> 144:ef7eb2e8f9f7 272 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @}
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
<> 144:ef7eb2e8f9f7 278 * @{
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280
<> 156:95d6b41a828b 281 #define SMBUS_NO_STARTSTOP (0x00000000U)
<> 144:ef7eb2e8f9f7 282 #define SMBUS_GENERATE_STOP I2C_CR2_STOP
<> 144:ef7eb2e8f9f7 283 #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
<> 144:ef7eb2e8f9f7 284 #define SMBUS_GENERATE_START_WRITE I2C_CR2_START
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
Anna Bridge 180:96ed750bd169 293 /* List of XferOptions in usage of :
Anna Bridge 180:96ed750bd169 294 * 1- Restart condition when direction change
Anna Bridge 180:96ed750bd169 295 * 2- No Restart condition in other use cases
Anna Bridge 180:96ed750bd169 296 */
<> 156:95d6b41a828b 297 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
<> 144:ef7eb2e8f9f7 298 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
Anna Bridge 180:96ed750bd169 299 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
<> 144:ef7eb2e8f9f7 300 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
<> 144:ef7eb2e8f9f7 301 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
<> 144:ef7eb2e8f9f7 302 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
Anna Bridge 180:96ed750bd169 303
Anna Bridge 180:96ed750bd169 304 /* List of XferOptions in usage of :
Anna Bridge 180:96ed750bd169 305 * 1- Restart condition in all use cases (direction change or not)
Anna Bridge 180:96ed750bd169 306 */
Anna Bridge 180:96ed750bd169 307 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
Anna Bridge 180:96ed750bd169 308 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
Anna Bridge 180:96ed750bd169 309 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
Anna Bridge 180:96ed750bd169 310 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
<> 144:ef7eb2e8f9f7 316 * @brief SMBUS Interrupt definition
<> 144:ef7eb2e8f9f7 317 * Elements values convention: 0xXXXXXXXX
<> 144:ef7eb2e8f9f7 318 * - XXXXXXXX : Interrupt control mask
<> 144:ef7eb2e8f9f7 319 * @{
<> 144:ef7eb2e8f9f7 320 */
<> 156:95d6b41a828b 321 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
<> 156:95d6b41a828b 322 #define SMBUS_IT_TCI I2C_CR1_TCIE
<> 156:95d6b41a828b 323 #define SMBUS_IT_STOPI I2C_CR1_STOPIE
<> 156:95d6b41a828b 324 #define SMBUS_IT_NACKI I2C_CR1_NACKIE
<> 156:95d6b41a828b 325 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
<> 156:95d6b41a828b 326 #define SMBUS_IT_RXI I2C_CR1_RXIE
<> 156:95d6b41a828b 327 #define SMBUS_IT_TXI I2C_CR1_TXIE
<> 156:95d6b41a828b 328 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
<> 156:95d6b41a828b 329 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
<> 156:95d6b41a828b 330 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
<> 156:95d6b41a828b 331 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
<> 144:ef7eb2e8f9f7 337 * @brief Flag definition
<> 144:ef7eb2e8f9f7 338 * Elements values convention: 0xXXXXYYYY
<> 144:ef7eb2e8f9f7 339 * - XXXXXXXX : Flag mask
<> 144:ef7eb2e8f9f7 340 * @{
Anna Bridge 180:96ed750bd169 341 */
<> 144:ef7eb2e8f9f7 342
<> 156:95d6b41a828b 343 #define SMBUS_FLAG_TXE I2C_ISR_TXE
<> 156:95d6b41a828b 344 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS
<> 156:95d6b41a828b 345 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE
<> 156:95d6b41a828b 346 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR
<> 156:95d6b41a828b 347 #define SMBUS_FLAG_AF I2C_ISR_NACKF
<> 156:95d6b41a828b 348 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF
<> 156:95d6b41a828b 349 #define SMBUS_FLAG_TC I2C_ISR_TC
<> 156:95d6b41a828b 350 #define SMBUS_FLAG_TCR I2C_ISR_TCR
<> 156:95d6b41a828b 351 #define SMBUS_FLAG_BERR I2C_ISR_BERR
<> 156:95d6b41a828b 352 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO
<> 156:95d6b41a828b 353 #define SMBUS_FLAG_OVR I2C_ISR_OVR
<> 156:95d6b41a828b 354 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR
<> 156:95d6b41a828b 355 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
<> 156:95d6b41a828b 356 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT
<> 156:95d6b41a828b 357 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY
<> 156:95d6b41a828b 358 #define SMBUS_FLAG_DIR I2C_ISR_DIR
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @}
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 368 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
<> 144:ef7eb2e8f9f7 369 * @{
Anna Bridge 180:96ed750bd169 370 */
Anna Bridge 180:96ed750bd169 371
<> 144:ef7eb2e8f9f7 372 /** @brief Reset SMBUS handle state.
<> 144:ef7eb2e8f9f7 373 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 374 * @retval None
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /** @brief Enable the specified SMBUS interrupts.
<> 144:ef7eb2e8f9f7 379 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 380 * @param __INTERRUPT__ specifies the interrupt source to enable.
<> 144:ef7eb2e8f9f7 381 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 382 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 383 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 384 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 385 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 386 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 387 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 388 * @arg @ref SMBUS_IT_TXI TX interrupt enable
Anna Bridge 180:96ed750bd169 389 *
<> 144:ef7eb2e8f9f7 390 * @retval None
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /** @brief Disable the specified SMBUS interrupts.
<> 144:ef7eb2e8f9f7 395 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 396 * @param __INTERRUPT__ specifies the interrupt source to disable.
<> 144:ef7eb2e8f9f7 397 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 398 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 399 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 400 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 401 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 402 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 403 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 404 * @arg @ref SMBUS_IT_TXI TX interrupt enable
Anna Bridge 180:96ed750bd169 405 *
<> 144:ef7eb2e8f9f7 406 * @retval None
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Anna Bridge 180:96ed750bd169 409
<> 144:ef7eb2e8f9f7 410 /** @brief Check whether the specified SMBUS interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 411 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 412 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
<> 144:ef7eb2e8f9f7 413 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 414 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 415 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 416 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 417 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 418 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 419 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 420 * @arg @ref SMBUS_IT_TXI TX interrupt enable
Anna Bridge 180:96ed750bd169 421 *
<> 144:ef7eb2e8f9f7 422 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /** @brief Check whether the specified SMBUS flag is set or not.
<> 144:ef7eb2e8f9f7 427 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 428 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 429 * This parameter can be one of the following values:
Anna Bridge 180:96ed750bd169 430 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
<> 144:ef7eb2e8f9f7 431 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
<> 144:ef7eb2e8f9f7 432 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
<> 144:ef7eb2e8f9f7 433 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
Anna Bridge 180:96ed750bd169 434 * @arg @ref SMBUS_FLAG_AF NACK received flag
<> 144:ef7eb2e8f9f7 435 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
Anna Bridge 180:96ed750bd169 436 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
Anna Bridge 180:96ed750bd169 437 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
<> 144:ef7eb2e8f9f7 438 * @arg @ref SMBUS_FLAG_BERR Bus error
<> 144:ef7eb2e8f9f7 439 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
Anna Bridge 180:96ed750bd169 440 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
<> 144:ef7eb2e8f9f7 441 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
Anna Bridge 180:96ed750bd169 442 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 443 * @arg @ref SMBUS_FLAG_ALERT SMBus alert
<> 144:ef7eb2e8f9f7 444 * @arg @ref SMBUS_FLAG_BUSY Bus busy
<> 144:ef7eb2e8f9f7 445 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
Anna Bridge 180:96ed750bd169 446 *
<> 144:ef7eb2e8f9f7 447 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 448 */
<> 156:95d6b41a828b 449 #define SMBUS_FLAG_MASK (0x0001FFFFU)
<> 144:ef7eb2e8f9f7 450 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
Anna Bridge 180:96ed750bd169 451
<> 144:ef7eb2e8f9f7 452 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
<> 144:ef7eb2e8f9f7 453 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 454 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 455 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 456 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
Anna Bridge 180:96ed750bd169 457 * @arg @ref SMBUS_FLAG_AF NACK received flag
<> 144:ef7eb2e8f9f7 458 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
<> 144:ef7eb2e8f9f7 459 * @arg @ref SMBUS_FLAG_BERR Bus error
<> 144:ef7eb2e8f9f7 460 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
Anna Bridge 180:96ed750bd169 461 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
<> 144:ef7eb2e8f9f7 462 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
Anna Bridge 180:96ed750bd169 463 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 464 * @arg @ref SMBUS_FLAG_ALERT SMBus alert
Anna Bridge 180:96ed750bd169 465 *
<> 144:ef7eb2e8f9f7 466 * @retval None
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Anna Bridge 180:96ed750bd169 469
<> 144:ef7eb2e8f9f7 470 /** @brief Enable the specified SMBUS peripheral.
Anna Bridge 180:96ed750bd169 471 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 472 * @retval None
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /** @brief Disable the specified SMBUS peripheral.
Anna Bridge 180:96ed750bd169 477 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 478 * @retval None
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
Anna Bridge 180:96ed750bd169 483 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 484 * @retval None
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @}
Anna Bridge 180:96ed750bd169 490 */
Anna Bridge 180:96ed750bd169 491
Anna Bridge 180:96ed750bd169 492
<> 144:ef7eb2e8f9f7 493 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 496 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
<> 144:ef7eb2e8f9f7 497 * @{
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
<> 144:ef7eb2e8f9f7 501 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
<> 144:ef7eb2e8f9f7 502
Anna Bridge 180:96ed750bd169 503 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
Anna Bridge 180:96ed750bd169 504
<> 144:ef7eb2e8f9f7 505 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
<> 144:ef7eb2e8f9f7 506 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
<> 144:ef7eb2e8f9f7 509 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
<> 144:ef7eb2e8f9f7 512 ((MASK) == SMBUS_OA2_MASK01) || \
<> 144:ef7eb2e8f9f7 513 ((MASK) == SMBUS_OA2_MASK02) || \
<> 144:ef7eb2e8f9f7 514 ((MASK) == SMBUS_OA2_MASK03) || \
<> 144:ef7eb2e8f9f7 515 ((MASK) == SMBUS_OA2_MASK04) || \
<> 144:ef7eb2e8f9f7 516 ((MASK) == SMBUS_OA2_MASK05) || \
<> 144:ef7eb2e8f9f7 517 ((MASK) == SMBUS_OA2_MASK06) || \
Anna Bridge 180:96ed750bd169 518 ((MASK) == SMBUS_OA2_MASK07))
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
<> 144:ef7eb2e8f9f7 521 ((CALL) == SMBUS_GENERALCALL_ENABLE))
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
<> 144:ef7eb2e8f9f7 524 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
<> 144:ef7eb2e8f9f7 527 ((PEC) == SMBUS_PEC_ENABLE))
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
<> 144:ef7eb2e8f9f7 530 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
<> 144:ef7eb2e8f9f7 531 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
<> 144:ef7eb2e8f9f7 534 ((MODE) == SMBUS_AUTOEND_MODE) || \
<> 144:ef7eb2e8f9f7 535 ((MODE) == SMBUS_SOFTEND_MODE) || \
Anna Bridge 180:96ed750bd169 536 ((MODE) == SMBUS_SENDPEC_MODE) || \
<> 144:ef7eb2e8f9f7 537 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
<> 144:ef7eb2e8f9f7 538 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
<> 144:ef7eb2e8f9f7 539 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
<> 144:ef7eb2e8f9f7 540 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
Anna Bridge 180:96ed750bd169 541
Anna Bridge 180:96ed750bd169 542
<> 144:ef7eb2e8f9f7 543 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
<> 144:ef7eb2e8f9f7 544 ((REQUEST) == SMBUS_GENERATE_START_READ) || \
<> 144:ef7eb2e8f9f7 545 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
<> 144:ef7eb2e8f9f7 546 ((REQUEST) == SMBUS_NO_STARTSTOP))
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
<> 144:ef7eb2e8f9f7 550 ((REQUEST) == SMBUS_NEXT_FRAME) || \
<> 144:ef7eb2e8f9f7 551 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
<> 144:ef7eb2e8f9f7 552 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
<> 144:ef7eb2e8f9f7 553 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
Anna Bridge 180:96ed750bd169 554 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
Anna Bridge 180:96ed750bd169 555 IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
Anna Bridge 180:96ed750bd169 556
Anna Bridge 180:96ed750bd169 557 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
Anna Bridge 180:96ed750bd169 558 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
Anna Bridge 180:96ed750bd169 559 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
Anna Bridge 180:96ed750bd169 560 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
<> 144:ef7eb2e8f9f7 563 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
<> 144:ef7eb2e8f9f7 566 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 567
<> 156:95d6b41a828b 568 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
<> 156:95d6b41a828b 569 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
<> 144:ef7eb2e8f9f7 570 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
<> 144:ef7eb2e8f9f7 571 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
<> 144:ef7eb2e8f9f7 572 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
<> 144:ef7eb2e8f9f7 575 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
<> 144:ef7eb2e8f9f7 576
<> 156:95d6b41a828b 577 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
<> 156:95d6b41a828b 578 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @}
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 585 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
<> 144:ef7eb2e8f9f7 586 * @{
<> 144:ef7eb2e8f9f7 587 */
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 590 * @{
<> 144:ef7eb2e8f9f7 591 */
Anna Bridge 180:96ed750bd169 592
<> 144:ef7eb2e8f9f7 593 /* Initialization and de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 594 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
Anna Bridge 180:96ed750bd169 595 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 596 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 597 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
Anna Bridge 180:96ed750bd169 598 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
Anna Bridge 180:96ed750bd169 599 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @}
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 606 * @{
<> 144:ef7eb2e8f9f7 607 */
Anna Bridge 180:96ed750bd169 608
<> 144:ef7eb2e8f9f7 609 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 610 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
<> 144:ef7eb2e8f9f7 611 * @{
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 /******* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 614 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 615 /**
<> 144:ef7eb2e8f9f7 616 * @}
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
<> 144:ef7eb2e8f9f7 620 * @{
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 /******* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 623 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 624 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 625 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
<> 144:ef7eb2e8f9f7 626 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 627 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 630 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 631 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 632 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 633 /**
<> 144:ef7eb2e8f9f7 634 * @}
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 638 * @{
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
<> 144:ef7eb2e8f9f7 641 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 642 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 643 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 644 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 645 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 646 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 647 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 144:ef7eb2e8f9f7 648 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 649 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @}
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
Anna Bridge 180:96ed750bd169 655 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 656 * @{
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Peripheral State and Errors functions **************************************************/
<> 144:ef7eb2e8f9f7 660 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 661 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @}
<> 144:ef7eb2e8f9f7 665 */
<> 156:95d6b41a828b 666
<> 144:ef7eb2e8f9f7 667 /**
<> 144:ef7eb2e8f9f7 668 * @}
Anna Bridge 180:96ed750bd169 669 */
<> 144:ef7eb2e8f9f7 670
<> 156:95d6b41a828b 671 /* Private Functions ---------------------------------------------------------*/
<> 156:95d6b41a828b 672 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
<> 156:95d6b41a828b 673 * @{
<> 156:95d6b41a828b 674 */
<> 156:95d6b41a828b 675 /* Private functions are defined in stm32f0xx_hal_smbus.c file */
<> 156:95d6b41a828b 676 /**
<> 156:95d6b41a828b 677 * @}
Anna Bridge 180:96ed750bd169 678 */
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /**
<> 144:ef7eb2e8f9f7 681 * @}
Anna Bridge 180:96ed750bd169 682 */
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /**
<> 144:ef7eb2e8f9f7 685 * @}
Anna Bridge 180:96ed750bd169 686 */
<> 156:95d6b41a828b 687
<> 156:95d6b41a828b 688 /**
<> 156:95d6b41a828b 689 * @}
Anna Bridge 180:96ed750bd169 690 */
<> 156:95d6b41a828b 691
<> 144:ef7eb2e8f9f7 692 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694 #endif
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 #endif /* __STM32F0xx_HAL_SMBUS_H */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/