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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_smbus.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SMBUS HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 156:95d6b41a828b 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_SMBUS_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_SMBUS_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SMBUS
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
<> 144:ef7eb2e8f9f7 63 * @brief SMBUS Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
<> 144:ef7eb2e8f9f7 69 This parameter calculated by referring to SMBUS initialization
<> 144:ef7eb2e8f9f7 70 section in Reference manual */
<> 144:ef7eb2e8f9f7 71 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref SMBUS_Analog_Filter */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 144:ef7eb2e8f9f7 75 This parameter can be a 7-bit or 10-bit address. */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref SMBUS_addressing_mode */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 144:ef7eb2e8f9f7 81 This parameter can be a value of @ref SMBUS_dual_addressing_mode */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 84 This parameter can be a 7-bit address. */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 87 This parameter can be a value of @ref SMBUS_own_address2_masks. */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref SMBUS_nostretch_mode */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref SMBUS_packet_error_check_mode */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref SMBUS_peripheral_mode */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
<> 144:ef7eb2e8f9f7 102 (Enable bits and different timeout values)
<> 144:ef7eb2e8f9f7 103 This parameter calculated by referring to SMBUS initialization
<> 144:ef7eb2e8f9f7 104 section in Reference manual */
<> 144:ef7eb2e8f9f7 105 } SMBUS_InitTypeDef;
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @}
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @defgroup HAL_state_definition HAL state definition
<> 144:ef7eb2e8f9f7 111 * @brief HAL State definition
<> 144:ef7eb2e8f9f7 112 * @{
<> 144:ef7eb2e8f9f7 113 */
<> 156:95d6b41a828b 114 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
<> 156:95d6b41a828b 115 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
<> 156:95d6b41a828b 116 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
<> 156:95d6b41a828b 117 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
<> 156:95d6b41a828b 118 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
<> 156:95d6b41a828b 119 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
<> 156:95d6b41a828b 120 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
<> 156:95d6b41a828b 121 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
<> 156:95d6b41a828b 122 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
<> 156:95d6b41a828b 123 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
<> 144:ef7eb2e8f9f7 129 * @brief SMBUS Error Code definition
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 156:95d6b41a828b 132 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 133 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
<> 156:95d6b41a828b 134 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
<> 156:95d6b41a828b 135 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
<> 156:95d6b41a828b 136 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
<> 156:95d6b41a828b 137 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
<> 156:95d6b41a828b 138 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
<> 156:95d6b41a828b 139 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
<> 156:95d6b41a828b 140 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
<> 144:ef7eb2e8f9f7 146 * @brief SMBUS handle Structure definition
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 typedef struct
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 I2C_TypeDef *Instance; /*!< SMBUS registers base address */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 uint16_t XferSize; /*!< SMBUS transfer size */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 __IO uint16_t XferCount; /*!< SMBUS transfer counter */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 __IO uint32_t XferOptions; /*!< SMBUS transfer options */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 HAL_LockTypeDef Lock; /*!< SMBUS locking object */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 __IO uint32_t State; /*!< SMBUS communication state */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 __IO uint32_t ErrorCode; /*!< SMBUS Error code */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 }SMBUS_HandleTypeDef;
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
<> 144:ef7eb2e8f9f7 182 * @{
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
<> 156:95d6b41a828b 188 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
<> 156:95d6b41a828b 189 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 156:95d6b41a828b 197 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
<> 156:95d6b41a828b 198 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @}
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
<> 144:ef7eb2e8f9f7 204 * @{
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 156:95d6b41a828b 207 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
<> 156:95d6b41a828b 208 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @}
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216
<> 156:95d6b41a828b 217 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
<> 156:95d6b41a828b 218 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
<> 156:95d6b41a828b 219 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
<> 156:95d6b41a828b 220 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
<> 156:95d6b41a828b 221 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
<> 156:95d6b41a828b 222 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
<> 156:95d6b41a828b 223 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
<> 156:95d6b41a828b 224 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @}
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
<> 156:95d6b41a828b 233 #define SMBUS_GENERALCALL_DISABLE (0x00000000U)
<> 156:95d6b41a828b 234 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
<> 144:ef7eb2e8f9f7 240 * @{
<> 144:ef7eb2e8f9f7 241 */
<> 156:95d6b41a828b 242 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
<> 156:95d6b41a828b 243 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 156:95d6b41a828b 251 #define SMBUS_PEC_DISABLE (0x00000000U)
<> 156:95d6b41a828b 252 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 156:95d6b41a828b 260 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
<> 156:95d6b41a828b 261 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
<> 156:95d6b41a828b 262 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @}
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270
<> 156:95d6b41a828b 271 #define SMBUS_SOFTEND_MODE (0x00000000U)
<> 144:ef7eb2e8f9f7 272 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
<> 144:ef7eb2e8f9f7 273 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
<> 144:ef7eb2e8f9f7 274 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
<> 144:ef7eb2e8f9f7 275 /**
<> 144:ef7eb2e8f9f7 276 * @}
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
<> 144:ef7eb2e8f9f7 280 * @{
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 156:95d6b41a828b 283 #define SMBUS_NO_STARTSTOP (0x00000000U)
<> 144:ef7eb2e8f9f7 284 #define SMBUS_GENERATE_STOP I2C_CR2_STOP
<> 144:ef7eb2e8f9f7 285 #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
<> 144:ef7eb2e8f9f7 286 #define SMBUS_GENERATE_START_WRITE I2C_CR2_START
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294
<> 156:95d6b41a828b 295 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
<> 144:ef7eb2e8f9f7 296 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
<> 144:ef7eb2e8f9f7 297 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
<> 144:ef7eb2e8f9f7 298 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
<> 144:ef7eb2e8f9f7 299 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
<> 144:ef7eb2e8f9f7 300 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @}
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
<> 144:ef7eb2e8f9f7 306 * @brief SMBUS Interrupt definition
<> 144:ef7eb2e8f9f7 307 * Elements values convention: 0xXXXXXXXX
<> 144:ef7eb2e8f9f7 308 * - XXXXXXXX : Interrupt control mask
<> 144:ef7eb2e8f9f7 309 * @{
<> 144:ef7eb2e8f9f7 310 */
<> 156:95d6b41a828b 311 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
<> 156:95d6b41a828b 312 #define SMBUS_IT_TCI I2C_CR1_TCIE
<> 156:95d6b41a828b 313 #define SMBUS_IT_STOPI I2C_CR1_STOPIE
<> 156:95d6b41a828b 314 #define SMBUS_IT_NACKI I2C_CR1_NACKIE
<> 156:95d6b41a828b 315 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
<> 156:95d6b41a828b 316 #define SMBUS_IT_RXI I2C_CR1_RXIE
<> 156:95d6b41a828b 317 #define SMBUS_IT_TXI I2C_CR1_TXIE
<> 156:95d6b41a828b 318 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
<> 156:95d6b41a828b 319 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
<> 156:95d6b41a828b 320 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
<> 156:95d6b41a828b 321 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
<> 144:ef7eb2e8f9f7 327 * @brief Flag definition
<> 144:ef7eb2e8f9f7 328 * Elements values convention: 0xXXXXYYYY
<> 144:ef7eb2e8f9f7 329 * - XXXXXXXX : Flag mask
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 156:95d6b41a828b 333 #define SMBUS_FLAG_TXE I2C_ISR_TXE
<> 156:95d6b41a828b 334 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS
<> 156:95d6b41a828b 335 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE
<> 156:95d6b41a828b 336 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR
<> 156:95d6b41a828b 337 #define SMBUS_FLAG_AF I2C_ISR_NACKF
<> 156:95d6b41a828b 338 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF
<> 156:95d6b41a828b 339 #define SMBUS_FLAG_TC I2C_ISR_TC
<> 156:95d6b41a828b 340 #define SMBUS_FLAG_TCR I2C_ISR_TCR
<> 156:95d6b41a828b 341 #define SMBUS_FLAG_BERR I2C_ISR_BERR
<> 156:95d6b41a828b 342 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO
<> 156:95d6b41a828b 343 #define SMBUS_FLAG_OVR I2C_ISR_OVR
<> 156:95d6b41a828b 344 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR
<> 156:95d6b41a828b 345 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
<> 156:95d6b41a828b 346 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT
<> 156:95d6b41a828b 347 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY
<> 156:95d6b41a828b 348 #define SMBUS_FLAG_DIR I2C_ISR_DIR
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 358 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
<> 144:ef7eb2e8f9f7 359 * @{
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /** @brief Reset SMBUS handle state.
<> 144:ef7eb2e8f9f7 363 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 364 * @retval None
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /** @brief Enable the specified SMBUS interrupts.
<> 144:ef7eb2e8f9f7 369 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 370 * @param __INTERRUPT__ specifies the interrupt source to enable.
<> 144:ef7eb2e8f9f7 371 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 372 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 373 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 374 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 375 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 376 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 377 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 378 * @arg @ref SMBUS_IT_TXI TX interrupt enable
<> 144:ef7eb2e8f9f7 379 *
<> 144:ef7eb2e8f9f7 380 * @retval None
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /** @brief Disable the specified SMBUS interrupts.
<> 144:ef7eb2e8f9f7 385 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 386 * @param __INTERRUPT__ specifies the interrupt source to disable.
<> 144:ef7eb2e8f9f7 387 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 388 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 389 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 390 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 391 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 392 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 393 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 394 * @arg @ref SMBUS_IT_TXI TX interrupt enable
<> 144:ef7eb2e8f9f7 395 *
<> 144:ef7eb2e8f9f7 396 * @retval None
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /** @brief Check whether the specified SMBUS interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 401 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 402 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
<> 144:ef7eb2e8f9f7 403 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 404 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 405 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 406 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 407 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 408 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 409 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 410 * @arg @ref SMBUS_IT_TXI TX interrupt enable
<> 144:ef7eb2e8f9f7 411 *
<> 144:ef7eb2e8f9f7 412 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /** @brief Check whether the specified SMBUS flag is set or not.
<> 144:ef7eb2e8f9f7 417 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 418 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 419 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 420 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
<> 144:ef7eb2e8f9f7 421 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
<> 144:ef7eb2e8f9f7 422 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
<> 144:ef7eb2e8f9f7 423 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
<> 144:ef7eb2e8f9f7 424 * @arg @ref SMBUS_FLAG_AF NACK received flag
<> 144:ef7eb2e8f9f7 425 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
<> 144:ef7eb2e8f9f7 426 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
<> 144:ef7eb2e8f9f7 427 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
<> 144:ef7eb2e8f9f7 428 * @arg @ref SMBUS_FLAG_BERR Bus error
<> 144:ef7eb2e8f9f7 429 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
<> 144:ef7eb2e8f9f7 430 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
<> 144:ef7eb2e8f9f7 431 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
<> 144:ef7eb2e8f9f7 432 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 433 * @arg @ref SMBUS_FLAG_ALERT SMBus alert
<> 144:ef7eb2e8f9f7 434 * @arg @ref SMBUS_FLAG_BUSY Bus busy
<> 144:ef7eb2e8f9f7 435 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
<> 144:ef7eb2e8f9f7 436 *
<> 144:ef7eb2e8f9f7 437 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 438 */
<> 156:95d6b41a828b 439 #define SMBUS_FLAG_MASK (0x0001FFFFU)
<> 144:ef7eb2e8f9f7 440 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
<> 144:ef7eb2e8f9f7 443 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 444 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 445 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 446 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
<> 144:ef7eb2e8f9f7 447 * @arg @ref SMBUS_FLAG_AF NACK received flag
<> 144:ef7eb2e8f9f7 448 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
<> 144:ef7eb2e8f9f7 449 * @arg @ref SMBUS_FLAG_BERR Bus error
<> 144:ef7eb2e8f9f7 450 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
<> 144:ef7eb2e8f9f7 451 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
<> 144:ef7eb2e8f9f7 452 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
<> 144:ef7eb2e8f9f7 453 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 454 * @arg @ref SMBUS_FLAG_ALERT SMBus alert
<> 144:ef7eb2e8f9f7 455 *
<> 144:ef7eb2e8f9f7 456 * @retval None
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /** @brief Enable the specified SMBUS peripheral.
<> 144:ef7eb2e8f9f7 461 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 462 * @retval None
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /** @brief Disable the specified SMBUS peripheral.
<> 144:ef7eb2e8f9f7 467 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 468 * @retval None
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
<> 144:ef7eb2e8f9f7 473 * @param __HANDLE__ specifies the SMBUS Handle.
<> 144:ef7eb2e8f9f7 474 * @retval None
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @}
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 486 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
<> 144:ef7eb2e8f9f7 487 * @{
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
<> 144:ef7eb2e8f9f7 491 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
<> 144:ef7eb2e8f9f7 494 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
<> 144:ef7eb2e8f9f7 497 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
<> 144:ef7eb2e8f9f7 500 ((MASK) == SMBUS_OA2_MASK01) || \
<> 144:ef7eb2e8f9f7 501 ((MASK) == SMBUS_OA2_MASK02) || \
<> 144:ef7eb2e8f9f7 502 ((MASK) == SMBUS_OA2_MASK03) || \
<> 144:ef7eb2e8f9f7 503 ((MASK) == SMBUS_OA2_MASK04) || \
<> 144:ef7eb2e8f9f7 504 ((MASK) == SMBUS_OA2_MASK05) || \
<> 144:ef7eb2e8f9f7 505 ((MASK) == SMBUS_OA2_MASK06) || \
<> 144:ef7eb2e8f9f7 506 ((MASK) == SMBUS_OA2_MASK07))
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
<> 144:ef7eb2e8f9f7 509 ((CALL) == SMBUS_GENERALCALL_ENABLE))
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
<> 144:ef7eb2e8f9f7 512 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
<> 144:ef7eb2e8f9f7 515 ((PEC) == SMBUS_PEC_ENABLE))
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
<> 144:ef7eb2e8f9f7 518 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
<> 144:ef7eb2e8f9f7 519 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
<> 144:ef7eb2e8f9f7 522 ((MODE) == SMBUS_AUTOEND_MODE) || \
<> 144:ef7eb2e8f9f7 523 ((MODE) == SMBUS_SOFTEND_MODE) || \
<> 144:ef7eb2e8f9f7 524 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
<> 144:ef7eb2e8f9f7 525 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
<> 144:ef7eb2e8f9f7 526 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
<> 144:ef7eb2e8f9f7 527 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
<> 144:ef7eb2e8f9f7 531 ((REQUEST) == SMBUS_GENERATE_START_READ) || \
<> 144:ef7eb2e8f9f7 532 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
<> 144:ef7eb2e8f9f7 533 ((REQUEST) == SMBUS_NO_STARTSTOP))
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
<> 144:ef7eb2e8f9f7 537 ((REQUEST) == SMBUS_NEXT_FRAME) || \
<> 144:ef7eb2e8f9f7 538 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
<> 144:ef7eb2e8f9f7 539 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
<> 144:ef7eb2e8f9f7 540 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
<> 144:ef7eb2e8f9f7 541 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
<> 144:ef7eb2e8f9f7 544 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
<> 144:ef7eb2e8f9f7 547 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 548
<> 156:95d6b41a828b 549 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
<> 156:95d6b41a828b 550 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
<> 144:ef7eb2e8f9f7 551 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
<> 144:ef7eb2e8f9f7 552 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
<> 144:ef7eb2e8f9f7 553 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
<> 144:ef7eb2e8f9f7 556 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
<> 144:ef7eb2e8f9f7 557
<> 156:95d6b41a828b 558 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
<> 156:95d6b41a828b 559 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @}
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Private Functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 566 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
<> 144:ef7eb2e8f9f7 567 * @{
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569 /* Private functions are defined in stm32f0xx_hal_smbus.c file */
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @}
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 575 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
<> 144:ef7eb2e8f9f7 576 * @{
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 580 * @{
<> 144:ef7eb2e8f9f7 581 */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Initialization and de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 584 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 585 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 586 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 587 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /**
<> 144:ef7eb2e8f9f7 590 * @}
<> 144:ef7eb2e8f9f7 591 */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 594 * @{
<> 144:ef7eb2e8f9f7 595 */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 598 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
<> 144:ef7eb2e8f9f7 599 * @{
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601 /******* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 602 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @}
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
<> 144:ef7eb2e8f9f7 608 * @{
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610 /******* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 611 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 612 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 613 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
<> 144:ef7eb2e8f9f7 614 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 615 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 618 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 619 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 620 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @}
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 626 * @{
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
<> 144:ef7eb2e8f9f7 629 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 630 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 631 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 632 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 633 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 634 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 635 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 144:ef7eb2e8f9f7 636 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 637 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @}
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 644 * @{
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Peripheral State and Errors functions **************************************************/
<> 144:ef7eb2e8f9f7 648 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 649 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @}
<> 144:ef7eb2e8f9f7 653 */
<> 156:95d6b41a828b 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @}
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658
<> 156:95d6b41a828b 659 /* Private Functions ---------------------------------------------------------*/
<> 156:95d6b41a828b 660 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
<> 156:95d6b41a828b 661 * @{
<> 156:95d6b41a828b 662 */
<> 156:95d6b41a828b 663 /* Private functions are defined in stm32f0xx_hal_smbus.c file */
<> 156:95d6b41a828b 664 /**
<> 156:95d6b41a828b 665 * @}
<> 156:95d6b41a828b 666 */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @}
<> 144:ef7eb2e8f9f7 670 */
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @}
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @}
<> 156:95d6b41a828b 678 */
<> 156:95d6b41a828b 679
<> 156:95d6b41a828b 680 /**
<> 156:95d6b41a828b 681 * @}
<> 156:95d6b41a828b 682 */
<> 156:95d6b41a828b 683
<> 144:ef7eb2e8f9f7 684 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686 #endif
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 #endif /* __STM32F0xx_HAL_SMBUS_H */
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/