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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_smbus.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief SMBUS HAL module driver.
Anna Bridge 180:96ed750bd169 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the System Management Bus (SMBus) peripheral,
<> 144:ef7eb2e8f9f7 8 * based on I2C principles of operation :
<> 144:ef7eb2e8f9f7 9 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + IO operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral State and Errors functions
Anna Bridge 180:96ed750bd169 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The SMBUS HAL driver can be used as follows:
Anna Bridge 180:96ed750bd169 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
Anna Bridge 180:96ed750bd169 21 SMBUS_HandleTypeDef hsmbus;
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
<> 144:ef7eb2e8f9f7 24 (##) Enable the SMBUSx interface clock
<> 144:ef7eb2e8f9f7 25 (##) SMBUS pins configuration
<> 144:ef7eb2e8f9f7 26 (+++) Enable the clock for the SMBUS GPIOs
<> 144:ef7eb2e8f9f7 27 (+++) Configure SMBUS pins as alternate function open-drain
<> 144:ef7eb2e8f9f7 28 (##) NVIC configuration if you need to use interrupt process
Anna Bridge 180:96ed750bd169 29 (+++) Configure the SMBUSx interrupt priority
<> 144:ef7eb2e8f9f7 30 (+++) Enable the NVIC SMBUS IRQ Channel
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
<> 144:ef7eb2e8f9f7 33 Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
<> 144:ef7eb2e8f9f7 34 Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
<> 144:ef7eb2e8f9f7 37 (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 38 by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (#) For SMBUS IO operations, only one mode of operations is available within this driver
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 45 ===================================
<> 144:ef7eb2e8f9f7 46 [..]
<> 144:ef7eb2e8f9f7 47 (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
<> 144:ef7eb2e8f9f7 48 (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 49 add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 50 (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
<> 144:ef7eb2e8f9f7 51 (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 52 add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 53 (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
<> 144:ef7eb2e8f9f7 54 (++) The associated previous transfer callback is called at the end of abort process
<> 144:ef7eb2e8f9f7 55 (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
<> 144:ef7eb2e8f9f7 56 (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
<> 144:ef7eb2e8f9f7 57 (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
<> 144:ef7eb2e8f9f7 58 using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
<> 144:ef7eb2e8f9f7 59 (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
<> 144:ef7eb2e8f9f7 60 add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
<> 144:ef7eb2e8f9f7 61 (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 62 add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
<> 144:ef7eb2e8f9f7 63 (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
<> 144:ef7eb2e8f9f7 64 (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 65 add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 66 (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
<> 144:ef7eb2e8f9f7 67 (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 68 add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 69 (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
<> 144:ef7eb2e8f9f7 70 (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
<> 144:ef7eb2e8f9f7 72 to check the Alert Error Code using function HAL_SMBUS_GetError()
<> 144:ef7eb2e8f9f7 73 (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
<> 144:ef7eb2e8f9f7 74 (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 75 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
<> 144:ef7eb2e8f9f7 76 to check the Error Code using function HAL_SMBUS_GetError()
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 *** SMBUS HAL driver macros list ***
<> 144:ef7eb2e8f9f7 79 ==================================
<> 144:ef7eb2e8f9f7 80 [..]
<> 144:ef7eb2e8f9f7 81 Below the list of most used macros in SMBUS HAL driver.
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
<> 144:ef7eb2e8f9f7 84 (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
<> 144:ef7eb2e8f9f7 85 (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
<> 144:ef7eb2e8f9f7 86 (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
<> 144:ef7eb2e8f9f7 87 (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
<> 144:ef7eb2e8f9f7 88 (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 [..]
<> 144:ef7eb2e8f9f7 91 (@) You can refer to the SMBUS HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 92
Anna Bridge 180:96ed750bd169 93
<> 144:ef7eb2e8f9f7 94 @endverbatim
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 * @attention
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 101 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 102 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 103 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 104 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 105 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 106 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 107 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 108 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 109 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 112 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 113 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 114 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 115 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 116 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 117 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 118 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 119 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 120 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 121 *
Anna Bridge 180:96ed750bd169 122 ******************************************************************************
Anna Bridge 180:96ed750bd169 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 126 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 129 * @{
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** @defgroup SMBUS SMBUS
<> 144:ef7eb2e8f9f7 133 * @brief SMBUS HAL module driver
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 #ifdef HAL_SMBUS_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
<> 144:ef7eb2e8f9f7 142 * @{
<> 144:ef7eb2e8f9f7 143 */
<> 156:95d6b41a828b 144 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
<> 156:95d6b41a828b 145 #define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
<> 156:95d6b41a828b 146 #define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
<> 156:95d6b41a828b 147 #define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
<> 156:95d6b41a828b 148 #define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
<> 156:95d6b41a828b 149 #define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
<> 156:95d6b41a828b 150 #define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
<> 156:95d6b41a828b 151 #define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
<> 156:95d6b41a828b 152 #define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
<> 156:95d6b41a828b 153 #define MAX_NBYTE_SIZE 255U
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
Anna Bridge 180:96ed750bd169 157
<> 144:ef7eb2e8f9f7 158 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 161 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
<> 144:ef7eb2e8f9f7 167 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
<> 144:ef7eb2e8f9f7 168 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 169 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 170
Anna Bridge 180:96ed750bd169 171 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
Anna Bridge 180:96ed750bd169 172
Anna Bridge 180:96ed750bd169 173 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
Anna Bridge 180:96ed750bd169 174
<> 144:ef7eb2e8f9f7 175 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
<> 144:ef7eb2e8f9f7 183 * @{
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
Anna Bridge 180:96ed750bd169 187 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 188 *
Anna Bridge 180:96ed750bd169 189 @verbatim
<> 144:ef7eb2e8f9f7 190 ===============================================================================
<> 144:ef7eb2e8f9f7 191 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 192 ===============================================================================
Anna Bridge 180:96ed750bd169 193 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 194 deinitialize the SMBUSx peripheral:
<> 144:ef7eb2e8f9f7 195
Anna Bridge 180:96ed750bd169 196 (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 197 all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
<> 144:ef7eb2e8f9f7 198
Anna Bridge 180:96ed750bd169 199 (+) Call the function HAL_SMBUS_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 200 the selected configuration:
<> 144:ef7eb2e8f9f7 201 (++) Clock Timing
<> 144:ef7eb2e8f9f7 202 (++) Bus Timeout
<> 144:ef7eb2e8f9f7 203 (++) Analog Filer mode
<> 144:ef7eb2e8f9f7 204 (++) Own Address 1
<> 144:ef7eb2e8f9f7 205 (++) Addressing mode (Master, Slave)
<> 144:ef7eb2e8f9f7 206 (++) Dual Addressing mode
<> 144:ef7eb2e8f9f7 207 (++) Own Address 2
<> 144:ef7eb2e8f9f7 208 (++) Own Address 2 Mask
<> 144:ef7eb2e8f9f7 209 (++) General call mode
<> 144:ef7eb2e8f9f7 210 (++) Nostretch mode
<> 144:ef7eb2e8f9f7 211 (++) Packet Error Check mode
<> 144:ef7eb2e8f9f7 212 (++) Peripheral mode
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214
Anna Bridge 180:96ed750bd169 215 (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
Anna Bridge 180:96ed750bd169 216 of the selected SMBUSx peripheral.
Anna Bridge 180:96ed750bd169 217
Anna Bridge 180:96ed750bd169 218 (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
Anna Bridge 180:96ed750bd169 219 HAL_SMBUS_ConfigDigitalFilter().
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 @endverbatim
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
Anna Bridge 180:96ed750bd169 226 * @brief Initialize the SMBUS according to the specified parameters
<> 144:ef7eb2e8f9f7 227 * in the SMBUS_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 228 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 229 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 230 * @retval HAL status
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
Anna Bridge 180:96ed750bd169 233 {
<> 144:ef7eb2e8f9f7 234 /* Check the SMBUS handle allocation */
Anna Bridge 180:96ed750bd169 235 if (hsmbus == NULL)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 238 }
Anna Bridge 180:96ed750bd169 239
<> 144:ef7eb2e8f9f7 240 /* Check the parameters */
<> 144:ef7eb2e8f9f7 241 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
<> 144:ef7eb2e8f9f7 242 assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
<> 144:ef7eb2e8f9f7 243 assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
<> 144:ef7eb2e8f9f7 244 assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
<> 144:ef7eb2e8f9f7 245 assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
<> 144:ef7eb2e8f9f7 246 assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
<> 144:ef7eb2e8f9f7 247 assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
<> 144:ef7eb2e8f9f7 248 assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
<> 144:ef7eb2e8f9f7 249 assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
<> 144:ef7eb2e8f9f7 250 assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
<> 144:ef7eb2e8f9f7 251 assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
<> 144:ef7eb2e8f9f7 252
Anna Bridge 180:96ed750bd169 253 if (hsmbus->State == HAL_SMBUS_STATE_RESET)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 256 hsmbus->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 259 HAL_SMBUS_MspInit(hsmbus);
<> 144:ef7eb2e8f9f7 260 }
Anna Bridge 180:96ed750bd169 261
<> 144:ef7eb2e8f9f7 262 hsmbus->State = HAL_SMBUS_STATE_BUSY;
Anna Bridge 180:96ed750bd169 263
<> 144:ef7eb2e8f9f7 264 /* Disable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 265 __HAL_SMBUS_DISABLE(hsmbus);
Anna Bridge 180:96ed750bd169 266
Anna Bridge 180:96ed750bd169 267 /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 268 /* Configure SMBUSx: Frequency range */
<> 144:ef7eb2e8f9f7 269 hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
Anna Bridge 180:96ed750bd169 270
Anna Bridge 180:96ed750bd169 271 /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 272 /* Configure SMBUSx: Bus Timeout */
<> 144:ef7eb2e8f9f7 273 hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
<> 144:ef7eb2e8f9f7 274 hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
<> 144:ef7eb2e8f9f7 275 hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 278 /* Configure SMBUSx: Own Address1 and ack own address1 mode */
<> 144:ef7eb2e8f9f7 279 hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
Anna Bridge 180:96ed750bd169 280
Anna Bridge 180:96ed750bd169 281 if (hsmbus->Init.OwnAddress1 != 0U)
<> 144:ef7eb2e8f9f7 282 {
Anna Bridge 180:96ed750bd169 283 if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 else /* SMBUS_ADDRESSINGMODE_10BIT */
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 294 /* Configure SMBUSx: Addressing Master mode */
Anna Bridge 180:96ed750bd169 295 if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
<> 144:ef7eb2e8f9f7 300 /* AUTOEND and NACK bit will be manage during Transfer process */
<> 144:ef7eb2e8f9f7 301 hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
Anna Bridge 180:96ed750bd169 302
Anna Bridge 180:96ed750bd169 303 /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 304 /* Configure SMBUSx: Dual mode and Own Address2 */
<> 156:95d6b41a828b 305 hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 308 /* Configure SMBUSx: Generalcall and NoStretch mode */
<> 144:ef7eb2e8f9f7 309 hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
Anna Bridge 180:96ed750bd169 310
<> 144:ef7eb2e8f9f7 311 /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
Anna Bridge 180:96ed750bd169 312 if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
Anna Bridge 180:96ed750bd169 313 && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Enable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 319 __HAL_SMBUS_ENABLE(hsmbus);
Anna Bridge 180:96ed750bd169 320
<> 144:ef7eb2e8f9f7 321 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 322 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 323 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 324
<> 144:ef7eb2e8f9f7 325 return HAL_OK;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
Anna Bridge 180:96ed750bd169 329 * @brief DeInitialize the SMBUS peripheral.
<> 144:ef7eb2e8f9f7 330 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 331 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 332 * @retval HAL status
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /* Check the SMBUS handle allocation */
Anna Bridge 180:96ed750bd169 337 if (hsmbus == NULL)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 340 }
Anna Bridge 180:96ed750bd169 341
<> 144:ef7eb2e8f9f7 342 /* Check the parameters */
<> 144:ef7eb2e8f9f7 343 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
Anna Bridge 180:96ed750bd169 344
<> 144:ef7eb2e8f9f7 345 hsmbus->State = HAL_SMBUS_STATE_BUSY;
Anna Bridge 180:96ed750bd169 346
<> 144:ef7eb2e8f9f7 347 /* Disable the SMBUS Peripheral Clock */
<> 144:ef7eb2e8f9f7 348 __HAL_SMBUS_DISABLE(hsmbus);
Anna Bridge 180:96ed750bd169 349
<> 144:ef7eb2e8f9f7 350 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 351 HAL_SMBUS_MspDeInit(hsmbus);
Anna Bridge 180:96ed750bd169 352
<> 144:ef7eb2e8f9f7 353 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 354 hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
<> 144:ef7eb2e8f9f7 355 hsmbus->State = HAL_SMBUS_STATE_RESET;
Anna Bridge 180:96ed750bd169 356
Anna Bridge 180:96ed750bd169 357 /* Release Lock */
<> 144:ef7eb2e8f9f7 358 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 359
<> 144:ef7eb2e8f9f7 360 return HAL_OK;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @brief Initialize the SMBUS MSP.
<> 144:ef7eb2e8f9f7 365 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 366 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 367 * @retval None
<> 144:ef7eb2e8f9f7 368 */
Anna Bridge 180:96ed750bd169 369 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 372 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 375 the HAL_SMBUS_MspInit could be implemented in the user file
Anna Bridge 180:96ed750bd169 376 */
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @brief DeInitialize the SMBUS MSP.
<> 144:ef7eb2e8f9f7 381 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 382 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 383 * @retval None
<> 144:ef7eb2e8f9f7 384 */
Anna Bridge 180:96ed750bd169 385 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 388 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 391 the HAL_SMBUS_MspDeInit could be implemented in the user file
Anna Bridge 180:96ed750bd169 392 */
Anna Bridge 180:96ed750bd169 393 }
Anna Bridge 180:96ed750bd169 394
Anna Bridge 180:96ed750bd169 395 /**
Anna Bridge 180:96ed750bd169 396 * @brief Configure Analog noise filter.
Anna Bridge 180:96ed750bd169 397 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
Anna Bridge 180:96ed750bd169 398 * the configuration information for the specified SMBUS.
Anna Bridge 180:96ed750bd169 399 * @param AnalogFilter This parameter can be one of the following values:
Anna Bridge 180:96ed750bd169 400 * @arg @ref SMBUS_ANALOGFILTER_ENABLE
Anna Bridge 180:96ed750bd169 401 * @arg @ref SMBUS_ANALOGFILTER_DISABLE
Anna Bridge 180:96ed750bd169 402 * @retval HAL status
Anna Bridge 180:96ed750bd169 403 */
Anna Bridge 180:96ed750bd169 404 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Anna Bridge 180:96ed750bd169 405 {
Anna Bridge 180:96ed750bd169 406 /* Check the parameters */
Anna Bridge 180:96ed750bd169 407 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
Anna Bridge 180:96ed750bd169 408 assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
Anna Bridge 180:96ed750bd169 409
Anna Bridge 180:96ed750bd169 410 if (hsmbus->State == HAL_SMBUS_STATE_READY)
Anna Bridge 180:96ed750bd169 411 {
Anna Bridge 180:96ed750bd169 412 /* Process Locked */
Anna Bridge 180:96ed750bd169 413 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 414
Anna Bridge 180:96ed750bd169 415 hsmbus->State = HAL_SMBUS_STATE_BUSY;
Anna Bridge 180:96ed750bd169 416
Anna Bridge 180:96ed750bd169 417 /* Disable the selected SMBUS peripheral */
Anna Bridge 180:96ed750bd169 418 __HAL_SMBUS_DISABLE(hsmbus);
Anna Bridge 180:96ed750bd169 419
Anna Bridge 180:96ed750bd169 420 /* Reset ANOFF bit */
Anna Bridge 180:96ed750bd169 421 hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
Anna Bridge 180:96ed750bd169 422
Anna Bridge 180:96ed750bd169 423 /* Set analog filter bit*/
Anna Bridge 180:96ed750bd169 424 hsmbus->Instance->CR1 |= AnalogFilter;
Anna Bridge 180:96ed750bd169 425
Anna Bridge 180:96ed750bd169 426 __HAL_SMBUS_ENABLE(hsmbus);
Anna Bridge 180:96ed750bd169 427
Anna Bridge 180:96ed750bd169 428 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 429
Anna Bridge 180:96ed750bd169 430 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 431 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 432
Anna Bridge 180:96ed750bd169 433 return HAL_OK;
Anna Bridge 180:96ed750bd169 434 }
Anna Bridge 180:96ed750bd169 435 else
Anna Bridge 180:96ed750bd169 436 {
Anna Bridge 180:96ed750bd169 437 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 438 }
Anna Bridge 180:96ed750bd169 439 }
Anna Bridge 180:96ed750bd169 440
Anna Bridge 180:96ed750bd169 441 /**
Anna Bridge 180:96ed750bd169 442 * @brief Configure Digital noise filter.
Anna Bridge 180:96ed750bd169 443 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
Anna Bridge 180:96ed750bd169 444 * the configuration information for the specified SMBUS.
Anna Bridge 180:96ed750bd169 445 * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Anna Bridge 180:96ed750bd169 446 * @retval HAL status
Anna Bridge 180:96ed750bd169 447 */
Anna Bridge 180:96ed750bd169 448 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Anna Bridge 180:96ed750bd169 449 {
Anna Bridge 180:96ed750bd169 450 uint32_t tmpreg = 0U;
Anna Bridge 180:96ed750bd169 451
Anna Bridge 180:96ed750bd169 452 /* Check the parameters */
Anna Bridge 180:96ed750bd169 453 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
Anna Bridge 180:96ed750bd169 454 assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
Anna Bridge 180:96ed750bd169 455
Anna Bridge 180:96ed750bd169 456 if (hsmbus->State == HAL_SMBUS_STATE_READY)
Anna Bridge 180:96ed750bd169 457 {
Anna Bridge 180:96ed750bd169 458 /* Process Locked */
Anna Bridge 180:96ed750bd169 459 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 460
Anna Bridge 180:96ed750bd169 461 hsmbus->State = HAL_SMBUS_STATE_BUSY;
Anna Bridge 180:96ed750bd169 462
Anna Bridge 180:96ed750bd169 463 /* Disable the selected SMBUS peripheral */
Anna Bridge 180:96ed750bd169 464 __HAL_SMBUS_DISABLE(hsmbus);
Anna Bridge 180:96ed750bd169 465
Anna Bridge 180:96ed750bd169 466 /* Get the old register value */
Anna Bridge 180:96ed750bd169 467 tmpreg = hsmbus->Instance->CR1;
Anna Bridge 180:96ed750bd169 468
Anna Bridge 180:96ed750bd169 469 /* Reset I2C DNF bits [11:8] */
Anna Bridge 180:96ed750bd169 470 tmpreg &= ~(I2C_CR1_DNF);
Anna Bridge 180:96ed750bd169 471
Anna Bridge 180:96ed750bd169 472 /* Set I2Cx DNF coefficient */
Anna Bridge 180:96ed750bd169 473 tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
Anna Bridge 180:96ed750bd169 474
Anna Bridge 180:96ed750bd169 475 /* Store the new register value */
Anna Bridge 180:96ed750bd169 476 hsmbus->Instance->CR1 = tmpreg;
Anna Bridge 180:96ed750bd169 477
Anna Bridge 180:96ed750bd169 478 __HAL_SMBUS_ENABLE(hsmbus);
Anna Bridge 180:96ed750bd169 479
Anna Bridge 180:96ed750bd169 480 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 481
Anna Bridge 180:96ed750bd169 482 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 483 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 484
Anna Bridge 180:96ed750bd169 485 return HAL_OK;
Anna Bridge 180:96ed750bd169 486 }
Anna Bridge 180:96ed750bd169 487 else
Anna Bridge 180:96ed750bd169 488 {
Anna Bridge 180:96ed750bd169 489 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 490 }
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @}
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
Anna Bridge 180:96ed750bd169 498 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 499 *
Anna Bridge 180:96ed750bd169 500 @verbatim
<> 144:ef7eb2e8f9f7 501 ===============================================================================
<> 144:ef7eb2e8f9f7 502 ##### IO operation functions #####
Anna Bridge 180:96ed750bd169 503 ===============================================================================
<> 144:ef7eb2e8f9f7 504 [..]
Anna Bridge 180:96ed750bd169 505 This subsection provides a set of functions allowing to manage the SMBUS data
<> 144:ef7eb2e8f9f7 506 transfers.
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 (#) Blocking mode function to check if device is ready for usage is :
<> 144:ef7eb2e8f9f7 509 (++) HAL_SMBUS_IsDeviceReady()
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 (#) There is only one mode of transfer:
<> 144:ef7eb2e8f9f7 512 (++) Non-Blocking mode : The communication is performed using Interrupts.
<> 144:ef7eb2e8f9f7 513 These functions return the status of the transfer startup.
Anna Bridge 180:96ed750bd169 514 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 515 dedicated SMBUS IRQ when using Interrupt mode.
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 (#) Non-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 518 (++) HAL_SMBUS_Master_Transmit_IT()
<> 144:ef7eb2e8f9f7 519 (++) HAL_SMBUS_Master_Receive_IT()
<> 144:ef7eb2e8f9f7 520 (++) HAL_SMBUS_Slave_Transmit_IT()
<> 144:ef7eb2e8f9f7 521 (++) HAL_SMBUS_Slave_Receive_IT()
<> 144:ef7eb2e8f9f7 522 (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
<> 144:ef7eb2e8f9f7 523 (++) HAL_SMBUS_DisableListen_IT()
<> 144:ef7eb2e8f9f7 524 (++) HAL_SMBUS_EnableAlert_IT()
<> 144:ef7eb2e8f9f7 525 (++) HAL_SMBUS_DisableAlert_IT()
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
<> 144:ef7eb2e8f9f7 528 (++) HAL_SMBUS_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 529 (++) HAL_SMBUS_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 530 (++) HAL_SMBUS_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 531 (++) HAL_SMBUS_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 532 (++) HAL_SMBUS_AddrCallback()
<> 144:ef7eb2e8f9f7 533 (++) HAL_SMBUS_ListenCpltCallback()
<> 144:ef7eb2e8f9f7 534 (++) HAL_SMBUS_ErrorCallback()
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 @endverbatim
<> 144:ef7eb2e8f9f7 537 * @{
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 542 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 543 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 544 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 545 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 546 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 547 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 548 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 549 * @retval HAL status
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Anna Bridge 180:96ed750bd169 552 {
<> 144:ef7eb2e8f9f7 553 /* Check the parameters */
<> 144:ef7eb2e8f9f7 554 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 555
Anna Bridge 180:96ed750bd169 556 if (hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 /* Process Locked */
<> 144:ef7eb2e8f9f7 559 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 560
<> 144:ef7eb2e8f9f7 561 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
<> 144:ef7eb2e8f9f7 562 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 563 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 564 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 565 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 566 hsmbus->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* In case of Quick command, remove autoend mode */
<> 144:ef7eb2e8f9f7 569 /* Manage the stop generation by software */
Anna Bridge 180:96ed750bd169 570 if (hsmbus->pBuffPtr == NULL)
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574
Anna Bridge 180:96ed750bd169 575 if (Size > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 else
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 582 }
Anna Bridge 180:96ed750bd169 583
<> 144:ef7eb2e8f9f7 584 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 585 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
Anna Bridge 180:96ed750bd169 586 if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
<> 144:ef7eb2e8f9f7 587 {
Anna Bridge 180:96ed750bd169 588 SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 else
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 /* If transfer direction not change, do not generate Restart Condition */
<> 144:ef7eb2e8f9f7 593 /* Mean Previous state is same as current state */
Anna Bridge 180:96ed750bd169 594 if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
<> 144:ef7eb2e8f9f7 595 {
Anna Bridge 180:96ed750bd169 596 SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598 /* Else transfer direction change, so generate Restart with new transfer direction */
<> 144:ef7eb2e8f9f7 599 else
<> 144:ef7eb2e8f9f7 600 {
Anna Bridge 180:96ed750bd169 601 /* Convert OTHER_xxx XferOptions if any */
Anna Bridge 180:96ed750bd169 602 SMBUS_ConvertOtherXferOptions(hsmbus);
Anna Bridge 180:96ed750bd169 603
Anna Bridge 180:96ed750bd169 604 /* Handle Transfer */
Anna Bridge 180:96ed750bd169 605 SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 609 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
Anna Bridge 180:96ed750bd169 610 if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 613 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615 }
Anna Bridge 180:96ed750bd169 616
<> 144:ef7eb2e8f9f7 617 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 618 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 619
Anna Bridge 180:96ed750bd169 620 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 621 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 622 process unlock */
<> 144:ef7eb2e8f9f7 623 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
Anna Bridge 180:96ed750bd169 624
<> 144:ef7eb2e8f9f7 625 return HAL_OK;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 else
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 630 }
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /**
<> 144:ef7eb2e8f9f7 634 * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 635 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 636 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 637 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 638 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 639 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 640 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 641 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 642 * @retval HAL status
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 /* Check the parameters */
<> 144:ef7eb2e8f9f7 647 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 648
Anna Bridge 180:96ed750bd169 649 if (hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 /* Process Locked */
<> 144:ef7eb2e8f9f7 652 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 653
<> 144:ef7eb2e8f9f7 654 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
<> 144:ef7eb2e8f9f7 655 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
Anna Bridge 180:96ed750bd169 656
<> 144:ef7eb2e8f9f7 657 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 658 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 659 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 660 hsmbus->XferOptions = XferOptions;
Anna Bridge 180:96ed750bd169 661
<> 144:ef7eb2e8f9f7 662 /* In case of Quick command, remove autoend mode */
<> 144:ef7eb2e8f9f7 663 /* Manage the stop generation by software */
Anna Bridge 180:96ed750bd169 664 if (hsmbus->pBuffPtr == NULL)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 667 }
Anna Bridge 180:96ed750bd169 668
Anna Bridge 180:96ed750bd169 669 if (Size > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673 else
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 676 }
Anna Bridge 180:96ed750bd169 677
<> 144:ef7eb2e8f9f7 678 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 679 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
Anna Bridge 180:96ed750bd169 680 if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
<> 144:ef7eb2e8f9f7 681 {
Anna Bridge 180:96ed750bd169 682 SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684 else
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 /* If transfer direction not change, do not generate Restart Condition */
<> 144:ef7eb2e8f9f7 687 /* Mean Previous state is same as current state */
Anna Bridge 180:96ed750bd169 688 if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
<> 144:ef7eb2e8f9f7 689 {
Anna Bridge 180:96ed750bd169 690 SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 /* Else transfer direction change, so generate Restart with new transfer direction */
<> 144:ef7eb2e8f9f7 693 else
<> 144:ef7eb2e8f9f7 694 {
Anna Bridge 180:96ed750bd169 695 /* Convert OTHER_xxx XferOptions if any */
Anna Bridge 180:96ed750bd169 696 SMBUS_ConvertOtherXferOptions(hsmbus);
Anna Bridge 180:96ed750bd169 697
Anna Bridge 180:96ed750bd169 698 /* Handle Transfer */
Anna Bridge 180:96ed750bd169 699 SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701 }
Anna Bridge 180:96ed750bd169 702
<> 144:ef7eb2e8f9f7 703 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 704 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 705
Anna Bridge 180:96ed750bd169 706 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 707 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 708 process unlock */
<> 144:ef7eb2e8f9f7 709 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
Anna Bridge 180:96ed750bd169 710
<> 144:ef7eb2e8f9f7 711 return HAL_OK;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 else
<> 144:ef7eb2e8f9f7 714 {
Anna Bridge 180:96ed750bd169 715 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 716 }
<> 144:ef7eb2e8f9f7 717 }
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /**
<> 144:ef7eb2e8f9f7 720 * @brief Abort a master/host SMBUS process communication with Interrupt.
<> 144:ef7eb2e8f9f7 721 * @note This abort can be called only if state is ready
<> 144:ef7eb2e8f9f7 722 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 723 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 724 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 725 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 726 * @retval HAL status
<> 144:ef7eb2e8f9f7 727 */
<> 144:ef7eb2e8f9f7 728 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
<> 144:ef7eb2e8f9f7 729 {
Anna Bridge 180:96ed750bd169 730 if (hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 /* Process Locked */
<> 144:ef7eb2e8f9f7 733 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 734
<> 144:ef7eb2e8f9f7 735 /* Keep the same state as previous */
<> 144:ef7eb2e8f9f7 736 /* to perform as well the call of the corresponding end of transfer callback */
Anna Bridge 180:96ed750bd169 737 if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
<> 144:ef7eb2e8f9f7 740 }
Anna Bridge 180:96ed750bd169 741 else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745 else
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 /* Wrong usage of abort function */
<> 144:ef7eb2e8f9f7 748 /* This function should be used only in case of abort monitored by master device */
<> 144:ef7eb2e8f9f7 749 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 750 }
<> 144:ef7eb2e8f9f7 751 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
Anna Bridge 180:96ed750bd169 752
<> 144:ef7eb2e8f9f7 753 /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
<> 144:ef7eb2e8f9f7 754 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
<> 156:95d6b41a828b 755 SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
Anna Bridge 180:96ed750bd169 756
<> 144:ef7eb2e8f9f7 757 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 758 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 759
Anna Bridge 180:96ed750bd169 760 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 761 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 762 process unlock */
Anna Bridge 180:96ed750bd169 763 if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 766 }
Anna Bridge 180:96ed750bd169 767 else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 770 }
Anna Bridge 180:96ed750bd169 771
<> 144:ef7eb2e8f9f7 772 return HAL_OK;
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774 else
<> 144:ef7eb2e8f9f7 775 {
Anna Bridge 180:96ed750bd169 776 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 777 }
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /**
<> 144:ef7eb2e8f9f7 781 * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 782 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 783 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 784 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 785 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 786 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 787 * @retval HAL status
<> 144:ef7eb2e8f9f7 788 */
<> 144:ef7eb2e8f9f7 789 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 /* Check the parameters */
<> 144:ef7eb2e8f9f7 792 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 793
Anna Bridge 180:96ed750bd169 794 if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 795 {
Anna Bridge 180:96ed750bd169 796 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 797 {
Anna Bridge 180:96ed750bd169 798 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<> 144:ef7eb2e8f9f7 802 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Process Locked */
<> 144:ef7eb2e8f9f7 805 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 806
<> 144:ef7eb2e8f9f7 807 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
<> 144:ef7eb2e8f9f7 808 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
Anna Bridge 180:96ed750bd169 809
<> 144:ef7eb2e8f9f7 810 /* Set SBC bit to manage Acknowledge at each bit */
<> 144:ef7eb2e8f9f7 811 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 814 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 817 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 818 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 819 hsmbus->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 820
Anna Bridge 180:96ed750bd169 821 /* Convert OTHER_xxx XferOptions if any */
Anna Bridge 180:96ed750bd169 822 SMBUS_ConvertOtherXferOptions(hsmbus);
Anna Bridge 180:96ed750bd169 823
Anna Bridge 180:96ed750bd169 824 if (Size > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828 else
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
Anna Bridge 180:96ed750bd169 834 if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
<> 144:ef7eb2e8f9f7 835 {
Anna Bridge 180:96ed750bd169 836 SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 else
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Set NBYTE to transmit */
Anna Bridge 180:96ed750bd169 841 SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 844 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
Anna Bridge 180:96ed750bd169 845 if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 848 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 }
Anna Bridge 180:96ed750bd169 851
<> 144:ef7eb2e8f9f7 852 /* Clear ADDR flag after prepare the transfer parameters */
<> 144:ef7eb2e8f9f7 853 /* This action will generate an acknowledge to the HOST */
Anna Bridge 180:96ed750bd169 854 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 857 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 858
Anna Bridge 180:96ed750bd169 859 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 860 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 861 process unlock */
<> 144:ef7eb2e8f9f7 862 /* REnable ADDR interrupt */
<> 144:ef7eb2e8f9f7 863 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 return HAL_OK;
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867 else
<> 144:ef7eb2e8f9f7 868 {
Anna Bridge 180:96ed750bd169 869 return HAL_ERROR;
Anna Bridge 180:96ed750bd169 870 }
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /**
<> 144:ef7eb2e8f9f7 874 * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 875 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 876 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 877 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 878 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 879 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 880 * @retval HAL status
<> 144:ef7eb2e8f9f7 881 */
<> 144:ef7eb2e8f9f7 882 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 /* Check the parameters */
<> 144:ef7eb2e8f9f7 885 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 886
Anna Bridge 180:96ed750bd169 887 if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 888 {
Anna Bridge 180:96ed750bd169 889 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 890 {
Anna Bridge 180:96ed750bd169 891 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 892 }
Anna Bridge 180:96ed750bd169 893
<> 144:ef7eb2e8f9f7 894 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<> 144:ef7eb2e8f9f7 895 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Process Locked */
<> 144:ef7eb2e8f9f7 898 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 899
<> 144:ef7eb2e8f9f7 900 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
<> 144:ef7eb2e8f9f7 901 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
Anna Bridge 180:96ed750bd169 902
<> 144:ef7eb2e8f9f7 903 /* Set SBC bit to manage Acknowledge at each bit */
<> 144:ef7eb2e8f9f7 904 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 907 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 910 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 911 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 912 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 913 hsmbus->XferOptions = XferOptions;
Anna Bridge 180:96ed750bd169 914
Anna Bridge 180:96ed750bd169 915 /* Convert OTHER_xxx XferOptions if any */
Anna Bridge 180:96ed750bd169 916 SMBUS_ConvertOtherXferOptions(hsmbus);
Anna Bridge 180:96ed750bd169 917
<> 144:ef7eb2e8f9f7 918 /* Set NBYTE to receive */
<> 144:ef7eb2e8f9f7 919 /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
<> 144:ef7eb2e8f9f7 920 /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
<> 144:ef7eb2e8f9f7 921 /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
<> 144:ef7eb2e8f9f7 922 /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
Anna Bridge 180:96ed750bd169 923 if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
<> 144:ef7eb2e8f9f7 924 {
<> 156:95d6b41a828b 925 SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927 else
<> 144:ef7eb2e8f9f7 928 {
<> 156:95d6b41a828b 929 SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 930 }
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Clear ADDR flag after prepare the transfer parameters */
<> 144:ef7eb2e8f9f7 933 /* This action will generate an acknowledge to the HOST */
Anna Bridge 180:96ed750bd169 934 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 937 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 938
Anna Bridge 180:96ed750bd169 939 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 940 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 941 process unlock */
<> 144:ef7eb2e8f9f7 942 /* REnable ADDR interrupt */
<> 144:ef7eb2e8f9f7 943 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 return HAL_OK;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947 else
<> 144:ef7eb2e8f9f7 948 {
Anna Bridge 180:96ed750bd169 949 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /**
<> 144:ef7eb2e8f9f7 954 * @brief Enable the Address listen mode with Interrupt.
<> 144:ef7eb2e8f9f7 955 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 956 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 957 * @retval HAL status
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 hsmbus->State = HAL_SMBUS_STATE_LISTEN;
Anna Bridge 180:96ed750bd169 962
<> 144:ef7eb2e8f9f7 963 /* Enable the Address Match interrupt */
<> 144:ef7eb2e8f9f7 964 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
Anna Bridge 180:96ed750bd169 965
<> 144:ef7eb2e8f9f7 966 return HAL_OK;
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /**
<> 144:ef7eb2e8f9f7 970 * @brief Disable the Address listen mode with Interrupt.
<> 144:ef7eb2e8f9f7 971 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 972 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 973 * @retval HAL status
<> 144:ef7eb2e8f9f7 974 */
<> 144:ef7eb2e8f9f7 975 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 /* Disable Address listen mode only if a transfer is not ongoing */
Anna Bridge 180:96ed750bd169 978 if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 981
<> 144:ef7eb2e8f9f7 982 /* Disable the Address Match interrupt */
<> 144:ef7eb2e8f9f7 983 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
Anna Bridge 180:96ed750bd169 984
<> 144:ef7eb2e8f9f7 985 return HAL_OK;
<> 144:ef7eb2e8f9f7 986 }
<> 144:ef7eb2e8f9f7 987 else
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /**
<> 144:ef7eb2e8f9f7 994 * @brief Enable the SMBUS alert mode with Interrupt.
<> 144:ef7eb2e8f9f7 995 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 996 * the configuration information for the specified SMBUSx peripheral.
<> 144:ef7eb2e8f9f7 997 * @retval HAL status
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Enable SMBus alert */
Anna Bridge 180:96ed750bd169 1002 hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /* Clear ALERT flag */
<> 144:ef7eb2e8f9f7 1005 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Enable Alert Interrupt */
<> 144:ef7eb2e8f9f7 1008 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
<> 144:ef7eb2e8f9f7 1009
Anna Bridge 180:96ed750bd169 1010 return HAL_OK;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @brief Disable the SMBUS alert mode with Interrupt.
<> 144:ef7eb2e8f9f7 1014 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1015 * the configuration information for the specified SMBUSx peripheral.
<> 144:ef7eb2e8f9f7 1016 * @retval HAL status
<> 144:ef7eb2e8f9f7 1017 */
<> 144:ef7eb2e8f9f7 1018 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1019 {
<> 144:ef7eb2e8f9f7 1020 /* Enable SMBus alert */
Anna Bridge 180:96ed750bd169 1021 hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
Anna Bridge 180:96ed750bd169 1022
<> 144:ef7eb2e8f9f7 1023 /* Disable Alert Interrupt */
<> 144:ef7eb2e8f9f7 1024 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
<> 144:ef7eb2e8f9f7 1025
Anna Bridge 180:96ed750bd169 1026 return HAL_OK;
<> 144:ef7eb2e8f9f7 1027 }
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /**
Anna Bridge 180:96ed750bd169 1030 * @brief Check if target device is ready for communication.
<> 144:ef7eb2e8f9f7 1031 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1032 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1033 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 1034 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 1035 * @param Trials Number of trials
<> 144:ef7eb2e8f9f7 1036 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 1037 * @retval HAL status
<> 144:ef7eb2e8f9f7 1038 */
<> 144:ef7eb2e8f9f7 1039 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Anna Bridge 180:96ed750bd169 1040 {
<> 156:95d6b41a828b 1041 uint32_t tickstart = 0U;
Anna Bridge 180:96ed750bd169 1042
<> 156:95d6b41a828b 1043 __IO uint32_t SMBUS_Trials = 0U;
Anna Bridge 180:96ed750bd169 1044
Anna Bridge 180:96ed750bd169 1045 if (hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 1046 {
Anna Bridge 180:96ed750bd169 1047 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
<> 144:ef7eb2e8f9f7 1048 {
<> 144:ef7eb2e8f9f7 1049 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Process Locked */
<> 144:ef7eb2e8f9f7 1053 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1054
<> 144:ef7eb2e8f9f7 1055 hsmbus->State = HAL_SMBUS_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1056 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
Anna Bridge 180:96ed750bd169 1057
<> 144:ef7eb2e8f9f7 1058 do
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 /* Generate Start */
Anna Bridge 180:96ed750bd169 1061 hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
Anna Bridge 180:96ed750bd169 1062
<> 144:ef7eb2e8f9f7 1063 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<> 144:ef7eb2e8f9f7 1064 /* Wait until STOPF flag is set or a NACK flag is set*/
<> 144:ef7eb2e8f9f7 1065 tickstart = HAL_GetTick();
Anna Bridge 180:96ed750bd169 1066 while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
<> 144:ef7eb2e8f9f7 1067 {
Anna Bridge 180:96ed750bd169 1068 if (Timeout != HAL_MAX_DELAY)
Anna Bridge 180:96ed750bd169 1069 {
Anna Bridge 180:96ed750bd169 1070 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 /* Device is ready */
<> 144:ef7eb2e8f9f7 1073 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 1074
<> 144:ef7eb2e8f9f7 1075 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1076 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1077 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1078 }
Anna Bridge 180:96ed750bd169 1079 }
<> 144:ef7eb2e8f9f7 1080 }
Anna Bridge 180:96ed750bd169 1081
<> 144:ef7eb2e8f9f7 1082 /* Check if the NACKF flag has not been set */
<> 144:ef7eb2e8f9f7 1083 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
<> 144:ef7eb2e8f9f7 1084 {
Anna Bridge 180:96ed750bd169 1085 /* Wait until STOPF flag is reset */
Anna Bridge 180:96ed750bd169 1086 if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1089 }
Anna Bridge 180:96ed750bd169 1090
<> 144:ef7eb2e8f9f7 1091 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1092 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /* Device is ready */
<> 144:ef7eb2e8f9f7 1095 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 1096
<> 144:ef7eb2e8f9f7 1097 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1098 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1099
<> 144:ef7eb2e8f9f7 1100 return HAL_OK;
<> 144:ef7eb2e8f9f7 1101 }
<> 144:ef7eb2e8f9f7 1102 else
<> 144:ef7eb2e8f9f7 1103 {
Anna Bridge 180:96ed750bd169 1104 /* Wait until STOPF flag is reset */
Anna Bridge 180:96ed750bd169 1105 if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 1106 {
<> 144:ef7eb2e8f9f7 1107 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1108 }
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 1111 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Clear STOP Flag, auto generated with autoend*/
<> 144:ef7eb2e8f9f7 1114 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1115 }
Anna Bridge 180:96ed750bd169 1116
<> 144:ef7eb2e8f9f7 1117 /* Check if the maximum allowed number of trials has been reached */
<> 144:ef7eb2e8f9f7 1118 if (SMBUS_Trials++ == Trials)
<> 144:ef7eb2e8f9f7 1119 {
<> 144:ef7eb2e8f9f7 1120 /* Generate Stop */
<> 144:ef7eb2e8f9f7 1121 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
Anna Bridge 180:96ed750bd169 1122
Anna Bridge 180:96ed750bd169 1123 /* Wait until STOPF flag is reset */
Anna Bridge 180:96ed750bd169 1124 if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1127 }
Anna Bridge 180:96ed750bd169 1128
<> 144:ef7eb2e8f9f7 1129 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1130 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
Anna Bridge 180:96ed750bd169 1131 }
Anna Bridge 180:96ed750bd169 1132 }
Anna Bridge 180:96ed750bd169 1133 while (SMBUS_Trials < Trials);
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1138 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1139
<> 144:ef7eb2e8f9f7 1140 return HAL_TIMEOUT;
Anna Bridge 180:96ed750bd169 1141 }
<> 144:ef7eb2e8f9f7 1142 else
<> 144:ef7eb2e8f9f7 1143 {
<> 144:ef7eb2e8f9f7 1144 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1145 }
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147 /**
<> 144:ef7eb2e8f9f7 1148 * @}
<> 144:ef7eb2e8f9f7 1149 */
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 1152 * @{
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /**
<> 144:ef7eb2e8f9f7 1156 * @brief Handle SMBUS event interrupt request.
<> 144:ef7eb2e8f9f7 1157 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1158 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1159 * @retval None
<> 144:ef7eb2e8f9f7 1160 */
<> 144:ef7eb2e8f9f7 1161 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1162 {
<> 156:95d6b41a828b 1163 uint32_t tmpisrvalue = 0U;
Anna Bridge 180:96ed750bd169 1164
<> 144:ef7eb2e8f9f7 1165 /* Use a local variable to store the current ISR flags */
<> 144:ef7eb2e8f9f7 1166 /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
<> 144:ef7eb2e8f9f7 1167 tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
Anna Bridge 180:96ed750bd169 1168
<> 144:ef7eb2e8f9f7 1169 /* SMBUS in mode Transmitter ---------------------------------------------------*/
Anna Bridge 180:96ed750bd169 1170 if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
Anna Bridge 180:96ed750bd169 1171 {
<> 144:ef7eb2e8f9f7 1172 /* Slave mode selected */
<> 144:ef7eb2e8f9f7 1173 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 SMBUS_Slave_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177 /* Master mode selected */
Anna Bridge 180:96ed750bd169 1178 else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 SMBUS_Master_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1181 }
<> 144:ef7eb2e8f9f7 1182 }
Anna Bridge 180:96ed750bd169 1183
<> 144:ef7eb2e8f9f7 1184 /* SMBUS in mode Receiver ----------------------------------------------------*/
Anna Bridge 180:96ed750bd169 1185 if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
<> 144:ef7eb2e8f9f7 1186 {
<> 144:ef7eb2e8f9f7 1187 /* Slave mode selected */
<> 144:ef7eb2e8f9f7 1188 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 SMBUS_Slave_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 /* Master mode selected */
Anna Bridge 180:96ed750bd169 1193 else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1194 {
<> 144:ef7eb2e8f9f7 1195 SMBUS_Master_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1196 }
Anna Bridge 180:96ed750bd169 1197 }
Anna Bridge 180:96ed750bd169 1198
Anna Bridge 180:96ed750bd169 1199 /* SMBUS in mode Listener Only --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1200 if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
Anna Bridge 180:96ed750bd169 1201 && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
<> 144:ef7eb2e8f9f7 1202 {
<> 144:ef7eb2e8f9f7 1203 if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1204 {
<> 144:ef7eb2e8f9f7 1205 SMBUS_Slave_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1206 }
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208 }
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /**
<> 144:ef7eb2e8f9f7 1211 * @brief Handle SMBUS error interrupt request.
<> 144:ef7eb2e8f9f7 1212 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1213 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1214 * @retval None
<> 144:ef7eb2e8f9f7 1215 */
<> 144:ef7eb2e8f9f7 1216 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1217 {
Anna Bridge 180:96ed750bd169 1218 SMBUS_ITErrorHandler(hsmbus);
<> 144:ef7eb2e8f9f7 1219 }
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /**
<> 144:ef7eb2e8f9f7 1222 * @brief Master Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1223 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1224 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1225 * @retval None
<> 144:ef7eb2e8f9f7 1226 */
Anna Bridge 180:96ed750bd169 1227 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1228 {
<> 144:ef7eb2e8f9f7 1229 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1230 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1233 the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
Anna Bridge 180:96ed750bd169 1234 */
<> 144:ef7eb2e8f9f7 1235 }
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /**
<> 144:ef7eb2e8f9f7 1238 * @brief Master Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1239 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1240 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1241 * @retval None
<> 144:ef7eb2e8f9f7 1242 */
<> 144:ef7eb2e8f9f7 1243 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1244 {
<> 144:ef7eb2e8f9f7 1245 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1246 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1249 the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1250 */
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /** @brief Slave Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1254 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1255 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1256 * @retval None
<> 144:ef7eb2e8f9f7 1257 */
Anna Bridge 180:96ed750bd169 1258 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1261 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1264 the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
Anna Bridge 180:96ed750bd169 1265 */
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /**
<> 144:ef7eb2e8f9f7 1269 * @brief Slave Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1270 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1271 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1272 * @retval None
<> 144:ef7eb2e8f9f7 1273 */
<> 144:ef7eb2e8f9f7 1274 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1277 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1280 the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1281 */
<> 144:ef7eb2e8f9f7 1282 }
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /**
<> 144:ef7eb2e8f9f7 1285 * @brief Slave Address Match callback.
<> 144:ef7eb2e8f9f7 1286 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1287 * the configuration information for the specified SMBUS.
Anna Bridge 180:96ed750bd169 1288 * @param TransferDirection Master request Transfer Direction (Write/Read)
Anna Bridge 180:96ed750bd169 1289 * @param AddrMatchCode Address Match Code
<> 144:ef7eb2e8f9f7 1290 * @retval None
<> 144:ef7eb2e8f9f7 1291 */
<> 144:ef7eb2e8f9f7 1292 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
<> 144:ef7eb2e8f9f7 1293 {
<> 144:ef7eb2e8f9f7 1294 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1295 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1296 UNUSED(TransferDirection);
<> 144:ef7eb2e8f9f7 1297 UNUSED(AddrMatchCode);
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1300 the HAL_SMBUS_AddrCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1301 */
<> 144:ef7eb2e8f9f7 1302 }
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /**
<> 144:ef7eb2e8f9f7 1305 * @brief Listen Complete callback.
<> 144:ef7eb2e8f9f7 1306 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1307 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1308 * @retval None
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1311 {
<> 144:ef7eb2e8f9f7 1312 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1313 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1314
Anna Bridge 180:96ed750bd169 1315 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1316 the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1317 */
<> 144:ef7eb2e8f9f7 1318 }
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 /**
<> 144:ef7eb2e8f9f7 1321 * @brief SMBUS error callback.
<> 144:ef7eb2e8f9f7 1322 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1323 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1324 * @retval None
<> 144:ef7eb2e8f9f7 1325 */
Anna Bridge 180:96ed750bd169 1326 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1327 {
<> 144:ef7eb2e8f9f7 1328 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1329 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1332 the HAL_SMBUS_ErrorCallback() could be implemented in the user file
Anna Bridge 180:96ed750bd169 1333 */
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /**
<> 144:ef7eb2e8f9f7 1337 * @}
Anna Bridge 180:96ed750bd169 1338 */
<> 144:ef7eb2e8f9f7 1339
Anna Bridge 180:96ed750bd169 1340 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
Anna Bridge 180:96ed750bd169 1341 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1342 *
Anna Bridge 180:96ed750bd169 1343 @verbatim
<> 144:ef7eb2e8f9f7 1344 ===============================================================================
<> 144:ef7eb2e8f9f7 1345 ##### Peripheral State and Errors functions #####
Anna Bridge 180:96ed750bd169 1346 ===============================================================================
<> 144:ef7eb2e8f9f7 1347 [..]
Anna Bridge 180:96ed750bd169 1348 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1349 and the data flow.
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 @endverbatim
<> 144:ef7eb2e8f9f7 1352 * @{
<> 144:ef7eb2e8f9f7 1353 */
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /**
<> 144:ef7eb2e8f9f7 1356 * @brief Return the SMBUS handle state.
<> 144:ef7eb2e8f9f7 1357 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1358 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1359 * @retval HAL state
<> 144:ef7eb2e8f9f7 1360 */
<> 144:ef7eb2e8f9f7 1361 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1362 {
<> 144:ef7eb2e8f9f7 1363 /* Return SMBUS handle state */
<> 144:ef7eb2e8f9f7 1364 return hsmbus->State;
<> 144:ef7eb2e8f9f7 1365 }
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /**
<> 144:ef7eb2e8f9f7 1368 * @brief Return the SMBUS error code.
<> 144:ef7eb2e8f9f7 1369 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1370 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1371 * @retval SMBUS Error Code
<> 144:ef7eb2e8f9f7 1372 */
<> 144:ef7eb2e8f9f7 1373 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1374 {
<> 144:ef7eb2e8f9f7 1375 return hsmbus->ErrorCode;
<> 144:ef7eb2e8f9f7 1376 }
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /**
<> 144:ef7eb2e8f9f7 1379 * @}
Anna Bridge 180:96ed750bd169 1380 */
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 /**
<> 144:ef7eb2e8f9f7 1383 * @}
Anna Bridge 180:96ed750bd169 1384 */
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
Anna Bridge 180:96ed750bd169 1387 * @brief Data transfers Private functions
<> 144:ef7eb2e8f9f7 1388 * @{
<> 144:ef7eb2e8f9f7 1389 */
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /**
<> 144:ef7eb2e8f9f7 1392 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
<> 144:ef7eb2e8f9f7 1393 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1394 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1395 * @retval HAL status
<> 144:ef7eb2e8f9f7 1396 */
Anna Bridge 180:96ed750bd169 1397 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 uint16_t DevAddress;
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 /* Process Locked */
<> 144:ef7eb2e8f9f7 1402 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1403
Anna Bridge 180:96ed750bd169 1404 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
<> 144:ef7eb2e8f9f7 1405 {
<> 144:ef7eb2e8f9f7 1406 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 1407 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
Anna Bridge 180:96ed750bd169 1408
<> 144:ef7eb2e8f9f7 1409 /* Set corresponding Error Code */
<> 144:ef7eb2e8f9f7 1410 /* No need to generate STOP, it is automatically done */
<> 144:ef7eb2e8f9f7 1411 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1414 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1415
Anna Bridge 180:96ed750bd169 1416 /* Call the Error callback to inform upper layer */
<> 144:ef7eb2e8f9f7 1417 HAL_SMBUS_ErrorCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1418 }
Anna Bridge 180:96ed750bd169 1419 else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
<> 144:ef7eb2e8f9f7 1420 {
Anna Bridge 180:96ed750bd169 1421 /* Check and treat errors if errors occurs during STOP process */
Anna Bridge 180:96ed750bd169 1422 SMBUS_ITErrorHandler(hsmbus);
Anna Bridge 180:96ed750bd169 1423
<> 144:ef7eb2e8f9f7 1424 /* Call the corresponding callback to inform upper layer of End of Transfer */
Anna Bridge 180:96ed750bd169 1425 if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1426 {
<> 144:ef7eb2e8f9f7 1427 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1428 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1431 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
Anna Bridge 180:96ed750bd169 1432
<> 144:ef7eb2e8f9f7 1433 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1434 SMBUS_RESET_CR2(hsmbus);
Anna Bridge 180:96ed750bd169 1435
<> 144:ef7eb2e8f9f7 1436 /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
<> 144:ef7eb2e8f9f7 1437 /* Disable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 1438 __HAL_SMBUS_DISABLE(hsmbus);
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1441 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1442
<> 144:ef7eb2e8f9f7 1443 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1444 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1445
<> 144:ef7eb2e8f9f7 1446 /* REenable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 1447 __HAL_SMBUS_ENABLE(hsmbus);
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1450 }
Anna Bridge 180:96ed750bd169 1451 else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1452 {
<> 156:95d6b41a828b 1453 /* Store Last receive data if any */
Anna Bridge 180:96ed750bd169 1454 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
<> 156:95d6b41a828b 1455 {
<> 156:95d6b41a828b 1456 /* Read data from RXDR */
<> 156:95d6b41a828b 1457 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 156:95d6b41a828b 1458
Anna Bridge 180:96ed750bd169 1459 if ((hsmbus->XferSize > 0U))
<> 156:95d6b41a828b 1460 {
<> 156:95d6b41a828b 1461 hsmbus->XferSize--;
<> 156:95d6b41a828b 1462 hsmbus->XferCount--;
<> 156:95d6b41a828b 1463 }
<> 156:95d6b41a828b 1464 }
<> 156:95d6b41a828b 1465
<> 144:ef7eb2e8f9f7 1466 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1467 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1470 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
Anna Bridge 180:96ed750bd169 1471
<> 144:ef7eb2e8f9f7 1472 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1473 SMBUS_RESET_CR2(hsmbus);
Anna Bridge 180:96ed750bd169 1474
<> 144:ef7eb2e8f9f7 1475 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1476 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1479 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1480
<> 144:ef7eb2e8f9f7 1481 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1482 }
<> 144:ef7eb2e8f9f7 1483 }
Anna Bridge 180:96ed750bd169 1484 else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
Anna Bridge 180:96ed750bd169 1485 {
<> 144:ef7eb2e8f9f7 1486 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 1487 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 144:ef7eb2e8f9f7 1488 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1489 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1490 }
Anna Bridge 180:96ed750bd169 1491 else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
<> 144:ef7eb2e8f9f7 1492 {
<> 144:ef7eb2e8f9f7 1493 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 1494 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
<> 144:ef7eb2e8f9f7 1495 hsmbus->XferSize--;
Anna Bridge 180:96ed750bd169 1496 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1497 }
Anna Bridge 180:96ed750bd169 1498 else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
<> 144:ef7eb2e8f9f7 1499 {
Anna Bridge 180:96ed750bd169 1500 if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
<> 144:ef7eb2e8f9f7 1501 {
<> 144:ef7eb2e8f9f7 1502 DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
Anna Bridge 180:96ed750bd169 1503
Anna Bridge 180:96ed750bd169 1504 if (hsmbus->XferCount > MAX_NBYTE_SIZE)
Anna Bridge 180:96ed750bd169 1505 {
<> 144:ef7eb2e8f9f7 1506 SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1507 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1508 }
<> 144:ef7eb2e8f9f7 1509 else
<> 144:ef7eb2e8f9f7 1510 {
<> 144:ef7eb2e8f9f7 1511 hsmbus->XferSize = hsmbus->XferCount;
Anna Bridge 180:96ed750bd169 1512 SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1513 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 1514 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
Anna Bridge 180:96ed750bd169 1515 if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 1516 {
<> 144:ef7eb2e8f9f7 1517 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1518 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1519 }
<> 144:ef7eb2e8f9f7 1520 }
<> 144:ef7eb2e8f9f7 1521 }
Anna Bridge 180:96ed750bd169 1522 else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
<> 144:ef7eb2e8f9f7 1523 {
<> 144:ef7eb2e8f9f7 1524 /* Call TxCpltCallback() if no stop mode is set */
Anna Bridge 180:96ed750bd169 1525 if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
<> 144:ef7eb2e8f9f7 1526 {
<> 144:ef7eb2e8f9f7 1527 /* Call the corresponding callback to inform upper layer of End of Transfer */
Anna Bridge 180:96ed750bd169 1528 if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1529 {
<> 144:ef7eb2e8f9f7 1530 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1531 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1532 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1533 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1536 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1537
<> 144:ef7eb2e8f9f7 1538 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1539 }
Anna Bridge 180:96ed750bd169 1540 else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1541 {
<> 144:ef7eb2e8f9f7 1542 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 1543 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1544 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1545
<> 144:ef7eb2e8f9f7 1546 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1547 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1548
<> 144:ef7eb2e8f9f7 1549 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1550 }
<> 144:ef7eb2e8f9f7 1551 }
<> 144:ef7eb2e8f9f7 1552 }
<> 144:ef7eb2e8f9f7 1553 }
Anna Bridge 180:96ed750bd169 1554 else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
<> 144:ef7eb2e8f9f7 1555 {
Anna Bridge 180:96ed750bd169 1556 if (hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1557 {
<> 144:ef7eb2e8f9f7 1558 /* Specific use case for Quick command */
Anna Bridge 180:96ed750bd169 1559 if (hsmbus->pBuffPtr == NULL)
<> 144:ef7eb2e8f9f7 1560 {
<> 144:ef7eb2e8f9f7 1561 /* Generate a Stop command */
<> 144:ef7eb2e8f9f7 1562 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
<> 144:ef7eb2e8f9f7 1563 }
<> 144:ef7eb2e8f9f7 1564 /* Call TxCpltCallback() if no stop mode is set */
Anna Bridge 180:96ed750bd169 1565 else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
<> 144:ef7eb2e8f9f7 1566 {
<> 144:ef7eb2e8f9f7 1567 /* No Generate Stop, to permit restart mode */
<> 144:ef7eb2e8f9f7 1568 /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
Anna Bridge 180:96ed750bd169 1569
<> 144:ef7eb2e8f9f7 1570 /* Call the corresponding callback to inform upper layer of End of Transfer */
Anna Bridge 180:96ed750bd169 1571 if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1572 {
<> 144:ef7eb2e8f9f7 1573 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1574 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1575 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1576 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1579 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1580
<> 144:ef7eb2e8f9f7 1581 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1582 }
Anna Bridge 180:96ed750bd169 1583 else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1584 {
<> 144:ef7eb2e8f9f7 1585 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 1586 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1587 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1590 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1591
<> 144:ef7eb2e8f9f7 1592 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1593 }
<> 144:ef7eb2e8f9f7 1594 }
<> 144:ef7eb2e8f9f7 1595 }
<> 144:ef7eb2e8f9f7 1596 }
Anna Bridge 180:96ed750bd169 1597
<> 144:ef7eb2e8f9f7 1598 /* Process Unlocked */
Anna Bridge 180:96ed750bd169 1599 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1600
Anna Bridge 180:96ed750bd169 1601 return HAL_OK;
Anna Bridge 180:96ed750bd169 1602 }
<> 144:ef7eb2e8f9f7 1603 /**
<> 144:ef7eb2e8f9f7 1604 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
<> 144:ef7eb2e8f9f7 1605 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1606 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1607 * @retval HAL status
<> 144:ef7eb2e8f9f7 1608 */
Anna Bridge 180:96ed750bd169 1609 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1610 {
<> 156:95d6b41a828b 1611 uint8_t TransferDirection = 0U;
<> 156:95d6b41a828b 1612 uint16_t SlaveAddrCode = 0U;
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /* Process Locked */
<> 144:ef7eb2e8f9f7 1615 __HAL_LOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1616
Anna Bridge 180:96ed750bd169 1617 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
<> 144:ef7eb2e8f9f7 1618 {
<> 144:ef7eb2e8f9f7 1619 /* Check that SMBUS transfer finished */
<> 144:ef7eb2e8f9f7 1620 /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
<> 144:ef7eb2e8f9f7 1621 /* Mean XferCount == 0*/
<> 144:ef7eb2e8f9f7 1622 /* So clear Flag NACKF only */
Anna Bridge 180:96ed750bd169 1623 if (hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1624 {
<> 144:ef7eb2e8f9f7 1625 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 1626 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1629 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1630 }
<> 144:ef7eb2e8f9f7 1631 else
<> 144:ef7eb2e8f9f7 1632 {
<> 144:ef7eb2e8f9f7 1633 /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
<> 144:ef7eb2e8f9f7 1634 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 1635 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /* Set HAL State to "Idle" State, mean to LISTEN state */
<> 144:ef7eb2e8f9f7 1638 /* So reset Slave Busy state */
<> 144:ef7eb2e8f9f7 1639 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1640 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
<> 144:ef7eb2e8f9f7 1641 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
<> 144:ef7eb2e8f9f7 1644 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
Anna Bridge 180:96ed750bd169 1645
<> 144:ef7eb2e8f9f7 1646 /* Set ErrorCode corresponding to a Non-Acknowledge */
<> 144:ef7eb2e8f9f7 1647 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
<> 144:ef7eb2e8f9f7 1648
<> 144:ef7eb2e8f9f7 1649 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1650 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1651
Anna Bridge 180:96ed750bd169 1652 /* Call the Error callback to inform upper layer */
<> 144:ef7eb2e8f9f7 1653 HAL_SMBUS_ErrorCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1654 }
<> 144:ef7eb2e8f9f7 1655 }
Anna Bridge 180:96ed750bd169 1656 else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
<> 144:ef7eb2e8f9f7 1657 {
<> 144:ef7eb2e8f9f7 1658 TransferDirection = SMBUS_GET_DIR(hsmbus);
<> 144:ef7eb2e8f9f7 1659 SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
Anna Bridge 180:96ed750bd169 1660
<> 144:ef7eb2e8f9f7 1661 /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
<> 144:ef7eb2e8f9f7 1662 /* Other ADDRInterrupt will be treat in next Listen usecase */
<> 144:ef7eb2e8f9f7 1663 __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
Anna Bridge 180:96ed750bd169 1664
<> 144:ef7eb2e8f9f7 1665 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1666 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1667
<> 144:ef7eb2e8f9f7 1668 /* Call Slave Addr callback */
<> 144:ef7eb2e8f9f7 1669 HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
<> 144:ef7eb2e8f9f7 1670 }
Anna Bridge 180:96ed750bd169 1671 else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
<> 144:ef7eb2e8f9f7 1672 {
Anna Bridge 180:96ed750bd169 1673 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1674 {
<> 144:ef7eb2e8f9f7 1675 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 1676 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 144:ef7eb2e8f9f7 1677 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1678 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1679
Anna Bridge 180:96ed750bd169 1680 if (hsmbus->XferCount == 1U)
<> 144:ef7eb2e8f9f7 1681 {
<> 144:ef7eb2e8f9f7 1682 /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
<> 144:ef7eb2e8f9f7 1683 /* or only the last Byte of Transfer */
<> 144:ef7eb2e8f9f7 1684 /* So reset the RELOAD bit mode */
<> 144:ef7eb2e8f9f7 1685 hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
Anna Bridge 180:96ed750bd169 1686 SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1687 }
Anna Bridge 180:96ed750bd169 1688 else if (hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1689 {
<> 144:ef7eb2e8f9f7 1690 /* Last Byte is received, disable Interrupt */
<> 144:ef7eb2e8f9f7 1691 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
Anna Bridge 180:96ed750bd169 1692
<> 144:ef7eb2e8f9f7 1693 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
<> 144:ef7eb2e8f9f7 1694 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1695 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
Anna Bridge 180:96ed750bd169 1696
<> 144:ef7eb2e8f9f7 1697 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1698 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /* Call the Rx complete callback to inform upper layer of the end of receive process */
<> 144:ef7eb2e8f9f7 1701 HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1702 }
<> 144:ef7eb2e8f9f7 1703 else
<> 144:ef7eb2e8f9f7 1704 {
<> 144:ef7eb2e8f9f7 1705 /* Set Reload for next Bytes */
<> 156:95d6b41a828b 1706 SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 /* Ack last Byte Read */
<> 144:ef7eb2e8f9f7 1709 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1710 }
Anna Bridge 180:96ed750bd169 1711 }
Anna Bridge 180:96ed750bd169 1712 else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1713 {
Anna Bridge 180:96ed750bd169 1714 if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
<> 144:ef7eb2e8f9f7 1715 {
Anna Bridge 180:96ed750bd169 1716 if (hsmbus->XferCount > MAX_NBYTE_SIZE)
Anna Bridge 180:96ed750bd169 1717 {
<> 156:95d6b41a828b 1718 SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1719 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1720 }
<> 144:ef7eb2e8f9f7 1721 else
<> 144:ef7eb2e8f9f7 1722 {
<> 144:ef7eb2e8f9f7 1723 hsmbus->XferSize = hsmbus->XferCount;
<> 156:95d6b41a828b 1724 SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1725 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 1726 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
Anna Bridge 180:96ed750bd169 1727 if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 1728 {
<> 144:ef7eb2e8f9f7 1729 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1730 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1731 }
<> 144:ef7eb2e8f9f7 1732 }
<> 144:ef7eb2e8f9f7 1733 }
<> 144:ef7eb2e8f9f7 1734 }
<> 144:ef7eb2e8f9f7 1735 }
Anna Bridge 180:96ed750bd169 1736 else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
<> 144:ef7eb2e8f9f7 1737 {
<> 144:ef7eb2e8f9f7 1738 /* Write data to TXDR only if XferCount not reach "0" */
<> 144:ef7eb2e8f9f7 1739 /* A TXIS flag can be set, during STOP treatment */
<> 156:95d6b41a828b 1740 /* Check if all Data have already been sent */
<> 144:ef7eb2e8f9f7 1741 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
Anna Bridge 180:96ed750bd169 1742 if (hsmbus->XferCount > 0U)
<> 144:ef7eb2e8f9f7 1743 {
<> 144:ef7eb2e8f9f7 1744 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 1745 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
<> 144:ef7eb2e8f9f7 1746 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1747 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1748 }
Anna Bridge 180:96ed750bd169 1749
Anna Bridge 180:96ed750bd169 1750 if (hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1751 {
<> 144:ef7eb2e8f9f7 1752 /* Last Byte is Transmitted */
<> 144:ef7eb2e8f9f7 1753 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
<> 144:ef7eb2e8f9f7 1754 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1755 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1756 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1759 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /* Call the Tx complete callback to inform upper layer of the end of transmit process */
<> 144:ef7eb2e8f9f7 1762 HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1763 }
<> 144:ef7eb2e8f9f7 1764 }
<> 144:ef7eb2e8f9f7 1765
<> 144:ef7eb2e8f9f7 1766 /* Check if STOPF is set */
Anna Bridge 180:96ed750bd169 1767 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
<> 144:ef7eb2e8f9f7 1768 {
Anna Bridge 180:96ed750bd169 1769 if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1770 {
<> 156:95d6b41a828b 1771 /* Store Last receive data if any */
Anna Bridge 180:96ed750bd169 1772 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
<> 156:95d6b41a828b 1773 {
<> 156:95d6b41a828b 1774 /* Read data from RXDR */
<> 156:95d6b41a828b 1775 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 156:95d6b41a828b 1776
Anna Bridge 180:96ed750bd169 1777 if ((hsmbus->XferSize > 0U))
<> 156:95d6b41a828b 1778 {
<> 156:95d6b41a828b 1779 hsmbus->XferSize--;
<> 156:95d6b41a828b 1780 hsmbus->XferCount--;
<> 156:95d6b41a828b 1781 }
<> 156:95d6b41a828b 1782 }
<> 156:95d6b41a828b 1783
<> 144:ef7eb2e8f9f7 1784 /* Disable RX and TX Interrupts */
<> 144:ef7eb2e8f9f7 1785 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 /* Disable ADDR Interrupt */
<> 144:ef7eb2e8f9f7 1788 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1791 hsmbus->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1792
<> 144:ef7eb2e8f9f7 1793 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1794 SMBUS_RESET_CR2(hsmbus);
Anna Bridge 180:96ed750bd169 1795
<> 144:ef7eb2e8f9f7 1796 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1797 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1798
Anna Bridge 180:96ed750bd169 1799 /* Clear ADDR flag */
Anna Bridge 180:96ed750bd169 1800 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 1801
<> 156:95d6b41a828b 1802 hsmbus->XferOptions = 0U;
<> 144:ef7eb2e8f9f7 1803 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1804 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 1805
<> 144:ef7eb2e8f9f7 1806 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1807 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1808
Anna Bridge 180:96ed750bd169 1809 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<> 144:ef7eb2e8f9f7 1810 HAL_SMBUS_ListenCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1811 }
<> 144:ef7eb2e8f9f7 1812 }
<> 144:ef7eb2e8f9f7 1813
<> 144:ef7eb2e8f9f7 1814 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1815 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 1816
Anna Bridge 180:96ed750bd169 1817 return HAL_OK;
Anna Bridge 180:96ed750bd169 1818 }
<> 144:ef7eb2e8f9f7 1819 /**
<> 144:ef7eb2e8f9f7 1820 * @brief Manage the enabling of Interrupts.
<> 144:ef7eb2e8f9f7 1821 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1822 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1823 * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
<> 144:ef7eb2e8f9f7 1824 * @retval HAL status
<> 144:ef7eb2e8f9f7 1825 */
Anna Bridge 180:96ed750bd169 1826 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
<> 144:ef7eb2e8f9f7 1827 {
<> 156:95d6b41a828b 1828 uint32_t tmpisr = 0U;
<> 144:ef7eb2e8f9f7 1829
Anna Bridge 180:96ed750bd169 1830 if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
<> 144:ef7eb2e8f9f7 1831 {
<> 144:ef7eb2e8f9f7 1832 /* Enable ERR interrupt */
<> 144:ef7eb2e8f9f7 1833 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1834 }
Anna Bridge 180:96ed750bd169 1835
Anna Bridge 180:96ed750bd169 1836 if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
<> 144:ef7eb2e8f9f7 1837 {
<> 144:ef7eb2e8f9f7 1838 /* Enable ADDR, STOP interrupt */
<> 144:ef7eb2e8f9f7 1839 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1840 }
Anna Bridge 180:96ed750bd169 1841
Anna Bridge 180:96ed750bd169 1842 if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
<> 144:ef7eb2e8f9f7 1843 {
<> 144:ef7eb2e8f9f7 1844 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
<> 144:ef7eb2e8f9f7 1845 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
<> 144:ef7eb2e8f9f7 1846 }
Anna Bridge 180:96ed750bd169 1847
Anna Bridge 180:96ed750bd169 1848 if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
<> 144:ef7eb2e8f9f7 1849 {
<> 144:ef7eb2e8f9f7 1850 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
<> 144:ef7eb2e8f9f7 1851 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
<> 144:ef7eb2e8f9f7 1852 }
Anna Bridge 180:96ed750bd169 1853
<> 144:ef7eb2e8f9f7 1854 /* Enable interrupts only at the end */
<> 144:ef7eb2e8f9f7 1855 /* to avoid the risk of SMBUS interrupt handle execution before */
<> 144:ef7eb2e8f9f7 1856 /* all interrupts requested done */
<> 144:ef7eb2e8f9f7 1857 __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
<> 144:ef7eb2e8f9f7 1858
Anna Bridge 180:96ed750bd169 1859 return HAL_OK;
<> 144:ef7eb2e8f9f7 1860 }
<> 144:ef7eb2e8f9f7 1861 /**
<> 144:ef7eb2e8f9f7 1862 * @brief Manage the disabling of Interrupts.
<> 144:ef7eb2e8f9f7 1863 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1864 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1865 * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
<> 144:ef7eb2e8f9f7 1866 * @retval HAL status
<> 144:ef7eb2e8f9f7 1867 */
Anna Bridge 180:96ed750bd169 1868 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
<> 144:ef7eb2e8f9f7 1869 {
<> 156:95d6b41a828b 1870 uint32_t tmpisr = 0U;
<> 144:ef7eb2e8f9f7 1871
Anna Bridge 180:96ed750bd169 1872 if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
<> 144:ef7eb2e8f9f7 1873 {
<> 144:ef7eb2e8f9f7 1874 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1875 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1876 }
Anna Bridge 180:96ed750bd169 1877
Anna Bridge 180:96ed750bd169 1878 if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
<> 144:ef7eb2e8f9f7 1879 {
<> 144:ef7eb2e8f9f7 1880 /* Disable TC, STOP, NACK, TXI interrupt */
<> 144:ef7eb2e8f9f7 1881 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
Anna Bridge 180:96ed750bd169 1882
Anna Bridge 180:96ed750bd169 1883 if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
Anna Bridge 180:96ed750bd169 1884 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
<> 144:ef7eb2e8f9f7 1885 {
<> 144:ef7eb2e8f9f7 1886 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1887 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1888 }
Anna Bridge 180:96ed750bd169 1889
Anna Bridge 180:96ed750bd169 1890 if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1891 {
<> 144:ef7eb2e8f9f7 1892 /* Disable STOPI, NACKI */
<> 144:ef7eb2e8f9f7 1893 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
<> 144:ef7eb2e8f9f7 1894 }
<> 144:ef7eb2e8f9f7 1895 }
Anna Bridge 180:96ed750bd169 1896
Anna Bridge 180:96ed750bd169 1897 if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
<> 144:ef7eb2e8f9f7 1898 {
<> 144:ef7eb2e8f9f7 1899 /* Disable TC, STOP, NACK, RXI interrupt */
<> 144:ef7eb2e8f9f7 1900 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
Anna Bridge 180:96ed750bd169 1901
Anna Bridge 180:96ed750bd169 1902 if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
Anna Bridge 180:96ed750bd169 1903 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
<> 144:ef7eb2e8f9f7 1904 {
<> 144:ef7eb2e8f9f7 1905 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1906 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1907 }
<> 144:ef7eb2e8f9f7 1908
Anna Bridge 180:96ed750bd169 1909 if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1910 {
<> 144:ef7eb2e8f9f7 1911 /* Disable STOPI, NACKI */
<> 144:ef7eb2e8f9f7 1912 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
<> 144:ef7eb2e8f9f7 1913 }
<> 144:ef7eb2e8f9f7 1914 }
Anna Bridge 180:96ed750bd169 1915
Anna Bridge 180:96ed750bd169 1916 if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
<> 144:ef7eb2e8f9f7 1917 {
<> 144:ef7eb2e8f9f7 1918 /* Enable ADDR, STOP interrupt */
<> 144:ef7eb2e8f9f7 1919 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
<> 144:ef7eb2e8f9f7 1920
Anna Bridge 180:96ed750bd169 1921 if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
<> 144:ef7eb2e8f9f7 1922 {
<> 144:ef7eb2e8f9f7 1923 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1924 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1925 }
<> 144:ef7eb2e8f9f7 1926 }
<> 144:ef7eb2e8f9f7 1927
<> 144:ef7eb2e8f9f7 1928 /* Disable interrupts only at the end */
<> 144:ef7eb2e8f9f7 1929 /* to avoid a breaking situation like at "t" time */
<> 144:ef7eb2e8f9f7 1930 /* all disable interrupts request are not done */
<> 144:ef7eb2e8f9f7 1931 __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
Anna Bridge 180:96ed750bd169 1932
<> 144:ef7eb2e8f9f7 1933 return HAL_OK;
<> 144:ef7eb2e8f9f7 1934 }
Anna Bridge 180:96ed750bd169 1935
Anna Bridge 180:96ed750bd169 1936 /**
Anna Bridge 180:96ed750bd169 1937 * @brief SMBUS interrupts error handler.
Anna Bridge 180:96ed750bd169 1938 * @param hsmbus SMBUS handle.
Anna Bridge 180:96ed750bd169 1939 * @retval None
Anna Bridge 180:96ed750bd169 1940 */
Anna Bridge 180:96ed750bd169 1941 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
Anna Bridge 180:96ed750bd169 1942 {
Anna Bridge 180:96ed750bd169 1943 uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
Anna Bridge 180:96ed750bd169 1944 uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
Anna Bridge 180:96ed750bd169 1945
Anna Bridge 180:96ed750bd169 1946 /* SMBUS Bus error interrupt occurred ------------------------------------*/
Anna Bridge 180:96ed750bd169 1947 if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
Anna Bridge 180:96ed750bd169 1948 {
Anna Bridge 180:96ed750bd169 1949 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
Anna Bridge 180:96ed750bd169 1950
Anna Bridge 180:96ed750bd169 1951 /* Clear BERR flag */
Anna Bridge 180:96ed750bd169 1952 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
Anna Bridge 180:96ed750bd169 1953 }
Anna Bridge 180:96ed750bd169 1954
Anna Bridge 180:96ed750bd169 1955 /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
Anna Bridge 180:96ed750bd169 1956 if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
Anna Bridge 180:96ed750bd169 1957 {
Anna Bridge 180:96ed750bd169 1958 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
Anna Bridge 180:96ed750bd169 1959
Anna Bridge 180:96ed750bd169 1960 /* Clear OVR flag */
Anna Bridge 180:96ed750bd169 1961 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
Anna Bridge 180:96ed750bd169 1962 }
Anna Bridge 180:96ed750bd169 1963
Anna Bridge 180:96ed750bd169 1964 /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
Anna Bridge 180:96ed750bd169 1965 if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
Anna Bridge 180:96ed750bd169 1966 {
Anna Bridge 180:96ed750bd169 1967 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
Anna Bridge 180:96ed750bd169 1968
Anna Bridge 180:96ed750bd169 1969 /* Clear ARLO flag */
Anna Bridge 180:96ed750bd169 1970 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
Anna Bridge 180:96ed750bd169 1971 }
Anna Bridge 180:96ed750bd169 1972
Anna Bridge 180:96ed750bd169 1973 /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
Anna Bridge 180:96ed750bd169 1974 if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
Anna Bridge 180:96ed750bd169 1975 {
Anna Bridge 180:96ed750bd169 1976 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
Anna Bridge 180:96ed750bd169 1977
Anna Bridge 180:96ed750bd169 1978 /* Clear TIMEOUT flag */
Anna Bridge 180:96ed750bd169 1979 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
Anna Bridge 180:96ed750bd169 1980 }
Anna Bridge 180:96ed750bd169 1981
Anna Bridge 180:96ed750bd169 1982 /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
Anna Bridge 180:96ed750bd169 1983 if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
Anna Bridge 180:96ed750bd169 1984 {
Anna Bridge 180:96ed750bd169 1985 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
Anna Bridge 180:96ed750bd169 1986
Anna Bridge 180:96ed750bd169 1987 /* Clear ALERT flag */
Anna Bridge 180:96ed750bd169 1988 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
Anna Bridge 180:96ed750bd169 1989 }
Anna Bridge 180:96ed750bd169 1990
Anna Bridge 180:96ed750bd169 1991 /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
Anna Bridge 180:96ed750bd169 1992 if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
Anna Bridge 180:96ed750bd169 1993 {
Anna Bridge 180:96ed750bd169 1994 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
Anna Bridge 180:96ed750bd169 1995
Anna Bridge 180:96ed750bd169 1996 /* Clear PEC error flag */
Anna Bridge 180:96ed750bd169 1997 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
Anna Bridge 180:96ed750bd169 1998 }
Anna Bridge 180:96ed750bd169 1999
Anna Bridge 180:96ed750bd169 2000 /* Call the Error Callback in case of Error detected */
Anna Bridge 180:96ed750bd169 2001 if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
Anna Bridge 180:96ed750bd169 2002 {
Anna Bridge 180:96ed750bd169 2003 /* Do not Reset the HAL state in case of ALERT error */
Anna Bridge 180:96ed750bd169 2004 if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
Anna Bridge 180:96ed750bd169 2005 {
Anna Bridge 180:96ed750bd169 2006 if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
Anna Bridge 180:96ed750bd169 2007 || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
Anna Bridge 180:96ed750bd169 2008 {
Anna Bridge 180:96ed750bd169 2009 /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
Anna Bridge 180:96ed750bd169 2010 /* keep HAL_SMBUS_STATE_LISTEN if set */
Anna Bridge 180:96ed750bd169 2011 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 2012 hsmbus->State = HAL_SMBUS_STATE_LISTEN;
Anna Bridge 180:96ed750bd169 2013 }
Anna Bridge 180:96ed750bd169 2014 }
Anna Bridge 180:96ed750bd169 2015
Anna Bridge 180:96ed750bd169 2016 /* Call the Error callback to inform upper layer */
Anna Bridge 180:96ed750bd169 2017 HAL_SMBUS_ErrorCallback(hsmbus);
Anna Bridge 180:96ed750bd169 2018 }
Anna Bridge 180:96ed750bd169 2019 }
Anna Bridge 180:96ed750bd169 2020
<> 144:ef7eb2e8f9f7 2021 /**
<> 144:ef7eb2e8f9f7 2022 * @brief Handle SMBUS Communication Timeout.
<> 144:ef7eb2e8f9f7 2023 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2024 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 2025 * @param Flag Specifies the SMBUS flag to check.
<> 144:ef7eb2e8f9f7 2026 * @param Status The new Flag status (SET or RESET).
<> 144:ef7eb2e8f9f7 2027 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 2028 * @retval HAL status
<> 144:ef7eb2e8f9f7 2029 */
Anna Bridge 180:96ed750bd169 2030 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Anna Bridge 180:96ed750bd169 2031 {
<> 144:ef7eb2e8f9f7 2032 uint32_t tickstart = HAL_GetTick();
Anna Bridge 180:96ed750bd169 2033
<> 144:ef7eb2e8f9f7 2034 /* Wait until flag is set */
Anna Bridge 180:96ed750bd169 2035 if (Status == RESET)
Anna Bridge 180:96ed750bd169 2036 {
Anna Bridge 180:96ed750bd169 2037 while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
<> 144:ef7eb2e8f9f7 2038 {
<> 144:ef7eb2e8f9f7 2039 /* Check for the Timeout */
Anna Bridge 180:96ed750bd169 2040 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2041 {
Anna Bridge 180:96ed750bd169 2042 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 2043 {
<> 144:ef7eb2e8f9f7 2044 hsmbus->PreviousState = hsmbus->State;
Anna Bridge 180:96ed750bd169 2045 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 2046
<> 144:ef7eb2e8f9f7 2047 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2048 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 2049
<> 144:ef7eb2e8f9f7 2050 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2051 }
<> 144:ef7eb2e8f9f7 2052 }
<> 144:ef7eb2e8f9f7 2053 }
<> 144:ef7eb2e8f9f7 2054 }
<> 144:ef7eb2e8f9f7 2055 else
<> 144:ef7eb2e8f9f7 2056 {
Anna Bridge 180:96ed750bd169 2057 while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
<> 144:ef7eb2e8f9f7 2058 {
<> 144:ef7eb2e8f9f7 2059 /* Check for the Timeout */
Anna Bridge 180:96ed750bd169 2060 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2061 {
Anna Bridge 180:96ed750bd169 2062 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 2063 {
<> 144:ef7eb2e8f9f7 2064 hsmbus->PreviousState = hsmbus->State;
Anna Bridge 180:96ed750bd169 2065 hsmbus->State = HAL_SMBUS_STATE_READY;
Anna Bridge 180:96ed750bd169 2066
<> 144:ef7eb2e8f9f7 2067 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2068 __HAL_UNLOCK(hsmbus);
Anna Bridge 180:96ed750bd169 2069
<> 144:ef7eb2e8f9f7 2070 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2071 }
<> 144:ef7eb2e8f9f7 2072 }
<> 144:ef7eb2e8f9f7 2073 }
<> 144:ef7eb2e8f9f7 2074 }
Anna Bridge 180:96ed750bd169 2075 return HAL_OK;
<> 144:ef7eb2e8f9f7 2076 }
<> 144:ef7eb2e8f9f7 2077
<> 144:ef7eb2e8f9f7 2078 /**
<> 144:ef7eb2e8f9f7 2079 * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
<> 144:ef7eb2e8f9f7 2080 * @param hsmbus SMBUS handle.
<> 144:ef7eb2e8f9f7 2081 * @param DevAddress specifies the slave address to be programmed.
<> 144:ef7eb2e8f9f7 2082 * @param Size specifies the number of bytes to be programmed.
<> 144:ef7eb2e8f9f7 2083 * This parameter must be a value between 0 and 255.
<> 144:ef7eb2e8f9f7 2084 * @param Mode New state of the SMBUS START condition generation.
<> 144:ef7eb2e8f9f7 2085 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 2086 * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
<> 144:ef7eb2e8f9f7 2087 * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
<> 144:ef7eb2e8f9f7 2088 * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
<> 144:ef7eb2e8f9f7 2089 * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
<> 144:ef7eb2e8f9f7 2090 * @param Request New state of the SMBUS START condition generation.
<> 144:ef7eb2e8f9f7 2091 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2092 * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
<> 144:ef7eb2e8f9f7 2093 * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
<> 144:ef7eb2e8f9f7 2094 * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
<> 144:ef7eb2e8f9f7 2095 * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
<> 144:ef7eb2e8f9f7 2096 * @retval None
<> 144:ef7eb2e8f9f7 2097 */
<> 144:ef7eb2e8f9f7 2098 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
<> 144:ef7eb2e8f9f7 2099 {
<> 156:95d6b41a828b 2100 uint32_t tmpreg = 0U;
Anna Bridge 180:96ed750bd169 2101
<> 144:ef7eb2e8f9f7 2102 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2103 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
<> 144:ef7eb2e8f9f7 2104 assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
<> 144:ef7eb2e8f9f7 2105 assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
Anna Bridge 180:96ed750bd169 2106
<> 144:ef7eb2e8f9f7 2107 /* Get the CR2 register value */
<> 144:ef7eb2e8f9f7 2108 tmpreg = hsmbus->Instance->CR2;
Anna Bridge 180:96ed750bd169 2109
<> 144:ef7eb2e8f9f7 2110 /* clear tmpreg specific bits */
<> 144:ef7eb2e8f9f7 2111 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
Anna Bridge 180:96ed750bd169 2112
<> 144:ef7eb2e8f9f7 2113 /* update tmpreg */
Anna Bridge 180:96ed750bd169 2114 tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \
Anna Bridge 180:96ed750bd169 2115 (uint32_t)Mode | (uint32_t)Request);
Anna Bridge 180:96ed750bd169 2116
<> 144:ef7eb2e8f9f7 2117 /* update CR2 register */
Anna Bridge 180:96ed750bd169 2118 hsmbus->Instance->CR2 = tmpreg;
Anna Bridge 180:96ed750bd169 2119 }
Anna Bridge 180:96ed750bd169 2120
Anna Bridge 180:96ed750bd169 2121 /**
Anna Bridge 180:96ed750bd169 2122 * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
Anna Bridge 180:96ed750bd169 2123 * @param hsmbus SMBUS handle.
Anna Bridge 180:96ed750bd169 2124 * @retval None
Anna Bridge 180:96ed750bd169 2125 */
Anna Bridge 180:96ed750bd169 2126 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
Anna Bridge 180:96ed750bd169 2127 {
Anna Bridge 180:96ed750bd169 2128 /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
Anna Bridge 180:96ed750bd169 2129 /* it request implicitly to generate a restart condition */
Anna Bridge 180:96ed750bd169 2130 /* set XferOptions to SMBUS_FIRST_FRAME */
Anna Bridge 180:96ed750bd169 2131 if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
Anna Bridge 180:96ed750bd169 2132 {
Anna Bridge 180:96ed750bd169 2133 hsmbus->XferOptions = SMBUS_FIRST_FRAME;
Anna Bridge 180:96ed750bd169 2134 }
Anna Bridge 180:96ed750bd169 2135 /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
Anna Bridge 180:96ed750bd169 2136 /* it request implicitly to generate a restart condition */
Anna Bridge 180:96ed750bd169 2137 /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
Anna Bridge 180:96ed750bd169 2138 else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
Anna Bridge 180:96ed750bd169 2139 {
Anna Bridge 180:96ed750bd169 2140 hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
Anna Bridge 180:96ed750bd169 2141 }
Anna Bridge 180:96ed750bd169 2142 /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
Anna Bridge 180:96ed750bd169 2143 /* it request implicitly to generate a restart condition */
Anna Bridge 180:96ed750bd169 2144 /* then generate a stop condition at the end of transfer */
Anna Bridge 180:96ed750bd169 2145 /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
Anna Bridge 180:96ed750bd169 2146 else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
Anna Bridge 180:96ed750bd169 2147 {
Anna Bridge 180:96ed750bd169 2148 hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
Anna Bridge 180:96ed750bd169 2149 }
Anna Bridge 180:96ed750bd169 2150 /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
Anna Bridge 180:96ed750bd169 2151 /* it request implicitly to generate a restart condition */
Anna Bridge 180:96ed750bd169 2152 /* then generate a stop condition at the end of transfer */
Anna Bridge 180:96ed750bd169 2153 /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
Anna Bridge 180:96ed750bd169 2154 else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
Anna Bridge 180:96ed750bd169 2155 {
Anna Bridge 180:96ed750bd169 2156 hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
Anna Bridge 180:96ed750bd169 2157 }
Anna Bridge 180:96ed750bd169 2158 }
<> 144:ef7eb2e8f9f7 2159 /**
<> 144:ef7eb2e8f9f7 2160 * @}
<> 144:ef7eb2e8f9f7 2161 */
<> 144:ef7eb2e8f9f7 2162
<> 144:ef7eb2e8f9f7 2163 #endif /* HAL_SMBUS_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2164 /**
<> 144:ef7eb2e8f9f7 2165 * @}
<> 144:ef7eb2e8f9f7 2166 */
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 /**
<> 144:ef7eb2e8f9f7 2169 * @}
<> 144:ef7eb2e8f9f7 2170 */
<> 144:ef7eb2e8f9f7 2171
<> 144:ef7eb2e8f9f7 2172 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/