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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_smbus.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief SMBUS HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the System Management Bus (SMBus) peripheral,
<> 144:ef7eb2e8f9f7 10 * based on I2C principles of operation :
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The SMBUS HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SMBUS_HandleTypeDef hsmbus;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
<> 144:ef7eb2e8f9f7 26 (##) Enable the SMBUSx interface clock
<> 144:ef7eb2e8f9f7 27 (##) SMBUS pins configuration
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the SMBUS GPIOs
<> 144:ef7eb2e8f9f7 29 (+++) Configure SMBUS pins as alternate function open-drain
<> 144:ef7eb2e8f9f7 30 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 31 (+++) Configure the SMBUSx interrupt priority
<> 144:ef7eb2e8f9f7 32 (+++) Enable the NVIC SMBUS IRQ Channel
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
<> 144:ef7eb2e8f9f7 35 Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
<> 144:ef7eb2e8f9f7 36 Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
<> 144:ef7eb2e8f9f7 39 (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 40 by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) For SMBUS IO operations, only one mode of operations is available within this driver
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 47 ===================================
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
<> 144:ef7eb2e8f9f7 50 (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 51 add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 52 (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
<> 144:ef7eb2e8f9f7 53 (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 54 add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 55 (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
<> 144:ef7eb2e8f9f7 56 (++) The associated previous transfer callback is called at the end of abort process
<> 144:ef7eb2e8f9f7 57 (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
<> 144:ef7eb2e8f9f7 58 (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
<> 144:ef7eb2e8f9f7 59 (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
<> 144:ef7eb2e8f9f7 60 using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
<> 144:ef7eb2e8f9f7 61 (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
<> 144:ef7eb2e8f9f7 62 add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
<> 144:ef7eb2e8f9f7 63 (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 64 add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
<> 144:ef7eb2e8f9f7 65 (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
<> 144:ef7eb2e8f9f7 66 (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 67 add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 68 (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
<> 144:ef7eb2e8f9f7 69 (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 70 add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 71 (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
<> 144:ef7eb2e8f9f7 72 (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
<> 144:ef7eb2e8f9f7 73 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
<> 144:ef7eb2e8f9f7 74 to check the Alert Error Code using function HAL_SMBUS_GetError()
<> 144:ef7eb2e8f9f7 75 (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
<> 144:ef7eb2e8f9f7 76 (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 77 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
<> 144:ef7eb2e8f9f7 78 to check the Error Code using function HAL_SMBUS_GetError()
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 *** SMBUS HAL driver macros list ***
<> 144:ef7eb2e8f9f7 81 ==================================
<> 144:ef7eb2e8f9f7 82 [..]
<> 144:ef7eb2e8f9f7 83 Below the list of most used macros in SMBUS HAL driver.
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
<> 144:ef7eb2e8f9f7 86 (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
<> 144:ef7eb2e8f9f7 87 (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
<> 144:ef7eb2e8f9f7 88 (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
<> 144:ef7eb2e8f9f7 89 (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
<> 144:ef7eb2e8f9f7 90 (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 [..]
<> 144:ef7eb2e8f9f7 93 (@) You can refer to the SMBUS HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 @endverbatim
<> 144:ef7eb2e8f9f7 97 ******************************************************************************
<> 144:ef7eb2e8f9f7 98 * @attention
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 103 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 104 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 105 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 106 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 107 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 108 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 109 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 110 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 111 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 114 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 115 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 116 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 117 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 118 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 119 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 120 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 121 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 122 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 ******************************************************************************
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup SMBUS SMBUS
<> 144:ef7eb2e8f9f7 135 * @brief SMBUS HAL module driver
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #ifdef HAL_SMBUS_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 156:95d6b41a828b 146 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
<> 156:95d6b41a828b 147 #define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
<> 156:95d6b41a828b 148 #define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
<> 156:95d6b41a828b 149 #define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
<> 156:95d6b41a828b 150 #define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
<> 156:95d6b41a828b 151 #define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
<> 156:95d6b41a828b 152 #define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
<> 156:95d6b41a828b 153 #define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
<> 156:95d6b41a828b 154 #define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
<> 156:95d6b41a828b 155 #define MAX_NBYTE_SIZE 255U
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 161 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 162 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 163 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
<> 144:ef7eb2e8f9f7 169 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
<> 144:ef7eb2e8f9f7 170 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 171 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 185 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 186 *
<> 144:ef7eb2e8f9f7 187 @verbatim
<> 144:ef7eb2e8f9f7 188 ===============================================================================
<> 144:ef7eb2e8f9f7 189 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 190 ===============================================================================
<> 144:ef7eb2e8f9f7 191 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 192 deinitialize the SMBUSx peripheral:
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 195 all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 (+) Call the function HAL_SMBUS_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 198 the selected configuration:
<> 144:ef7eb2e8f9f7 199 (++) Clock Timing
<> 144:ef7eb2e8f9f7 200 (++) Bus Timeout
<> 144:ef7eb2e8f9f7 201 (++) Analog Filer mode
<> 144:ef7eb2e8f9f7 202 (++) Own Address 1
<> 144:ef7eb2e8f9f7 203 (++) Addressing mode (Master, Slave)
<> 144:ef7eb2e8f9f7 204 (++) Dual Addressing mode
<> 144:ef7eb2e8f9f7 205 (++) Own Address 2
<> 144:ef7eb2e8f9f7 206 (++) Own Address 2 Mask
<> 144:ef7eb2e8f9f7 207 (++) General call mode
<> 144:ef7eb2e8f9f7 208 (++) Nostretch mode
<> 144:ef7eb2e8f9f7 209 (++) Packet Error Check mode
<> 144:ef7eb2e8f9f7 210 (++) Peripheral mode
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 214 of the selected SMBUSx peripheral.
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 @endverbatim
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /**
<> 144:ef7eb2e8f9f7 221 * @brief Initialize the SMBUS according to the specified parameters
<> 144:ef7eb2e8f9f7 222 * in the SMBUS_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 223 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 224 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 225 * @retval HAL status
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /* Check the SMBUS handle allocation */
<> 144:ef7eb2e8f9f7 230 if(hsmbus == NULL)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Check the parameters */
<> 144:ef7eb2e8f9f7 236 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
<> 144:ef7eb2e8f9f7 237 assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
<> 144:ef7eb2e8f9f7 238 assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
<> 144:ef7eb2e8f9f7 239 assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
<> 144:ef7eb2e8f9f7 240 assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
<> 144:ef7eb2e8f9f7 241 assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
<> 144:ef7eb2e8f9f7 242 assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
<> 144:ef7eb2e8f9f7 243 assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
<> 144:ef7eb2e8f9f7 244 assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
<> 144:ef7eb2e8f9f7 245 assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
<> 144:ef7eb2e8f9f7 246 assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 if(hsmbus->State == HAL_SMBUS_STATE_RESET)
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 251 hsmbus->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 254 HAL_SMBUS_MspInit(hsmbus);
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 hsmbus->State = HAL_SMBUS_STATE_BUSY;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Disable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 260 __HAL_SMBUS_DISABLE(hsmbus);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 263 /* Configure SMBUSx: Frequency range */
<> 144:ef7eb2e8f9f7 264 hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 267 /* Configure SMBUSx: Bus Timeout */
<> 144:ef7eb2e8f9f7 268 hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
<> 144:ef7eb2e8f9f7 269 hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
<> 144:ef7eb2e8f9f7 270 hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 273 /* Configure SMBUSx: Own Address1 and ack own address1 mode */
<> 144:ef7eb2e8f9f7 274 hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
<> 144:ef7eb2e8f9f7 275
<> 156:95d6b41a828b 276 if(hsmbus->Init.OwnAddress1 != 0U)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282 else /* SMBUS_ADDRESSINGMODE_10BIT */
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 289 /* Configure SMBUSx: Addressing Master mode */
<> 144:ef7eb2e8f9f7 290 if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
<> 144:ef7eb2e8f9f7 295 /* AUTOEND and NACK bit will be manage during Transfer process */
<> 144:ef7eb2e8f9f7 296 hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 299 /* Configure SMBUSx: Dual mode and Own Address2 */
<> 156:95d6b41a828b 300 hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 303 /* Configure SMBUSx: Generalcall and NoStretch mode */
<> 144:ef7eb2e8f9f7 304 hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
<> 144:ef7eb2e8f9f7 307 if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
<> 144:ef7eb2e8f9f7 308 && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Enable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 314 __HAL_SMBUS_ENABLE(hsmbus);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 317 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 318 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 return HAL_OK;
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @brief DeInitialize the SMBUS peripheral.
<> 144:ef7eb2e8f9f7 325 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 326 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 327 * @retval HAL status
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 /* Check the SMBUS handle allocation */
<> 144:ef7eb2e8f9f7 332 if(hsmbus == NULL)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Check the parameters */
<> 144:ef7eb2e8f9f7 338 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 hsmbus->State = HAL_SMBUS_STATE_BUSY;
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Disable the SMBUS Peripheral Clock */
<> 144:ef7eb2e8f9f7 343 __HAL_SMBUS_DISABLE(hsmbus);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 346 HAL_SMBUS_MspDeInit(hsmbus);
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 349 hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
<> 144:ef7eb2e8f9f7 350 hsmbus->State = HAL_SMBUS_STATE_RESET;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Release Lock */
<> 144:ef7eb2e8f9f7 353 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 return HAL_OK;
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @brief Initialize the SMBUS MSP.
<> 144:ef7eb2e8f9f7 360 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 361 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 362 * @retval None
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 367 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 370 the HAL_SMBUS_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @brief DeInitialize the SMBUS MSP.
<> 144:ef7eb2e8f9f7 376 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 377 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 378 * @retval None
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 383 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 386 the HAL_SMBUS_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @}
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 395 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 396 *
<> 144:ef7eb2e8f9f7 397 @verbatim
<> 144:ef7eb2e8f9f7 398 ===============================================================================
<> 144:ef7eb2e8f9f7 399 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 400 ===============================================================================
<> 144:ef7eb2e8f9f7 401 [..]
<> 144:ef7eb2e8f9f7 402 This subsection provides a set of functions allowing to manage the SMBUS data
<> 144:ef7eb2e8f9f7 403 transfers.
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 (#) Blocking mode function to check if device is ready for usage is :
<> 144:ef7eb2e8f9f7 406 (++) HAL_SMBUS_IsDeviceReady()
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 (#) There is only one mode of transfer:
<> 144:ef7eb2e8f9f7 409 (++) Non-Blocking mode : The communication is performed using Interrupts.
<> 144:ef7eb2e8f9f7 410 These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 411 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 412 dedicated SMBUS IRQ when using Interrupt mode.
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 (#) Non-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 415 (++) HAL_SMBUS_Master_Transmit_IT()
<> 144:ef7eb2e8f9f7 416 (++) HAL_SMBUS_Master_Receive_IT()
<> 144:ef7eb2e8f9f7 417 (++) HAL_SMBUS_Slave_Transmit_IT()
<> 144:ef7eb2e8f9f7 418 (++) HAL_SMBUS_Slave_Receive_IT()
<> 144:ef7eb2e8f9f7 419 (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
<> 144:ef7eb2e8f9f7 420 (++) HAL_SMBUS_DisableListen_IT()
<> 144:ef7eb2e8f9f7 421 (++) HAL_SMBUS_EnableAlert_IT()
<> 144:ef7eb2e8f9f7 422 (++) HAL_SMBUS_DisableAlert_IT()
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
<> 144:ef7eb2e8f9f7 425 (++) HAL_SMBUS_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 426 (++) HAL_SMBUS_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 427 (++) HAL_SMBUS_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 428 (++) HAL_SMBUS_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 429 (++) HAL_SMBUS_AddrCallback()
<> 144:ef7eb2e8f9f7 430 (++) HAL_SMBUS_ListenCpltCallback()
<> 144:ef7eb2e8f9f7 431 (++) HAL_SMBUS_ErrorCallback()
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 @endverbatim
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 439 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 440 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 441 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 442 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 443 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 444 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 445 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 446 * @retval HAL status
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 /* Check the parameters */
<> 144:ef7eb2e8f9f7 451 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 if(hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 /* Process Locked */
<> 144:ef7eb2e8f9f7 456 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
<> 144:ef7eb2e8f9f7 459 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 460 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 461 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 462 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 463 hsmbus->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* In case of Quick command, remove autoend mode */
<> 144:ef7eb2e8f9f7 466 /* Manage the stop generation by software */
<> 144:ef7eb2e8f9f7 467 if(hsmbus->pBuffPtr == NULL)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 if(Size > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476 else
<> 144:ef7eb2e8f9f7 477 {
<> 144:ef7eb2e8f9f7 478 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 482 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 483 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 else
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 /* If transfer direction not change, do not generate Restart Condition */
<> 144:ef7eb2e8f9f7 490 /* Mean Previous state is same as current state */
<> 144:ef7eb2e8f9f7 491 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 /* Else transfer direction change, so generate Restart with new transfer direction */
<> 144:ef7eb2e8f9f7 496 else
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 502 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
<> 144:ef7eb2e8f9f7 503 if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 506 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 511 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 514 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 515 process unlock */
<> 144:ef7eb2e8f9f7 516 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 return HAL_OK;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520 else
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 528 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 529 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 530 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 531 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 532 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 533 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 534 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 535 * @retval HAL status
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 /* Check the parameters */
<> 144:ef7eb2e8f9f7 540 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 if(hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 /* Process Locked */
<> 144:ef7eb2e8f9f7 545 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
<> 144:ef7eb2e8f9f7 548 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 551 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 552 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 553 hsmbus->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* In case of Quick command, remove autoend mode */
<> 144:ef7eb2e8f9f7 556 /* Manage the stop generation by software */
<> 144:ef7eb2e8f9f7 557 if(hsmbus->pBuffPtr == NULL)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 if(Size > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566 else
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 572 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 573 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 else
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 /* If transfer direction not change, do not generate Restart Condition */
<> 144:ef7eb2e8f9f7 580 /* Mean Previous state is same as current state */
<> 144:ef7eb2e8f9f7 581 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585 /* Else transfer direction change, so generate Restart with new transfer direction */
<> 144:ef7eb2e8f9f7 586 else
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 593 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 596 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 597 process unlock */
<> 144:ef7eb2e8f9f7 598 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 return HAL_OK;
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602 else
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @brief Abort a master/host SMBUS process communication with Interrupt.
<> 144:ef7eb2e8f9f7 610 * @note This abort can be called only if state is ready
<> 144:ef7eb2e8f9f7 611 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 612 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 613 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 614 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 615 * @retval HAL status
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 if(hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 /* Process Locked */
<> 144:ef7eb2e8f9f7 622 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Keep the same state as previous */
<> 144:ef7eb2e8f9f7 625 /* to perform as well the call of the corresponding end of transfer callback */
<> 144:ef7eb2e8f9f7 626 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
<> 144:ef7eb2e8f9f7 629 }
<> 144:ef7eb2e8f9f7 630 else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634 else
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 /* Wrong usage of abort function */
<> 144:ef7eb2e8f9f7 637 /* This function should be used only in case of abort monitored by master device */
<> 144:ef7eb2e8f9f7 638 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
<> 144:ef7eb2e8f9f7 643 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
<> 156:95d6b41a828b 644 SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 647 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 650 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 651 process unlock */
<> 144:ef7eb2e8f9f7 652 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 return HAL_OK;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663 else
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /**
<> 144:ef7eb2e8f9f7 670 * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 671 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 672 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 673 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 674 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 675 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 676 * @retval HAL status
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 /* Check the parameters */
<> 144:ef7eb2e8f9f7 681 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 684 {
<> 156:95d6b41a828b 685 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 688 }
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<> 144:ef7eb2e8f9f7 691 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Process Locked */
<> 144:ef7eb2e8f9f7 694 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
<> 144:ef7eb2e8f9f7 697 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Set SBC bit to manage Acknowledge at each bit */
<> 144:ef7eb2e8f9f7 700 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 703 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 706 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 707 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 708 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 709 hsmbus->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 if(Size > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715 else
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 721 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
<> 144:ef7eb2e8f9f7 722 {
<> 156:95d6b41a828b 723 SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725 else
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 /* Set NBYTE to transmit */
<> 156:95d6b41a828b 728 SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 731 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
<> 144:ef7eb2e8f9f7 732 if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 735 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Clear ADDR flag after prepare the transfer parameters */
<> 144:ef7eb2e8f9f7 740 /* This action will generate an acknowledge to the HOST */
<> 144:ef7eb2e8f9f7 741 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 744 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 747 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 748 process unlock */
<> 144:ef7eb2e8f9f7 749 /* REnable ADDR interrupt */
<> 144:ef7eb2e8f9f7 750 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 return HAL_OK;
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754 else
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /**
<> 144:ef7eb2e8f9f7 761 * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 762 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 763 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 764 * @param pData Pointer to data buffer
<> 144:ef7eb2e8f9f7 765 * @param Size Amount of data to be sent
<> 144:ef7eb2e8f9f7 766 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
<> 144:ef7eb2e8f9f7 767 * @retval HAL status
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 /* Check the parameters */
<> 144:ef7eb2e8f9f7 772 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 775 {
<> 156:95d6b41a828b 776 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 777 {
<> 144:ef7eb2e8f9f7 778 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<> 144:ef7eb2e8f9f7 782 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Process Locked */
<> 144:ef7eb2e8f9f7 785 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
<> 144:ef7eb2e8f9f7 788 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Set SBC bit to manage Acknowledge at each bit */
<> 144:ef7eb2e8f9f7 791 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 794 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 797 hsmbus->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 798 hsmbus->XferSize = Size;
<> 144:ef7eb2e8f9f7 799 hsmbus->XferCount = Size;
<> 144:ef7eb2e8f9f7 800 hsmbus->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Set NBYTE to receive */
<> 144:ef7eb2e8f9f7 803 /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
<> 144:ef7eb2e8f9f7 804 /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
<> 144:ef7eb2e8f9f7 805 /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
<> 144:ef7eb2e8f9f7 806 /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
<> 156:95d6b41a828b 807 if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
<> 144:ef7eb2e8f9f7 808 {
<> 156:95d6b41a828b 809 SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811 else
<> 144:ef7eb2e8f9f7 812 {
<> 156:95d6b41a828b 813 SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Clear ADDR flag after prepare the transfer parameters */
<> 144:ef7eb2e8f9f7 817 /* This action will generate an acknowledge to the HOST */
<> 144:ef7eb2e8f9f7 818 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 821 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Note : The SMBUS interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 824 to avoid the risk of SMBUS interrupt handle execution before current
<> 144:ef7eb2e8f9f7 825 process unlock */
<> 144:ef7eb2e8f9f7 826 /* REnable ADDR interrupt */
<> 144:ef7eb2e8f9f7 827 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 return HAL_OK;
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831 else
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /**
<> 144:ef7eb2e8f9f7 838 * @brief Enable the Address listen mode with Interrupt.
<> 144:ef7eb2e8f9f7 839 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 840 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 841 * @retval HAL status
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 hsmbus->State = HAL_SMBUS_STATE_LISTEN;
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Enable the Address Match interrupt */
<> 144:ef7eb2e8f9f7 848 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 return HAL_OK;
<> 144:ef7eb2e8f9f7 851 }
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /**
<> 144:ef7eb2e8f9f7 854 * @brief Disable the Address listen mode with Interrupt.
<> 144:ef7eb2e8f9f7 855 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 856 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 857 * @retval HAL status
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Disable Address listen mode only if a transfer is not ongoing */
<> 144:ef7eb2e8f9f7 862 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Disable the Address Match interrupt */
<> 144:ef7eb2e8f9f7 867 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 return HAL_OK;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871 else
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @brief Enable the SMBUS alert mode with Interrupt.
<> 144:ef7eb2e8f9f7 879 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 880 * the configuration information for the specified SMBUSx peripheral.
<> 144:ef7eb2e8f9f7 881 * @retval HAL status
<> 144:ef7eb2e8f9f7 882 */
<> 144:ef7eb2e8f9f7 883 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 /* Enable SMBus alert */
<> 144:ef7eb2e8f9f7 886 hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Clear ALERT flag */
<> 144:ef7eb2e8f9f7 889 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /* Enable Alert Interrupt */
<> 144:ef7eb2e8f9f7 892 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 return HAL_OK;
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @brief Disable the SMBUS alert mode with Interrupt.
<> 144:ef7eb2e8f9f7 898 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 899 * the configuration information for the specified SMBUSx peripheral.
<> 144:ef7eb2e8f9f7 900 * @retval HAL status
<> 144:ef7eb2e8f9f7 901 */
<> 144:ef7eb2e8f9f7 902 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 /* Enable SMBus alert */
<> 144:ef7eb2e8f9f7 905 hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Disable Alert Interrupt */
<> 144:ef7eb2e8f9f7 908 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 return HAL_OK;
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /**
<> 144:ef7eb2e8f9f7 914 * @brief Check if target device is ready for communication.
<> 144:ef7eb2e8f9f7 915 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 916 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 917 * @param DevAddress Target device address: The device 7 bits address value
<> 144:ef7eb2e8f9f7 918 * in datasheet must be shift at right before call interface
<> 144:ef7eb2e8f9f7 919 * @param Trials Number of trials
<> 144:ef7eb2e8f9f7 920 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 921 * @retval HAL status
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 924 {
<> 156:95d6b41a828b 925 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 926
<> 156:95d6b41a828b 927 __IO uint32_t SMBUS_Trials = 0U;
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 if(hsmbus->State == HAL_SMBUS_STATE_READY)
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
<> 144:ef7eb2e8f9f7 932 {
<> 144:ef7eb2e8f9f7 933 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Process Locked */
<> 144:ef7eb2e8f9f7 937 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 hsmbus->State = HAL_SMBUS_STATE_BUSY;
<> 144:ef7eb2e8f9f7 940 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 do
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 /* Generate Start */
<> 144:ef7eb2e8f9f7 945 hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<> 144:ef7eb2e8f9f7 948 /* Wait until STOPF flag is set or a NACK flag is set*/
<> 144:ef7eb2e8f9f7 949 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 950 while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
<> 144:ef7eb2e8f9f7 951 {
<> 144:ef7eb2e8f9f7 952 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 953 {
<> 156:95d6b41a828b 954 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 955 {
<> 144:ef7eb2e8f9f7 956 /* Device is ready */
<> 144:ef7eb2e8f9f7 957 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 960 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 961 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 962 }
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964 }
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 /* Check if the NACKF flag has not been set */
<> 144:ef7eb2e8f9f7 967 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
<> 144:ef7eb2e8f9f7 968 {
<> 144:ef7eb2e8f9f7 969 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 970 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 976 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 /* Device is ready */
<> 144:ef7eb2e8f9f7 979 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 982 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 return HAL_OK;
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986 else
<> 144:ef7eb2e8f9f7 987 {
<> 144:ef7eb2e8f9f7 988 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 989 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 992 }
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 995 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /* Clear STOP Flag, auto generated with autoend*/
<> 144:ef7eb2e8f9f7 998 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Check if the maximum allowed number of trials has been reached */
<> 144:ef7eb2e8f9f7 1002 if (SMBUS_Trials++ == Trials)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 /* Generate Stop */
<> 144:ef7eb2e8f9f7 1005 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 1008 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 1009 {
<> 144:ef7eb2e8f9f7 1010 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1014 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016 }while(SMBUS_Trials < Trials);
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1021 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025 else
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1028 }
<> 144:ef7eb2e8f9f7 1029 }
<> 144:ef7eb2e8f9f7 1030 /**
<> 144:ef7eb2e8f9f7 1031 * @}
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 1035 * @{
<> 144:ef7eb2e8f9f7 1036 */
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /**
<> 144:ef7eb2e8f9f7 1039 * @brief Handle SMBUS event interrupt request.
<> 144:ef7eb2e8f9f7 1040 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1041 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1042 * @retval None
<> 144:ef7eb2e8f9f7 1043 */
<> 144:ef7eb2e8f9f7 1044 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1045 {
<> 156:95d6b41a828b 1046 uint32_t tmpisrvalue = 0U;
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 /* Use a local variable to store the current ISR flags */
<> 144:ef7eb2e8f9f7 1049 /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
<> 144:ef7eb2e8f9f7 1050 tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* SMBUS in mode Transmitter ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1053 if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 /* Slave mode selected */
<> 144:ef7eb2e8f9f7 1056 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 SMBUS_Slave_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060 /* Master mode selected */
<> 144:ef7eb2e8f9f7 1061 else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1062 {
<> 144:ef7eb2e8f9f7 1063 SMBUS_Master_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* SMBUS in mode Receiver ----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1068 if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 /* Slave mode selected */
<> 144:ef7eb2e8f9f7 1071 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 SMBUS_Slave_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075 /* Master mode selected */
<> 144:ef7eb2e8f9f7 1076 else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 SMBUS_Master_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* SMBUS in mode Listener Only --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1083 if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
<> 144:ef7eb2e8f9f7 1084 && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
<> 144:ef7eb2e8f9f7 1085 {
<> 144:ef7eb2e8f9f7 1086 if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 SMBUS_Slave_ISR(hsmbus);
<> 144:ef7eb2e8f9f7 1089 }
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /**
<> 144:ef7eb2e8f9f7 1094 * @brief Handle SMBUS error interrupt request.
<> 144:ef7eb2e8f9f7 1095 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1096 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1097 * @retval None
<> 144:ef7eb2e8f9f7 1098 */
<> 144:ef7eb2e8f9f7 1099 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1100 {
<> 144:ef7eb2e8f9f7 1101 /* SMBUS Bus error interrupt occurred ------------------------------------*/
<> 144:ef7eb2e8f9f7 1102 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* Clear BERR flag */
<> 144:ef7eb2e8f9f7 1107 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
<> 144:ef7eb2e8f9f7 1108 }
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
<> 144:ef7eb2e8f9f7 1111 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 1112 {
<> 144:ef7eb2e8f9f7 1113 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* Clear OVR flag */
<> 144:ef7eb2e8f9f7 1116 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
<> 144:ef7eb2e8f9f7 1120 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 1121 {
<> 144:ef7eb2e8f9f7 1122 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /* Clear ARLO flag */
<> 144:ef7eb2e8f9f7 1125 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 1129 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 1130 {
<> 144:ef7eb2e8f9f7 1131 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /* Clear TIMEOUT flag */
<> 144:ef7eb2e8f9f7 1134 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
<> 144:ef7eb2e8f9f7 1135 }
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1138 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 1139 {
<> 144:ef7eb2e8f9f7 1140 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /* Clear ALERT flag */
<> 144:ef7eb2e8f9f7 1143 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
<> 144:ef7eb2e8f9f7 1144 }
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
<> 144:ef7eb2e8f9f7 1147 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 1148 {
<> 144:ef7eb2e8f9f7 1149 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /* Clear PEC error flag */
<> 144:ef7eb2e8f9f7 1152 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
<> 144:ef7eb2e8f9f7 1153 }
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Call the Error Callback in case of Error detected */
<> 144:ef7eb2e8f9f7 1156 if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
<> 144:ef7eb2e8f9f7 1157 {
<> 144:ef7eb2e8f9f7 1158 /* Do not Reset the HAL state in case of ALERT error */
<> 144:ef7eb2e8f9f7 1159 if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
<> 144:ef7eb2e8f9f7 1160 {
<> 144:ef7eb2e8f9f7 1161 if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1162 || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
<> 144:ef7eb2e8f9f7 1165 /* keep HAL_SMBUS_STATE_LISTEN if set */
<> 144:ef7eb2e8f9f7 1166 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1167 hsmbus->State = HAL_SMBUS_STATE_LISTEN;
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Call the Error callback to prevent upper layer */
<> 144:ef7eb2e8f9f7 1172 HAL_SMBUS_ErrorCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1173 }
<> 144:ef7eb2e8f9f7 1174 }
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /**
<> 144:ef7eb2e8f9f7 1177 * @brief Master Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1178 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1179 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1180 * @retval None
<> 144:ef7eb2e8f9f7 1181 */
<> 144:ef7eb2e8f9f7 1182 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1183 {
<> 144:ef7eb2e8f9f7 1184 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1185 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1188 the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1189 */
<> 144:ef7eb2e8f9f7 1190 }
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /**
<> 144:ef7eb2e8f9f7 1193 * @brief Master Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1194 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1195 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1196 * @retval None
<> 144:ef7eb2e8f9f7 1197 */
<> 144:ef7eb2e8f9f7 1198 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1199 {
<> 144:ef7eb2e8f9f7 1200 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1201 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1204 the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206 }
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /** @brief Slave Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1209 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1210 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1211 * @retval None
<> 144:ef7eb2e8f9f7 1212 */
<> 144:ef7eb2e8f9f7 1213 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1214 {
<> 144:ef7eb2e8f9f7 1215 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1216 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1219 the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221 }
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /**
<> 144:ef7eb2e8f9f7 1224 * @brief Slave Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1225 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1226 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1227 * @retval None
<> 144:ef7eb2e8f9f7 1228 */
<> 144:ef7eb2e8f9f7 1229 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1232 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1235 the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1236 */
<> 144:ef7eb2e8f9f7 1237 }
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /**
<> 144:ef7eb2e8f9f7 1240 * @brief Slave Address Match callback.
<> 144:ef7eb2e8f9f7 1241 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1242 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1243 * @param TransferDirection: Master request Transfer Direction (Write/Read)
<> 144:ef7eb2e8f9f7 1244 * @param AddrMatchCode: Address Match Code
<> 144:ef7eb2e8f9f7 1245 * @retval None
<> 144:ef7eb2e8f9f7 1246 */
<> 144:ef7eb2e8f9f7 1247 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1250 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1251 UNUSED(TransferDirection);
<> 144:ef7eb2e8f9f7 1252 UNUSED(AddrMatchCode);
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1255 the HAL_SMBUS_AddrCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1256 */
<> 144:ef7eb2e8f9f7 1257 }
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /**
<> 144:ef7eb2e8f9f7 1260 * @brief Listen Complete callback.
<> 144:ef7eb2e8f9f7 1261 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1262 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1263 * @retval None
<> 144:ef7eb2e8f9f7 1264 */
<> 144:ef7eb2e8f9f7 1265 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1266 {
<> 144:ef7eb2e8f9f7 1267 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1268 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1271 the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1272 */
<> 144:ef7eb2e8f9f7 1273 }
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /**
<> 144:ef7eb2e8f9f7 1276 * @brief SMBUS error callback.
<> 144:ef7eb2e8f9f7 1277 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1278 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1279 * @retval None
<> 144:ef7eb2e8f9f7 1280 */
<> 144:ef7eb2e8f9f7 1281 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1282 {
<> 144:ef7eb2e8f9f7 1283 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1284 UNUSED(hsmbus);
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1287 the HAL_SMBUS_ErrorCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 1288 */
<> 144:ef7eb2e8f9f7 1289 }
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /**
<> 144:ef7eb2e8f9f7 1292 * @}
<> 144:ef7eb2e8f9f7 1293 */
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1296 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1297 *
<> 144:ef7eb2e8f9f7 1298 @verbatim
<> 144:ef7eb2e8f9f7 1299 ===============================================================================
<> 144:ef7eb2e8f9f7 1300 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1301 ===============================================================================
<> 144:ef7eb2e8f9f7 1302 [..]
<> 144:ef7eb2e8f9f7 1303 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1304 and the data flow.
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 @endverbatim
<> 144:ef7eb2e8f9f7 1307 * @{
<> 144:ef7eb2e8f9f7 1308 */
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /**
<> 144:ef7eb2e8f9f7 1311 * @brief Return the SMBUS handle state.
<> 144:ef7eb2e8f9f7 1312 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1313 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1314 * @retval HAL state
<> 144:ef7eb2e8f9f7 1315 */
<> 144:ef7eb2e8f9f7 1316 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 /* Return SMBUS handle state */
<> 144:ef7eb2e8f9f7 1319 return hsmbus->State;
<> 144:ef7eb2e8f9f7 1320 }
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /**
<> 144:ef7eb2e8f9f7 1323 * @brief Return the SMBUS error code.
<> 144:ef7eb2e8f9f7 1324 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1325 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1326 * @retval SMBUS Error Code
<> 144:ef7eb2e8f9f7 1327 */
<> 144:ef7eb2e8f9f7 1328 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1329 {
<> 144:ef7eb2e8f9f7 1330 return hsmbus->ErrorCode;
<> 144:ef7eb2e8f9f7 1331 }
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /**
<> 144:ef7eb2e8f9f7 1334 * @}
<> 144:ef7eb2e8f9f7 1335 */
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /**
<> 144:ef7eb2e8f9f7 1338 * @}
<> 144:ef7eb2e8f9f7 1339 */
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
<> 144:ef7eb2e8f9f7 1342 * @brief Data transfers Private functions
<> 144:ef7eb2e8f9f7 1343 * @{
<> 144:ef7eb2e8f9f7 1344 */
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /**
<> 144:ef7eb2e8f9f7 1347 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
<> 144:ef7eb2e8f9f7 1348 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1349 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1350 * @retval HAL status
<> 144:ef7eb2e8f9f7 1351 */
<> 144:ef7eb2e8f9f7 1352 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1353 {
<> 144:ef7eb2e8f9f7 1354 uint16_t DevAddress;
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Process Locked */
<> 144:ef7eb2e8f9f7 1357 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 1362 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Set corresponding Error Code */
<> 144:ef7eb2e8f9f7 1365 /* No need to generate STOP, it is automatically done */
<> 144:ef7eb2e8f9f7 1366 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1369 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 /* Call the Error callback to prevent upper layer */
<> 144:ef7eb2e8f9f7 1372 HAL_SMBUS_ErrorCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
<> 144:ef7eb2e8f9f7 1375 {
<> 144:ef7eb2e8f9f7 1376 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 1377 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1378 {
<> 144:ef7eb2e8f9f7 1379 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1380 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1383 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1384
<> 144:ef7eb2e8f9f7 1385 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1386 SMBUS_RESET_CR2(hsmbus);
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
<> 144:ef7eb2e8f9f7 1389 /* Disable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 1390 __HAL_SMBUS_DISABLE(hsmbus);
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1393 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1396 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 /* REenable the selected SMBUS peripheral */
<> 144:ef7eb2e8f9f7 1399 __HAL_SMBUS_ENABLE(hsmbus);
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1402 }
<> 144:ef7eb2e8f9f7 1403 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1404 {
<> 156:95d6b41a828b 1405 /* Store Last receive data if any */
<> 156:95d6b41a828b 1406 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
<> 156:95d6b41a828b 1407 {
<> 156:95d6b41a828b 1408 /* Read data from RXDR */
<> 156:95d6b41a828b 1409 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 156:95d6b41a828b 1410
<> 156:95d6b41a828b 1411 if((hsmbus->XferSize > 0U))
<> 156:95d6b41a828b 1412 {
<> 156:95d6b41a828b 1413 hsmbus->XferSize--;
<> 156:95d6b41a828b 1414 hsmbus->XferCount--;
<> 156:95d6b41a828b 1415 }
<> 156:95d6b41a828b 1416 }
<> 156:95d6b41a828b 1417
<> 144:ef7eb2e8f9f7 1418 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1419 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1422 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1425 SMBUS_RESET_CR2(hsmbus);
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1428 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1431 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1432
<> 144:ef7eb2e8f9f7 1433 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435 }
<> 144:ef7eb2e8f9f7 1436 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
<> 144:ef7eb2e8f9f7 1437 {
<> 144:ef7eb2e8f9f7 1438 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 1439 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 144:ef7eb2e8f9f7 1440 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1441 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1442 }
<> 144:ef7eb2e8f9f7 1443 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
<> 144:ef7eb2e8f9f7 1444 {
<> 144:ef7eb2e8f9f7 1445 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 1446 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
<> 144:ef7eb2e8f9f7 1447 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1448 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1449 }
<> 144:ef7eb2e8f9f7 1450 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
<> 144:ef7eb2e8f9f7 1451 {
<> 156:95d6b41a828b 1452 if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
<> 144:ef7eb2e8f9f7 1453 {
<> 144:ef7eb2e8f9f7 1454 DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 if(hsmbus->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1457 {
<> 144:ef7eb2e8f9f7 1458 SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1459 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1460 }
<> 144:ef7eb2e8f9f7 1461 else
<> 144:ef7eb2e8f9f7 1462 {
<> 144:ef7eb2e8f9f7 1463 hsmbus->XferSize = hsmbus->XferCount;
<> 144:ef7eb2e8f9f7 1464 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1465 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 1466 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
<> 144:ef7eb2e8f9f7 1467 if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 1468 {
<> 144:ef7eb2e8f9f7 1469 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1470 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1471 }
<> 144:ef7eb2e8f9f7 1472 }
<> 144:ef7eb2e8f9f7 1473 }
<> 156:95d6b41a828b 1474 else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
<> 144:ef7eb2e8f9f7 1475 {
<> 144:ef7eb2e8f9f7 1476 /* Call TxCpltCallback() if no stop mode is set */
<> 144:ef7eb2e8f9f7 1477 if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
<> 144:ef7eb2e8f9f7 1478 {
<> 144:ef7eb2e8f9f7 1479 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 1480 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1481 {
<> 144:ef7eb2e8f9f7 1482 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1483 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1484 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1485 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1488 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1491 }
<> 144:ef7eb2e8f9f7 1492 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1493 {
<> 144:ef7eb2e8f9f7 1494 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 1495 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1496 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1499 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1502 }
<> 144:ef7eb2e8f9f7 1503 }
<> 144:ef7eb2e8f9f7 1504 }
<> 144:ef7eb2e8f9f7 1505 }
<> 144:ef7eb2e8f9f7 1506 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
<> 144:ef7eb2e8f9f7 1507 {
<> 156:95d6b41a828b 1508 if(hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1509 {
<> 144:ef7eb2e8f9f7 1510 /* Specific use case for Quick command */
<> 144:ef7eb2e8f9f7 1511 if(hsmbus->pBuffPtr == NULL)
<> 144:ef7eb2e8f9f7 1512 {
<> 144:ef7eb2e8f9f7 1513 /* Generate a Stop command */
<> 144:ef7eb2e8f9f7 1514 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
<> 144:ef7eb2e8f9f7 1515 }
<> 144:ef7eb2e8f9f7 1516 /* Call TxCpltCallback() if no stop mode is set */
<> 144:ef7eb2e8f9f7 1517 else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
<> 144:ef7eb2e8f9f7 1518 {
<> 144:ef7eb2e8f9f7 1519 /* No Generate Stop, to permit restart mode */
<> 144:ef7eb2e8f9f7 1520 /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 1523 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
<> 144:ef7eb2e8f9f7 1524 {
<> 144:ef7eb2e8f9f7 1525 /* Disable Interrupt */
<> 144:ef7eb2e8f9f7 1526 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1527 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1528 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1531 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1532
<> 144:ef7eb2e8f9f7 1533 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1534 }
<> 144:ef7eb2e8f9f7 1535 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 1536 {
<> 144:ef7eb2e8f9f7 1537 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 1538 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1539 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1542 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1545 }
<> 144:ef7eb2e8f9f7 1546 }
<> 144:ef7eb2e8f9f7 1547 }
<> 144:ef7eb2e8f9f7 1548 }
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1551 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 return HAL_OK;
<> 144:ef7eb2e8f9f7 1554 }
<> 144:ef7eb2e8f9f7 1555 /**
<> 144:ef7eb2e8f9f7 1556 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
<> 144:ef7eb2e8f9f7 1557 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1558 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1559 * @retval HAL status
<> 144:ef7eb2e8f9f7 1560 */
<> 144:ef7eb2e8f9f7 1561 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
<> 144:ef7eb2e8f9f7 1562 {
<> 156:95d6b41a828b 1563 uint8_t TransferDirection = 0U;
<> 156:95d6b41a828b 1564 uint16_t SlaveAddrCode = 0U;
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /* Process Locked */
<> 144:ef7eb2e8f9f7 1567 __HAL_LOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
<> 144:ef7eb2e8f9f7 1570 {
<> 144:ef7eb2e8f9f7 1571 /* Check that SMBUS transfer finished */
<> 144:ef7eb2e8f9f7 1572 /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
<> 144:ef7eb2e8f9f7 1573 /* Mean XferCount == 0*/
<> 144:ef7eb2e8f9f7 1574 /* So clear Flag NACKF only */
<> 156:95d6b41a828b 1575 if(hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1576 {
<> 144:ef7eb2e8f9f7 1577 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 1578 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1581 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1582 }
<> 144:ef7eb2e8f9f7 1583 else
<> 144:ef7eb2e8f9f7 1584 {
<> 144:ef7eb2e8f9f7 1585 /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
<> 144:ef7eb2e8f9f7 1586 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 1587 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 /* Set HAL State to "Idle" State, mean to LISTEN state */
<> 144:ef7eb2e8f9f7 1590 /* So reset Slave Busy state */
<> 144:ef7eb2e8f9f7 1591 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1592 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
<> 144:ef7eb2e8f9f7 1593 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
<> 144:ef7eb2e8f9f7 1596 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1597
<> 144:ef7eb2e8f9f7 1598 /* Set ErrorCode corresponding to a Non-Acknowledge */
<> 144:ef7eb2e8f9f7 1599 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1602 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 /* Call the Error callback to prevent upper layer */
<> 144:ef7eb2e8f9f7 1605 HAL_SMBUS_ErrorCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1606 }
<> 144:ef7eb2e8f9f7 1607 }
<> 144:ef7eb2e8f9f7 1608 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
<> 144:ef7eb2e8f9f7 1609 {
<> 144:ef7eb2e8f9f7 1610 TransferDirection = SMBUS_GET_DIR(hsmbus);
<> 144:ef7eb2e8f9f7 1611 SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613 /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
<> 144:ef7eb2e8f9f7 1614 /* Other ADDRInterrupt will be treat in next Listen usecase */
<> 144:ef7eb2e8f9f7 1615 __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1618 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 /* Call Slave Addr callback */
<> 144:ef7eb2e8f9f7 1621 HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
<> 144:ef7eb2e8f9f7 1622 }
<> 144:ef7eb2e8f9f7 1623 else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
<> 144:ef7eb2e8f9f7 1624 {
<> 144:ef7eb2e8f9f7 1625 if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1626 {
<> 144:ef7eb2e8f9f7 1627 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 1628 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 144:ef7eb2e8f9f7 1629 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1630 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1631
<> 156:95d6b41a828b 1632 if(hsmbus->XferCount == 1U)
<> 144:ef7eb2e8f9f7 1633 {
<> 144:ef7eb2e8f9f7 1634 /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
<> 144:ef7eb2e8f9f7 1635 /* or only the last Byte of Transfer */
<> 144:ef7eb2e8f9f7 1636 /* So reset the RELOAD bit mode */
<> 144:ef7eb2e8f9f7 1637 hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
<> 156:95d6b41a828b 1638 SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1639 }
<> 156:95d6b41a828b 1640 else if(hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1641 {
<> 144:ef7eb2e8f9f7 1642 /* Last Byte is received, disable Interrupt */
<> 144:ef7eb2e8f9f7 1643 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
<> 144:ef7eb2e8f9f7 1646 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1647 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
<> 144:ef7eb2e8f9f7 1648
<> 144:ef7eb2e8f9f7 1649 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1650 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /* Call the Rx complete callback to inform upper layer of the end of receive process */
<> 144:ef7eb2e8f9f7 1653 HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1654 }
<> 144:ef7eb2e8f9f7 1655 else
<> 144:ef7eb2e8f9f7 1656 {
<> 144:ef7eb2e8f9f7 1657 /* Set Reload for next Bytes */
<> 156:95d6b41a828b 1658 SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 /* Ack last Byte Read */
<> 144:ef7eb2e8f9f7 1661 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1662 }
<> 144:ef7eb2e8f9f7 1663 }
<> 144:ef7eb2e8f9f7 1664 else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1665 {
<> 156:95d6b41a828b 1666 if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
<> 144:ef7eb2e8f9f7 1667 {
<> 144:ef7eb2e8f9f7 1668 if(hsmbus->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1669 {
<> 156:95d6b41a828b 1670 SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1671 hsmbus->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1672 }
<> 144:ef7eb2e8f9f7 1673 else
<> 144:ef7eb2e8f9f7 1674 {
<> 144:ef7eb2e8f9f7 1675 hsmbus->XferSize = hsmbus->XferCount;
<> 156:95d6b41a828b 1676 SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1677 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
<> 144:ef7eb2e8f9f7 1678 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
<> 144:ef7eb2e8f9f7 1679 if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1682 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1683 }
<> 144:ef7eb2e8f9f7 1684 }
<> 144:ef7eb2e8f9f7 1685 }
<> 144:ef7eb2e8f9f7 1686 }
<> 144:ef7eb2e8f9f7 1687 }
<> 144:ef7eb2e8f9f7 1688 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
<> 144:ef7eb2e8f9f7 1689 {
<> 144:ef7eb2e8f9f7 1690 /* Write data to TXDR only if XferCount not reach "0" */
<> 144:ef7eb2e8f9f7 1691 /* A TXIS flag can be set, during STOP treatment */
<> 156:95d6b41a828b 1692 /* Check if all Data have already been sent */
<> 144:ef7eb2e8f9f7 1693 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
<> 156:95d6b41a828b 1694 if(hsmbus->XferCount > 0U)
<> 144:ef7eb2e8f9f7 1695 {
<> 144:ef7eb2e8f9f7 1696 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 1697 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
<> 144:ef7eb2e8f9f7 1698 hsmbus->XferCount--;
<> 144:ef7eb2e8f9f7 1699 hsmbus->XferSize--;
<> 144:ef7eb2e8f9f7 1700 }
<> 144:ef7eb2e8f9f7 1701
<> 156:95d6b41a828b 1702 if(hsmbus->XferCount == 0U)
<> 144:ef7eb2e8f9f7 1703 {
<> 144:ef7eb2e8f9f7 1704 /* Last Byte is Transmitted */
<> 144:ef7eb2e8f9f7 1705 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
<> 144:ef7eb2e8f9f7 1706 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1707 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1708 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1711 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 /* Call the Tx complete callback to inform upper layer of the end of transmit process */
<> 144:ef7eb2e8f9f7 1714 HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1715 }
<> 144:ef7eb2e8f9f7 1716 }
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718 /* Check if STOPF is set */
<> 144:ef7eb2e8f9f7 1719 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
<> 144:ef7eb2e8f9f7 1720 {
<> 144:ef7eb2e8f9f7 1721 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1722 {
<> 156:95d6b41a828b 1723 /* Store Last receive data if any */
<> 156:95d6b41a828b 1724 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
<> 156:95d6b41a828b 1725 {
<> 156:95d6b41a828b 1726 /* Read data from RXDR */
<> 156:95d6b41a828b 1727 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
<> 156:95d6b41a828b 1728
<> 156:95d6b41a828b 1729 if((hsmbus->XferSize > 0U))
<> 156:95d6b41a828b 1730 {
<> 156:95d6b41a828b 1731 hsmbus->XferSize--;
<> 156:95d6b41a828b 1732 hsmbus->XferCount--;
<> 156:95d6b41a828b 1733 }
<> 156:95d6b41a828b 1734 }
<> 156:95d6b41a828b 1735
<> 144:ef7eb2e8f9f7 1736 /* Disable RX and TX Interrupts */
<> 144:ef7eb2e8f9f7 1737 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 /* Disable ADDR Interrupt */
<> 144:ef7eb2e8f9f7 1740 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1743 hsmbus->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1744
<> 144:ef7eb2e8f9f7 1745 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1746 SMBUS_RESET_CR2(hsmbus);
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1749 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 1752 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 1753
<> 156:95d6b41a828b 1754 hsmbus->XferOptions = 0U;
<> 144:ef7eb2e8f9f7 1755 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1756 hsmbus->State = HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1759 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
<> 144:ef7eb2e8f9f7 1762 HAL_SMBUS_ListenCpltCallback(hsmbus);
<> 144:ef7eb2e8f9f7 1763 }
<> 144:ef7eb2e8f9f7 1764 }
<> 144:ef7eb2e8f9f7 1765
<> 144:ef7eb2e8f9f7 1766 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1767 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 return HAL_OK;
<> 144:ef7eb2e8f9f7 1770 }
<> 144:ef7eb2e8f9f7 1771 /**
<> 144:ef7eb2e8f9f7 1772 * @brief Manage the enabling of Interrupts.
<> 144:ef7eb2e8f9f7 1773 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1774 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1775 * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
<> 144:ef7eb2e8f9f7 1776 * @retval HAL status
<> 144:ef7eb2e8f9f7 1777 */
<> 144:ef7eb2e8f9f7 1778 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
<> 144:ef7eb2e8f9f7 1779 {
<> 156:95d6b41a828b 1780 uint32_t tmpisr = 0U;
<> 144:ef7eb2e8f9f7 1781
<> 144:ef7eb2e8f9f7 1782 if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
<> 144:ef7eb2e8f9f7 1783 {
<> 144:ef7eb2e8f9f7 1784 /* Enable ERR interrupt */
<> 144:ef7eb2e8f9f7 1785 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1786 }
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
<> 144:ef7eb2e8f9f7 1789 {
<> 144:ef7eb2e8f9f7 1790 /* Enable ADDR, STOP interrupt */
<> 144:ef7eb2e8f9f7 1791 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1792 }
<> 144:ef7eb2e8f9f7 1793
<> 144:ef7eb2e8f9f7 1794 if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
<> 144:ef7eb2e8f9f7 1795 {
<> 144:ef7eb2e8f9f7 1796 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
<> 144:ef7eb2e8f9f7 1797 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
<> 144:ef7eb2e8f9f7 1798 }
<> 144:ef7eb2e8f9f7 1799
<> 144:ef7eb2e8f9f7 1800 if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
<> 144:ef7eb2e8f9f7 1801 {
<> 144:ef7eb2e8f9f7 1802 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
<> 144:ef7eb2e8f9f7 1803 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
<> 144:ef7eb2e8f9f7 1804 }
<> 144:ef7eb2e8f9f7 1805
<> 144:ef7eb2e8f9f7 1806 /* Enable interrupts only at the end */
<> 144:ef7eb2e8f9f7 1807 /* to avoid the risk of SMBUS interrupt handle execution before */
<> 144:ef7eb2e8f9f7 1808 /* all interrupts requested done */
<> 144:ef7eb2e8f9f7 1809 __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 return HAL_OK;
<> 144:ef7eb2e8f9f7 1812 }
<> 144:ef7eb2e8f9f7 1813 /**
<> 144:ef7eb2e8f9f7 1814 * @brief Manage the disabling of Interrupts.
<> 144:ef7eb2e8f9f7 1815 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1816 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1817 * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
<> 144:ef7eb2e8f9f7 1818 * @retval HAL status
<> 144:ef7eb2e8f9f7 1819 */
<> 144:ef7eb2e8f9f7 1820 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
<> 144:ef7eb2e8f9f7 1821 {
<> 156:95d6b41a828b 1822 uint32_t tmpisr = 0U;
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
<> 144:ef7eb2e8f9f7 1825 {
<> 144:ef7eb2e8f9f7 1826 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1827 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1828 }
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
<> 144:ef7eb2e8f9f7 1831 {
<> 144:ef7eb2e8f9f7 1832 /* Disable TC, STOP, NACK, TXI interrupt */
<> 144:ef7eb2e8f9f7 1833 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
<> 144:ef7eb2e8f9f7 1834
<> 144:ef7eb2e8f9f7 1835 if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
<> 144:ef7eb2e8f9f7 1836 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
<> 144:ef7eb2e8f9f7 1837 {
<> 144:ef7eb2e8f9f7 1838 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1839 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1840 }
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1843 {
<> 144:ef7eb2e8f9f7 1844 /* Disable STOPI, NACKI */
<> 144:ef7eb2e8f9f7 1845 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
<> 144:ef7eb2e8f9f7 1846 }
<> 144:ef7eb2e8f9f7 1847 }
<> 144:ef7eb2e8f9f7 1848
<> 144:ef7eb2e8f9f7 1849 if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
<> 144:ef7eb2e8f9f7 1850 {
<> 144:ef7eb2e8f9f7 1851 /* Disable TC, STOP, NACK, RXI interrupt */
<> 144:ef7eb2e8f9f7 1852 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
<> 144:ef7eb2e8f9f7 1853
<> 144:ef7eb2e8f9f7 1854 if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
<> 144:ef7eb2e8f9f7 1855 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
<> 144:ef7eb2e8f9f7 1856 {
<> 144:ef7eb2e8f9f7 1857 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1858 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 1862 {
<> 144:ef7eb2e8f9f7 1863 /* Disable STOPI, NACKI */
<> 144:ef7eb2e8f9f7 1864 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
<> 144:ef7eb2e8f9f7 1865 }
<> 144:ef7eb2e8f9f7 1866 }
<> 144:ef7eb2e8f9f7 1867
<> 144:ef7eb2e8f9f7 1868 if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
<> 144:ef7eb2e8f9f7 1869 {
<> 144:ef7eb2e8f9f7 1870 /* Enable ADDR, STOP interrupt */
<> 144:ef7eb2e8f9f7 1871 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
<> 144:ef7eb2e8f9f7 1872
<> 144:ef7eb2e8f9f7 1873 if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
<> 144:ef7eb2e8f9f7 1874 {
<> 144:ef7eb2e8f9f7 1875 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 1876 tmpisr |= SMBUS_IT_ERRI;
<> 144:ef7eb2e8f9f7 1877 }
<> 144:ef7eb2e8f9f7 1878 }
<> 144:ef7eb2e8f9f7 1879
<> 144:ef7eb2e8f9f7 1880 /* Disable interrupts only at the end */
<> 144:ef7eb2e8f9f7 1881 /* to avoid a breaking situation like at "t" time */
<> 144:ef7eb2e8f9f7 1882 /* all disable interrupts request are not done */
<> 144:ef7eb2e8f9f7 1883 __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 return HAL_OK;
<> 144:ef7eb2e8f9f7 1886 }
<> 144:ef7eb2e8f9f7 1887 /**
<> 144:ef7eb2e8f9f7 1888 * @brief Handle SMBUS Communication Timeout.
<> 144:ef7eb2e8f9f7 1889 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1890 * the configuration information for the specified SMBUS.
<> 144:ef7eb2e8f9f7 1891 * @param Flag Specifies the SMBUS flag to check.
<> 144:ef7eb2e8f9f7 1892 * @param Status The new Flag status (SET or RESET).
<> 144:ef7eb2e8f9f7 1893 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 1894 * @retval HAL status
<> 144:ef7eb2e8f9f7 1895 */
<> 144:ef7eb2e8f9f7 1896 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1897 {
<> 144:ef7eb2e8f9f7 1898 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1901 if(Status == RESET)
<> 144:ef7eb2e8f9f7 1902 {
<> 144:ef7eb2e8f9f7 1903 while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1904 {
<> 144:ef7eb2e8f9f7 1905 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1906 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1907 {
<> 156:95d6b41a828b 1908 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1909 {
<> 144:ef7eb2e8f9f7 1910 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1911 hsmbus->State= HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1912
<> 144:ef7eb2e8f9f7 1913 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1914 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1915
<> 144:ef7eb2e8f9f7 1916 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1917 }
<> 144:ef7eb2e8f9f7 1918 }
<> 144:ef7eb2e8f9f7 1919 }
<> 144:ef7eb2e8f9f7 1920 }
<> 144:ef7eb2e8f9f7 1921 else
<> 144:ef7eb2e8f9f7 1922 {
<> 144:ef7eb2e8f9f7 1923 while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1924 {
<> 144:ef7eb2e8f9f7 1925 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1926 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1927 {
<> 156:95d6b41a828b 1928 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1929 {
<> 144:ef7eb2e8f9f7 1930 hsmbus->PreviousState = hsmbus->State;
<> 144:ef7eb2e8f9f7 1931 hsmbus->State= HAL_SMBUS_STATE_READY;
<> 144:ef7eb2e8f9f7 1932
<> 144:ef7eb2e8f9f7 1933 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1934 __HAL_UNLOCK(hsmbus);
<> 144:ef7eb2e8f9f7 1935
<> 144:ef7eb2e8f9f7 1936 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1937 }
<> 144:ef7eb2e8f9f7 1938 }
<> 144:ef7eb2e8f9f7 1939 }
<> 144:ef7eb2e8f9f7 1940 }
<> 144:ef7eb2e8f9f7 1941 return HAL_OK;
<> 144:ef7eb2e8f9f7 1942 }
<> 144:ef7eb2e8f9f7 1943
<> 144:ef7eb2e8f9f7 1944 /**
<> 144:ef7eb2e8f9f7 1945 * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
<> 144:ef7eb2e8f9f7 1946 * @param hsmbus SMBUS handle.
<> 144:ef7eb2e8f9f7 1947 * @param DevAddress specifies the slave address to be programmed.
<> 144:ef7eb2e8f9f7 1948 * @param Size specifies the number of bytes to be programmed.
<> 144:ef7eb2e8f9f7 1949 * This parameter must be a value between 0 and 255.
<> 144:ef7eb2e8f9f7 1950 * @param Mode New state of the SMBUS START condition generation.
<> 144:ef7eb2e8f9f7 1951 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 1952 * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
<> 144:ef7eb2e8f9f7 1953 * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
<> 144:ef7eb2e8f9f7 1954 * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
<> 144:ef7eb2e8f9f7 1955 * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
<> 144:ef7eb2e8f9f7 1956 * @param Request New state of the SMBUS START condition generation.
<> 144:ef7eb2e8f9f7 1957 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1958 * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
<> 144:ef7eb2e8f9f7 1959 * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
<> 144:ef7eb2e8f9f7 1960 * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
<> 144:ef7eb2e8f9f7 1961 * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
<> 144:ef7eb2e8f9f7 1962 * @retval None
<> 144:ef7eb2e8f9f7 1963 */
<> 144:ef7eb2e8f9f7 1964 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
<> 144:ef7eb2e8f9f7 1965 {
<> 156:95d6b41a828b 1966 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1969 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
<> 144:ef7eb2e8f9f7 1970 assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
<> 144:ef7eb2e8f9f7 1971 assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
<> 144:ef7eb2e8f9f7 1972
<> 144:ef7eb2e8f9f7 1973 /* Get the CR2 register value */
<> 144:ef7eb2e8f9f7 1974 tmpreg = hsmbus->Instance->CR2;
<> 144:ef7eb2e8f9f7 1975
<> 144:ef7eb2e8f9f7 1976 /* clear tmpreg specific bits */
<> 144:ef7eb2e8f9f7 1977 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
<> 144:ef7eb2e8f9f7 1978
<> 144:ef7eb2e8f9f7 1979 /* update tmpreg */
<> 156:95d6b41a828b 1980 tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
<> 144:ef7eb2e8f9f7 1981 (uint32_t)Mode | (uint32_t)Request);
<> 144:ef7eb2e8f9f7 1982
<> 144:ef7eb2e8f9f7 1983 /* update CR2 register */
<> 144:ef7eb2e8f9f7 1984 hsmbus->Instance->CR2 = tmpreg;
<> 144:ef7eb2e8f9f7 1985 }
<> 144:ef7eb2e8f9f7 1986 /**
<> 144:ef7eb2e8f9f7 1987 * @}
<> 144:ef7eb2e8f9f7 1988 */
<> 144:ef7eb2e8f9f7 1989
<> 144:ef7eb2e8f9f7 1990 #endif /* HAL_SMBUS_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1991 /**
<> 144:ef7eb2e8f9f7 1992 * @}
<> 144:ef7eb2e8f9f7 1993 */
<> 144:ef7eb2e8f9f7 1994
<> 144:ef7eb2e8f9f7 1995 /**
<> 144:ef7eb2e8f9f7 1996 * @}
<> 144:ef7eb2e8f9f7 1997 */
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/