mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 187:0387e8f68319
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 170:19eb464bc2be | 1 | /* mbed Microcontroller Library |
Kojto | 170:19eb464bc2be | 2 | * Copyright (c) 2006-2017 ARM Limited |
Kojto | 170:19eb464bc2be | 3 | * |
Kojto | 170:19eb464bc2be | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
Kojto | 170:19eb464bc2be | 5 | * you may not use this file except in compliance with the License. |
Kojto | 170:19eb464bc2be | 6 | * You may obtain a copy of the License at |
Kojto | 170:19eb464bc2be | 7 | * |
Kojto | 170:19eb464bc2be | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
Kojto | 170:19eb464bc2be | 9 | * |
Kojto | 170:19eb464bc2be | 10 | * Unless required by applicable law or agreed to in writing, software |
Kojto | 170:19eb464bc2be | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
Kojto | 170:19eb464bc2be | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
Kojto | 170:19eb464bc2be | 13 | * See the License for the specific language governing permissions and |
Kojto | 170:19eb464bc2be | 14 | * limitations under the License. |
Kojto | 170:19eb464bc2be | 15 | */ |
Kojto | 170:19eb464bc2be | 16 | |
Kojto | 170:19eb464bc2be | 17 | /** |
Kojto | 170:19eb464bc2be | 18 | * This file configures the system clock as follows: |
Kojto | 170:19eb464bc2be | 19 | *----------------------------------------------------------------- |
Kojto | 170:19eb464bc2be | 20 | * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
Kojto | 170:19eb464bc2be | 21 | * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
Kojto | 170:19eb464bc2be | 22 | * | 3- USE_PLL_HSI (internal 8 MHz) |
Kojto | 170:19eb464bc2be | 23 | *----------------------------------------------------------------- |
Kojto | 170:19eb464bc2be | 24 | * SYSCLK(MHz) | 48 |
Kojto | 170:19eb464bc2be | 25 | * AHBCLK (MHz) | 48 |
Kojto | 170:19eb464bc2be | 26 | * APB1CLK (MHz) | 48 |
Kojto | 170:19eb464bc2be | 27 | * USB capable | NO |
Kojto | 170:19eb464bc2be | 28 | *----------------------------------------------------------------- |
Kojto | 170:19eb464bc2be | 29 | */ |
Kojto | 170:19eb464bc2be | 30 | |
Kojto | 170:19eb464bc2be | 31 | #include "stm32f0xx.h" |
AnnaBridge | 187:0387e8f68319 | 32 | #include "mbed_error.h" |
Kojto | 170:19eb464bc2be | 33 | |
Kojto | 170:19eb464bc2be | 34 | #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not connected by default) |
Kojto | 170:19eb464bc2be | 35 | #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) |
Kojto | 170:19eb464bc2be | 36 | #define USE_PLL_HSI 0x2 // Use HSI internal clock |
Kojto | 170:19eb464bc2be | 37 | |
Kojto | 170:19eb464bc2be | 38 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
Kojto | 170:19eb464bc2be | 39 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
Kojto | 170:19eb464bc2be | 40 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
Kojto | 170:19eb464bc2be | 41 | |
Kojto | 170:19eb464bc2be | 42 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
Kojto | 170:19eb464bc2be | 43 | uint8_t SetSysClock_PLL_HSI(void); |
Kojto | 170:19eb464bc2be | 44 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
Kojto | 170:19eb464bc2be | 45 | |
Kojto | 170:19eb464bc2be | 46 | |
Kojto | 170:19eb464bc2be | 47 | /** |
Kojto | 170:19eb464bc2be | 48 | * @brief Setup the microcontroller system. |
Kojto | 170:19eb464bc2be | 49 | * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. |
Kojto | 170:19eb464bc2be | 50 | * @param None |
Kojto | 170:19eb464bc2be | 51 | * @retval None |
Kojto | 170:19eb464bc2be | 52 | */ |
Kojto | 170:19eb464bc2be | 53 | void SystemInit(void) |
Kojto | 170:19eb464bc2be | 54 | { |
Kojto | 170:19eb464bc2be | 55 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
Kojto | 170:19eb464bc2be | 56 | /* Set HSION bit */ |
Kojto | 170:19eb464bc2be | 57 | RCC->CR |= (uint32_t)0x00000001U; |
Kojto | 170:19eb464bc2be | 58 | |
Kojto | 170:19eb464bc2be | 59 | #if defined (STM32F051x8) || defined (STM32F058x8) |
Kojto | 170:19eb464bc2be | 60 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ |
Kojto | 170:19eb464bc2be | 61 | RCC->CFGR &= (uint32_t)0xF8FFB80CU; |
Kojto | 170:19eb464bc2be | 62 | #else |
Kojto | 170:19eb464bc2be | 63 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ |
Kojto | 170:19eb464bc2be | 64 | RCC->CFGR &= (uint32_t)0x08FFB80CU; |
Kojto | 170:19eb464bc2be | 65 | #endif /* STM32F051x8 or STM32F058x8 */ |
Kojto | 170:19eb464bc2be | 66 | |
Kojto | 170:19eb464bc2be | 67 | /* Reset HSEON, CSSON and PLLON bits */ |
Kojto | 170:19eb464bc2be | 68 | RCC->CR &= (uint32_t)0xFEF6FFFFU; |
Kojto | 170:19eb464bc2be | 69 | |
Kojto | 170:19eb464bc2be | 70 | /* Reset HSEBYP bit */ |
Kojto | 170:19eb464bc2be | 71 | RCC->CR &= (uint32_t)0xFFFBFFFFU; |
Kojto | 170:19eb464bc2be | 72 | |
Kojto | 170:19eb464bc2be | 73 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
Kojto | 170:19eb464bc2be | 74 | RCC->CFGR &= (uint32_t)0xFFC0FFFFU; |
Kojto | 170:19eb464bc2be | 75 | |
Kojto | 170:19eb464bc2be | 76 | /* Reset PREDIV[3:0] bits */ |
Kojto | 170:19eb464bc2be | 77 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; |
Kojto | 170:19eb464bc2be | 78 | |
Kojto | 170:19eb464bc2be | 79 | #if defined (STM32F072xB) || defined (STM32F078xx) |
Kojto | 170:19eb464bc2be | 80 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
Kojto | 170:19eb464bc2be | 81 | RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; |
Kojto | 170:19eb464bc2be | 82 | #elif defined (STM32F071xB) |
Kojto | 170:19eb464bc2be | 83 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
Kojto | 170:19eb464bc2be | 84 | RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; |
Kojto | 170:19eb464bc2be | 85 | #elif defined (STM32F091xC) || defined (STM32F098xx) |
Kojto | 170:19eb464bc2be | 86 | /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
Kojto | 170:19eb464bc2be | 87 | RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; |
Kojto | 170:19eb464bc2be | 88 | #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) |
Kojto | 170:19eb464bc2be | 89 | /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ |
Kojto | 170:19eb464bc2be | 90 | RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; |
Kojto | 170:19eb464bc2be | 91 | #elif defined (STM32F051x8) || defined (STM32F058xx) |
Kojto | 170:19eb464bc2be | 92 | /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
Kojto | 170:19eb464bc2be | 93 | RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; |
Kojto | 170:19eb464bc2be | 94 | #elif defined (STM32F042x6) || defined (STM32F048xx) |
Kojto | 170:19eb464bc2be | 95 | /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
Kojto | 170:19eb464bc2be | 96 | RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; |
Kojto | 170:19eb464bc2be | 97 | #elif defined (STM32F070x6) || defined (STM32F070xB) |
Kojto | 170:19eb464bc2be | 98 | /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ |
Kojto | 170:19eb464bc2be | 99 | RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; |
Kojto | 170:19eb464bc2be | 100 | /* Set default USB clock to PLLCLK, since there is no HSI48 */ |
Kojto | 170:19eb464bc2be | 101 | RCC->CFGR3 |= (uint32_t)0x00000080U; |
Kojto | 170:19eb464bc2be | 102 | #else |
Kojto | 170:19eb464bc2be | 103 | #warning "No target selected" |
Kojto | 170:19eb464bc2be | 104 | #endif |
Kojto | 170:19eb464bc2be | 105 | |
Kojto | 170:19eb464bc2be | 106 | /* Reset HSI14 bit */ |
Kojto | 170:19eb464bc2be | 107 | RCC->CR2 &= (uint32_t)0xFFFFFFFEU; |
Kojto | 170:19eb464bc2be | 108 | |
Kojto | 170:19eb464bc2be | 109 | /* Disable all interrupts */ |
Kojto | 170:19eb464bc2be | 110 | RCC->CIR = 0x00000000U; |
Kojto | 170:19eb464bc2be | 111 | |
Kojto | 170:19eb464bc2be | 112 | /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */ |
Kojto | 170:19eb464bc2be | 113 | RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; |
Kojto | 170:19eb464bc2be | 114 | } |
Kojto | 170:19eb464bc2be | 115 | |
Kojto | 170:19eb464bc2be | 116 | /** |
Kojto | 170:19eb464bc2be | 117 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
Kojto | 170:19eb464bc2be | 118 | * AHB/APBx prescalers and Flash settings |
Kojto | 170:19eb464bc2be | 119 | * @note This function should be called only once the RCC clock configuration |
Kojto | 170:19eb464bc2be | 120 | * is reset to the default reset state (done in SystemInit() function). |
Kojto | 170:19eb464bc2be | 121 | * @param None |
Kojto | 170:19eb464bc2be | 122 | * @retval None |
Kojto | 170:19eb464bc2be | 123 | */ |
Kojto | 170:19eb464bc2be | 124 | void SetSysClock(void) |
Kojto | 170:19eb464bc2be | 125 | { |
Kojto | 170:19eb464bc2be | 126 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) |
Kojto | 170:19eb464bc2be | 127 | /* 1- Try to start with HSE and external clock */ |
Kojto | 170:19eb464bc2be | 128 | if (SetSysClock_PLL_HSE(1) == 0) |
Kojto | 170:19eb464bc2be | 129 | #endif |
Kojto | 170:19eb464bc2be | 130 | { |
Kojto | 170:19eb464bc2be | 131 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) |
Kojto | 170:19eb464bc2be | 132 | /* 2- If fail try to start with HSE and external xtal */ |
Kojto | 170:19eb464bc2be | 133 | if (SetSysClock_PLL_HSE(0) == 0) |
Kojto | 170:19eb464bc2be | 134 | #endif |
Kojto | 170:19eb464bc2be | 135 | { |
Kojto | 170:19eb464bc2be | 136 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
Kojto | 170:19eb464bc2be | 137 | /* 3- If fail start with HSI clock */ |
Kojto | 170:19eb464bc2be | 138 | if (SetSysClock_PLL_HSI() == 0) |
Kojto | 170:19eb464bc2be | 139 | #endif |
Kojto | 170:19eb464bc2be | 140 | { |
AnnaBridge | 187:0387e8f68319 | 141 | { |
AnnaBridge | 187:0387e8f68319 | 142 | error("SetSysClock failed\n"); |
Kojto | 170:19eb464bc2be | 143 | } |
Kojto | 170:19eb464bc2be | 144 | } |
Kojto | 170:19eb464bc2be | 145 | } |
Kojto | 170:19eb464bc2be | 146 | } |
Kojto | 170:19eb464bc2be | 147 | |
Kojto | 170:19eb464bc2be | 148 | /* Output clock on MCO pin(PA8) for debugging purpose */ |
Kojto | 170:19eb464bc2be | 149 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz |
Kojto | 170:19eb464bc2be | 150 | } |
Kojto | 170:19eb464bc2be | 151 | |
Kojto | 170:19eb464bc2be | 152 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
Kojto | 170:19eb464bc2be | 153 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 154 | /* PLL (clocked by HSE) used as System clock source */ |
Kojto | 170:19eb464bc2be | 155 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 156 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
Kojto | 170:19eb464bc2be | 157 | { |
Kojto | 170:19eb464bc2be | 158 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 159 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 160 | |
Kojto | 170:19eb464bc2be | 161 | //Select HSI as system clock source to allow modification of the PLL configuration |
Kojto | 170:19eb464bc2be | 162 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
Kojto | 170:19eb464bc2be | 163 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; |
Kojto | 170:19eb464bc2be | 164 | if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 165 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 166 | } |
Kojto | 170:19eb464bc2be | 167 | |
Kojto | 170:19eb464bc2be | 168 | |
Kojto | 170:19eb464bc2be | 169 | // Select HSE oscillator as PLL source |
Kojto | 170:19eb464bc2be | 170 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
Kojto | 170:19eb464bc2be | 171 | if (bypass == 0) { |
Kojto | 170:19eb464bc2be | 172 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
Kojto | 170:19eb464bc2be | 173 | } else { |
Kojto | 170:19eb464bc2be | 174 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only |
Kojto | 170:19eb464bc2be | 175 | } |
Kojto | 170:19eb464bc2be | 176 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
Kojto | 170:19eb464bc2be | 177 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
Kojto | 170:19eb464bc2be | 178 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; |
Kojto | 170:19eb464bc2be | 179 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
Kojto | 170:19eb464bc2be | 180 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 181 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 182 | } |
Kojto | 170:19eb464bc2be | 183 | |
Kojto | 170:19eb464bc2be | 184 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
Kojto | 170:19eb464bc2be | 185 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
Kojto | 170:19eb464bc2be | 186 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
Kojto | 170:19eb464bc2be | 187 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
Kojto | 170:19eb464bc2be | 188 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
Kojto | 170:19eb464bc2be | 189 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 190 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 191 | } |
Kojto | 170:19eb464bc2be | 192 | |
Kojto | 170:19eb464bc2be | 193 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz |
Kojto | 170:19eb464bc2be | 194 | |
Kojto | 170:19eb464bc2be | 195 | return 1; // OK |
Kojto | 170:19eb464bc2be | 196 | } |
Kojto | 170:19eb464bc2be | 197 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
Kojto | 170:19eb464bc2be | 198 | |
Kojto | 170:19eb464bc2be | 199 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
Kojto | 170:19eb464bc2be | 200 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 201 | /* PLL (clocked by HSI) used as System clock source */ |
Kojto | 170:19eb464bc2be | 202 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 203 | uint8_t SetSysClock_PLL_HSI(void) |
Kojto | 170:19eb464bc2be | 204 | { |
Kojto | 170:19eb464bc2be | 205 | RCC_OscInitTypeDef RCC_OscInitStruct; |
Kojto | 170:19eb464bc2be | 206 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
Kojto | 170:19eb464bc2be | 207 | |
Kojto | 170:19eb464bc2be | 208 | // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) |
Kojto | 170:19eb464bc2be | 209 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
Kojto | 170:19eb464bc2be | 210 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
Kojto | 170:19eb464bc2be | 211 | RCC_OscInitStruct.LSEState = RCC_LSE_OFF; |
Kojto | 170:19eb464bc2be | 212 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
Kojto | 170:19eb464bc2be | 213 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
Kojto | 170:19eb464bc2be | 214 | RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; |
Kojto | 170:19eb464bc2be | 215 | RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; |
Kojto | 170:19eb464bc2be | 216 | RCC_OscInitStruct.LSIState = RCC_LSI_OFF; |
Kojto | 170:19eb464bc2be | 217 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
Kojto | 170:19eb464bc2be | 218 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 |
Kojto | 170:19eb464bc2be | 219 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; |
Kojto | 170:19eb464bc2be | 220 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
Kojto | 170:19eb464bc2be | 221 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 222 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 223 | } |
Kojto | 170:19eb464bc2be | 224 | |
Kojto | 170:19eb464bc2be | 225 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
Kojto | 170:19eb464bc2be | 226 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
Kojto | 170:19eb464bc2be | 227 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
Kojto | 170:19eb464bc2be | 228 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
Kojto | 170:19eb464bc2be | 229 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
Kojto | 170:19eb464bc2be | 230 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 231 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 232 | } |
Kojto | 170:19eb464bc2be | 233 | |
Kojto | 170:19eb464bc2be | 234 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz |
Kojto | 170:19eb464bc2be | 235 | |
Kojto | 170:19eb464bc2be | 236 | return 1; // OK |
Kojto | 170:19eb464bc2be | 237 | } |
Kojto | 170:19eb464bc2be | 238 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |