mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_GigaDevice/TARGET_GD32F4XX/sleep.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2018 GigaDevice Semiconductor Inc.
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 5 *
AnnaBridge 189:f392fc9709a3 6 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 7 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 8 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 13 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 15 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 16 * limitations under the License.
AnnaBridge 189:f392fc9709a3 17 */
AnnaBridge 189:f392fc9709a3 18
AnnaBridge 189:f392fc9709a3 19 #if DEVICE_SLEEP
AnnaBridge 189:f392fc9709a3 20
AnnaBridge 189:f392fc9709a3 21 #include "sleep_api.h"
AnnaBridge 189:f392fc9709a3 22 #include "us_ticker_api.h"
AnnaBridge 189:f392fc9709a3 23 #include "mbed_critical.h"
AnnaBridge 189:f392fc9709a3 24 #include "mbed_error.h"
AnnaBridge 189:f392fc9709a3 25
AnnaBridge 189:f392fc9709a3 26 extern void ticker_timer_data_save(void);
AnnaBridge 189:f392fc9709a3 27 extern void ticker_timer_data_restore(void);
AnnaBridge 189:f392fc9709a3 28 extern int serial_busy_state_check(void);
AnnaBridge 189:f392fc9709a3 29 extern int mbed_sdk_inited;
AnnaBridge 189:f392fc9709a3 30
AnnaBridge 189:f392fc9709a3 31 /*!
AnnaBridge 189:f392fc9709a3 32 \brief configure the system clock to 200M by PLL which selects HXTAL(25M) as its clock source
AnnaBridge 189:f392fc9709a3 33 \param[in] none
AnnaBridge 189:f392fc9709a3 34 \param[out] none
AnnaBridge 189:f392fc9709a3 35 \retval none
AnnaBridge 189:f392fc9709a3 36 */
AnnaBridge 189:f392fc9709a3 37 static void system_clock_200m_25m_hxtal(void)
AnnaBridge 189:f392fc9709a3 38 {
AnnaBridge 189:f392fc9709a3 39 uint32_t timeout = 0U;
AnnaBridge 189:f392fc9709a3 40 uint32_t stab_flag = 0U;
AnnaBridge 189:f392fc9709a3 41
AnnaBridge 189:f392fc9709a3 42 /* enable HXTAL */
AnnaBridge 189:f392fc9709a3 43 RCU_CTL |= RCU_CTL_HXTALEN;
AnnaBridge 189:f392fc9709a3 44
AnnaBridge 189:f392fc9709a3 45 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
AnnaBridge 189:f392fc9709a3 46 do {
AnnaBridge 189:f392fc9709a3 47 timeout++;
AnnaBridge 189:f392fc9709a3 48 stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
AnnaBridge 189:f392fc9709a3 49 } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /* if fail */
AnnaBridge 189:f392fc9709a3 52 if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
AnnaBridge 189:f392fc9709a3 53 while (1) {
AnnaBridge 189:f392fc9709a3 54 }
AnnaBridge 189:f392fc9709a3 55 }
AnnaBridge 189:f392fc9709a3 56
AnnaBridge 189:f392fc9709a3 57 RCU_APB1EN |= RCU_APB1EN_PMUEN;
AnnaBridge 189:f392fc9709a3 58 PMU_CTL |= PMU_CTL_LDOVS;
AnnaBridge 189:f392fc9709a3 59
AnnaBridge 189:f392fc9709a3 60 /* HXTAL is stable */
AnnaBridge 189:f392fc9709a3 61 /* AHB = SYSCLK */
AnnaBridge 189:f392fc9709a3 62 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
AnnaBridge 189:f392fc9709a3 63 /* APB2 = AHB/2 */
AnnaBridge 189:f392fc9709a3 64 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
AnnaBridge 189:f392fc9709a3 65 /* APB1 = AHB/4 */
AnnaBridge 189:f392fc9709a3 66 RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
AnnaBridge 189:f392fc9709a3 67
AnnaBridge 189:f392fc9709a3 68 /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
AnnaBridge 189:f392fc9709a3 69 RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
AnnaBridge 189:f392fc9709a3 70 (RCU_PLLSRC_HXTAL) | (9U << 24U));
AnnaBridge 189:f392fc9709a3 71
AnnaBridge 189:f392fc9709a3 72 /* enable PLL */
AnnaBridge 189:f392fc9709a3 73 RCU_CTL |= RCU_CTL_PLLEN;
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 /* wait until PLL is stable */
AnnaBridge 189:f392fc9709a3 76 while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
AnnaBridge 189:f392fc9709a3 77 }
AnnaBridge 189:f392fc9709a3 78
AnnaBridge 189:f392fc9709a3 79 /* Enable the high-drive to extend the clock frequency to 200 Mhz */
AnnaBridge 189:f392fc9709a3 80 PMU_CTL |= PMU_CTL_HDEN;
AnnaBridge 189:f392fc9709a3 81 while (0U == (PMU_CS & PMU_CS_HDRF)) {
AnnaBridge 189:f392fc9709a3 82 }
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 /* select the high-drive mode */
AnnaBridge 189:f392fc9709a3 85 PMU_CTL |= PMU_CTL_HDS;
AnnaBridge 189:f392fc9709a3 86 while (0U == (PMU_CS & PMU_CS_HDSRF)) {
AnnaBridge 189:f392fc9709a3 87 }
AnnaBridge 189:f392fc9709a3 88
AnnaBridge 189:f392fc9709a3 89 /* select PLL as system clock */
AnnaBridge 189:f392fc9709a3 90 RCU_CFG0 &= ~RCU_CFG0_SCS;
AnnaBridge 189:f392fc9709a3 91 RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
AnnaBridge 189:f392fc9709a3 92
AnnaBridge 189:f392fc9709a3 93 /* wait until PLL is selected as system clock */
AnnaBridge 189:f392fc9709a3 94 while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
AnnaBridge 189:f392fc9709a3 95 }
AnnaBridge 189:f392fc9709a3 96 }
AnnaBridge 189:f392fc9709a3 97
AnnaBridge 189:f392fc9709a3 98
AnnaBridge 189:f392fc9709a3 99 /** Send the microcontroller to sleep
AnnaBridge 189:f392fc9709a3 100 *
AnnaBridge 189:f392fc9709a3 101 * The processor is setup ready for sleep, and sent to sleep. In this mode, the
AnnaBridge 189:f392fc9709a3 102 * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
AnnaBridge 189:f392fc9709a3 103 * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
AnnaBridge 189:f392fc9709a3 104 * memory state are maintained, and the peripherals continue to work and can generate interrupts.
AnnaBridge 189:f392fc9709a3 105 *
AnnaBridge 189:f392fc9709a3 106 * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
AnnaBridge 189:f392fc9709a3 107 *
AnnaBridge 189:f392fc9709a3 108 * The wake-up time shall be less than 10 us.
AnnaBridge 189:f392fc9709a3 109 *
AnnaBridge 189:f392fc9709a3 110 */
AnnaBridge 189:f392fc9709a3 111 void hal_sleep(void)
AnnaBridge 189:f392fc9709a3 112 {
AnnaBridge 189:f392fc9709a3 113 /* disable interrupts */
AnnaBridge 189:f392fc9709a3 114 core_util_critical_section_enter();
AnnaBridge 189:f392fc9709a3 115
AnnaBridge 189:f392fc9709a3 116 /* enter SLEEP mode */
AnnaBridge 189:f392fc9709a3 117 pmu_to_sleepmode(WFI_CMD);
AnnaBridge 189:f392fc9709a3 118
AnnaBridge 189:f392fc9709a3 119 /* enable interrupts */
AnnaBridge 189:f392fc9709a3 120 core_util_critical_section_exit();
AnnaBridge 189:f392fc9709a3 121 }
AnnaBridge 189:f392fc9709a3 122
AnnaBridge 189:f392fc9709a3 123
AnnaBridge 189:f392fc9709a3 124 /** Send the microcontroller to deep sleep
AnnaBridge 189:f392fc9709a3 125 *
AnnaBridge 189:f392fc9709a3 126 * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
AnnaBridge 189:f392fc9709a3 127 * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks.
AnnaBridge 189:f392fc9709a3 128 * All state is still maintained.
AnnaBridge 189:f392fc9709a3 129 *
AnnaBridge 189:f392fc9709a3 130 * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer.
AnnaBridge 189:f392fc9709a3 131 *
AnnaBridge 189:f392fc9709a3 132 * The wake-up time shall be less than 10 ms.
AnnaBridge 189:f392fc9709a3 133 */
AnnaBridge 189:f392fc9709a3 134 void hal_deepsleep(void)
AnnaBridge 189:f392fc9709a3 135 {
AnnaBridge 189:f392fc9709a3 136 if (0 != serial_busy_state_check()) {
AnnaBridge 189:f392fc9709a3 137 return;
AnnaBridge 189:f392fc9709a3 138 }
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 /* disable interrupts */
AnnaBridge 189:f392fc9709a3 141 core_util_critical_section_enter();
AnnaBridge 189:f392fc9709a3 142
AnnaBridge 189:f392fc9709a3 143 ticker_timer_data_save();
AnnaBridge 189:f392fc9709a3 144
AnnaBridge 189:f392fc9709a3 145 /* enter DEEP-SLEEP mode */
AnnaBridge 189:f392fc9709a3 146 rcu_periph_clock_enable(RCU_PMU);
AnnaBridge 189:f392fc9709a3 147 pmu_to_deepsleepmode(PMU_LDO_NORMAL, WFI_CMD);
AnnaBridge 189:f392fc9709a3 148
AnnaBridge 189:f392fc9709a3 149 mbed_sdk_inited = 0;
AnnaBridge 189:f392fc9709a3 150
AnnaBridge 189:f392fc9709a3 151 /* reconfigure the PLL and set the system clock to the highest frequence after weak up */
AnnaBridge 189:f392fc9709a3 152 system_clock_200m_25m_hxtal();
AnnaBridge 189:f392fc9709a3 153
AnnaBridge 189:f392fc9709a3 154 ticker_timer_data_restore();
AnnaBridge 189:f392fc9709a3 155 mbed_sdk_inited = 1;
AnnaBridge 189:f392fc9709a3 156
AnnaBridge 189:f392fc9709a3 157 /* enable interrupts */
AnnaBridge 189:f392fc9709a3 158 core_util_critical_section_exit();
AnnaBridge 189:f392fc9709a3 159 }
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 #endif /* DEVICE_SLEEP */