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targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /*!
AnnaBridge 189:f392fc9709a3 2 \file gd32f30x_enet.h
AnnaBridge 189:f392fc9709a3 3 \brief definitions for the ENET
AnnaBridge 189:f392fc9709a3 4
AnnaBridge 189:f392fc9709a3 5 \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed)
AnnaBridge 189:f392fc9709a3 6 */
AnnaBridge 189:f392fc9709a3 7
AnnaBridge 189:f392fc9709a3 8 /*
AnnaBridge 189:f392fc9709a3 9 Copyright (c) 2018, GigaDevice Semiconductor Inc.
AnnaBridge 189:f392fc9709a3 10
AnnaBridge 189:f392fc9709a3 11 All rights reserved.
AnnaBridge 189:f392fc9709a3 12
AnnaBridge 189:f392fc9709a3 13 Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 14 are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 15
AnnaBridge 189:f392fc9709a3 16 1. Redistributions of source code must retain the above copyright notice, this
AnnaBridge 189:f392fc9709a3 17 list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 18 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 19 this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 20 and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 21 3. Neither the name of the copyright holder nor the names of its contributors
AnnaBridge 189:f392fc9709a3 22 may be used to endorse or promote products derived from this software without
AnnaBridge 189:f392fc9709a3 23 specific prior written permission.
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 189:f392fc9709a3 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
AnnaBridge 189:f392fc9709a3 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
AnnaBridge 189:f392fc9709a3 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
AnnaBridge 189:f392fc9709a3 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
AnnaBridge 189:f392fc9709a3 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
AnnaBridge 189:f392fc9709a3 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 189:f392fc9709a3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
AnnaBridge 189:f392fc9709a3 34 OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 35 */
AnnaBridge 189:f392fc9709a3 36
AnnaBridge 189:f392fc9709a3 37 #ifndef GD32F30X_ENET_H
AnnaBridge 189:f392fc9709a3 38 #define GD32F30X_ENET_H
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #include "gd32f30x.h"
AnnaBridge 189:f392fc9709a3 41 #include <stdlib.h>
AnnaBridge 189:f392fc9709a3 42
AnnaBridge 189:f392fc9709a3 43 #define IF_USE_EXTERNPHY_LIB 0
AnnaBridge 189:f392fc9709a3 44 #if (1 == IF_USE_EXTERNPHY_LIB)
AnnaBridge 189:f392fc9709a3 45 #include "phy.h"
AnnaBridge 189:f392fc9709a3 46 #endif
AnnaBridge 189:f392fc9709a3 47
AnnaBridge 189:f392fc9709a3 48 #ifndef ENET_RXBUF_NUM
AnnaBridge 189:f392fc9709a3 49 #define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */
AnnaBridge 189:f392fc9709a3 50 #endif
AnnaBridge 189:f392fc9709a3 51
AnnaBridge 189:f392fc9709a3 52 #ifndef ENET_TXBUF_NUM
AnnaBridge 189:f392fc9709a3 53 #define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */
AnnaBridge 189:f392fc9709a3 54 #endif
AnnaBridge 189:f392fc9709a3 55
AnnaBridge 189:f392fc9709a3 56 #ifndef ENET_RXBUF_SIZE
AnnaBridge 189:f392fc9709a3 57 #define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */
AnnaBridge 189:f392fc9709a3 58 #endif
AnnaBridge 189:f392fc9709a3 59
AnnaBridge 189:f392fc9709a3 60 #ifndef ENET_TXBUF_SIZE
AnnaBridge 189:f392fc9709a3 61 #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */
AnnaBridge 189:f392fc9709a3 62 #endif
AnnaBridge 189:f392fc9709a3 63
AnnaBridge 189:f392fc9709a3 64 /* #define SELECT_DESCRIPTORS_ENHANCED_MODE */
AnnaBridge 189:f392fc9709a3 65
AnnaBridge 189:f392fc9709a3 66 /* #define USE_DELAY */
AnnaBridge 189:f392fc9709a3 67
AnnaBridge 189:f392fc9709a3 68 #ifndef _PHY_H_
AnnaBridge 189:f392fc9709a3 69 #define DP83848 0
AnnaBridge 189:f392fc9709a3 70 #define LAN8700 1
AnnaBridge 189:f392fc9709a3 71 #define PHY_TYPE DP83848
AnnaBridge 189:f392fc9709a3 72
AnnaBridge 189:f392fc9709a3 73 #define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 /* PHY read write timeouts */
AnnaBridge 189:f392fc9709a3 76 #define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */
AnnaBridge 189:f392fc9709a3 77 #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */
AnnaBridge 189:f392fc9709a3 78
AnnaBridge 189:f392fc9709a3 79 /* PHY delay */
AnnaBridge 189:f392fc9709a3 80 #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */
AnnaBridge 189:f392fc9709a3 81 #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 /* PHY register address */
AnnaBridge 189:f392fc9709a3 84 #define PHY_REG_BCR 0U /*!< tranceiver basic control register */
AnnaBridge 189:f392fc9709a3 85 #define PHY_REG_BSR 1U /*!< tranceiver basic status register */
AnnaBridge 189:f392fc9709a3 86
AnnaBridge 189:f392fc9709a3 87 /* PHY basic control register */
AnnaBridge 189:f392fc9709a3 88 #define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */
AnnaBridge 189:f392fc9709a3 89 #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */
AnnaBridge 189:f392fc9709a3 90 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */
AnnaBridge 189:f392fc9709a3 91 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */
AnnaBridge 189:f392fc9709a3 92 #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */
AnnaBridge 189:f392fc9709a3 93 #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */
AnnaBridge 189:f392fc9709a3 94 #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */
AnnaBridge 189:f392fc9709a3 95 #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */
AnnaBridge 189:f392fc9709a3 96 #define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */
AnnaBridge 189:f392fc9709a3 97 #define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */
AnnaBridge 189:f392fc9709a3 98
AnnaBridge 189:f392fc9709a3 99 /* PHY basic status register */
AnnaBridge 189:f392fc9709a3 100 #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */
AnnaBridge 189:f392fc9709a3 101 #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */
AnnaBridge 189:f392fc9709a3 102 #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */
AnnaBridge 189:f392fc9709a3 103
AnnaBridge 189:f392fc9709a3 104 #if(PHY_TYPE == LAN8700)
AnnaBridge 189:f392fc9709a3 105 #define PHY_SR 31U /*!< tranceiver status register */
AnnaBridge 189:f392fc9709a3 106 #define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */
AnnaBridge 189:f392fc9709a3 107 #define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */
AnnaBridge 189:f392fc9709a3 108 #elif(PHY_TYPE == DP83848)
AnnaBridge 189:f392fc9709a3 109 #define PHY_SR 16U /*!< tranceiver status register */
AnnaBridge 189:f392fc9709a3 110 #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */
AnnaBridge 189:f392fc9709a3 111 #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */
AnnaBridge 189:f392fc9709a3 112 #endif /* PHY_TYPE */
AnnaBridge 189:f392fc9709a3 113
AnnaBridge 189:f392fc9709a3 114 #endif /* _PHY_H_ */
AnnaBridge 189:f392fc9709a3 115
AnnaBridge 189:f392fc9709a3 116
AnnaBridge 189:f392fc9709a3 117 /* ENET definitions */
AnnaBridge 189:f392fc9709a3 118 #define ENET ENET_BASE
AnnaBridge 189:f392fc9709a3 119
AnnaBridge 189:f392fc9709a3 120 /* registers definitions */
AnnaBridge 189:f392fc9709a3 121 #define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */
AnnaBridge 189:f392fc9709a3 122 #define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */
AnnaBridge 189:f392fc9709a3 123 #define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */
AnnaBridge 189:f392fc9709a3 124 #define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */
AnnaBridge 189:f392fc9709a3 125 #define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */
AnnaBridge 189:f392fc9709a3 126 #define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */
AnnaBridge 189:f392fc9709a3 127 #define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */
AnnaBridge 189:f392fc9709a3 128 #define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */
AnnaBridge 189:f392fc9709a3 129 #define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */
AnnaBridge 189:f392fc9709a3 130 #define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */
AnnaBridge 189:f392fc9709a3 131 #define ENET_MAC_DBG REG32((ENET) + 0x34U) /*!< ethernet MAC debug register */
AnnaBridge 189:f392fc9709a3 132 #define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */
AnnaBridge 189:f392fc9709a3 133 #define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */
AnnaBridge 189:f392fc9709a3 134 #define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */
AnnaBridge 189:f392fc9709a3 135 #define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */
AnnaBridge 189:f392fc9709a3 136 #define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */
AnnaBridge 189:f392fc9709a3 137 #define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */
AnnaBridge 189:f392fc9709a3 138 #define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */
AnnaBridge 189:f392fc9709a3 139 #define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */
AnnaBridge 189:f392fc9709a3 140 #define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */
AnnaBridge 189:f392fc9709a3 141 #define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */
AnnaBridge 189:f392fc9709a3 142 #define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */
AnnaBridge 189:f392fc9709a3 143
AnnaBridge 189:f392fc9709a3 144 #define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */
AnnaBridge 189:f392fc9709a3 145 #define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */
AnnaBridge 189:f392fc9709a3 146 #define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */
AnnaBridge 189:f392fc9709a3 147 #define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */
AnnaBridge 189:f392fc9709a3 148 #define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */
AnnaBridge 189:f392fc9709a3 149 #define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */
AnnaBridge 189:f392fc9709a3 150 #define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */
AnnaBridge 189:f392fc9709a3 151 #define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */
AnnaBridge 189:f392fc9709a3 152 #define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */
AnnaBridge 189:f392fc9709a3 153 #define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */
AnnaBridge 189:f392fc9709a3 154 #define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */
AnnaBridge 189:f392fc9709a3 155
AnnaBridge 189:f392fc9709a3 156 #define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */
AnnaBridge 189:f392fc9709a3 157 #define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */
AnnaBridge 189:f392fc9709a3 158 #define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */
AnnaBridge 189:f392fc9709a3 159 #define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */
AnnaBridge 189:f392fc9709a3 160 #define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */
AnnaBridge 189:f392fc9709a3 161 #define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */
AnnaBridge 189:f392fc9709a3 162 #define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */
AnnaBridge 189:f392fc9709a3 163 #define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */
AnnaBridge 189:f392fc9709a3 164 #define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */
AnnaBridge 189:f392fc9709a3 165 #define ENET_PTP_TSF REG32((ENET) + 0x728U) /*!< ethernet PTP time stamp flag register */
AnnaBridge 189:f392fc9709a3 166 #define ENET_PTP_PPSCTL REG32((ENET) + 0x72CU) /*!< ethernet PTP PPS control register */
AnnaBridge 189:f392fc9709a3 167
AnnaBridge 189:f392fc9709a3 168 #define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */
AnnaBridge 189:f392fc9709a3 169 #define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */
AnnaBridge 189:f392fc9709a3 170 #define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */
AnnaBridge 189:f392fc9709a3 171 #define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */
AnnaBridge 189:f392fc9709a3 172 #define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */
AnnaBridge 189:f392fc9709a3 173 #define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */
AnnaBridge 189:f392fc9709a3 174 #define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */
AnnaBridge 189:f392fc9709a3 175 #define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */
AnnaBridge 189:f392fc9709a3 176 #define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */
AnnaBridge 189:f392fc9709a3 177 #define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */
AnnaBridge 189:f392fc9709a3 178 #define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */
AnnaBridge 189:f392fc9709a3 179 #define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */
AnnaBridge 189:f392fc9709a3 180 #define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */
AnnaBridge 189:f392fc9709a3 181 #define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */
AnnaBridge 189:f392fc9709a3 182
AnnaBridge 189:f392fc9709a3 183 /* bits definitions */
AnnaBridge 189:f392fc9709a3 184 /* ENET_MAC_CFG */
AnnaBridge 189:f392fc9709a3 185 #define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */
AnnaBridge 189:f392fc9709a3 186 #define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */
AnnaBridge 189:f392fc9709a3 187 #define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */
AnnaBridge 189:f392fc9709a3 188 #define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */
AnnaBridge 189:f392fc9709a3 189 #define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */
AnnaBridge 189:f392fc9709a3 190 #define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */
AnnaBridge 189:f392fc9709a3 191 #define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */
AnnaBridge 189:f392fc9709a3 192 #define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */
AnnaBridge 189:f392fc9709a3 193 #define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */
AnnaBridge 189:f392fc9709a3 194 #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */
AnnaBridge 189:f392fc9709a3 195 #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */
AnnaBridge 189:f392fc9709a3 196 #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */
AnnaBridge 189:f392fc9709a3 197 #define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */
AnnaBridge 189:f392fc9709a3 198 #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */
AnnaBridge 189:f392fc9709a3 199 #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */
AnnaBridge 189:f392fc9709a3 200 #define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */
AnnaBridge 189:f392fc9709a3 201
AnnaBridge 189:f392fc9709a3 202 /* ENET_MAC_FRMF */
AnnaBridge 189:f392fc9709a3 203 #define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */
AnnaBridge 189:f392fc9709a3 204 #define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */
AnnaBridge 189:f392fc9709a3 205 #define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */
AnnaBridge 189:f392fc9709a3 206 #define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */
AnnaBridge 189:f392fc9709a3 207 #define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */
AnnaBridge 189:f392fc9709a3 208 #define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */
AnnaBridge 189:f392fc9709a3 209 #define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */
AnnaBridge 189:f392fc9709a3 210 #define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */
AnnaBridge 189:f392fc9709a3 211 #define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */
AnnaBridge 189:f392fc9709a3 212 #define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */
AnnaBridge 189:f392fc9709a3 213 #define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */
AnnaBridge 189:f392fc9709a3 214
AnnaBridge 189:f392fc9709a3 215 /* ENET_MAC_HLH */
AnnaBridge 189:f392fc9709a3 216 #define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */
AnnaBridge 189:f392fc9709a3 217
AnnaBridge 189:f392fc9709a3 218 /* ENET_MAC_HLL */
AnnaBridge 189:f392fc9709a3 219 #define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */
AnnaBridge 189:f392fc9709a3 220
AnnaBridge 189:f392fc9709a3 221 /* ENET_MAC_PHY_CTL */
AnnaBridge 189:f392fc9709a3 222 #define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */
AnnaBridge 189:f392fc9709a3 223 #define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */
AnnaBridge 189:f392fc9709a3 224 #define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */
AnnaBridge 189:f392fc9709a3 225 #define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */
AnnaBridge 189:f392fc9709a3 226 #define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */
AnnaBridge 189:f392fc9709a3 227
AnnaBridge 189:f392fc9709a3 228 /* ENET_MAC_PHY_DATA */
AnnaBridge 189:f392fc9709a3 229 #define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */
AnnaBridge 189:f392fc9709a3 230
AnnaBridge 189:f392fc9709a3 231 /* ENET_MAC_FCTL */
AnnaBridge 189:f392fc9709a3 232 #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */
AnnaBridge 189:f392fc9709a3 233 #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */
AnnaBridge 189:f392fc9709a3 234 #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */
AnnaBridge 189:f392fc9709a3 235 #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */
AnnaBridge 189:f392fc9709a3 236 #define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */
AnnaBridge 189:f392fc9709a3 237 #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */
AnnaBridge 189:f392fc9709a3 238 #define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */
AnnaBridge 189:f392fc9709a3 239
AnnaBridge 189:f392fc9709a3 240 /* ENET_MAC_VLT */
AnnaBridge 189:f392fc9709a3 241 #define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */
AnnaBridge 189:f392fc9709a3 242 #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */
AnnaBridge 189:f392fc9709a3 243
AnnaBridge 189:f392fc9709a3 244 /* ENET_MAC_RWFF */
AnnaBridge 189:f392fc9709a3 245 #define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */
AnnaBridge 189:f392fc9709a3 246
AnnaBridge 189:f392fc9709a3 247 /* ENET_MAC_WUM */
AnnaBridge 189:f392fc9709a3 248 #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */
AnnaBridge 189:f392fc9709a3 249 #define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */
AnnaBridge 189:f392fc9709a3 250 #define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */
AnnaBridge 189:f392fc9709a3 251 #define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */
AnnaBridge 189:f392fc9709a3 252 #define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */
AnnaBridge 189:f392fc9709a3 253 #define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */
AnnaBridge 189:f392fc9709a3 254 #define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */
AnnaBridge 189:f392fc9709a3 255
AnnaBridge 189:f392fc9709a3 256 /* ENET_MAC_DBG */
AnnaBridge 189:f392fc9709a3 257 #define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */
AnnaBridge 189:f392fc9709a3 258 #define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */
AnnaBridge 189:f392fc9709a3 259 #define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */
AnnaBridge 189:f392fc9709a3 260 #define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */
AnnaBridge 189:f392fc9709a3 261 #define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */
AnnaBridge 189:f392fc9709a3 262 #define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */
AnnaBridge 189:f392fc9709a3 263 #define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */
AnnaBridge 189:f392fc9709a3 264 #define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */
AnnaBridge 189:f392fc9709a3 265 #define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */
AnnaBridge 189:f392fc9709a3 266 #define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */
AnnaBridge 189:f392fc9709a3 267 #define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */
AnnaBridge 189:f392fc9709a3 268 #define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */
AnnaBridge 189:f392fc9709a3 269
AnnaBridge 189:f392fc9709a3 270 /* ENET_MAC_INTF */
AnnaBridge 189:f392fc9709a3 271 #define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */
AnnaBridge 189:f392fc9709a3 272 #define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */
AnnaBridge 189:f392fc9709a3 273 #define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */
AnnaBridge 189:f392fc9709a3 274 #define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */
AnnaBridge 189:f392fc9709a3 275 #define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */
AnnaBridge 189:f392fc9709a3 276
AnnaBridge 189:f392fc9709a3 277 /* ENET_MAC_INTMSK */
AnnaBridge 189:f392fc9709a3 278 #define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */
AnnaBridge 189:f392fc9709a3 279 #define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */
AnnaBridge 189:f392fc9709a3 280
AnnaBridge 189:f392fc9709a3 281 /* ENET_MAC_ADDR0H */
AnnaBridge 189:f392fc9709a3 282 #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */
AnnaBridge 189:f392fc9709a3 283 #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */
AnnaBridge 189:f392fc9709a3 284
AnnaBridge 189:f392fc9709a3 285 /* ENET_MAC_ADDR0L */
AnnaBridge 189:f392fc9709a3 286 #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */
AnnaBridge 189:f392fc9709a3 287
AnnaBridge 189:f392fc9709a3 288 /* ENET_MAC_ADDR1H */
AnnaBridge 189:f392fc9709a3 289 #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */
AnnaBridge 189:f392fc9709a3 290 #define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */
AnnaBridge 189:f392fc9709a3 291 #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */
AnnaBridge 189:f392fc9709a3 292 #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */
AnnaBridge 189:f392fc9709a3 293
AnnaBridge 189:f392fc9709a3 294 /* ENET_MAC_ADDR1L */
AnnaBridge 189:f392fc9709a3 295 #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */
AnnaBridge 189:f392fc9709a3 296
AnnaBridge 189:f392fc9709a3 297 /* ENET_MAC_ADDR2H */
AnnaBridge 189:f392fc9709a3 298 #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */
AnnaBridge 189:f392fc9709a3 299 #define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */
AnnaBridge 189:f392fc9709a3 300 #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */
AnnaBridge 189:f392fc9709a3 301 #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */
AnnaBridge 189:f392fc9709a3 302
AnnaBridge 189:f392fc9709a3 303 /* ENET_MAC_ADDR2L */
AnnaBridge 189:f392fc9709a3 304 #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */
AnnaBridge 189:f392fc9709a3 305
AnnaBridge 189:f392fc9709a3 306 /* ENET_MAC_ADDR3H */
AnnaBridge 189:f392fc9709a3 307 #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */
AnnaBridge 189:f392fc9709a3 308 #define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */
AnnaBridge 189:f392fc9709a3 309 #define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */
AnnaBridge 189:f392fc9709a3 310 #define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */
AnnaBridge 189:f392fc9709a3 311
AnnaBridge 189:f392fc9709a3 312 /* ENET_MAC_ADDR3L */
AnnaBridge 189:f392fc9709a3 313 #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */
AnnaBridge 189:f392fc9709a3 314
AnnaBridge 189:f392fc9709a3 315 /* ENET_MAC_FCTH */
AnnaBridge 189:f392fc9709a3 316 #define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */
AnnaBridge 189:f392fc9709a3 317 #define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */
AnnaBridge 189:f392fc9709a3 318
AnnaBridge 189:f392fc9709a3 319 /* ENET_MSC_CTL */
AnnaBridge 189:f392fc9709a3 320 #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */
AnnaBridge 189:f392fc9709a3 321 #define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */
AnnaBridge 189:f392fc9709a3 322 #define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */
AnnaBridge 189:f392fc9709a3 323 #define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */
AnnaBridge 189:f392fc9709a3 324 #define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */
AnnaBridge 189:f392fc9709a3 325 #define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */
AnnaBridge 189:f392fc9709a3 326
AnnaBridge 189:f392fc9709a3 327 /* ENET_MSC_RINTF */
AnnaBridge 189:f392fc9709a3 328 #define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */
AnnaBridge 189:f392fc9709a3 329 #define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */
AnnaBridge 189:f392fc9709a3 330 #define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */
AnnaBridge 189:f392fc9709a3 331
AnnaBridge 189:f392fc9709a3 332 /* ENET_MSC_TINTF */
AnnaBridge 189:f392fc9709a3 333 #define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */
AnnaBridge 189:f392fc9709a3 334 #define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */
AnnaBridge 189:f392fc9709a3 335 #define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */
AnnaBridge 189:f392fc9709a3 336
AnnaBridge 189:f392fc9709a3 337 /* ENET_MSC_RINTMSK */
AnnaBridge 189:f392fc9709a3 338 #define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */
AnnaBridge 189:f392fc9709a3 339 #define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */
AnnaBridge 189:f392fc9709a3 340 #define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */
AnnaBridge 189:f392fc9709a3 341
AnnaBridge 189:f392fc9709a3 342 /* ENET_MSC_TINTMSK */
AnnaBridge 189:f392fc9709a3 343 #define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */
AnnaBridge 189:f392fc9709a3 344 #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */
AnnaBridge 189:f392fc9709a3 345 #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */
AnnaBridge 189:f392fc9709a3 346
AnnaBridge 189:f392fc9709a3 347 /* ENET_MSC_SCCNT */
AnnaBridge 189:f392fc9709a3 348 #define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */
AnnaBridge 189:f392fc9709a3 349
AnnaBridge 189:f392fc9709a3 350 /* ENET_MSC_MSCCNT */
AnnaBridge 189:f392fc9709a3 351 #define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */
AnnaBridge 189:f392fc9709a3 352
AnnaBridge 189:f392fc9709a3 353 /* ENET_MSC_TGFCNT */
AnnaBridge 189:f392fc9709a3 354 #define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */
AnnaBridge 189:f392fc9709a3 355
AnnaBridge 189:f392fc9709a3 356 /* ENET_MSC_RFCECNT */
AnnaBridge 189:f392fc9709a3 357 #define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */
AnnaBridge 189:f392fc9709a3 358
AnnaBridge 189:f392fc9709a3 359 /* ENET_MSC_RFAECNT */
AnnaBridge 189:f392fc9709a3 360 #define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */
AnnaBridge 189:f392fc9709a3 361
AnnaBridge 189:f392fc9709a3 362 /* ENET_MSC_RGUFCNT */
AnnaBridge 189:f392fc9709a3 363 #define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */
AnnaBridge 189:f392fc9709a3 364
AnnaBridge 189:f392fc9709a3 365 /* ENET_PTP_TSCTL */
AnnaBridge 189:f392fc9709a3 366 #define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */
AnnaBridge 189:f392fc9709a3 367 #define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */
AnnaBridge 189:f392fc9709a3 368 #define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */
AnnaBridge 189:f392fc9709a3 369 #define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */
AnnaBridge 189:f392fc9709a3 370 #define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */
AnnaBridge 189:f392fc9709a3 371 #define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */
AnnaBridge 189:f392fc9709a3 372 #define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */
AnnaBridge 189:f392fc9709a3 373 #define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */
AnnaBridge 189:f392fc9709a3 374 #define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */
AnnaBridge 189:f392fc9709a3 375 #define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */
AnnaBridge 189:f392fc9709a3 376 #define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */
AnnaBridge 189:f392fc9709a3 377 #define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */
AnnaBridge 189:f392fc9709a3 378 #define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */
AnnaBridge 189:f392fc9709a3 379 #define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */
AnnaBridge 189:f392fc9709a3 380 #define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */
AnnaBridge 189:f392fc9709a3 381 #define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */
AnnaBridge 189:f392fc9709a3 382
AnnaBridge 189:f392fc9709a3 383 /* ENET_PTP_SSINC */
AnnaBridge 189:f392fc9709a3 384 #define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */
AnnaBridge 189:f392fc9709a3 385
AnnaBridge 189:f392fc9709a3 386 /* ENET_PTP_TSH */
AnnaBridge 189:f392fc9709a3 387 #define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */
AnnaBridge 189:f392fc9709a3 388
AnnaBridge 189:f392fc9709a3 389 /* ENET_PTP_TSL */
AnnaBridge 189:f392fc9709a3 390 #define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */
AnnaBridge 189:f392fc9709a3 391 #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */
AnnaBridge 189:f392fc9709a3 392
AnnaBridge 189:f392fc9709a3 393 /* ENET_PTP_TSUH */
AnnaBridge 189:f392fc9709a3 394 #define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */
AnnaBridge 189:f392fc9709a3 395
AnnaBridge 189:f392fc9709a3 396 /* ENET_PTP_TSUL */
AnnaBridge 189:f392fc9709a3 397 #define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */
AnnaBridge 189:f392fc9709a3 398 #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */
AnnaBridge 189:f392fc9709a3 399
AnnaBridge 189:f392fc9709a3 400 /* ENET_PTP_TSADDEND */
AnnaBridge 189:f392fc9709a3 401 #define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */
AnnaBridge 189:f392fc9709a3 402
AnnaBridge 189:f392fc9709a3 403 /* ENET_PTP_ETH */
AnnaBridge 189:f392fc9709a3 404 #define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */
AnnaBridge 189:f392fc9709a3 405
AnnaBridge 189:f392fc9709a3 406 /* ENET_PTP_ETL */
AnnaBridge 189:f392fc9709a3 407 #define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */
AnnaBridge 189:f392fc9709a3 408
AnnaBridge 189:f392fc9709a3 409 /* ENET_PTP_TSF */
AnnaBridge 189:f392fc9709a3 410 #define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */
AnnaBridge 189:f392fc9709a3 411 #define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */
AnnaBridge 189:f392fc9709a3 412
AnnaBridge 189:f392fc9709a3 413 /* ENET_PTP_PPSCTL */
AnnaBridge 189:f392fc9709a3 414 #define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */
AnnaBridge 189:f392fc9709a3 415
AnnaBridge 189:f392fc9709a3 416 /* ENET_DMA_BCTL */
AnnaBridge 189:f392fc9709a3 417 #define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */
AnnaBridge 189:f392fc9709a3 418 #define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */
AnnaBridge 189:f392fc9709a3 419 #define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */
AnnaBridge 189:f392fc9709a3 420 #define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */
AnnaBridge 189:f392fc9709a3 421 #define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */
AnnaBridge 189:f392fc9709a3 422 #define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */
AnnaBridge 189:f392fc9709a3 423 #define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */
AnnaBridge 189:f392fc9709a3 424 #define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */
AnnaBridge 189:f392fc9709a3 425 #define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */
AnnaBridge 189:f392fc9709a3 426 #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */
AnnaBridge 189:f392fc9709a3 427 #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */
AnnaBridge 189:f392fc9709a3 428 #define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */
AnnaBridge 189:f392fc9709a3 429
AnnaBridge 189:f392fc9709a3 430 /* ENET_DMA_TPEN */
AnnaBridge 189:f392fc9709a3 431 #define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */
AnnaBridge 189:f392fc9709a3 432
AnnaBridge 189:f392fc9709a3 433 /* ENET_DMA_RPEN */
AnnaBridge 189:f392fc9709a3 434 #define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */
AnnaBridge 189:f392fc9709a3 435
AnnaBridge 189:f392fc9709a3 436 /* ENET_DMA_RDTADDR */
AnnaBridge 189:f392fc9709a3 437 #define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */
AnnaBridge 189:f392fc9709a3 438
AnnaBridge 189:f392fc9709a3 439 /* ENET_DMA_TDTADDR */
AnnaBridge 189:f392fc9709a3 440 #define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */
AnnaBridge 189:f392fc9709a3 441
AnnaBridge 189:f392fc9709a3 442 /* ENET_DMA_STAT */
AnnaBridge 189:f392fc9709a3 443 #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */
AnnaBridge 189:f392fc9709a3 444 #define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */
AnnaBridge 189:f392fc9709a3 445 #define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */
AnnaBridge 189:f392fc9709a3 446 #define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */
AnnaBridge 189:f392fc9709a3 447 #define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */
AnnaBridge 189:f392fc9709a3 448 #define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */
AnnaBridge 189:f392fc9709a3 449 #define ENET_DMA_STAT_RS BIT(6) /*!< receive status */
AnnaBridge 189:f392fc9709a3 450 #define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */
AnnaBridge 189:f392fc9709a3 451 #define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */
AnnaBridge 189:f392fc9709a3 452 #define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */
AnnaBridge 189:f392fc9709a3 453 #define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */
AnnaBridge 189:f392fc9709a3 454 #define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */
AnnaBridge 189:f392fc9709a3 455 #define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */
AnnaBridge 189:f392fc9709a3 456 #define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */
AnnaBridge 189:f392fc9709a3 457 #define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */
AnnaBridge 189:f392fc9709a3 458 #define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */
AnnaBridge 189:f392fc9709a3 459 #define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */
AnnaBridge 189:f392fc9709a3 460 #define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */
AnnaBridge 189:f392fc9709a3 461 #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */
AnnaBridge 189:f392fc9709a3 462 #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */
AnnaBridge 189:f392fc9709a3 463 #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */
AnnaBridge 189:f392fc9709a3 464
AnnaBridge 189:f392fc9709a3 465 /* ENET_DMA_CTL */
AnnaBridge 189:f392fc9709a3 466 #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */
AnnaBridge 189:f392fc9709a3 467 #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */
AnnaBridge 189:f392fc9709a3 468 #define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */
AnnaBridge 189:f392fc9709a3 469 #define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */
AnnaBridge 189:f392fc9709a3 470 #define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */
AnnaBridge 189:f392fc9709a3 471 #define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */
AnnaBridge 189:f392fc9709a3 472 #define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */
AnnaBridge 189:f392fc9709a3 473 #define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */
AnnaBridge 189:f392fc9709a3 474 #define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */
AnnaBridge 189:f392fc9709a3 475 #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */
AnnaBridge 189:f392fc9709a3 476 #define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */
AnnaBridge 189:f392fc9709a3 477 #define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */
AnnaBridge 189:f392fc9709a3 478
AnnaBridge 189:f392fc9709a3 479 /* ENET_DMA_INTEN */
AnnaBridge 189:f392fc9709a3 480 #define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */
AnnaBridge 189:f392fc9709a3 481 #define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */
AnnaBridge 189:f392fc9709a3 482 #define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */
AnnaBridge 189:f392fc9709a3 483 #define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */
AnnaBridge 189:f392fc9709a3 484 #define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */
AnnaBridge 189:f392fc9709a3 485 #define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */
AnnaBridge 189:f392fc9709a3 486 #define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */
AnnaBridge 189:f392fc9709a3 487 #define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */
AnnaBridge 189:f392fc9709a3 488 #define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */
AnnaBridge 189:f392fc9709a3 489 #define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */
AnnaBridge 189:f392fc9709a3 490 #define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */
AnnaBridge 189:f392fc9709a3 491 #define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */
AnnaBridge 189:f392fc9709a3 492 #define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */
AnnaBridge 189:f392fc9709a3 493 #define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */
AnnaBridge 189:f392fc9709a3 494 #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */
AnnaBridge 189:f392fc9709a3 495
AnnaBridge 189:f392fc9709a3 496 /* ENET_DMA_MFBOCNT */
AnnaBridge 189:f392fc9709a3 497 #define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */
AnnaBridge 189:f392fc9709a3 498 #define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */
AnnaBridge 189:f392fc9709a3 499
AnnaBridge 189:f392fc9709a3 500 /* ENET_DMA_RSWDC */
AnnaBridge 189:f392fc9709a3 501 #define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */
AnnaBridge 189:f392fc9709a3 502
AnnaBridge 189:f392fc9709a3 503 /* ENET_DMA_CTDADDR */
AnnaBridge 189:f392fc9709a3 504 #define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */
AnnaBridge 189:f392fc9709a3 505
AnnaBridge 189:f392fc9709a3 506 /* ENET_DMA_CRDADDR */
AnnaBridge 189:f392fc9709a3 507 #define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */
AnnaBridge 189:f392fc9709a3 508
AnnaBridge 189:f392fc9709a3 509 /* ENET_DMA_CTBADDR */
AnnaBridge 189:f392fc9709a3 510 #define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */
AnnaBridge 189:f392fc9709a3 511
AnnaBridge 189:f392fc9709a3 512 /* ENET_DMA_CRBADDR */
AnnaBridge 189:f392fc9709a3 513 #define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */
AnnaBridge 189:f392fc9709a3 514
AnnaBridge 189:f392fc9709a3 515 /* ENET DMA Tx descriptor TDES0 */
AnnaBridge 189:f392fc9709a3 516 #define ENET_TDES0_DB BIT(0) /*!< deferred */
AnnaBridge 189:f392fc9709a3 517 #define ENET_TDES0_UFE BIT(1) /*!< underflow error */
AnnaBridge 189:f392fc9709a3 518 #define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */
AnnaBridge 189:f392fc9709a3 519 #define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */
AnnaBridge 189:f392fc9709a3 520 #define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */
AnnaBridge 189:f392fc9709a3 521 #define ENET_TDES0_ECO BIT(8) /*!< excessive collision */
AnnaBridge 189:f392fc9709a3 522 #define ENET_TDES0_LCO BIT(9) /*!< late collision */
AnnaBridge 189:f392fc9709a3 523 #define ENET_TDES0_NCA BIT(10) /*!< no carrier */
AnnaBridge 189:f392fc9709a3 524 #define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */
AnnaBridge 189:f392fc9709a3 525 #define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */
AnnaBridge 189:f392fc9709a3 526 #define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */
AnnaBridge 189:f392fc9709a3 527 #define ENET_TDES0_JT BIT(14) /*!< jabber timeout */
AnnaBridge 189:f392fc9709a3 528 #define ENET_TDES0_ES BIT(15) /*!< error summary */
AnnaBridge 189:f392fc9709a3 529 #define ENET_TDES0_IPHE BIT(16) /*!< IP header error */
AnnaBridge 189:f392fc9709a3 530 #define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */
AnnaBridge 189:f392fc9709a3 531 #define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */
AnnaBridge 189:f392fc9709a3 532 #define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/
AnnaBridge 189:f392fc9709a3 533 #define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */
AnnaBridge 189:f392fc9709a3 534 #define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */
AnnaBridge 189:f392fc9709a3 535 #define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */
AnnaBridge 189:f392fc9709a3 536 #define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */
AnnaBridge 189:f392fc9709a3 537 #define ENET_TDES0_FSG BIT(28) /*!< first segment */
AnnaBridge 189:f392fc9709a3 538 #define ENET_TDES0_LSG BIT(29) /*!< last segment */
AnnaBridge 189:f392fc9709a3 539 #define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */
AnnaBridge 189:f392fc9709a3 540 #define ENET_TDES0_DAV BIT(31) /*!< DAV bit */
AnnaBridge 189:f392fc9709a3 541
AnnaBridge 189:f392fc9709a3 542 /* ENET DMA Tx descriptor TDES1 */
AnnaBridge 189:f392fc9709a3 543 #define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */
AnnaBridge 189:f392fc9709a3 544 #define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */
AnnaBridge 189:f392fc9709a3 545
AnnaBridge 189:f392fc9709a3 546 /* ENET DMA Tx descriptor TDES2 */
AnnaBridge 189:f392fc9709a3 547 #define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */
AnnaBridge 189:f392fc9709a3 548
AnnaBridge 189:f392fc9709a3 549 /* ENET DMA Tx descriptor TDES3 */
AnnaBridge 189:f392fc9709a3 550 #define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */
AnnaBridge 189:f392fc9709a3 551
AnnaBridge 189:f392fc9709a3 552 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
AnnaBridge 189:f392fc9709a3 553 /* ENET DMA Tx descriptor TDES6 */
AnnaBridge 189:f392fc9709a3 554 #define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */
AnnaBridge 189:f392fc9709a3 555
AnnaBridge 189:f392fc9709a3 556 /* ENET DMA Tx descriptor TDES7 */
AnnaBridge 189:f392fc9709a3 557 #define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */
AnnaBridge 189:f392fc9709a3 558 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */
AnnaBridge 189:f392fc9709a3 559
AnnaBridge 189:f392fc9709a3 560 /* ENET DMA Rx descriptor RDES0 */
AnnaBridge 189:f392fc9709a3 561 #define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */
AnnaBridge 189:f392fc9709a3 562 #define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */
AnnaBridge 189:f392fc9709a3 563 #define ENET_RDES0_CERR BIT(1) /*!< CRC error */
AnnaBridge 189:f392fc9709a3 564 #define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */
AnnaBridge 189:f392fc9709a3 565 #define ENET_RDES0_RERR BIT(3) /*!< receive error */
AnnaBridge 189:f392fc9709a3 566 #define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */
AnnaBridge 189:f392fc9709a3 567 #define ENET_RDES0_FRMT BIT(5) /*!< frame type */
AnnaBridge 189:f392fc9709a3 568 #define ENET_RDES0_LCO BIT(6) /*!< late collision */
AnnaBridge 189:f392fc9709a3 569 #define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */
AnnaBridge 189:f392fc9709a3 570 #define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */
AnnaBridge 189:f392fc9709a3 571 #define ENET_RDES0_LDES BIT(8) /*!< last descriptor */
AnnaBridge 189:f392fc9709a3 572 #define ENET_RDES0_FDES BIT(9) /*!< first descriptor */
AnnaBridge 189:f392fc9709a3 573 #define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */
AnnaBridge 189:f392fc9709a3 574 #define ENET_RDES0_OERR BIT(11) /*!< overflow Error */
AnnaBridge 189:f392fc9709a3 575 #define ENET_RDES0_LERR BIT(12) /*!< length error */
AnnaBridge 189:f392fc9709a3 576 #define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */
AnnaBridge 189:f392fc9709a3 577 #define ENET_RDES0_DERR BIT(14) /*!< descriptor error */
AnnaBridge 189:f392fc9709a3 578 #define ENET_RDES0_ERRS BIT(15) /*!< error summary */
AnnaBridge 189:f392fc9709a3 579 #define ENET_RDES0_FRML BITS(16,29) /*!< frame length */
AnnaBridge 189:f392fc9709a3 580 #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */
AnnaBridge 189:f392fc9709a3 581 #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */
AnnaBridge 189:f392fc9709a3 582
AnnaBridge 189:f392fc9709a3 583 /* ENET DMA Rx descriptor RDES1 */
AnnaBridge 189:f392fc9709a3 584 #define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */
AnnaBridge 189:f392fc9709a3 585 #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */
AnnaBridge 189:f392fc9709a3 586 #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/
AnnaBridge 189:f392fc9709a3 587 #define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */
AnnaBridge 189:f392fc9709a3 588 #define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */
AnnaBridge 189:f392fc9709a3 589
AnnaBridge 189:f392fc9709a3 590 /* ENET DMA Rx descriptor RDES2 */
AnnaBridge 189:f392fc9709a3 591 #define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */
AnnaBridge 189:f392fc9709a3 592
AnnaBridge 189:f392fc9709a3 593 /* ENET DMA Rx descriptor RDES3 */
AnnaBridge 189:f392fc9709a3 594 #define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */
AnnaBridge 189:f392fc9709a3 595
AnnaBridge 189:f392fc9709a3 596 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
AnnaBridge 189:f392fc9709a3 597 /* ENET DMA Rx descriptor RDES4 */
AnnaBridge 189:f392fc9709a3 598 #define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */
AnnaBridge 189:f392fc9709a3 599 #define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */
AnnaBridge 189:f392fc9709a3 600 #define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */
AnnaBridge 189:f392fc9709a3 601 #define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */
AnnaBridge 189:f392fc9709a3 602 #define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */
AnnaBridge 189:f392fc9709a3 603 #define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */
AnnaBridge 189:f392fc9709a3 604 #define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */
AnnaBridge 189:f392fc9709a3 605 #define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */
AnnaBridge 189:f392fc9709a3 606 #define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */
AnnaBridge 189:f392fc9709a3 607
AnnaBridge 189:f392fc9709a3 608 /* ENET DMA Rx descriptor RDES6 */
AnnaBridge 189:f392fc9709a3 609 #define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */
AnnaBridge 189:f392fc9709a3 610
AnnaBridge 189:f392fc9709a3 611 /* ENET DMA Rx descriptor RDES7 */
AnnaBridge 189:f392fc9709a3 612 #define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */
AnnaBridge 189:f392fc9709a3 613 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */
AnnaBridge 189:f392fc9709a3 614
AnnaBridge 189:f392fc9709a3 615 /* constants definitions */
AnnaBridge 189:f392fc9709a3 616 /* define bit position and its register index offset */
AnnaBridge 189:f392fc9709a3 617 #define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
AnnaBridge 189:f392fc9709a3 618 #define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6)))
AnnaBridge 189:f392fc9709a3 619 #define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
AnnaBridge 189:f392fc9709a3 620
AnnaBridge 189:f392fc9709a3 621 /* ENET clock range judgement */
AnnaBridge 189:f392fc9709a3 622 #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m)))
AnnaBridge 189:f392fc9709a3 623
AnnaBridge 189:f392fc9709a3 624 /* define MAC address configuration and reference address */
AnnaBridge 189:f392fc9709a3 625 #define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4])
AnnaBridge 189:f392fc9709a3 626 #define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0])
AnnaBridge 189:f392fc9709a3 627 #define ENET_ADDRH_BASE ((ENET) + 0x40U)
AnnaBridge 189:f392fc9709a3 628 #define ENET_ADDRL_BASE ((ENET) + 0x44U)
AnnaBridge 189:f392fc9709a3 629 #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU))
AnnaBridge 189:f392fc9709a3 630
AnnaBridge 189:f392fc9709a3 631 /* register offset */
AnnaBridge 189:f392fc9709a3 632 #define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */
AnnaBridge 189:f392fc9709a3 633 #define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */
AnnaBridge 189:f392fc9709a3 634 #define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */
AnnaBridge 189:f392fc9709a3 635 #define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */
AnnaBridge 189:f392fc9709a3 636
AnnaBridge 189:f392fc9709a3 637 #define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */
AnnaBridge 189:f392fc9709a3 638 #define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */
AnnaBridge 189:f392fc9709a3 639 #define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */
AnnaBridge 189:f392fc9709a3 640 #define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */
AnnaBridge 189:f392fc9709a3 641 #define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */
AnnaBridge 189:f392fc9709a3 642 #define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */
AnnaBridge 189:f392fc9709a3 643 #define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */
AnnaBridge 189:f392fc9709a3 644 #define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */
AnnaBridge 189:f392fc9709a3 645 #define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */
AnnaBridge 189:f392fc9709a3 646 #define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */
AnnaBridge 189:f392fc9709a3 647
AnnaBridge 189:f392fc9709a3 648 #define PTP_TSF_REG_OFFSET 0x0728U /*!< PTP time stamp flag register offset */
AnnaBridge 189:f392fc9709a3 649
AnnaBridge 189:f392fc9709a3 650 #define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */
AnnaBridge 189:f392fc9709a3 651 #define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */
AnnaBridge 189:f392fc9709a3 652 #define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */
AnnaBridge 189:f392fc9709a3 653 #define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */
AnnaBridge 189:f392fc9709a3 654 #define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */
AnnaBridge 189:f392fc9709a3 655 #define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */
AnnaBridge 189:f392fc9709a3 656 #define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */
AnnaBridge 189:f392fc9709a3 657 #define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */
AnnaBridge 189:f392fc9709a3 658
AnnaBridge 189:f392fc9709a3 659 /* ENET status flag get */
AnnaBridge 189:f392fc9709a3 660 typedef enum {
AnnaBridge 189:f392fc9709a3 661 /* ENET_MAC_WUM register */
AnnaBridge 189:f392fc9709a3 662 ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */
AnnaBridge 189:f392fc9709a3 663 ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */
AnnaBridge 189:f392fc9709a3 664 /* ENET_MAC_FCTL register */
AnnaBridge 189:f392fc9709a3 665 ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */
AnnaBridge 189:f392fc9709a3 666 /* ENET_MAC_INTF register */
AnnaBridge 189:f392fc9709a3 667 ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */
AnnaBridge 189:f392fc9709a3 668 ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */
AnnaBridge 189:f392fc9709a3 669 ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */
AnnaBridge 189:f392fc9709a3 670 ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */
AnnaBridge 189:f392fc9709a3 671 ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */
AnnaBridge 189:f392fc9709a3 672 /* ENET_PTP_TSF register */
AnnaBridge 189:f392fc9709a3 673 ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */
AnnaBridge 189:f392fc9709a3 674 ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */
AnnaBridge 189:f392fc9709a3 675 /* ENET_MSC_RINTF register */
AnnaBridge 189:f392fc9709a3 676 ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */
AnnaBridge 189:f392fc9709a3 677 ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */
AnnaBridge 189:f392fc9709a3 678 ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */
AnnaBridge 189:f392fc9709a3 679 /* ENET_MSC_TINTF register */
AnnaBridge 189:f392fc9709a3 680 ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */
AnnaBridge 189:f392fc9709a3 681 ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */
AnnaBridge 189:f392fc9709a3 682 ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */
AnnaBridge 189:f392fc9709a3 683 /* ENET_DMA_STAT register */
AnnaBridge 189:f392fc9709a3 684 ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
AnnaBridge 189:f392fc9709a3 685 ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
AnnaBridge 189:f392fc9709a3 686 ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 687 ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
AnnaBridge 189:f392fc9709a3 688 ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
AnnaBridge 189:f392fc9709a3 689 ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
AnnaBridge 189:f392fc9709a3 690 ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
AnnaBridge 189:f392fc9709a3 691 ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 692 ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
AnnaBridge 189:f392fc9709a3 693 ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
AnnaBridge 189:f392fc9709a3 694 ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
AnnaBridge 189:f392fc9709a3 695 ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
AnnaBridge 189:f392fc9709a3 696 ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
AnnaBridge 189:f392fc9709a3 697 ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 698 ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 699 ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */
AnnaBridge 189:f392fc9709a3 700 ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */
AnnaBridge 189:f392fc9709a3 701 ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */
AnnaBridge 189:f392fc9709a3 702 ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */
AnnaBridge 189:f392fc9709a3 703 ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */
AnnaBridge 189:f392fc9709a3 704 ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */
AnnaBridge 189:f392fc9709a3 705 } enet_flag_enum;
AnnaBridge 189:f392fc9709a3 706
AnnaBridge 189:f392fc9709a3 707 /* ENET stutus flag clear */
AnnaBridge 189:f392fc9709a3 708 typedef enum {
AnnaBridge 189:f392fc9709a3 709 /* ENET_DMA_STAT register */
AnnaBridge 189:f392fc9709a3 710 ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
AnnaBridge 189:f392fc9709a3 711 ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
AnnaBridge 189:f392fc9709a3 712 ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 713 ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
AnnaBridge 189:f392fc9709a3 714 ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
AnnaBridge 189:f392fc9709a3 715 ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
AnnaBridge 189:f392fc9709a3 716 ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
AnnaBridge 189:f392fc9709a3 717 ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 718 ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
AnnaBridge 189:f392fc9709a3 719 ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
AnnaBridge 189:f392fc9709a3 720 ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
AnnaBridge 189:f392fc9709a3 721 ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
AnnaBridge 189:f392fc9709a3 722 ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
AnnaBridge 189:f392fc9709a3 723 ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 724 ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 725 } enet_flag_clear_enum;
AnnaBridge 189:f392fc9709a3 726
AnnaBridge 189:f392fc9709a3 727 /* ENET interrupt enable/disable */
AnnaBridge 189:f392fc9709a3 728 typedef enum {
AnnaBridge 189:f392fc9709a3 729 /* ENET_MAC_INTMSK register */
AnnaBridge 189:f392fc9709a3 730 ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */
AnnaBridge 189:f392fc9709a3 731 ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */
AnnaBridge 189:f392fc9709a3 732 /* ENET_MSC_RINTMSK register */
AnnaBridge 189:f392fc9709a3 733 ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */
AnnaBridge 189:f392fc9709a3 734 ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */
AnnaBridge 189:f392fc9709a3 735 ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */
AnnaBridge 189:f392fc9709a3 736 /* ENET_MSC_TINTMSK register */
AnnaBridge 189:f392fc9709a3 737 ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */
AnnaBridge 189:f392fc9709a3 738 ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */
AnnaBridge 189:f392fc9709a3 739 ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */
AnnaBridge 189:f392fc9709a3 740 /* ENET_DMA_INTEN register */
AnnaBridge 189:f392fc9709a3 741 ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */
AnnaBridge 189:f392fc9709a3 742 ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */
AnnaBridge 189:f392fc9709a3 743 ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */
AnnaBridge 189:f392fc9709a3 744 ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */
AnnaBridge 189:f392fc9709a3 745 ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */
AnnaBridge 189:f392fc9709a3 746 ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */
AnnaBridge 189:f392fc9709a3 747 ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */
AnnaBridge 189:f392fc9709a3 748 ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */
AnnaBridge 189:f392fc9709a3 749 ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */
AnnaBridge 189:f392fc9709a3 750 ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */
AnnaBridge 189:f392fc9709a3 751 ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */
AnnaBridge 189:f392fc9709a3 752 ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */
AnnaBridge 189:f392fc9709a3 753 ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */
AnnaBridge 189:f392fc9709a3 754 ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */
AnnaBridge 189:f392fc9709a3 755 ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */
AnnaBridge 189:f392fc9709a3 756 } enet_int_enum;
AnnaBridge 189:f392fc9709a3 757
AnnaBridge 189:f392fc9709a3 758 /* ENET interrupt flag get */
AnnaBridge 189:f392fc9709a3 759 typedef enum {
AnnaBridge 189:f392fc9709a3 760 /* ENET_MAC_INTF register */
AnnaBridge 189:f392fc9709a3 761 ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */
AnnaBridge 189:f392fc9709a3 762 ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */
AnnaBridge 189:f392fc9709a3 763 ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */
AnnaBridge 189:f392fc9709a3 764 ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */
AnnaBridge 189:f392fc9709a3 765 ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */
AnnaBridge 189:f392fc9709a3 766 /* ENET_MSC_RINTF register */
AnnaBridge 189:f392fc9709a3 767 ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */
AnnaBridge 189:f392fc9709a3 768 ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */
AnnaBridge 189:f392fc9709a3 769 ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */
AnnaBridge 189:f392fc9709a3 770 /* ENET_MSC_TINTF register */
AnnaBridge 189:f392fc9709a3 771 ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */
AnnaBridge 189:f392fc9709a3 772 ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */
AnnaBridge 189:f392fc9709a3 773 ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */
AnnaBridge 189:f392fc9709a3 774 /* ENET_DMA_STAT register */
AnnaBridge 189:f392fc9709a3 775 ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
AnnaBridge 189:f392fc9709a3 776 ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
AnnaBridge 189:f392fc9709a3 777 ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 778 ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
AnnaBridge 189:f392fc9709a3 779 ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
AnnaBridge 189:f392fc9709a3 780 ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
AnnaBridge 189:f392fc9709a3 781 ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
AnnaBridge 189:f392fc9709a3 782 ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 783 ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
AnnaBridge 189:f392fc9709a3 784 ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
AnnaBridge 189:f392fc9709a3 785 ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
AnnaBridge 189:f392fc9709a3 786 ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
AnnaBridge 189:f392fc9709a3 787 ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
AnnaBridge 189:f392fc9709a3 788 ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 789 ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 790 ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */
AnnaBridge 189:f392fc9709a3 791 ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */
AnnaBridge 189:f392fc9709a3 792 ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */
AnnaBridge 189:f392fc9709a3 793 } enet_int_flag_enum;
AnnaBridge 189:f392fc9709a3 794
AnnaBridge 189:f392fc9709a3 795 /* ENET interrupt flag clear */
AnnaBridge 189:f392fc9709a3 796 typedef enum {
AnnaBridge 189:f392fc9709a3 797 /* ENET_DMA_STAT register */
AnnaBridge 189:f392fc9709a3 798 ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
AnnaBridge 189:f392fc9709a3 799 ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
AnnaBridge 189:f392fc9709a3 800 ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 801 ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
AnnaBridge 189:f392fc9709a3 802 ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
AnnaBridge 189:f392fc9709a3 803 ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
AnnaBridge 189:f392fc9709a3 804 ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
AnnaBridge 189:f392fc9709a3 805 ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
AnnaBridge 189:f392fc9709a3 806 ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
AnnaBridge 189:f392fc9709a3 807 ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
AnnaBridge 189:f392fc9709a3 808 ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
AnnaBridge 189:f392fc9709a3 809 ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
AnnaBridge 189:f392fc9709a3 810 ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
AnnaBridge 189:f392fc9709a3 811 ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 812 ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
AnnaBridge 189:f392fc9709a3 813 } enet_int_flag_clear_enum;
AnnaBridge 189:f392fc9709a3 814
AnnaBridge 189:f392fc9709a3 815 /* current RX/TX descriptor/buffer/descriptor table address get */
AnnaBridge 189:f392fc9709a3 816 typedef enum {
AnnaBridge 189:f392fc9709a3 817 ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */
AnnaBridge 189:f392fc9709a3 818 ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */
AnnaBridge 189:f392fc9709a3 819 ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */
AnnaBridge 189:f392fc9709a3 820 ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */
AnnaBridge 189:f392fc9709a3 821 ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */
AnnaBridge 189:f392fc9709a3 822 ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */
AnnaBridge 189:f392fc9709a3 823 } enet_desc_reg_enum;
AnnaBridge 189:f392fc9709a3 824
AnnaBridge 189:f392fc9709a3 825 /* MAC statistics counter get */
AnnaBridge 189:f392fc9709a3 826 typedef enum {
AnnaBridge 189:f392fc9709a3 827 ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */
AnnaBridge 189:f392fc9709a3 828 ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */
AnnaBridge 189:f392fc9709a3 829 ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */
AnnaBridge 189:f392fc9709a3 830 ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */
AnnaBridge 189:f392fc9709a3 831 ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */
AnnaBridge 189:f392fc9709a3 832 ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */
AnnaBridge 189:f392fc9709a3 833 } enet_msc_counter_enum;
AnnaBridge 189:f392fc9709a3 834
AnnaBridge 189:f392fc9709a3 835 /* function option, used for ENET initialization */
AnnaBridge 189:f392fc9709a3 836 typedef enum {
AnnaBridge 189:f392fc9709a3 837 FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */
AnnaBridge 189:f392fc9709a3 838 DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */
AnnaBridge 189:f392fc9709a3 839 DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */
AnnaBridge 189:f392fc9709a3 840 DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */
AnnaBridge 189:f392fc9709a3 841 STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */
AnnaBridge 189:f392fc9709a3 842 DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */
AnnaBridge 189:f392fc9709a3 843 VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */
AnnaBridge 189:f392fc9709a3 844 FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */
AnnaBridge 189:f392fc9709a3 845 HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */
AnnaBridge 189:f392fc9709a3 846 HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */
AnnaBridge 189:f392fc9709a3 847 FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */
AnnaBridge 189:f392fc9709a3 848 HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */
AnnaBridge 189:f392fc9709a3 849 TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */
AnnaBridge 189:f392fc9709a3 850 INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */
AnnaBridge 189:f392fc9709a3 851 } enet_option_enum;
AnnaBridge 189:f392fc9709a3 852
AnnaBridge 189:f392fc9709a3 853 /* phy mode and mac loopback configurations */
AnnaBridge 189:f392fc9709a3 854 typedef enum {
AnnaBridge 189:f392fc9709a3 855 ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */
AnnaBridge 189:f392fc9709a3 856 ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */
AnnaBridge 189:f392fc9709a3 857 ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD, /*!< 100Mbit/s, half-duplex */
AnnaBridge 189:f392fc9709a3 858 ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */
AnnaBridge 189:f392fc9709a3 859 ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */
AnnaBridge 189:f392fc9709a3 860 ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */
AnnaBridge 189:f392fc9709a3 861 } enet_mediamode_enum;
AnnaBridge 189:f392fc9709a3 862
AnnaBridge 189:f392fc9709a3 863 /* IP frame checksum function */
AnnaBridge 189:f392fc9709a3 864 typedef enum {
AnnaBridge 189:f392fc9709a3 865 ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */
AnnaBridge 189:f392fc9709a3 866 ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */
AnnaBridge 189:f392fc9709a3 867 ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO | ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame
AnnaBridge 189:f392fc9709a3 868 with only payload error but no other errors will not be dropped */
AnnaBridge 189:f392fc9709a3 869 } enet_chksumconf_enum;
AnnaBridge 189:f392fc9709a3 870
AnnaBridge 189:f392fc9709a3 871 /* received frame filter function */
AnnaBridge 189:f392fc9709a3 872 typedef enum {
AnnaBridge 189:f392fc9709a3 873 ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */
AnnaBridge 189:f392fc9709a3 874 ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */
AnnaBridge 189:f392fc9709a3 875 ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */
AnnaBridge 189:f392fc9709a3 876 ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */
AnnaBridge 189:f392fc9709a3 877 } enet_frmrecept_enum;
AnnaBridge 189:f392fc9709a3 878
AnnaBridge 189:f392fc9709a3 879 /* register group value get */
AnnaBridge 189:f392fc9709a3 880 typedef enum {
AnnaBridge 189:f392fc9709a3 881 ALL_MAC_REG = 0, /*!< MAC register group */
AnnaBridge 189:f392fc9709a3 882 ALL_MSC_REG = 22, /*!< MSC register group */
AnnaBridge 189:f392fc9709a3 883 ALL_PTP_REG = 33, /*!< PTP register group */
AnnaBridge 189:f392fc9709a3 884 ALL_DMA_REG = 44, /*!< DMA register group */
AnnaBridge 189:f392fc9709a3 885 } enet_registers_type_enum;
AnnaBridge 189:f392fc9709a3 886
AnnaBridge 189:f392fc9709a3 887 /* dma direction select */
AnnaBridge 189:f392fc9709a3 888 typedef enum {
AnnaBridge 189:f392fc9709a3 889 ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */
AnnaBridge 189:f392fc9709a3 890 ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */
AnnaBridge 189:f392fc9709a3 891 } enet_dmadirection_enum;
AnnaBridge 189:f392fc9709a3 892
AnnaBridge 189:f392fc9709a3 893 /* PHY operation direction select */
AnnaBridge 189:f392fc9709a3 894 typedef enum {
AnnaBridge 189:f392fc9709a3 895 ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */
AnnaBridge 189:f392fc9709a3 896 ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */
AnnaBridge 189:f392fc9709a3 897 } enet_phydirection_enum;
AnnaBridge 189:f392fc9709a3 898
AnnaBridge 189:f392fc9709a3 899 /* register operation direction select */
AnnaBridge 189:f392fc9709a3 900 typedef enum {
AnnaBridge 189:f392fc9709a3 901 ENET_REG_READ, /*!< read register */
AnnaBridge 189:f392fc9709a3 902 ENET_REG_WRITE /*!< write register */
AnnaBridge 189:f392fc9709a3 903 } enet_regdirection_enum;
AnnaBridge 189:f392fc9709a3 904
AnnaBridge 189:f392fc9709a3 905 /* ENET MAC addresses */
AnnaBridge 189:f392fc9709a3 906 typedef enum {
AnnaBridge 189:f392fc9709a3 907 ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */
AnnaBridge 189:f392fc9709a3 908 ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */
AnnaBridge 189:f392fc9709a3 909 ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */
AnnaBridge 189:f392fc9709a3 910 ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */
AnnaBridge 189:f392fc9709a3 911 } enet_macaddress_enum;
AnnaBridge 189:f392fc9709a3 912
AnnaBridge 189:f392fc9709a3 913 /* descriptor information */
AnnaBridge 189:f392fc9709a3 914 typedef enum {
AnnaBridge 189:f392fc9709a3 915 TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */
AnnaBridge 189:f392fc9709a3 916 TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */
AnnaBridge 189:f392fc9709a3 917 RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */
AnnaBridge 189:f392fc9709a3 918 RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */
AnnaBridge 189:f392fc9709a3 919 RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */
AnnaBridge 189:f392fc9709a3 920 RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */
AnnaBridge 189:f392fc9709a3 921 } enet_descstate_enum;
AnnaBridge 189:f392fc9709a3 922
AnnaBridge 189:f392fc9709a3 923 /* MSC counters preset mode */
AnnaBridge 189:f392fc9709a3 924 typedef enum {
AnnaBridge 189:f392fc9709a3 925 ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */
AnnaBridge 189:f392fc9709a3 926 ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */
AnnaBridge 189:f392fc9709a3 927 ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */
AnnaBridge 189:f392fc9709a3 928 } enet_msc_preset_enum;
AnnaBridge 189:f392fc9709a3 929
AnnaBridge 189:f392fc9709a3 930 /* structure for initialization of the ENET */
AnnaBridge 189:f392fc9709a3 931 typedef struct {
AnnaBridge 189:f392fc9709a3 932 uint32_t option_enable; /*!< select which function to configure */
AnnaBridge 189:f392fc9709a3 933 uint32_t forward_frame; /*!< frame forward related parameters */
AnnaBridge 189:f392fc9709a3 934 uint32_t dmabus_mode; /*!< DMA bus mode related parameters */
AnnaBridge 189:f392fc9709a3 935 uint32_t dma_maxburst; /*!< DMA max burst related parameters */
AnnaBridge 189:f392fc9709a3 936 uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */
AnnaBridge 189:f392fc9709a3 937 uint32_t store_forward_mode; /*!< store forward mode related parameters */
AnnaBridge 189:f392fc9709a3 938 uint32_t dma_function; /*!< DMA control related parameters */
AnnaBridge 189:f392fc9709a3 939 uint32_t vlan_config; /*!< VLAN tag related parameters */
AnnaBridge 189:f392fc9709a3 940 uint32_t flow_control; /*!< flow control related parameters */
AnnaBridge 189:f392fc9709a3 941 uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */
AnnaBridge 189:f392fc9709a3 942 uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */
AnnaBridge 189:f392fc9709a3 943 uint32_t framesfilter_mode; /*!< frame filter control related parameters */
AnnaBridge 189:f392fc9709a3 944 uint32_t halfduplex_param; /*!< halfduplex related parameters */
AnnaBridge 189:f392fc9709a3 945 uint32_t timer_config; /*!< frame timer related parameters */
AnnaBridge 189:f392fc9709a3 946 uint32_t interframegap; /*!< inter frame gap related parameters */
AnnaBridge 189:f392fc9709a3 947 } enet_initpara_struct;
AnnaBridge 189:f392fc9709a3 948
AnnaBridge 189:f392fc9709a3 949 /* structure for ENET DMA desciptors */
AnnaBridge 189:f392fc9709a3 950 typedef struct {
AnnaBridge 189:f392fc9709a3 951 uint32_t status; /*!< status */
AnnaBridge 189:f392fc9709a3 952 uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */
AnnaBridge 189:f392fc9709a3 953 uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */
AnnaBridge 189:f392fc9709a3 954 uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */
AnnaBridge 189:f392fc9709a3 955
AnnaBridge 189:f392fc9709a3 956 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
AnnaBridge 189:f392fc9709a3 957 uint32_t extended_status; /*!< extended status */
AnnaBridge 189:f392fc9709a3 958 uint32_t reserved; /*!< reserved */
AnnaBridge 189:f392fc9709a3 959 uint32_t timestamp_low; /*!< timestamp low */
AnnaBridge 189:f392fc9709a3 960 uint32_t timestamp_high; /*!< timestamp high */
AnnaBridge 189:f392fc9709a3 961 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */
AnnaBridge 189:f392fc9709a3 962
AnnaBridge 189:f392fc9709a3 963 } enet_descriptors_struct;
AnnaBridge 189:f392fc9709a3 964
AnnaBridge 189:f392fc9709a3 965 /* structure of PTP system time */
AnnaBridge 189:f392fc9709a3 966 typedef struct {
AnnaBridge 189:f392fc9709a3 967 uint32_t second; /*!< second of system time */
AnnaBridge 189:f392fc9709a3 968 uint32_t nanosecond; /*!< nanosecond of system time */
AnnaBridge 189:f392fc9709a3 969 uint32_t sign; /*!< sign of system time */
AnnaBridge 189:f392fc9709a3 970 } enet_ptp_systime_struct;
AnnaBridge 189:f392fc9709a3 971
AnnaBridge 189:f392fc9709a3 972 /* mac_cfg register value */
AnnaBridge 189:f392fc9709a3 973 #define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */
AnnaBridge 189:f392fc9709a3 974 #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */
AnnaBridge 189:f392fc9709a3 975 #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */
AnnaBridge 189:f392fc9709a3 976 #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */
AnnaBridge 189:f392fc9709a3 977 #define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */
AnnaBridge 189:f392fc9709a3 978
AnnaBridge 189:f392fc9709a3 979 #define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */
AnnaBridge 189:f392fc9709a3 980 #define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */
AnnaBridge 189:f392fc9709a3 981 #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */
AnnaBridge 189:f392fc9709a3 982 #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */
AnnaBridge 189:f392fc9709a3 983 #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */
AnnaBridge 189:f392fc9709a3 984 #define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */
AnnaBridge 189:f392fc9709a3 985 #define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */
AnnaBridge 189:f392fc9709a3 986 #define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */
AnnaBridge 189:f392fc9709a3 987 #define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */
AnnaBridge 189:f392fc9709a3 988
AnnaBridge 189:f392fc9709a3 989 #define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */
AnnaBridge 189:f392fc9709a3 990 #define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */
AnnaBridge 189:f392fc9709a3 991 #define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */
AnnaBridge 189:f392fc9709a3 992
AnnaBridge 189:f392fc9709a3 993 #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */
AnnaBridge 189:f392fc9709a3 994 #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */
AnnaBridge 189:f392fc9709a3 995
AnnaBridge 189:f392fc9709a3 996 #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */
AnnaBridge 189:f392fc9709a3 997 #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */
AnnaBridge 189:f392fc9709a3 998
AnnaBridge 189:f392fc9709a3 999 #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */
AnnaBridge 189:f392fc9709a3 1000 #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */
AnnaBridge 189:f392fc9709a3 1001
AnnaBridge 189:f392fc9709a3 1002 #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */
AnnaBridge 189:f392fc9709a3 1003 #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */
AnnaBridge 189:f392fc9709a3 1004
AnnaBridge 189:f392fc9709a3 1005 #define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */
AnnaBridge 189:f392fc9709a3 1006 #define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */
AnnaBridge 189:f392fc9709a3 1007
AnnaBridge 189:f392fc9709a3 1008 #define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */
AnnaBridge 189:f392fc9709a3 1009 #define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */
AnnaBridge 189:f392fc9709a3 1010
AnnaBridge 189:f392fc9709a3 1011 #define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */
AnnaBridge 189:f392fc9709a3 1012 #define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */
AnnaBridge 189:f392fc9709a3 1013
AnnaBridge 189:f392fc9709a3 1014 #define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */
AnnaBridge 189:f392fc9709a3 1015 #define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */
AnnaBridge 189:f392fc9709a3 1016
AnnaBridge 189:f392fc9709a3 1017 #define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/
AnnaBridge 189:f392fc9709a3 1018 #define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */
AnnaBridge 189:f392fc9709a3 1019
AnnaBridge 189:f392fc9709a3 1020 #define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */
AnnaBridge 189:f392fc9709a3 1021 #define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */
AnnaBridge 189:f392fc9709a3 1022 #define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */
AnnaBridge 189:f392fc9709a3 1023
AnnaBridge 189:f392fc9709a3 1024 #define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */
AnnaBridge 189:f392fc9709a3 1025 #define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */
AnnaBridge 189:f392fc9709a3 1026
AnnaBridge 189:f392fc9709a3 1027 /* mac_frmf register value */
AnnaBridge 189:f392fc9709a3 1028 #define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */
AnnaBridge 189:f392fc9709a3 1029 #define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */
AnnaBridge 189:f392fc9709a3 1030 #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */
AnnaBridge 189:f392fc9709a3 1031 #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */
AnnaBridge 189:f392fc9709a3 1032 #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */
AnnaBridge 189:f392fc9709a3 1033
AnnaBridge 189:f392fc9709a3 1034 #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */
AnnaBridge 189:f392fc9709a3 1035 #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */
AnnaBridge 189:f392fc9709a3 1036
AnnaBridge 189:f392fc9709a3 1037 #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */
AnnaBridge 189:f392fc9709a3 1038 #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */
AnnaBridge 189:f392fc9709a3 1039 #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */
AnnaBridge 189:f392fc9709a3 1040 #define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */
AnnaBridge 189:f392fc9709a3 1041 #define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */
AnnaBridge 189:f392fc9709a3 1042
AnnaBridge 189:f392fc9709a3 1043 #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */
AnnaBridge 189:f392fc9709a3 1044 #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */
AnnaBridge 189:f392fc9709a3 1045
AnnaBridge 189:f392fc9709a3 1046 #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */
AnnaBridge 189:f392fc9709a3 1047 #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */
AnnaBridge 189:f392fc9709a3 1048 #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */
AnnaBridge 189:f392fc9709a3 1049
AnnaBridge 189:f392fc9709a3 1050 #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */
AnnaBridge 189:f392fc9709a3 1051 #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */
AnnaBridge 189:f392fc9709a3 1052
AnnaBridge 189:f392fc9709a3 1053 #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */
AnnaBridge 189:f392fc9709a3 1054 #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */
AnnaBridge 189:f392fc9709a3 1055 #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */
AnnaBridge 189:f392fc9709a3 1056 #define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */
AnnaBridge 189:f392fc9709a3 1057 #define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */
AnnaBridge 189:f392fc9709a3 1058 #define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */
AnnaBridge 189:f392fc9709a3 1059 #define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */
AnnaBridge 189:f392fc9709a3 1060
AnnaBridge 189:f392fc9709a3 1061 #define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */
AnnaBridge 189:f392fc9709a3 1062 #define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */
AnnaBridge 189:f392fc9709a3 1063 #define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */
AnnaBridge 189:f392fc9709a3 1064 #define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */
AnnaBridge 189:f392fc9709a3 1065
AnnaBridge 189:f392fc9709a3 1066 /* mac_phy_ctl register value */
AnnaBridge 189:f392fc9709a3 1067 #define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */
AnnaBridge 189:f392fc9709a3 1068 #define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */
AnnaBridge 189:f392fc9709a3 1069 #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */
AnnaBridge 189:f392fc9709a3 1070 #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */
AnnaBridge 189:f392fc9709a3 1071 #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */
AnnaBridge 189:f392fc9709a3 1072
AnnaBridge 189:f392fc9709a3 1073 #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */
AnnaBridge 189:f392fc9709a3 1074
AnnaBridge 189:f392fc9709a3 1075 #define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */
AnnaBridge 189:f392fc9709a3 1076
AnnaBridge 189:f392fc9709a3 1077 /* mac_phy_data register value */
AnnaBridge 189:f392fc9709a3 1078 #define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */
AnnaBridge 189:f392fc9709a3 1079
AnnaBridge 189:f392fc9709a3 1080 /* mac_fctl register value */
AnnaBridge 189:f392fc9709a3 1081 #define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */
AnnaBridge 189:f392fc9709a3 1082 #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */
AnnaBridge 189:f392fc9709a3 1083 #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */
AnnaBridge 189:f392fc9709a3 1084 #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */
AnnaBridge 189:f392fc9709a3 1085 #define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */
AnnaBridge 189:f392fc9709a3 1086
AnnaBridge 189:f392fc9709a3 1087 #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */
AnnaBridge 189:f392fc9709a3 1088 #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */
AnnaBridge 189:f392fc9709a3 1089 #define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */
AnnaBridge 189:f392fc9709a3 1090
AnnaBridge 189:f392fc9709a3 1091 #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */
AnnaBridge 189:f392fc9709a3 1092 #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */
AnnaBridge 189:f392fc9709a3 1093
AnnaBridge 189:f392fc9709a3 1094 #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */
AnnaBridge 189:f392fc9709a3 1095 #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */
AnnaBridge 189:f392fc9709a3 1096 #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */
AnnaBridge 189:f392fc9709a3 1097
AnnaBridge 189:f392fc9709a3 1098 #define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */
AnnaBridge 189:f392fc9709a3 1099 #define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */
AnnaBridge 189:f392fc9709a3 1100 #define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */
AnnaBridge 189:f392fc9709a3 1101
AnnaBridge 189:f392fc9709a3 1102 #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */
AnnaBridge 189:f392fc9709a3 1103 #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */
AnnaBridge 189:f392fc9709a3 1104 #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */
AnnaBridge 189:f392fc9709a3 1105
AnnaBridge 189:f392fc9709a3 1106 #define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */
AnnaBridge 189:f392fc9709a3 1107 /* mac_vlt register value */
AnnaBridge 189:f392fc9709a3 1108 #define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */
AnnaBridge 189:f392fc9709a3 1109
AnnaBridge 189:f392fc9709a3 1110 #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */
AnnaBridge 189:f392fc9709a3 1111 #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */
AnnaBridge 189:f392fc9709a3 1112
AnnaBridge 189:f392fc9709a3 1113 /* mac_wum register value */
AnnaBridge 189:f392fc9709a3 1114 #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */
AnnaBridge 189:f392fc9709a3 1115 #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */
AnnaBridge 189:f392fc9709a3 1116 #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */
AnnaBridge 189:f392fc9709a3 1117 #define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */
AnnaBridge 189:f392fc9709a3 1118 #define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */
AnnaBridge 189:f392fc9709a3 1119 #define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */
AnnaBridge 189:f392fc9709a3 1120 #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */
AnnaBridge 189:f392fc9709a3 1121
AnnaBridge 189:f392fc9709a3 1122 /* mac_dbg register value */
AnnaBridge 189:f392fc9709a3 1123 #define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */
AnnaBridge 189:f392fc9709a3 1124 #define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */
AnnaBridge 189:f392fc9709a3 1125 #define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */
AnnaBridge 189:f392fc9709a3 1126 #define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */
AnnaBridge 189:f392fc9709a3 1127 #define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */
AnnaBridge 189:f392fc9709a3 1128 #define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */
AnnaBridge 189:f392fc9709a3 1129 #define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */
AnnaBridge 189:f392fc9709a3 1130 #define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */
AnnaBridge 189:f392fc9709a3 1131 #define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */
AnnaBridge 189:f392fc9709a3 1132 #define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */
AnnaBridge 189:f392fc9709a3 1133 #define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */
AnnaBridge 189:f392fc9709a3 1134 #define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */
AnnaBridge 189:f392fc9709a3 1135
AnnaBridge 189:f392fc9709a3 1136 #define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */
AnnaBridge 189:f392fc9709a3 1137
AnnaBridge 189:f392fc9709a3 1138 #define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */
AnnaBridge 189:f392fc9709a3 1139
AnnaBridge 189:f392fc9709a3 1140 #define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */
AnnaBridge 189:f392fc9709a3 1141
AnnaBridge 189:f392fc9709a3 1142 #define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */
AnnaBridge 189:f392fc9709a3 1143
AnnaBridge 189:f392fc9709a3 1144 #define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */
AnnaBridge 189:f392fc9709a3 1145
AnnaBridge 189:f392fc9709a3 1146 /* mac_addr0h register value */
AnnaBridge 189:f392fc9709a3 1147 #define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */
AnnaBridge 189:f392fc9709a3 1148
AnnaBridge 189:f392fc9709a3 1149 /* mac_addrxh register value, x = 1,2,3 */
AnnaBridge 189:f392fc9709a3 1150 #define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */
AnnaBridge 189:f392fc9709a3 1151
AnnaBridge 189:f392fc9709a3 1152 #define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */
AnnaBridge 189:f392fc9709a3 1153 #define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */
AnnaBridge 189:f392fc9709a3 1154 #define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */
AnnaBridge 189:f392fc9709a3 1155 #define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */
AnnaBridge 189:f392fc9709a3 1156 #define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */
AnnaBridge 189:f392fc9709a3 1157 #define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */
AnnaBridge 189:f392fc9709a3 1158
AnnaBridge 189:f392fc9709a3 1159 #define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */
AnnaBridge 189:f392fc9709a3 1160 #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */
AnnaBridge 189:f392fc9709a3 1161
AnnaBridge 189:f392fc9709a3 1162 /* mac_fcth register value */
AnnaBridge 189:f392fc9709a3 1163 #define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */
AnnaBridge 189:f392fc9709a3 1164 #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */
AnnaBridge 189:f392fc9709a3 1165 #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */
AnnaBridge 189:f392fc9709a3 1166 #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */
AnnaBridge 189:f392fc9709a3 1167 #define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */
AnnaBridge 189:f392fc9709a3 1168 #define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */
AnnaBridge 189:f392fc9709a3 1169 #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */
AnnaBridge 189:f392fc9709a3 1170 #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */
AnnaBridge 189:f392fc9709a3 1171
AnnaBridge 189:f392fc9709a3 1172 #define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */
AnnaBridge 189:f392fc9709a3 1173 #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */
AnnaBridge 189:f392fc9709a3 1174 #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */
AnnaBridge 189:f392fc9709a3 1175 #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */
AnnaBridge 189:f392fc9709a3 1176 #define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */
AnnaBridge 189:f392fc9709a3 1177 #define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */
AnnaBridge 189:f392fc9709a3 1178 #define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */
AnnaBridge 189:f392fc9709a3 1179 #define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */
AnnaBridge 189:f392fc9709a3 1180
AnnaBridge 189:f392fc9709a3 1181 /* msc_ctl register value */
AnnaBridge 189:f392fc9709a3 1182 #define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */
AnnaBridge 189:f392fc9709a3 1183 #define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */
AnnaBridge 189:f392fc9709a3 1184 #define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */
AnnaBridge 189:f392fc9709a3 1185
AnnaBridge 189:f392fc9709a3 1186 /* ptp_tsctl register value */
AnnaBridge 189:f392fc9709a3 1187 #define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */
AnnaBridge 189:f392fc9709a3 1188
AnnaBridge 189:f392fc9709a3 1189 #define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */
AnnaBridge 189:f392fc9709a3 1190 #define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */
AnnaBridge 189:f392fc9709a3 1191 #define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */
AnnaBridge 189:f392fc9709a3 1192 #define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */
AnnaBridge 189:f392fc9709a3 1193 #define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */
AnnaBridge 189:f392fc9709a3 1194 #define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */
AnnaBridge 189:f392fc9709a3 1195 #define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */
AnnaBridge 189:f392fc9709a3 1196
AnnaBridge 189:f392fc9709a3 1197 /* ptp_ssinc register value */
AnnaBridge 189:f392fc9709a3 1198 #define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */
AnnaBridge 189:f392fc9709a3 1199
AnnaBridge 189:f392fc9709a3 1200 /* ptp_tsl register value */
AnnaBridge 189:f392fc9709a3 1201 #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */
AnnaBridge 189:f392fc9709a3 1202
AnnaBridge 189:f392fc9709a3 1203 #define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */
AnnaBridge 189:f392fc9709a3 1204 #define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */
AnnaBridge 189:f392fc9709a3 1205
AnnaBridge 189:f392fc9709a3 1206 #define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */
AnnaBridge 189:f392fc9709a3 1207
AnnaBridge 189:f392fc9709a3 1208 /* ptp_tsul register value */
AnnaBridge 189:f392fc9709a3 1209 #define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */
AnnaBridge 189:f392fc9709a3 1210
AnnaBridge 189:f392fc9709a3 1211 #define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */
AnnaBridge 189:f392fc9709a3 1212 #define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */
AnnaBridge 189:f392fc9709a3 1213
AnnaBridge 189:f392fc9709a3 1214 /* ptp_ppsctl register value */
AnnaBridge 189:f392fc9709a3 1215 #define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */
AnnaBridge 189:f392fc9709a3 1216 #define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */
AnnaBridge 189:f392fc9709a3 1217 #define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */
AnnaBridge 189:f392fc9709a3 1218 #define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */
AnnaBridge 189:f392fc9709a3 1219 #define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */
AnnaBridge 189:f392fc9709a3 1220 #define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */
AnnaBridge 189:f392fc9709a3 1221 #define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */
AnnaBridge 189:f392fc9709a3 1222 #define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */
AnnaBridge 189:f392fc9709a3 1223 #define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */
AnnaBridge 189:f392fc9709a3 1224 #define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */
AnnaBridge 189:f392fc9709a3 1225 #define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */
AnnaBridge 189:f392fc9709a3 1226 #define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */
AnnaBridge 189:f392fc9709a3 1227 #define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */
AnnaBridge 189:f392fc9709a3 1228 #define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */
AnnaBridge 189:f392fc9709a3 1229 #define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */
AnnaBridge 189:f392fc9709a3 1230 #define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */
AnnaBridge 189:f392fc9709a3 1231 #define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */
AnnaBridge 189:f392fc9709a3 1232
AnnaBridge 189:f392fc9709a3 1233 /* dma_bctl register value */
AnnaBridge 189:f392fc9709a3 1234 #define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */
AnnaBridge 189:f392fc9709a3 1235 #define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */
AnnaBridge 189:f392fc9709a3 1236
AnnaBridge 189:f392fc9709a3 1237 #define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */
AnnaBridge 189:f392fc9709a3 1238 #define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */
AnnaBridge 189:f392fc9709a3 1239
AnnaBridge 189:f392fc9709a3 1240 #define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */
AnnaBridge 189:f392fc9709a3 1241 #define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */
AnnaBridge 189:f392fc9709a3 1242 #define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */
AnnaBridge 189:f392fc9709a3 1243 #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */
AnnaBridge 189:f392fc9709a3 1244 #define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */
AnnaBridge 189:f392fc9709a3 1245 #define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */
AnnaBridge 189:f392fc9709a3 1246 #define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */
AnnaBridge 189:f392fc9709a3 1247 #define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */
AnnaBridge 189:f392fc9709a3 1248 #define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */
AnnaBridge 189:f392fc9709a3 1249 #define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */
AnnaBridge 189:f392fc9709a3 1250 #define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */
AnnaBridge 189:f392fc9709a3 1251 #define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */
AnnaBridge 189:f392fc9709a3 1252 #define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */
AnnaBridge 189:f392fc9709a3 1253
AnnaBridge 189:f392fc9709a3 1254 #define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */
AnnaBridge 189:f392fc9709a3 1255 #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/
AnnaBridge 189:f392fc9709a3 1256 #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/
AnnaBridge 189:f392fc9709a3 1257 #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */
AnnaBridge 189:f392fc9709a3 1258 #define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */
AnnaBridge 189:f392fc9709a3 1259 #define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */
AnnaBridge 189:f392fc9709a3 1260
AnnaBridge 189:f392fc9709a3 1261 #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */
AnnaBridge 189:f392fc9709a3 1262 #define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */
AnnaBridge 189:f392fc9709a3 1263
AnnaBridge 189:f392fc9709a3 1264 #define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */
AnnaBridge 189:f392fc9709a3 1265 #define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */
AnnaBridge 189:f392fc9709a3 1266 #define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */
AnnaBridge 189:f392fc9709a3 1267 #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */
AnnaBridge 189:f392fc9709a3 1268 #define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */
AnnaBridge 189:f392fc9709a3 1269 #define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */
AnnaBridge 189:f392fc9709a3 1270 #define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */
AnnaBridge 189:f392fc9709a3 1271 #define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */
AnnaBridge 189:f392fc9709a3 1272 #define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */
AnnaBridge 189:f392fc9709a3 1273 #define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */
AnnaBridge 189:f392fc9709a3 1274 #define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */
AnnaBridge 189:f392fc9709a3 1275 #define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */
AnnaBridge 189:f392fc9709a3 1276 #define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */
AnnaBridge 189:f392fc9709a3 1277
AnnaBridge 189:f392fc9709a3 1278 #define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */
AnnaBridge 189:f392fc9709a3 1279 #define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */
AnnaBridge 189:f392fc9709a3 1280
AnnaBridge 189:f392fc9709a3 1281 #define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */
AnnaBridge 189:f392fc9709a3 1282 #define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */
AnnaBridge 189:f392fc9709a3 1283
AnnaBridge 189:f392fc9709a3 1284 #define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */
AnnaBridge 189:f392fc9709a3 1285 #define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */
AnnaBridge 189:f392fc9709a3 1286
AnnaBridge 189:f392fc9709a3 1287 /* dma_stat register value */
AnnaBridge 189:f392fc9709a3 1288 #define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */
AnnaBridge 189:f392fc9709a3 1289 #define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */
AnnaBridge 189:f392fc9709a3 1290 #define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */
AnnaBridge 189:f392fc9709a3 1291 #define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */
AnnaBridge 189:f392fc9709a3 1292 #define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */
AnnaBridge 189:f392fc9709a3 1293 #define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */
AnnaBridge 189:f392fc9709a3 1294 #define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */
AnnaBridge 189:f392fc9709a3 1295
AnnaBridge 189:f392fc9709a3 1296 #define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */
AnnaBridge 189:f392fc9709a3 1297 #define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */
AnnaBridge 189:f392fc9709a3 1298 #define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */
AnnaBridge 189:f392fc9709a3 1299 #define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */
AnnaBridge 189:f392fc9709a3 1300 #define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */
AnnaBridge 189:f392fc9709a3 1301 #define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */
AnnaBridge 189:f392fc9709a3 1302 #define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */
AnnaBridge 189:f392fc9709a3 1303
AnnaBridge 189:f392fc9709a3 1304 #define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */
AnnaBridge 189:f392fc9709a3 1305 #define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */
AnnaBridge 189:f392fc9709a3 1306 #define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */
AnnaBridge 189:f392fc9709a3 1307 #define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */
AnnaBridge 189:f392fc9709a3 1308
AnnaBridge 189:f392fc9709a3 1309 /* dma_ctl register value */
AnnaBridge 189:f392fc9709a3 1310 #define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */
AnnaBridge 189:f392fc9709a3 1311 #define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */
AnnaBridge 189:f392fc9709a3 1312 #define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */
AnnaBridge 189:f392fc9709a3 1313 #define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */
AnnaBridge 189:f392fc9709a3 1314 #define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */
AnnaBridge 189:f392fc9709a3 1315
AnnaBridge 189:f392fc9709a3 1316 #define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */
AnnaBridge 189:f392fc9709a3 1317 #define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */
AnnaBridge 189:f392fc9709a3 1318 #define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */
AnnaBridge 189:f392fc9709a3 1319 #define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */
AnnaBridge 189:f392fc9709a3 1320 #define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */
AnnaBridge 189:f392fc9709a3 1321 #define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */
AnnaBridge 189:f392fc9709a3 1322 #define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */
AnnaBridge 189:f392fc9709a3 1323 #define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */
AnnaBridge 189:f392fc9709a3 1324 #define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */
AnnaBridge 189:f392fc9709a3 1325
AnnaBridge 189:f392fc9709a3 1326 #define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */
AnnaBridge 189:f392fc9709a3 1327 #define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */
AnnaBridge 189:f392fc9709a3 1328
AnnaBridge 189:f392fc9709a3 1329 #define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */
AnnaBridge 189:f392fc9709a3 1330 #define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */
AnnaBridge 189:f392fc9709a3 1331
AnnaBridge 189:f392fc9709a3 1332 #define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */
AnnaBridge 189:f392fc9709a3 1333 #define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */
AnnaBridge 189:f392fc9709a3 1334 #define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */
AnnaBridge 189:f392fc9709a3 1335
AnnaBridge 189:f392fc9709a3 1336 #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */
AnnaBridge 189:f392fc9709a3 1337 #define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */
AnnaBridge 189:f392fc9709a3 1338
AnnaBridge 189:f392fc9709a3 1339 #define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */
AnnaBridge 189:f392fc9709a3 1340 #define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */
AnnaBridge 189:f392fc9709a3 1341 #define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */
AnnaBridge 189:f392fc9709a3 1342
AnnaBridge 189:f392fc9709a3 1343 #define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */
AnnaBridge 189:f392fc9709a3 1344 #define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */
AnnaBridge 189:f392fc9709a3 1345 #define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */
AnnaBridge 189:f392fc9709a3 1346
AnnaBridge 189:f392fc9709a3 1347 #define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/
AnnaBridge 189:f392fc9709a3 1348 #define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */
AnnaBridge 189:f392fc9709a3 1349 #define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */
AnnaBridge 189:f392fc9709a3 1350
AnnaBridge 189:f392fc9709a3 1351 /* dma_mfbocnt register value */
AnnaBridge 189:f392fc9709a3 1352 #define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */
AnnaBridge 189:f392fc9709a3 1353
AnnaBridge 189:f392fc9709a3 1354 #define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */
AnnaBridge 189:f392fc9709a3 1355
AnnaBridge 189:f392fc9709a3 1356 /* dma_rswdc register value */
AnnaBridge 189:f392fc9709a3 1357 #define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */
AnnaBridge 189:f392fc9709a3 1358
AnnaBridge 189:f392fc9709a3 1359 /* dma tx descriptor tdes0 register value */
AnnaBridge 189:f392fc9709a3 1360 #define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */
AnnaBridge 189:f392fc9709a3 1361 #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */
AnnaBridge 189:f392fc9709a3 1362
AnnaBridge 189:f392fc9709a3 1363 #define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */
AnnaBridge 189:f392fc9709a3 1364 #define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */
AnnaBridge 189:f392fc9709a3 1365 #define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */
AnnaBridge 189:f392fc9709a3 1366 #define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */
AnnaBridge 189:f392fc9709a3 1367 #define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */
AnnaBridge 189:f392fc9709a3 1368
AnnaBridge 189:f392fc9709a3 1369 /* dma tx descriptor tdes1 register value */
AnnaBridge 189:f392fc9709a3 1370 #define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */
AnnaBridge 189:f392fc9709a3 1371
AnnaBridge 189:f392fc9709a3 1372 #define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */
AnnaBridge 189:f392fc9709a3 1373
AnnaBridge 189:f392fc9709a3 1374 /* dma rx descriptor rdes0 register value */
AnnaBridge 189:f392fc9709a3 1375 #define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */
AnnaBridge 189:f392fc9709a3 1376 #define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */
AnnaBridge 189:f392fc9709a3 1377
AnnaBridge 189:f392fc9709a3 1378 /* dma rx descriptor rdes1 register value */
AnnaBridge 189:f392fc9709a3 1379 #define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */
AnnaBridge 189:f392fc9709a3 1380 #define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */
AnnaBridge 189:f392fc9709a3 1381
AnnaBridge 189:f392fc9709a3 1382 #define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */
AnnaBridge 189:f392fc9709a3 1383
AnnaBridge 189:f392fc9709a3 1384 #define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */
AnnaBridge 189:f392fc9709a3 1385
AnnaBridge 189:f392fc9709a3 1386 /* dma rx descriptor rdes4 register value */
AnnaBridge 189:f392fc9709a3 1387 #define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */
AnnaBridge 189:f392fc9709a3 1388 #define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */
AnnaBridge 189:f392fc9709a3 1389
AnnaBridge 189:f392fc9709a3 1390 #define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */
AnnaBridge 189:f392fc9709a3 1391 #define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */
AnnaBridge 189:f392fc9709a3 1392
AnnaBridge 189:f392fc9709a3 1393 /* ENET register mask value */
AnnaBridge 189:f392fc9709a3 1394 #define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */
AnnaBridge 189:f392fc9709a3 1395 #define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */
AnnaBridge 189:f392fc9709a3 1396 #define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */
AnnaBridge 189:f392fc9709a3 1397 #define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */
AnnaBridge 189:f392fc9709a3 1398 #define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */
AnnaBridge 189:f392fc9709a3 1399
AnnaBridge 189:f392fc9709a3 1400 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
AnnaBridge 189:f392fc9709a3 1401 #define ETH_DMATXDESC_SIZE 0x20U /*!< TxDMA enhanced descriptor size */
AnnaBridge 189:f392fc9709a3 1402 #define ETH_DMARXDESC_SIZE 0x20U /*!< RxDMA enhanced descriptor size */
AnnaBridge 189:f392fc9709a3 1403 #else
AnnaBridge 189:f392fc9709a3 1404 #define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */
AnnaBridge 189:f392fc9709a3 1405 #define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */
AnnaBridge 189:f392fc9709a3 1406 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */
AnnaBridge 189:f392fc9709a3 1407
AnnaBridge 189:f392fc9709a3 1408
AnnaBridge 189:f392fc9709a3 1409 typedef enum {
AnnaBridge 189:f392fc9709a3 1410 ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */
AnnaBridge 189:f392fc9709a3 1411 ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */
AnnaBridge 189:f392fc9709a3 1412 ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */
AnnaBridge 189:f392fc9709a3 1413 ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */
AnnaBridge 189:f392fc9709a3 1414 ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */
AnnaBridge 189:f392fc9709a3 1415 ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */
AnnaBridge 189:f392fc9709a3 1416 ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */
AnnaBridge 189:f392fc9709a3 1417 ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU | BIT(31)), /*!< the system timestamp uses the fine method for updating */
AnnaBridge 189:f392fc9709a3 1418 ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */
AnnaBridge 189:f392fc9709a3 1419 ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */
AnnaBridge 189:f392fc9709a3 1420 ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */
AnnaBridge 189:f392fc9709a3 1421 ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV | BIT(31)), /*!< version 2 */
AnnaBridge 189:f392fc9709a3 1422 ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */
AnnaBridge 189:f392fc9709a3 1423 ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN | BIT(31)), /*!< only event type messages are taken snapshot */
AnnaBridge 189:f392fc9709a3 1424 ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */
AnnaBridge 189:f392fc9709a3 1425 ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN | BIT(31)), /*!< snapshot is only take for master node message */
AnnaBridge 189:f392fc9709a3 1426 ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */
AnnaBridge 189:f392fc9709a3 1427 } enet_ptp_function_enum;
AnnaBridge 189:f392fc9709a3 1428
AnnaBridge 189:f392fc9709a3 1429
AnnaBridge 189:f392fc9709a3 1430 /* ENET remote wake-up frame register length */
AnnaBridge 189:f392fc9709a3 1431 #define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */
AnnaBridge 189:f392fc9709a3 1432
AnnaBridge 189:f392fc9709a3 1433 /* ENET frame size */
AnnaBridge 189:f392fc9709a3 1434 #define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */
AnnaBridge 189:f392fc9709a3 1435
AnnaBridge 189:f392fc9709a3 1436 /* ENET delay timeout */
AnnaBridge 189:f392fc9709a3 1437 #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */
AnnaBridge 189:f392fc9709a3 1438 #define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */
AnnaBridge 189:f392fc9709a3 1439
AnnaBridge 189:f392fc9709a3 1440
AnnaBridge 189:f392fc9709a3 1441
AnnaBridge 189:f392fc9709a3 1442 /* function declarations */
AnnaBridge 189:f392fc9709a3 1443 /* main function */
AnnaBridge 189:f392fc9709a3 1444 /* deinitialize the ENET, and reset structure parameters for ENET initialization */
AnnaBridge 189:f392fc9709a3 1445 void enet_deinit(void);
AnnaBridge 189:f392fc9709a3 1446 /* configure the parameters which are usually less cared for initialization */
AnnaBridge 189:f392fc9709a3 1447 void enet_initpara_config(enet_option_enum option, uint32_t para);
AnnaBridge 189:f392fc9709a3 1448 /* initialize ENET peripheral with generally concerned parameters and the less cared parameters */
AnnaBridge 189:f392fc9709a3 1449 ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept);
AnnaBridge 189:f392fc9709a3 1450 /* reset all core internal registers located in CLK_TX and CLK_RX */
AnnaBridge 189:f392fc9709a3 1451 ErrStatus enet_software_reset(void);
AnnaBridge 189:f392fc9709a3 1452 /* check receive frame valid and return frame size */
AnnaBridge 189:f392fc9709a3 1453 uint32_t enet_rxframe_size_get(void);
AnnaBridge 189:f392fc9709a3 1454 /* initialize the dma tx/rx descriptors's parameters in chain mode */
AnnaBridge 189:f392fc9709a3 1455 void enet_descriptors_chain_init(enet_dmadirection_enum direction);
AnnaBridge 189:f392fc9709a3 1456 /* initialize the dma tx/rx descriptors's parameters in ring mode */
AnnaBridge 189:f392fc9709a3 1457 void enet_descriptors_ring_init(enet_dmadirection_enum direction);
AnnaBridge 189:f392fc9709a3 1458 /* handle current received frame data to application buffer */
AnnaBridge 189:f392fc9709a3 1459 ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize);
AnnaBridge 189:f392fc9709a3 1460 /* handle current received frame but without data copy to application buffer */
AnnaBridge 189:f392fc9709a3 1461 #define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U)
AnnaBridge 189:f392fc9709a3 1462 /* handle application buffer data to transmit it */
AnnaBridge 189:f392fc9709a3 1463 ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length);
AnnaBridge 189:f392fc9709a3 1464 /* handle current transmit frame but without data copy from application buffer */
AnnaBridge 189:f392fc9709a3 1465 #define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len))
AnnaBridge 189:f392fc9709a3 1466 /* configure the transmit IP frame checksum offload calculation and insertion */
AnnaBridge 189:f392fc9709a3 1467 void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum);
AnnaBridge 189:f392fc9709a3 1468 /* ENET Tx and Rx function enable (include MAC and DMA module) */
AnnaBridge 189:f392fc9709a3 1469 void enet_enable(void);
AnnaBridge 189:f392fc9709a3 1470 /* ENET Tx and Rx function disable (include MAC and DMA module) */
AnnaBridge 189:f392fc9709a3 1471 void enet_disable(void);
AnnaBridge 189:f392fc9709a3 1472 /* configure MAC address */
AnnaBridge 189:f392fc9709a3 1473 void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]);
AnnaBridge 189:f392fc9709a3 1474 /* get MAC address */
AnnaBridge 189:f392fc9709a3 1475 void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]);
AnnaBridge 189:f392fc9709a3 1476
AnnaBridge 189:f392fc9709a3 1477 /* get the ENET MAC/MSC/PTP/DMA status flag */
AnnaBridge 189:f392fc9709a3 1478 FlagStatus enet_flag_get(enet_flag_enum enet_flag);
AnnaBridge 189:f392fc9709a3 1479 /* clear the ENET DMA status flag */
AnnaBridge 189:f392fc9709a3 1480 void enet_flag_clear(enet_flag_clear_enum enet_flag);
AnnaBridge 189:f392fc9709a3 1481 /* enable ENET MAC/MSC/DMA interrupt */
AnnaBridge 189:f392fc9709a3 1482 void enet_interrupt_enable(enet_int_enum enet_int);
AnnaBridge 189:f392fc9709a3 1483 /* disable ENET MAC/MSC/DMA interrupt */
AnnaBridge 189:f392fc9709a3 1484 void enet_interrupt_disable(enet_int_enum enet_int);
AnnaBridge 189:f392fc9709a3 1485 /* get ENET MAC/MSC/DMA interrupt flag */
AnnaBridge 189:f392fc9709a3 1486 FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag);
AnnaBridge 189:f392fc9709a3 1487 /* clear ENET DMA interrupt flag */
AnnaBridge 189:f392fc9709a3 1488 void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear);
AnnaBridge 189:f392fc9709a3 1489
AnnaBridge 189:f392fc9709a3 1490 /* MAC function */
AnnaBridge 189:f392fc9709a3 1491 /* ENET Tx function enable (include MAC and DMA module) */
AnnaBridge 189:f392fc9709a3 1492 void enet_tx_enable(void);
AnnaBridge 189:f392fc9709a3 1493 /* ENET Tx function disable (include MAC and DMA module) */
AnnaBridge 189:f392fc9709a3 1494 void enet_tx_disable(void);
AnnaBridge 189:f392fc9709a3 1495 /* ENET Rx function enable (include MAC and DMA module) */
AnnaBridge 189:f392fc9709a3 1496 void enet_rx_enable(void);
AnnaBridge 189:f392fc9709a3 1497 /* ENET Rx function disable (include MAC and DMA module) */
AnnaBridge 189:f392fc9709a3 1498 void enet_rx_disable(void);
AnnaBridge 189:f392fc9709a3 1499 /* put registers value into the application buffer */
AnnaBridge 189:f392fc9709a3 1500 void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num);
AnnaBridge 189:f392fc9709a3 1501 /* get the enet debug status from the debug register */
AnnaBridge 189:f392fc9709a3 1502 uint32_t enet_debug_status_get(uint32_t mac_debug);
AnnaBridge 189:f392fc9709a3 1503 /* enable the MAC address filter */
AnnaBridge 189:f392fc9709a3 1504 void enet_address_filter_enable(enet_macaddress_enum mac_addr);
AnnaBridge 189:f392fc9709a3 1505 /* disable the MAC address filter */
AnnaBridge 189:f392fc9709a3 1506 void enet_address_filter_disable(enet_macaddress_enum mac_addr);
AnnaBridge 189:f392fc9709a3 1507 /* configure the MAC address filter */
AnnaBridge 189:f392fc9709a3 1508 void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type);
AnnaBridge 189:f392fc9709a3 1509 /* PHY interface configuration (configure SMI clock and reset PHY chip) */
AnnaBridge 189:f392fc9709a3 1510 ErrStatus enet_phy_config(void);
AnnaBridge 189:f392fc9709a3 1511 /* write to/read from a PHY register */
AnnaBridge 189:f392fc9709a3 1512 ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue);
AnnaBridge 189:f392fc9709a3 1513 /* enable the loopback function of phy chip */
AnnaBridge 189:f392fc9709a3 1514 ErrStatus enet_phyloopback_enable(void);
AnnaBridge 189:f392fc9709a3 1515 /* disable the loopback function of phy chip */
AnnaBridge 189:f392fc9709a3 1516 ErrStatus enet_phyloopback_disable(void);
AnnaBridge 189:f392fc9709a3 1517 /* enable ENET forward feature */
AnnaBridge 189:f392fc9709a3 1518 void enet_forward_feature_enable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1519 /* disable ENET forward feature */
AnnaBridge 189:f392fc9709a3 1520 void enet_forward_feature_disable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1521 /* enable ENET fliter feature */
AnnaBridge 189:f392fc9709a3 1522 void enet_fliter_feature_enable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1523 /* disable ENET fliter feature */
AnnaBridge 189:f392fc9709a3 1524 void enet_fliter_feature_disable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1525
AnnaBridge 189:f392fc9709a3 1526 /* flow control function */
AnnaBridge 189:f392fc9709a3 1527 /* generate the pause frame, ENET will send pause frame after enable transmit flow control */
AnnaBridge 189:f392fc9709a3 1528 ErrStatus enet_pauseframe_generate(void);
AnnaBridge 189:f392fc9709a3 1529 /* configure the pause frame detect type */
AnnaBridge 189:f392fc9709a3 1530 void enet_pauseframe_detect_config(uint32_t detect);
AnnaBridge 189:f392fc9709a3 1531 /* configure the pause frame parameters */
AnnaBridge 189:f392fc9709a3 1532 void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold);
AnnaBridge 189:f392fc9709a3 1533 /* configure the threshold of the flow control(deactive and active threshold) */
AnnaBridge 189:f392fc9709a3 1534 void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active);
AnnaBridge 189:f392fc9709a3 1535 /* enable ENET flow control feature */
AnnaBridge 189:f392fc9709a3 1536 void enet_flowcontrol_feature_enable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1537 /* disable ENET flow control feature */
AnnaBridge 189:f392fc9709a3 1538 void enet_flowcontrol_feature_disable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1539
AnnaBridge 189:f392fc9709a3 1540 /* DMA function */
AnnaBridge 189:f392fc9709a3 1541 /* get the dma transmit/receive process state */
AnnaBridge 189:f392fc9709a3 1542 uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction);
AnnaBridge 189:f392fc9709a3 1543 /* poll the dma transmission/reception enable */
AnnaBridge 189:f392fc9709a3 1544 void enet_dmaprocess_resume(enet_dmadirection_enum direction);
AnnaBridge 189:f392fc9709a3 1545 /* check and recover the Rx process */
AnnaBridge 189:f392fc9709a3 1546 void enet_rxprocess_check_recovery(void);
AnnaBridge 189:f392fc9709a3 1547 /* flush the ENET transmit fifo, and wait until the flush operation completes */
AnnaBridge 189:f392fc9709a3 1548 ErrStatus enet_txfifo_flush(void);
AnnaBridge 189:f392fc9709a3 1549 /* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */
AnnaBridge 189:f392fc9709a3 1550 uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get);
AnnaBridge 189:f392fc9709a3 1551 /* get the Tx or Rx descriptor information */
AnnaBridge 189:f392fc9709a3 1552 uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get);
AnnaBridge 189:f392fc9709a3 1553 /* get the number of missed frames during receiving */
AnnaBridge 189:f392fc9709a3 1554 void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop);
AnnaBridge 189:f392fc9709a3 1555
AnnaBridge 189:f392fc9709a3 1556 /* descriptor function */
AnnaBridge 189:f392fc9709a3 1557 /* get the bit flag of ENET dma descriptor */
AnnaBridge 189:f392fc9709a3 1558 FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag);
AnnaBridge 189:f392fc9709a3 1559 /* set the bit flag of ENET dma tx descriptor */
AnnaBridge 189:f392fc9709a3 1560 void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag);
AnnaBridge 189:f392fc9709a3 1561 /* clear the bit flag of ENET dma tx descriptor */
AnnaBridge 189:f392fc9709a3 1562 void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag);
AnnaBridge 189:f392fc9709a3 1563 /* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */
AnnaBridge 189:f392fc9709a3 1564 void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc);
AnnaBridge 189:f392fc9709a3 1565 /* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */
AnnaBridge 189:f392fc9709a3 1566 void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time);
AnnaBridge 189:f392fc9709a3 1567 /* drop current receive frame */
AnnaBridge 189:f392fc9709a3 1568 void enet_rxframe_drop(void);
AnnaBridge 189:f392fc9709a3 1569 /* enable DMA feature */
AnnaBridge 189:f392fc9709a3 1570 void enet_dma_feature_enable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1571 /* disable DMA feature */
AnnaBridge 189:f392fc9709a3 1572 void enet_dma_feature_disable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1573
AnnaBridge 189:f392fc9709a3 1574
AnnaBridge 189:f392fc9709a3 1575 /* special enhanced mode function */
AnnaBridge 189:f392fc9709a3 1576 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
AnnaBridge 189:f392fc9709a3 1577 /* get the bit of extended status flag in ENET DMA descriptor */
AnnaBridge 189:f392fc9709a3 1578 uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status);
AnnaBridge 189:f392fc9709a3 1579 /* configure descriptor to work in enhanced mode */
AnnaBridge 189:f392fc9709a3 1580 void enet_desc_select_enhanced_mode(void);
AnnaBridge 189:f392fc9709a3 1581 /* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */
AnnaBridge 189:f392fc9709a3 1582 void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction);
AnnaBridge 189:f392fc9709a3 1583 /* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */
AnnaBridge 189:f392fc9709a3 1584 void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction);
AnnaBridge 189:f392fc9709a3 1585 /* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */
AnnaBridge 189:f392fc9709a3 1586 ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]);
AnnaBridge 189:f392fc9709a3 1587 /* handle current received frame but without data copy to application buffer in PTP enhanced mode */
AnnaBridge 189:f392fc9709a3 1588 #define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr))
AnnaBridge 189:f392fc9709a3 1589 /* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */
AnnaBridge 189:f392fc9709a3 1590 ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]);
AnnaBridge 189:f392fc9709a3 1591 /* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */
AnnaBridge 189:f392fc9709a3 1592 #define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr))
AnnaBridge 189:f392fc9709a3 1593
AnnaBridge 189:f392fc9709a3 1594 #else
AnnaBridge 189:f392fc9709a3 1595
AnnaBridge 189:f392fc9709a3 1596 /* configure descriptor to work in normal mode */
AnnaBridge 189:f392fc9709a3 1597 void enet_desc_select_normal_mode(void);
AnnaBridge 189:f392fc9709a3 1598 /* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */
AnnaBridge 189:f392fc9709a3 1599 void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
AnnaBridge 189:f392fc9709a3 1600 /* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */
AnnaBridge 189:f392fc9709a3 1601 void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
AnnaBridge 189:f392fc9709a3 1602 /* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */
AnnaBridge 189:f392fc9709a3 1603 ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]);
AnnaBridge 189:f392fc9709a3 1604 /* handle current received frame but without data copy to application buffer in PTP normal mode */
AnnaBridge 189:f392fc9709a3 1605 #define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr))
AnnaBridge 189:f392fc9709a3 1606 /* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */
AnnaBridge 189:f392fc9709a3 1607 ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]);
AnnaBridge 189:f392fc9709a3 1608 /* handle current transmit frame but without data copy from application buffer in PTP normal mode */
AnnaBridge 189:f392fc9709a3 1609 #define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr))
AnnaBridge 189:f392fc9709a3 1610
AnnaBridge 189:f392fc9709a3 1611 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */
AnnaBridge 189:f392fc9709a3 1612
AnnaBridge 189:f392fc9709a3 1613 /* WUM function */
AnnaBridge 189:f392fc9709a3 1614 /* wakeup frame filter register pointer reset */
AnnaBridge 189:f392fc9709a3 1615 void enet_wum_filter_register_pointer_reset(void);
AnnaBridge 189:f392fc9709a3 1616 /* set the remote wakeup frame registers */
AnnaBridge 189:f392fc9709a3 1617 void enet_wum_filter_config(uint32_t pdata[]);
AnnaBridge 189:f392fc9709a3 1618 /* enable wakeup management features */
AnnaBridge 189:f392fc9709a3 1619 void enet_wum_feature_enable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1620 /* disable wakeup management features */
AnnaBridge 189:f392fc9709a3 1621 void enet_wum_feature_disable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1622
AnnaBridge 189:f392fc9709a3 1623 /* MSC function */
AnnaBridge 189:f392fc9709a3 1624 /* reset the MAC statistics counters */
AnnaBridge 189:f392fc9709a3 1625 void enet_msc_counters_reset(void);
AnnaBridge 189:f392fc9709a3 1626 /* enable the MAC statistics counter features */
AnnaBridge 189:f392fc9709a3 1627 void enet_msc_feature_enable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1628 /* disable the MAC statistics counter features */
AnnaBridge 189:f392fc9709a3 1629 void enet_msc_feature_disable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1630 /* configure MAC statistics counters preset mode */
AnnaBridge 189:f392fc9709a3 1631 void enet_msc_counters_preset_config(enet_msc_preset_enum mode);
AnnaBridge 189:f392fc9709a3 1632 /* get MAC statistics counter */
AnnaBridge 189:f392fc9709a3 1633 uint32_t enet_msc_counters_get(enet_msc_counter_enum counter);
AnnaBridge 189:f392fc9709a3 1634
AnnaBridge 189:f392fc9709a3 1635 /* PTP function */
AnnaBridge 189:f392fc9709a3 1636 /* change subsecond to nanosecond */
AnnaBridge 189:f392fc9709a3 1637 uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond);
AnnaBridge 189:f392fc9709a3 1638 /* change nanosecond to subsecond */
AnnaBridge 189:f392fc9709a3 1639 uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond);
AnnaBridge 189:f392fc9709a3 1640 /* enable the PTP features */
AnnaBridge 189:f392fc9709a3 1641 void enet_ptp_feature_enable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1642 /* disable the PTP features */
AnnaBridge 189:f392fc9709a3 1643 void enet_ptp_feature_disable(uint32_t feature);
AnnaBridge 189:f392fc9709a3 1644 /* configure the PTP timestamp function */
AnnaBridge 189:f392fc9709a3 1645 ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func);
AnnaBridge 189:f392fc9709a3 1646 /* configure the PTP system time subsecond increment value */
AnnaBridge 189:f392fc9709a3 1647 void enet_ptp_subsecond_increment_config(uint32_t subsecond);
AnnaBridge 189:f392fc9709a3 1648 /* adjusting the PTP clock frequency only in fine update mode */
AnnaBridge 189:f392fc9709a3 1649 void enet_ptp_timestamp_addend_config(uint32_t add);
AnnaBridge 189:f392fc9709a3 1650 /* initializing or adding/subtracting to second of the PTP system time */
AnnaBridge 189:f392fc9709a3 1651 void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond);
AnnaBridge 189:f392fc9709a3 1652 /* configure the PTP expected target time */
AnnaBridge 189:f392fc9709a3 1653 void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond);
AnnaBridge 189:f392fc9709a3 1654 /* get the PTP current system time */
AnnaBridge 189:f392fc9709a3 1655 void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct);
AnnaBridge 189:f392fc9709a3 1656 /* configure the PPS output frequency */
AnnaBridge 189:f392fc9709a3 1657 void enet_ptp_pps_output_frequency_config(uint32_t freq);
AnnaBridge 189:f392fc9709a3 1658 /* configure and start PTP timestamp counter */
AnnaBridge 189:f392fc9709a3 1659 void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg);
AnnaBridge 189:f392fc9709a3 1660 /* adjust frequency in fine method by configure addend register */
AnnaBridge 189:f392fc9709a3 1661 void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg);
AnnaBridge 189:f392fc9709a3 1662 /* update system time in coarse method */
AnnaBridge 189:f392fc9709a3 1663 void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct);
AnnaBridge 189:f392fc9709a3 1664 /* set system time in fine method */
AnnaBridge 189:f392fc9709a3 1665 void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct);
AnnaBridge 189:f392fc9709a3 1666 /* get the ptp flag status */
AnnaBridge 189:f392fc9709a3 1667 FlagStatus enet_ptp_flag_get(uint32_t flag);
AnnaBridge 189:f392fc9709a3 1668
AnnaBridge 189:f392fc9709a3 1669 /* internal function */
AnnaBridge 189:f392fc9709a3 1670 /* reset the ENET initpara struct, call it before using enet_initpara_config() */
AnnaBridge 189:f392fc9709a3 1671 void enet_initpara_reset(void);
AnnaBridge 189:f392fc9709a3 1672
AnnaBridge 189:f392fc9709a3 1673 #endif /* GD32F30X_ENET_H */