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mbed library sources. Supersedes mbed-src.

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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 189:f392fc9709a3 1 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 2 * \file system_psoc6.h
AnnaBridge 189:f392fc9709a3 3 * \version 2.30
AnnaBridge 189:f392fc9709a3 4 *
AnnaBridge 189:f392fc9709a3 5 * \brief Device system header file.
AnnaBridge 189:f392fc9709a3 6 *
AnnaBridge 189:f392fc9709a3 7 ********************************************************************************
AnnaBridge 189:f392fc9709a3 8 * \copyright
AnnaBridge 189:f392fc9709a3 9 * Copyright 2016-2019 Cypress Semiconductor Corporation
AnnaBridge 189:f392fc9709a3 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 13 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 14 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 15 *
AnnaBridge 189:f392fc9709a3 16 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 17 *
AnnaBridge 189:f392fc9709a3 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 19 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 21 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 22 * limitations under the License.
AnnaBridge 189:f392fc9709a3 23 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25
AnnaBridge 189:f392fc9709a3 26 #ifndef _SYSTEM_PSOC6_H_
AnnaBridge 189:f392fc9709a3 27 #define _SYSTEM_PSOC6_H_
AnnaBridge 189:f392fc9709a3 28
AnnaBridge 189:f392fc9709a3 29 /**
AnnaBridge 189:f392fc9709a3 30 * \addtogroup group_system_config
AnnaBridge 189:f392fc9709a3 31 * \{
AnnaBridge 189:f392fc9709a3 32 * Provides device startup, system configuration, and linker script files.
AnnaBridge 189:f392fc9709a3 33 * The system startup provides the followings features:
AnnaBridge 189:f392fc9709a3 34 * - See \ref group_system_config_device_initialization for the:
AnnaBridge 189:f392fc9709a3 35 * * \ref group_system_config_dual_core_device_initialization
AnnaBridge 189:f392fc9709a3 36 * * \ref group_system_config_single_core_device_initialization
AnnaBridge 189:f392fc9709a3 37 * - \ref group_system_config_device_memory_definition
AnnaBridge 189:f392fc9709a3 38 * - \ref group_system_config_heap_stack_config
AnnaBridge 189:f392fc9709a3 39 * - \ref group_system_config_merge_apps
AnnaBridge 189:f392fc9709a3 40 * - \ref group_system_config_default_handlers
AnnaBridge 189:f392fc9709a3 41 * - \ref group_system_config_device_vector_table
AnnaBridge 189:f392fc9709a3 42 * - \ref group_system_config_cm4_functions
AnnaBridge 189:f392fc9709a3 43 *
AnnaBridge 189:f392fc9709a3 44 * \section group_system_config_configuration Configuration Considerations
AnnaBridge 189:f392fc9709a3 45 *
AnnaBridge 189:f392fc9709a3 46 * \subsection group_system_config_device_memory_definition Device Memory Definition
AnnaBridge 189:f392fc9709a3 47 * The flash and RAM allocation for each CPU is defined by the linker scripts.
AnnaBridge 189:f392fc9709a3 48 * For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
AnnaBridge 189:f392fc9709a3 49 * 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
AnnaBridge 189:f392fc9709a3 50 * For Single-Core devices the system reserves additional 80 bytes of RAM.
AnnaBridge 189:f392fc9709a3 51 * Using the reserved memory area for other purposes will lead to unexpected behavior.
AnnaBridge 189:f392fc9709a3 52 *
AnnaBridge 189:f392fc9709a3 53 * \note The linker files provided with the PDL are generic and handle all common
AnnaBridge 189:f392fc9709a3 54 * use cases. Your project may not use every section defined in the linker files.
AnnaBridge 189:f392fc9709a3 55 * In that case you may see warnings during the build process. To eliminate build
AnnaBridge 189:f392fc9709a3 56 * warnings in your project, you can simply comment out or remove the relevant
AnnaBridge 189:f392fc9709a3 57 * code in the linker file.
AnnaBridge 189:f392fc9709a3 58 *
AnnaBridge 189:f392fc9709a3 59 * <b>ARM GCC</b>\n
AnnaBridge 189:f392fc9709a3 60 * The flash and RAM sections for the CPU are defined in the linker files:
AnnaBridge 189:f392fc9709a3 61 * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
AnnaBridge 189:f392fc9709a3 62 * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
AnnaBridge 189:f392fc9709a3 63 * \note If the start of the Cortex-M4 application image is changed, the value
AnnaBridge 189:f392fc9709a3 64 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
AnnaBridge 189:f392fc9709a3 65 * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
AnnaBridge 189:f392fc9709a3 66 * Cy_SysEnableCM4() function call.
AnnaBridge 189:f392fc9709a3 67 *
AnnaBridge 189:f392fc9709a3 68 * Change the flash and RAM sizes by editing the macros value in the
AnnaBridge 189:f392fc9709a3 69 * linker files for both CPUs:
AnnaBridge 189:f392fc9709a3 70 * - 'xx_cm0plus.ld', where 'xx' is the device group:
AnnaBridge 189:f392fc9709a3 71 * \code
AnnaBridge 189:f392fc9709a3 72 * flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
AnnaBridge 189:f392fc9709a3 73 * ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
AnnaBridge 189:f392fc9709a3 74 * \endcode
AnnaBridge 189:f392fc9709a3 75 * - 'xx_cm4_dual.ld', where 'xx' is the device group:
AnnaBridge 189:f392fc9709a3 76 * \code
AnnaBridge 189:f392fc9709a3 77 * flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
AnnaBridge 189:f392fc9709a3 78 * ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
AnnaBridge 189:f392fc9709a3 79 * \endcode
AnnaBridge 189:f392fc9709a3 80 *
AnnaBridge 189:f392fc9709a3 81 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
AnnaBridge 189:f392fc9709a3 82 * value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
AnnaBridge 189:f392fc9709a3 83 * by either:
AnnaBridge 189:f392fc9709a3 84 * - Passing the following commands to the compiler:\n
AnnaBridge 189:f392fc9709a3 85 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
AnnaBridge 189:f392fc9709a3 86 * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
AnnaBridge 189:f392fc9709a3 87 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
AnnaBridge 189:f392fc9709a3 88 *
AnnaBridge 189:f392fc9709a3 89 * <b>ARM MDK</b>\n
AnnaBridge 189:f392fc9709a3 90 * The flash and RAM sections for the CPU are defined in the linker files:
AnnaBridge 189:f392fc9709a3 91 * 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
AnnaBridge 189:f392fc9709a3 92 * 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
AnnaBridge 189:f392fc9709a3 93 * \note If the start of the Cortex-M4 application image is changed, the value
AnnaBridge 189:f392fc9709a3 94 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
AnnaBridge 189:f392fc9709a3 95 * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
AnnaBridge 189:f392fc9709a3 96 * Cy_SysEnableCM4() function call.
AnnaBridge 189:f392fc9709a3 97 *
AnnaBridge 189:f392fc9709a3 98 * \note The linker files provided with the PDL are generic and handle all common
AnnaBridge 189:f392fc9709a3 99 * use cases. Your project may not use every section defined in the linker files.
AnnaBridge 189:f392fc9709a3 100 * In that case you may see the warnings during the build process:
AnnaBridge 189:f392fc9709a3 101 * L6314W (no section matches pattern) and/or L6329W
AnnaBridge 189:f392fc9709a3 102 * (pattern only matches removed unused sections). In your project, you can
AnnaBridge 189:f392fc9709a3 103 * suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
AnnaBridge 189:f392fc9709a3 104 * the linker. You can also comment out or remove the relevant code in the linker
AnnaBridge 189:f392fc9709a3 105 * file.
AnnaBridge 189:f392fc9709a3 106 *
AnnaBridge 189:f392fc9709a3 107 * Change the flash and RAM sizes by editing the macros value in the
AnnaBridge 189:f392fc9709a3 108 * linker files for both CPUs:
AnnaBridge 189:f392fc9709a3 109 * - 'xx_cm0plus.scat', where 'xx' is the device group:
AnnaBridge 189:f392fc9709a3 110 * \code
AnnaBridge 189:f392fc9709a3 111 * #define FLASH_START 0x10000000
AnnaBridge 189:f392fc9709a3 112 * #define FLASH_SIZE 0x00080000
AnnaBridge 189:f392fc9709a3 113 * #define RAM_START 0x08000000
AnnaBridge 189:f392fc9709a3 114 * #define RAM_SIZE 0x00024000
AnnaBridge 189:f392fc9709a3 115 * \endcode
AnnaBridge 189:f392fc9709a3 116 * - 'xx_cm4_dual.scat', where 'xx' is the device group:
AnnaBridge 189:f392fc9709a3 117 * \code
AnnaBridge 189:f392fc9709a3 118 * #define FLASH_START 0x10080000
AnnaBridge 189:f392fc9709a3 119 * #define FLASH_SIZE 0x00080000
AnnaBridge 189:f392fc9709a3 120 * #define RAM_START 0x08024000
AnnaBridge 189:f392fc9709a3 121 * #define RAM_SIZE 0x00023800
AnnaBridge 189:f392fc9709a3 122 * \endcode
AnnaBridge 189:f392fc9709a3 123 *
AnnaBridge 189:f392fc9709a3 124 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
AnnaBridge 189:f392fc9709a3 125 * value in the 'xx_cm4_dual.scat' file,
AnnaBridge 189:f392fc9709a3 126 * where 'xx' is the device group. Do this by either:
AnnaBridge 189:f392fc9709a3 127 * - Passing the following commands to the compiler:\n
AnnaBridge 189:f392fc9709a3 128 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
AnnaBridge 189:f392fc9709a3 129 * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
AnnaBridge 189:f392fc9709a3 130 * 'xx' is device family:\n
AnnaBridge 189:f392fc9709a3 131 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
AnnaBridge 189:f392fc9709a3 132 *
AnnaBridge 189:f392fc9709a3 133 * <b>IAR</b>\n
AnnaBridge 189:f392fc9709a3 134 * The flash and RAM sections for the CPU are defined in the linker files:
AnnaBridge 189:f392fc9709a3 135 * 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
AnnaBridge 189:f392fc9709a3 136 * 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
AnnaBridge 189:f392fc9709a3 137 * \note If the start of the Cortex-M4 application image is changed, the value
AnnaBridge 189:f392fc9709a3 138 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
AnnaBridge 189:f392fc9709a3 139 * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
AnnaBridge 189:f392fc9709a3 140 * Cy_SysEnableCM4() function call.
AnnaBridge 189:f392fc9709a3 141 *
AnnaBridge 189:f392fc9709a3 142 * Change the flash and RAM sizes by editing the macros value in the
AnnaBridge 189:f392fc9709a3 143 * linker files for both CPUs:
AnnaBridge 189:f392fc9709a3 144 * - 'xx_cm0plus.icf', where 'xx' is the device group:
AnnaBridge 189:f392fc9709a3 145 * \code
AnnaBridge 189:f392fc9709a3 146 * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
AnnaBridge 189:f392fc9709a3 147 * define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
AnnaBridge 189:f392fc9709a3 148 * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
AnnaBridge 189:f392fc9709a3 149 * define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
AnnaBridge 189:f392fc9709a3 150 * \endcode
AnnaBridge 189:f392fc9709a3 151 * - 'xx_cm4_dual.icf', where 'xx' is the device group:
AnnaBridge 189:f392fc9709a3 152 * \code
AnnaBridge 189:f392fc9709a3 153 * define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
AnnaBridge 189:f392fc9709a3 154 * define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
AnnaBridge 189:f392fc9709a3 155 * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
AnnaBridge 189:f392fc9709a3 156 * define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
AnnaBridge 189:f392fc9709a3 157 * \endcode
AnnaBridge 189:f392fc9709a3 158 *
AnnaBridge 189:f392fc9709a3 159 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
AnnaBridge 189:f392fc9709a3 160 * __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
AnnaBridge 189:f392fc9709a3 161 * is the device group. Do this by either:
AnnaBridge 189:f392fc9709a3 162 * - Passing the following commands to the compiler:\n
AnnaBridge 189:f392fc9709a3 163 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
AnnaBridge 189:f392fc9709a3 164 * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
AnnaBridge 189:f392fc9709a3 165 * 'xx' is device family:\n
AnnaBridge 189:f392fc9709a3 166 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
AnnaBridge 189:f392fc9709a3 167 *
AnnaBridge 189:f392fc9709a3 168 * \subsection group_system_config_device_initialization Device Initialization
AnnaBridge 189:f392fc9709a3 169 * After a power-on-reset (POR), the boot process is handled by the boot code
AnnaBridge 189:f392fc9709a3 170 * from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
AnnaBridge 189:f392fc9709a3 171 * code passes the control to the Cortex-M0+ startup code located in flash.
AnnaBridge 189:f392fc9709a3 172 *
AnnaBridge 189:f392fc9709a3 173 * \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
AnnaBridge 189:f392fc9709a3 174 * The Cortex-M0+ startup code performs the device initialization by a call to
AnnaBridge 189:f392fc9709a3 175 * SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
AnnaBridge 189:f392fc9709a3 176 * by default. Enable the core using the \ref Cy_SysEnableCM4() function.
AnnaBridge 189:f392fc9709a3 177 * See \ref group_system_config_cm4_functions for more details.
AnnaBridge 189:f392fc9709a3 178 * \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
AnnaBridge 189:f392fc9709a3 179 * The function has a separate implementation on each core.
AnnaBridge 189:f392fc9709a3 180 * Both function implementations unlock and disable the WDT.
AnnaBridge 189:f392fc9709a3 181 * Therefore enable the WDT after both cores have been initialized.
AnnaBridge 189:f392fc9709a3 182 *
AnnaBridge 189:f392fc9709a3 183 * \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
AnnaBridge 189:f392fc9709a3 184 * The Cortex-M0+ core is not user-accessible on these devices. In this case the
AnnaBridge 189:f392fc9709a3 185 * Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
AnnaBridge 189:f392fc9709a3 186 *
AnnaBridge 189:f392fc9709a3 187 * \subsection group_system_config_heap_stack_config Heap and Stack Configuration
AnnaBridge 189:f392fc9709a3 188 * There are two ways to adjust heap and stack configurations:
AnnaBridge 189:f392fc9709a3 189 * -# Editing source code files
AnnaBridge 189:f392fc9709a3 190 * -# Specifying via command line
AnnaBridge 189:f392fc9709a3 191 *
AnnaBridge 189:f392fc9709a3 192 * By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
AnnaBridge 189:f392fc9709a3 193 *
AnnaBridge 189:f392fc9709a3 194 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
AnnaBridge 189:f392fc9709a3 195 * - <b>Editing source code files</b>\n
AnnaBridge 189:f392fc9709a3 196 * The heap and stack sizes are defined in the assembler startup files
AnnaBridge 189:f392fc9709a3 197 * (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
AnnaBridge 189:f392fc9709a3 198 * Change the heap and stack sizes by modifying the following lines:\n
AnnaBridge 189:f392fc9709a3 199 * \code .equ Stack_Size, 0x00001000 \endcode
AnnaBridge 189:f392fc9709a3 200 * \code .equ Heap_Size, 0x00000400 \endcode
AnnaBridge 189:f392fc9709a3 201 *
AnnaBridge 189:f392fc9709a3 202 * - <b>Specifying via command line</b>\n
AnnaBridge 189:f392fc9709a3 203 * Change the heap and stack sizes passing the following commands to the compiler:\n
AnnaBridge 189:f392fc9709a3 204 * \code -D __STACK_SIZE=0x000000400 \endcode
AnnaBridge 189:f392fc9709a3 205 * \code -D __HEAP_SIZE=0x000000100 \endcode
AnnaBridge 189:f392fc9709a3 206 *
AnnaBridge 189:f392fc9709a3 207 * \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
AnnaBridge 189:f392fc9709a3 208 * - <b>Editing source code files</b>\n
AnnaBridge 189:f392fc9709a3 209 * The heap and stack sizes are defined in the assembler startup files
AnnaBridge 189:f392fc9709a3 210 * (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
AnnaBridge 189:f392fc9709a3 211 * Change the heap and stack sizes by modifying the following lines:\n
AnnaBridge 189:f392fc9709a3 212 * \code Stack_Size EQU 0x00001000 \endcode
AnnaBridge 189:f392fc9709a3 213 * \code Heap_Size EQU 0x00000400 \endcode
AnnaBridge 189:f392fc9709a3 214 *
AnnaBridge 189:f392fc9709a3 215 * - <b>Specifying via command line</b>\n
AnnaBridge 189:f392fc9709a3 216 * Change the heap and stack sizes passing the following commands to the assembler:\n
AnnaBridge 189:f392fc9709a3 217 * \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
AnnaBridge 189:f392fc9709a3 218 * \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
AnnaBridge 189:f392fc9709a3 219 *
AnnaBridge 189:f392fc9709a3 220 * \subsubsection group_system_config_heap_stack_config_iar IAR
AnnaBridge 189:f392fc9709a3 221 * - <b>Editing source code files</b>\n
AnnaBridge 189:f392fc9709a3 222 * The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
AnnaBridge 189:f392fc9709a3 223 * where 'xx' is the device family, and 'yy' is the target CPU; for example,
AnnaBridge 189:f392fc9709a3 224 * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
AnnaBridge 189:f392fc9709a3 225 * Change the heap and stack sizes by modifying the following lines:\n
AnnaBridge 189:f392fc9709a3 226 * \code Stack_Size EQU 0x00001000 \endcode
AnnaBridge 189:f392fc9709a3 227 * \code Heap_Size EQU 0x00000400 \endcode
AnnaBridge 189:f392fc9709a3 228 *
AnnaBridge 189:f392fc9709a3 229 * - <b>Specifying via command line</b>\n
AnnaBridge 189:f392fc9709a3 230 * Change the heap and stack sizes passing the following commands to the
AnnaBridge 189:f392fc9709a3 231 * linker (including quotation marks):\n
AnnaBridge 189:f392fc9709a3 232 * \code --define_symbol __STACK_SIZE=0x000000400 \endcode
AnnaBridge 189:f392fc9709a3 233 * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
AnnaBridge 189:f392fc9709a3 234 *
AnnaBridge 189:f392fc9709a3 235 * \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
AnnaBridge 189:f392fc9709a3 236 * The CM0+ project and linker script build the CM0+ application image. Similarly,
AnnaBridge 189:f392fc9709a3 237 * the CM4 linker script builds the CM4 application image. Each specifies
AnnaBridge 189:f392fc9709a3 238 * locations, sizes, and contents of sections in memory. See
AnnaBridge 189:f392fc9709a3 239 * \ref group_system_config_device_memory_definition for the symbols and default
AnnaBridge 189:f392fc9709a3 240 * values.
AnnaBridge 189:f392fc9709a3 241 *
AnnaBridge 189:f392fc9709a3 242 * The cymcuelftool is invoked by a post-build command. The precise project
AnnaBridge 189:f392fc9709a3 243 * setting is IDE-specific.
AnnaBridge 189:f392fc9709a3 244 *
AnnaBridge 189:f392fc9709a3 245 * The cymcuelftool combines the two executables. The tool examines the
AnnaBridge 189:f392fc9709a3 246 * executables to ensure that memory regions either do not overlap, or contain
AnnaBridge 189:f392fc9709a3 247 * identical bytes (shared). If there are no problems, it creates a new ELF file
AnnaBridge 189:f392fc9709a3 248 * with the merged image, without changing any of the addresses or data.
AnnaBridge 189:f392fc9709a3 249 *
AnnaBridge 189:f392fc9709a3 250 * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
AnnaBridge 189:f392fc9709a3 251 * The default interrupt handler functions are defined as weak functions to a dummy
AnnaBridge 189:f392fc9709a3 252 * handler in the startup file. The naming convention for the interrupt handler names
AnnaBridge 189:f392fc9709a3 253 * is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
AnnaBridge 189:f392fc9709a3 254 * user code by defining the handler function using the same name. For example:
AnnaBridge 189:f392fc9709a3 255 * \code
AnnaBridge 189:f392fc9709a3 256 * void scb_0_interrupt_IRQHandler(void)
AnnaBridge 189:f392fc9709a3 257 *{
AnnaBridge 189:f392fc9709a3 258 * ...
AnnaBridge 189:f392fc9709a3 259 *}
AnnaBridge 189:f392fc9709a3 260 * \endcode
AnnaBridge 189:f392fc9709a3 261 *
AnnaBridge 189:f392fc9709a3 262 * \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
AnnaBridge 189:f392fc9709a3 263 * This process uses memory sections defined in the linker script. The startup
AnnaBridge 189:f392fc9709a3 264 * code actually defines the contents of the vector table and performs the copy.
AnnaBridge 189:f392fc9709a3 265 * \subsubsection group_system_config_device_vector_table_gcc ARM GCC
AnnaBridge 189:f392fc9709a3 266 * The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
AnnaBridge 189:f392fc9709a3 267 * 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
AnnaBridge 189:f392fc9709a3 268 * It defines sections and locations in memory.\n
AnnaBridge 189:f392fc9709a3 269 * Copy interrupt vectors from flash to RAM: \n
AnnaBridge 189:f392fc9709a3 270 * From: \code LONG (__Vectors) \endcode
AnnaBridge 189:f392fc9709a3 271 * To: \code LONG (__ram_vectors_start__) \endcode
AnnaBridge 189:f392fc9709a3 272 * Size: \code LONG (__Vectors_End - __Vectors) \endcode
AnnaBridge 189:f392fc9709a3 273 * The vector table address (and the vector table itself) are defined in the
AnnaBridge 189:f392fc9709a3 274 * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
AnnaBridge 189:f392fc9709a3 275 * The code in these files copies the vector table from Flash to RAM.
AnnaBridge 189:f392fc9709a3 276 * \subsubsection group_system_config_device_vector_table_mdk ARM MDK
AnnaBridge 189:f392fc9709a3 277 * The linker script file is 'xx_yy.scat', where 'xx' is the device family,
AnnaBridge 189:f392fc9709a3 278 * and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
AnnaBridge 189:f392fc9709a3 279 * cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
AnnaBridge 189:f392fc9709a3 280 * (RESET_RAM) shall be first in the RAM section.\n
AnnaBridge 189:f392fc9709a3 281 * RESET_RAM represents the vector table. It is defined in the assembler startup
AnnaBridge 189:f392fc9709a3 282 * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
AnnaBridge 189:f392fc9709a3 283 * The code in these files copies the vector table from Flash to RAM.
AnnaBridge 189:f392fc9709a3 284 *
AnnaBridge 189:f392fc9709a3 285 * \subsubsection group_system_config_device_vector_table_iar IAR
AnnaBridge 189:f392fc9709a3 286 * The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
AnnaBridge 189:f392fc9709a3 287 * 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
AnnaBridge 189:f392fc9709a3 288 * This file defines the .intvec_ram section and its location.
AnnaBridge 189:f392fc9709a3 289 * \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
AnnaBridge 189:f392fc9709a3 290 * The vector table address (and the vector table itself) are defined in the
AnnaBridge 189:f392fc9709a3 291 * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
AnnaBridge 189:f392fc9709a3 292 * The code in these files copies the vector table from Flash to RAM.
AnnaBridge 189:f392fc9709a3 293 *
AnnaBridge 189:f392fc9709a3 294 * \section group_system_config_more_information More Information
AnnaBridge 189:f392fc9709a3 295 * Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
AnnaBridge 189:f392fc9709a3 296 * more details.
AnnaBridge 189:f392fc9709a3 297 *
AnnaBridge 189:f392fc9709a3 298 * \section group_system_config_MISRA MISRA Compliance
AnnaBridge 189:f392fc9709a3 299 *
AnnaBridge 189:f392fc9709a3 300 * <table class="doxtable">
AnnaBridge 189:f392fc9709a3 301 * <tr>
AnnaBridge 189:f392fc9709a3 302 * <th>MISRA Rule</th>
AnnaBridge 189:f392fc9709a3 303 * <th>Rule Class (Required/Advisory)</th>
AnnaBridge 189:f392fc9709a3 304 * <th>Rule Description</th>
AnnaBridge 189:f392fc9709a3 305 * <th>Description of Deviation(s)</th>
AnnaBridge 189:f392fc9709a3 306 * </tr>
AnnaBridge 189:f392fc9709a3 307 * <tr>
AnnaBridge 189:f392fc9709a3 308 * <td>2.3</td>
AnnaBridge 189:f392fc9709a3 309 * <td>R</td>
AnnaBridge 189:f392fc9709a3 310 * <td>The character sequence // shall not be used within a comment.</td>
AnnaBridge 189:f392fc9709a3 311 * <td>The comments provide a useful WEB link to the documentation.</td>
AnnaBridge 189:f392fc9709a3 312 * </tr>
AnnaBridge 189:f392fc9709a3 313 * </table>
AnnaBridge 189:f392fc9709a3 314 *
AnnaBridge 189:f392fc9709a3 315 * \section group_system_config_changelog Changelog
AnnaBridge 189:f392fc9709a3 316 * <table class="doxtable">
AnnaBridge 189:f392fc9709a3 317 * <tr>
AnnaBridge 189:f392fc9709a3 318 * <th>Version</th>
AnnaBridge 189:f392fc9709a3 319 * <th>Changes</th>
AnnaBridge 189:f392fc9709a3 320 * <th>Reason for Change</th>
AnnaBridge 189:f392fc9709a3 321 * </tr>
AnnaBridge 189:f392fc9709a3 322 * <tr>
AnnaBridge 189:f392fc9709a3 323 * <td rowspan="2">2.30</td>
AnnaBridge 189:f392fc9709a3 324 * <td>Added assembler files, linker skripts for Mbed OS.</td>
AnnaBridge 189:f392fc9709a3 325 * <td>Added Arm Mbed OS embedded operating system support.</td>
AnnaBridge 189:f392fc9709a3 326 * </tr>
AnnaBridge 189:f392fc9709a3 327 * <tr>
AnnaBridge 189:f392fc9709a3 328 * <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
AnnaBridge 189:f392fc9709a3 329 * <td>Enhanced PDL usability.</td>
AnnaBridge 189:f392fc9709a3 330 * </tr>
AnnaBridge 189:f392fc9709a3 331 * <tr>
AnnaBridge 189:f392fc9709a3 332 * <td>2.20</td>
AnnaBridge 189:f392fc9709a3 333 * <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
AnnaBridge 189:f392fc9709a3 334 * <td>Changed the IPC driver configuration method from compile time to run time.</td>
AnnaBridge 189:f392fc9709a3 335 * </tr>
AnnaBridge 189:f392fc9709a3 336 * <tr>
AnnaBridge 189:f392fc9709a3 337 * <td rowspan="2"> 2.10</td>
AnnaBridge 189:f392fc9709a3 338 * <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
AnnaBridge 189:f392fc9709a3 339 * Removed $Sub$$main symbol for ARM MDK compiler.
AnnaBridge 189:f392fc9709a3 340 * </td>
AnnaBridge 189:f392fc9709a3 341 * <td>uVision Debugger support.</td>
AnnaBridge 189:f392fc9709a3 342 * </tr>
AnnaBridge 189:f392fc9709a3 343 * <tr>
AnnaBridge 189:f392fc9709a3 344 * <td>Updated description of the Startup behavior for Single-Core Devices. \n
AnnaBridge 189:f392fc9709a3 345 * Added note about WDT disabling by SystemInit() function.
AnnaBridge 189:f392fc9709a3 346 * </td>
AnnaBridge 189:f392fc9709a3 347 * <td>Documentation improvement.</td>
AnnaBridge 189:f392fc9709a3 348 * </tr>
AnnaBridge 189:f392fc9709a3 349 * <tr>
AnnaBridge 189:f392fc9709a3 350 * <td rowspan="4"> 2.0</td>
AnnaBridge 189:f392fc9709a3 351 * <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
AnnaBridge 189:f392fc9709a3 352 * Single core device support.
AnnaBridge 189:f392fc9709a3 353 * </td>
AnnaBridge 189:f392fc9709a3 354 * <td></td>
AnnaBridge 189:f392fc9709a3 355 * </tr>
AnnaBridge 189:f392fc9709a3 356 * <tr>
AnnaBridge 189:f392fc9709a3 357 * <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
AnnaBridge 189:f392fc9709a3 358 * Renamed 'wflash' memory region to 'em_eeprom'.
AnnaBridge 189:f392fc9709a3 359 * </td>
AnnaBridge 189:f392fc9709a3 360 * <td>Linker scripts usability improvement.</td>
AnnaBridge 189:f392fc9709a3 361 * </tr>
AnnaBridge 189:f392fc9709a3 362 * <tr>
AnnaBridge 189:f392fc9709a3 363 * <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
AnnaBridge 189:f392fc9709a3 364 * <td>Reserved system resources for internal operations.</td>
AnnaBridge 189:f392fc9709a3 365 * </tr>
AnnaBridge 189:f392fc9709a3 366 * <tr>
AnnaBridge 189:f392fc9709a3 367 * <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
AnnaBridge 189:f392fc9709a3 368 * <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
AnnaBridge 189:f392fc9709a3 369 * </tr>
AnnaBridge 189:f392fc9709a3 370 * <tr>
AnnaBridge 189:f392fc9709a3 371 * <td>1.0</td>
AnnaBridge 189:f392fc9709a3 372 * <td>Initial version</td>
AnnaBridge 189:f392fc9709a3 373 * <td></td>
AnnaBridge 189:f392fc9709a3 374 * </tr>
AnnaBridge 189:f392fc9709a3 375 * </table>
AnnaBridge 189:f392fc9709a3 376 *
AnnaBridge 189:f392fc9709a3 377 *
AnnaBridge 189:f392fc9709a3 378 * \defgroup group_system_config_macro Macro
AnnaBridge 189:f392fc9709a3 379 * \{
AnnaBridge 189:f392fc9709a3 380 * \defgroup group_system_config_system_macro System
AnnaBridge 189:f392fc9709a3 381 * \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
AnnaBridge 189:f392fc9709a3 382 * \defgroup group_system_config_user_settings_macro User Settings
AnnaBridge 189:f392fc9709a3 383 * \}
AnnaBridge 189:f392fc9709a3 384 * \defgroup group_system_config_functions Functions
AnnaBridge 189:f392fc9709a3 385 * \{
AnnaBridge 189:f392fc9709a3 386 * \defgroup group_system_config_system_functions System
AnnaBridge 189:f392fc9709a3 387 * \defgroup group_system_config_cm4_functions Cortex-M4 Control
AnnaBridge 189:f392fc9709a3 388 * \}
AnnaBridge 189:f392fc9709a3 389 * \defgroup group_system_config_globals Global Variables
AnnaBridge 189:f392fc9709a3 390 *
AnnaBridge 189:f392fc9709a3 391 * \}
AnnaBridge 189:f392fc9709a3 392 */
AnnaBridge 189:f392fc9709a3 393
AnnaBridge 189:f392fc9709a3 394 /**
AnnaBridge 189:f392fc9709a3 395 * \addtogroup group_system_config_system_functions
AnnaBridge 189:f392fc9709a3 396 * \{
AnnaBridge 189:f392fc9709a3 397 * \details
AnnaBridge 189:f392fc9709a3 398 * The following system functions implement CMSIS Core functions.
AnnaBridge 189:f392fc9709a3 399 * Refer to the [CMSIS documentation]
AnnaBridge 189:f392fc9709a3 400 * (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
AnnaBridge 189:f392fc9709a3 401 * for more details.
AnnaBridge 189:f392fc9709a3 402 * \}
AnnaBridge 189:f392fc9709a3 403 */
AnnaBridge 189:f392fc9709a3 404
AnnaBridge 189:f392fc9709a3 405 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 406 extern "C" {
AnnaBridge 189:f392fc9709a3 407 #endif
AnnaBridge 189:f392fc9709a3 408
AnnaBridge 189:f392fc9709a3 409
AnnaBridge 189:f392fc9709a3 410 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 411 * Include files
AnnaBridge 189:f392fc9709a3 412 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 413 #include <stdint.h>
AnnaBridge 189:f392fc9709a3 414
AnnaBridge 189:f392fc9709a3 415
AnnaBridge 189:f392fc9709a3 416 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 417 * Global preprocessor symbols/macros ('define')
AnnaBridge 189:f392fc9709a3 418 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 419 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
AnnaBridge 189:f392fc9709a3 420 (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
AnnaBridge 189:f392fc9709a3 421 (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
AnnaBridge 189:f392fc9709a3 422 #define CY_SYSTEM_CPU_CM0P 1UL
AnnaBridge 189:f392fc9709a3 423 #else
AnnaBridge 189:f392fc9709a3 424 #define CY_SYSTEM_CPU_CM0P 0UL
AnnaBridge 189:f392fc9709a3 425 #endif
AnnaBridge 189:f392fc9709a3 426
AnnaBridge 189:f392fc9709a3 427 #if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
AnnaBridge 189:f392fc9709a3 428 #include "cyfitter.h"
AnnaBridge 189:f392fc9709a3 429 #endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
AnnaBridge 189:f392fc9709a3 430
AnnaBridge 189:f392fc9709a3 431
AnnaBridge 189:f392fc9709a3 432
AnnaBridge 189:f392fc9709a3 433
AnnaBridge 189:f392fc9709a3 434 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 435 *
AnnaBridge 189:f392fc9709a3 436 * START OF USER SETTINGS HERE
AnnaBridge 189:f392fc9709a3 437 * ===========================
AnnaBridge 189:f392fc9709a3 438 *
AnnaBridge 189:f392fc9709a3 439 * All lines with '<<<' can be set by user.
AnnaBridge 189:f392fc9709a3 440 *
AnnaBridge 189:f392fc9709a3 441 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 442
AnnaBridge 189:f392fc9709a3 443 /**
AnnaBridge 189:f392fc9709a3 444 * \addtogroup group_system_config_user_settings_macro
AnnaBridge 189:f392fc9709a3 445 * \{
AnnaBridge 189:f392fc9709a3 446 */
AnnaBridge 189:f392fc9709a3 447
AnnaBridge 189:f392fc9709a3 448 #if defined (CYDEV_CLK_EXTCLK__HZ)
AnnaBridge 189:f392fc9709a3 449 #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
AnnaBridge 189:f392fc9709a3 450 #else
AnnaBridge 189:f392fc9709a3 451 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 452 * External Clock Frequency (in Hz, [value]UL). If compiled within
AnnaBridge 189:f392fc9709a3 453 * PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
AnnaBridge 189:f392fc9709a3 454 * Otherwise, edit the value below.
AnnaBridge 189:f392fc9709a3 455 * <i>(USER SETTING)</i>
AnnaBridge 189:f392fc9709a3 456 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 457 #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
AnnaBridge 189:f392fc9709a3 458 #endif /* (CYDEV_CLK_EXTCLK__HZ) */
AnnaBridge 189:f392fc9709a3 459
AnnaBridge 189:f392fc9709a3 460
AnnaBridge 189:f392fc9709a3 461 #if defined (CYDEV_CLK_ECO__HZ)
AnnaBridge 189:f392fc9709a3 462 #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
AnnaBridge 189:f392fc9709a3 463 #else
AnnaBridge 189:f392fc9709a3 464 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 465 * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
AnnaBridge 189:f392fc9709a3 466 * within PSoC Creator and the clock is enabled in the DWR, the value from DWR
AnnaBridge 189:f392fc9709a3 467 * used.
AnnaBridge 189:f392fc9709a3 468 * <i>(USER SETTING)</i>
AnnaBridge 189:f392fc9709a3 469 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 470 #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
AnnaBridge 189:f392fc9709a3 471 #endif /* (CYDEV_CLK_ECO__HZ) */
AnnaBridge 189:f392fc9709a3 472
AnnaBridge 189:f392fc9709a3 473
AnnaBridge 189:f392fc9709a3 474 #if defined (CYDEV_CLK_ALTHF__HZ)
AnnaBridge 189:f392fc9709a3 475 #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
AnnaBridge 189:f392fc9709a3 476 #else
AnnaBridge 189:f392fc9709a3 477 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 478 * \brief Alternate high frequency (in Hz, [value]UL). If compiled within
AnnaBridge 189:f392fc9709a3 479 * PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
AnnaBridge 189:f392fc9709a3 480 * Otherwise, edit the value below.
AnnaBridge 189:f392fc9709a3 481 * <i>(USER SETTING)</i>
AnnaBridge 189:f392fc9709a3 482 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 483 #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
AnnaBridge 189:f392fc9709a3 484 #endif /* (CYDEV_CLK_ALTHF__HZ) */
AnnaBridge 189:f392fc9709a3 485
AnnaBridge 189:f392fc9709a3 486
AnnaBridge 189:f392fc9709a3 487 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 488 * \brief Start address of the Cortex-M4 application ([address]UL)
AnnaBridge 189:f392fc9709a3 489 * <i>(USER SETTING)</i>
AnnaBridge 189:f392fc9709a3 490 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 491 #if !defined (CY_CORTEX_M4_APPL_ADDR)
AnnaBridge 189:f392fc9709a3 492 #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
AnnaBridge 189:f392fc9709a3 493 #endif /* (CY_CORTEX_M4_APPL_ADDR) */
AnnaBridge 189:f392fc9709a3 494
AnnaBridge 189:f392fc9709a3 495
AnnaBridge 189:f392fc9709a3 496 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 497 * \brief IPC Semaphores allocation ([value]UL).
AnnaBridge 189:f392fc9709a3 498 * <i>(USER SETTING)</i>
AnnaBridge 189:f392fc9709a3 499 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 500 #define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
AnnaBridge 189:f392fc9709a3 501
AnnaBridge 189:f392fc9709a3 502
AnnaBridge 189:f392fc9709a3 503 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 504 * \brief IPC Pipe definitions ([value]UL).
AnnaBridge 189:f392fc9709a3 505 * <i>(USER SETTING)</i>
AnnaBridge 189:f392fc9709a3 506 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 507 #define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
AnnaBridge 189:f392fc9709a3 508
AnnaBridge 189:f392fc9709a3 509
AnnaBridge 189:f392fc9709a3 510 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 511 *
AnnaBridge 189:f392fc9709a3 512 * END OF USER SETTINGS HERE
AnnaBridge 189:f392fc9709a3 513 * =========================
AnnaBridge 189:f392fc9709a3 514 *
AnnaBridge 189:f392fc9709a3 515 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 516
AnnaBridge 189:f392fc9709a3 517 /** \} group_system_config_user_settings_macro */
AnnaBridge 189:f392fc9709a3 518
AnnaBridge 189:f392fc9709a3 519
AnnaBridge 189:f392fc9709a3 520 /**
AnnaBridge 189:f392fc9709a3 521 * \addtogroup group_system_config_system_macro
AnnaBridge 189:f392fc9709a3 522 * \{
AnnaBridge 189:f392fc9709a3 523 */
AnnaBridge 189:f392fc9709a3 524
AnnaBridge 189:f392fc9709a3 525 #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
AnnaBridge 189:f392fc9709a3 526 /** The Cortex-M0+ startup driver identifier */
AnnaBridge 189:f392fc9709a3 527 #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
AnnaBridge 189:f392fc9709a3 528 #endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
AnnaBridge 189:f392fc9709a3 529
AnnaBridge 189:f392fc9709a3 530 #if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
AnnaBridge 189:f392fc9709a3 531 /** The Cortex-M4 startup driver identifier */
AnnaBridge 189:f392fc9709a3 532 #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
AnnaBridge 189:f392fc9709a3 533 #endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
AnnaBridge 189:f392fc9709a3 534
AnnaBridge 189:f392fc9709a3 535 /** \} group_system_config_system_macro */
AnnaBridge 189:f392fc9709a3 536
AnnaBridge 189:f392fc9709a3 537
AnnaBridge 189:f392fc9709a3 538 /**
AnnaBridge 189:f392fc9709a3 539 * \addtogroup group_system_config_system_functions
AnnaBridge 189:f392fc9709a3 540 * \{
AnnaBridge 189:f392fc9709a3 541 */
AnnaBridge 189:f392fc9709a3 542 #if defined(__ARMCC_VERSION)
AnnaBridge 189:f392fc9709a3 543 extern void SystemInit(void) __attribute__((constructor));
AnnaBridge 189:f392fc9709a3 544 #else
AnnaBridge 189:f392fc9709a3 545 extern void SystemInit(void);
AnnaBridge 189:f392fc9709a3 546 #endif /* (__ARMCC_VERSION) */
AnnaBridge 189:f392fc9709a3 547
AnnaBridge 189:f392fc9709a3 548 extern void SystemCoreClockUpdate(void);
AnnaBridge 189:f392fc9709a3 549 /** \} group_system_config_system_functions */
AnnaBridge 189:f392fc9709a3 550
AnnaBridge 189:f392fc9709a3 551
AnnaBridge 189:f392fc9709a3 552 /**
AnnaBridge 189:f392fc9709a3 553 * \addtogroup group_system_config_cm4_functions
AnnaBridge 189:f392fc9709a3 554 * \{
AnnaBridge 189:f392fc9709a3 555 */
AnnaBridge 189:f392fc9709a3 556 extern uint32_t Cy_SysGetCM4Status(void);
AnnaBridge 189:f392fc9709a3 557 extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
AnnaBridge 189:f392fc9709a3 558 extern void Cy_SysDisableCM4(void);
AnnaBridge 189:f392fc9709a3 559 extern void Cy_SysRetainCM4(void);
AnnaBridge 189:f392fc9709a3 560 extern void Cy_SysResetCM4(void);
AnnaBridge 189:f392fc9709a3 561 /** \} group_system_config_cm4_functions */
AnnaBridge 189:f392fc9709a3 562
AnnaBridge 189:f392fc9709a3 563
AnnaBridge 189:f392fc9709a3 564 /** \cond */
AnnaBridge 189:f392fc9709a3 565 extern void Default_Handler (void);
AnnaBridge 189:f392fc9709a3 566
AnnaBridge 189:f392fc9709a3 567 void Cy_SysIpcPipeIsrCm0(void);
AnnaBridge 189:f392fc9709a3 568 void Cy_SysIpcPipeIsrCm4(void);
AnnaBridge 189:f392fc9709a3 569
AnnaBridge 189:f392fc9709a3 570 extern void Cy_SystemInit(void);
AnnaBridge 189:f392fc9709a3 571 extern void Cy_SystemInitFpuEnable(void);
AnnaBridge 189:f392fc9709a3 572
AnnaBridge 189:f392fc9709a3 573 extern uint32_t cy_delayFreqHz;
AnnaBridge 189:f392fc9709a3 574 extern uint32_t cy_delayFreqKhz;
AnnaBridge 189:f392fc9709a3 575 extern uint8_t cy_delayFreqMhz;
AnnaBridge 189:f392fc9709a3 576 extern uint32_t cy_delay32kMs;
AnnaBridge 189:f392fc9709a3 577 /** \endcond */
AnnaBridge 189:f392fc9709a3 578
AnnaBridge 189:f392fc9709a3 579
AnnaBridge 189:f392fc9709a3 580 #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
AnnaBridge 189:f392fc9709a3 581 /**
AnnaBridge 189:f392fc9709a3 582 * \addtogroup group_system_config_cm4_status_macro
AnnaBridge 189:f392fc9709a3 583 * \{
AnnaBridge 189:f392fc9709a3 584 */
AnnaBridge 189:f392fc9709a3 585 #define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
AnnaBridge 189:f392fc9709a3 586 #define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
AnnaBridge 189:f392fc9709a3 587 #define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
AnnaBridge 189:f392fc9709a3 588 #define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
AnnaBridge 189:f392fc9709a3 589 /** \} group_system_config_cm4_status_macro */
AnnaBridge 189:f392fc9709a3 590
AnnaBridge 189:f392fc9709a3 591 #endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
AnnaBridge 189:f392fc9709a3 592
AnnaBridge 189:f392fc9709a3 593
AnnaBridge 189:f392fc9709a3 594 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 595 * IPC Configuration
AnnaBridge 189:f392fc9709a3 596 * =========================
AnnaBridge 189:f392fc9709a3 597 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 598 /* IPC CY_PIPE default configuration */
AnnaBridge 189:f392fc9709a3 599 #define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
AnnaBridge 189:f392fc9709a3 600
AnnaBridge 189:f392fc9709a3 601 #define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
AnnaBridge 189:f392fc9709a3 602 #define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
AnnaBridge 189:f392fc9709a3 603 #define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
AnnaBridge 189:f392fc9709a3 604
AnnaBridge 189:f392fc9709a3 605 #define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
AnnaBridge 189:f392fc9709a3 606 #define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
AnnaBridge 189:f392fc9709a3 607
AnnaBridge 189:f392fc9709a3 608
AnnaBridge 189:f392fc9709a3 609 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 610 /*
AnnaBridge 189:f392fc9709a3 611 * The System pipe configuration defines the IPC channel number, interrupt
AnnaBridge 189:f392fc9709a3 612 * number, and the pipe interrupt mask for the endpoint.
AnnaBridge 189:f392fc9709a3 613 *
AnnaBridge 189:f392fc9709a3 614 * The format of the endPoint configuration
AnnaBridge 189:f392fc9709a3 615 * Bits[31:16] Interrupt Mask
AnnaBridge 189:f392fc9709a3 616 * Bits[15:8 ] IPC interrupt
AnnaBridge 189:f392fc9709a3 617 * Bits[ 7:0 ] IPC channel
AnnaBridge 189:f392fc9709a3 618 */
AnnaBridge 189:f392fc9709a3 619
AnnaBridge 189:f392fc9709a3 620 /* System Pipe addresses */
AnnaBridge 189:f392fc9709a3 621 /* CyPipe defines */
AnnaBridge 189:f392fc9709a3 622
AnnaBridge 189:f392fc9709a3 623 #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
AnnaBridge 189:f392fc9709a3 624
AnnaBridge 189:f392fc9709a3 625 #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
AnnaBridge 189:f392fc9709a3 626 | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
AnnaBridge 189:f392fc9709a3 627 | CY_IPC_CHAN_CYPIPE_EP0)
AnnaBridge 189:f392fc9709a3 628 #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
AnnaBridge 189:f392fc9709a3 629 | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
AnnaBridge 189:f392fc9709a3 630 | CY_IPC_CHAN_CYPIPE_EP1)
AnnaBridge 189:f392fc9709a3 631
AnnaBridge 189:f392fc9709a3 632 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 633
AnnaBridge 189:f392fc9709a3 634
AnnaBridge 189:f392fc9709a3 635 /** \addtogroup group_system_config_globals
AnnaBridge 189:f392fc9709a3 636 * \{
AnnaBridge 189:f392fc9709a3 637 */
AnnaBridge 189:f392fc9709a3 638
AnnaBridge 189:f392fc9709a3 639 extern uint32_t SystemCoreClock;
AnnaBridge 189:f392fc9709a3 640 extern uint32_t cy_BleEcoClockFreqHz;
AnnaBridge 189:f392fc9709a3 641 extern uint32_t cy_Hfclk0FreqHz;
AnnaBridge 189:f392fc9709a3 642 extern uint32_t cy_PeriClkFreqHz;
AnnaBridge 189:f392fc9709a3 643
AnnaBridge 189:f392fc9709a3 644 /** \} group_system_config_globals */
AnnaBridge 189:f392fc9709a3 645
AnnaBridge 189:f392fc9709a3 646
AnnaBridge 189:f392fc9709a3 647
AnnaBridge 189:f392fc9709a3 648 /** \cond INTERNAL */
AnnaBridge 189:f392fc9709a3 649 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 650 * Backward compatibility macro. The following code is DEPRECATED and must
AnnaBridge 189:f392fc9709a3 651 * not be used in new projects
AnnaBridge 189:f392fc9709a3 652 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 653
AnnaBridge 189:f392fc9709a3 654 /* BWC defines for functions related to enter/exit critical section */
AnnaBridge 189:f392fc9709a3 655 #define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
AnnaBridge 189:f392fc9709a3 656 #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
AnnaBridge 189:f392fc9709a3 657 #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
AnnaBridge 189:f392fc9709a3 658 #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
AnnaBridge 189:f392fc9709a3 659
AnnaBridge 189:f392fc9709a3 660 /** \endcond */
AnnaBridge 189:f392fc9709a3 661
AnnaBridge 189:f392fc9709a3 662 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 663 }
AnnaBridge 189:f392fc9709a3 664 #endif
AnnaBridge 189:f392fc9709a3 665
AnnaBridge 189:f392fc9709a3 666 #endif /* _SYSTEM_PSOC6_H_ */
AnnaBridge 189:f392fc9709a3 667
AnnaBridge 189:f392fc9709a3 668
AnnaBridge 189:f392fc9709a3 669 /* [] END OF FILE */