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cmsis/BUILD/mbed/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/stm32l0xx_ll_lpuart.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l0xx_ll_lpuart.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of LPUART LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L0xx_LL_LPUART_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L0xx_LL_LPUART_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l0xx.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#if defined (LPUART1)
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @defgroup LPUART_LL LPUART
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59
AnnaBridge	189:f392fc9709a3	60	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	61	/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
AnnaBridge	189:f392fc9709a3	62	* @{
AnnaBridge	189:f392fc9709a3	63	*/
AnnaBridge	189:f392fc9709a3	64
AnnaBridge	189:f392fc9709a3	65	/* Defines used for the bit position in the register and perform offsets*/
AnnaBridge	189:f392fc9709a3	66	#define LPUART_POSITION_CR1_DEDT (uint32_t)16U
AnnaBridge	189:f392fc9709a3	67	#define LPUART_POSITION_CR1_DEAT (uint32_t)21U
AnnaBridge	189:f392fc9709a3	68	#define LPUART_POSITION_CR2_ADD (uint32_t)24U
AnnaBridge	189:f392fc9709a3	69
AnnaBridge	189:f392fc9709a3	70	/* Defines used in Baud Rate related macros and corresponding register setting computation */
AnnaBridge	189:f392fc9709a3	71	#define LPUART_LPUARTDIV_FREQ_MUL (uint32_t)(256U)
AnnaBridge	189:f392fc9709a3	72	#define LPUART_BRR_MASK (uint32_t)(0x000FFFFFU)
AnnaBridge	189:f392fc9709a3	73	#define LPUART_BRR_MIN_VALUE (uint32_t)(0x00000300U)
AnnaBridge	189:f392fc9709a3	74	/**
AnnaBridge	189:f392fc9709a3	75	* @}
AnnaBridge	189:f392fc9709a3	76	*/
AnnaBridge	189:f392fc9709a3	77
AnnaBridge	189:f392fc9709a3	78
AnnaBridge	189:f392fc9709a3	79	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	80	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	81	/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
AnnaBridge	189:f392fc9709a3	82	* @{
AnnaBridge	189:f392fc9709a3	83	*/
AnnaBridge	189:f392fc9709a3	84	/**
AnnaBridge	189:f392fc9709a3	85	* @}
AnnaBridge	189:f392fc9709a3	86	*/
AnnaBridge	189:f392fc9709a3	87	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	88
AnnaBridge	189:f392fc9709a3	89	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	90	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	91	/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
AnnaBridge	189:f392fc9709a3	92	* @{
AnnaBridge	189:f392fc9709a3	93	*/
AnnaBridge	189:f392fc9709a3	94
AnnaBridge	189:f392fc9709a3	95	/**
AnnaBridge	189:f392fc9709a3	96	* @brief LL LPUART Init Structure definition
AnnaBridge	189:f392fc9709a3	97	*/
AnnaBridge	189:f392fc9709a3	98	typedef struct
AnnaBridge	189:f392fc9709a3	99	{
AnnaBridge	189:f392fc9709a3	100	uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
AnnaBridge	189:f392fc9709a3	101
AnnaBridge	189:f392fc9709a3	102	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
AnnaBridge	189:f392fc9709a3	103
AnnaBridge	189:f392fc9709a3	104	uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
AnnaBridge	189:f392fc9709a3	105	This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
AnnaBridge	189:f392fc9709a3	106
AnnaBridge	189:f392fc9709a3	107	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
AnnaBridge	189:f392fc9709a3	108
AnnaBridge	189:f392fc9709a3	109	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
AnnaBridge	189:f392fc9709a3	110	This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
AnnaBridge	189:f392fc9709a3	111
AnnaBridge	189:f392fc9709a3	112	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
AnnaBridge	189:f392fc9709a3	113
AnnaBridge	189:f392fc9709a3	114	uint32_t Parity; /*!< Specifies the parity mode.
AnnaBridge	189:f392fc9709a3	115	This parameter can be a value of @ref LPUART_LL_EC_PARITY.
AnnaBridge	189:f392fc9709a3	116
AnnaBridge	189:f392fc9709a3	117	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
AnnaBridge	189:f392fc9709a3	118
AnnaBridge	189:f392fc9709a3	119	uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
AnnaBridge	189:f392fc9709a3	120	This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
AnnaBridge	189:f392fc9709a3	121
AnnaBridge	189:f392fc9709a3	122	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
AnnaBridge	189:f392fc9709a3	123
AnnaBridge	189:f392fc9709a3	124	uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
AnnaBridge	189:f392fc9709a3	125	This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
AnnaBridge	189:f392fc9709a3	126
AnnaBridge	189:f392fc9709a3	127	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
AnnaBridge	189:f392fc9709a3	128
AnnaBridge	189:f392fc9709a3	129	} LL_LPUART_InitTypeDef;
AnnaBridge	189:f392fc9709a3	130
AnnaBridge	189:f392fc9709a3	131	/**
AnnaBridge	189:f392fc9709a3	132	* @}
AnnaBridge	189:f392fc9709a3	133	*/
AnnaBridge	189:f392fc9709a3	134	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	135
AnnaBridge	189:f392fc9709a3	136	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	137	/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
AnnaBridge	189:f392fc9709a3	138	* @{
AnnaBridge	189:f392fc9709a3	139	*/
AnnaBridge	189:f392fc9709a3	140
AnnaBridge	189:f392fc9709a3	141	/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	189:f392fc9709a3	142	* @brief Flags defines which can be used with LL_LPUART_WriteReg function
AnnaBridge	189:f392fc9709a3	143	* @{
AnnaBridge	189:f392fc9709a3	144	*/
AnnaBridge	189:f392fc9709a3	145	#define LL_LPUART_ICR_PECF USART_ICR_PECF /!< Parity error flag /
AnnaBridge	189:f392fc9709a3	146	#define LL_LPUART_ICR_FECF USART_ICR_FECF /!< Framing error flag /
AnnaBridge	189:f392fc9709a3	147	#define LL_LPUART_ICR_NCF USART_ICR_NCF /!< Noise detected flag /
AnnaBridge	189:f392fc9709a3	148	#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /!< Overrun error flag /
AnnaBridge	189:f392fc9709a3	149	#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /!< Idle line detected flag /
AnnaBridge	189:f392fc9709a3	150	#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /!< Transmission complete flag /
AnnaBridge	189:f392fc9709a3	151	#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /!< CTS flag /
AnnaBridge	189:f392fc9709a3	152	#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /!< Character match flag /
AnnaBridge	189:f392fc9709a3	153	#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /!< Wakeup from Stop mode flag /
AnnaBridge	189:f392fc9709a3	154	/**
AnnaBridge	189:f392fc9709a3	155	* @}
AnnaBridge	189:f392fc9709a3	156	*/
AnnaBridge	189:f392fc9709a3	157
AnnaBridge	189:f392fc9709a3	158	/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	159	* @brief Flags defines which can be used with LL_LPUART_ReadReg function
AnnaBridge	189:f392fc9709a3	160	* @{
AnnaBridge	189:f392fc9709a3	161	*/
AnnaBridge	189:f392fc9709a3	162	#define LL_LPUART_ISR_PE USART_ISR_PE /!< Parity error flag /
AnnaBridge	189:f392fc9709a3	163	#define LL_LPUART_ISR_FE USART_ISR_FE /!< Framing error flag /
AnnaBridge	189:f392fc9709a3	164	#define LL_LPUART_ISR_NE USART_ISR_NE /!< Noise detected flag /
AnnaBridge	189:f392fc9709a3	165	#define LL_LPUART_ISR_ORE USART_ISR_ORE /!< Overrun error flag /
AnnaBridge	189:f392fc9709a3	166	#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /!< Idle line detected flag /
AnnaBridge	189:f392fc9709a3	167	#define LL_LPUART_ISR_RXNE USART_ISR_RXNE /!< Read data register not empty flag /
AnnaBridge	189:f392fc9709a3	168	#define LL_LPUART_ISR_TC USART_ISR_TC /!< Transmission complete flag /
AnnaBridge	189:f392fc9709a3	169	#define LL_LPUART_ISR_TXE USART_ISR_TXE /!< Transmit data register empty flag /
AnnaBridge	189:f392fc9709a3	170	#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /!< CTS interrupt flag /
AnnaBridge	189:f392fc9709a3	171	#define LL_LPUART_ISR_CTS USART_ISR_CTS /!< CTS flag /
AnnaBridge	189:f392fc9709a3	172	#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /!< Busy flag /
AnnaBridge	189:f392fc9709a3	173	#define LL_LPUART_ISR_CMF USART_ISR_CMF /!< Character match flag /
AnnaBridge	189:f392fc9709a3	174	#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /!< Send break flag /
AnnaBridge	189:f392fc9709a3	175	#define LL_LPUART_ISR_RWU USART_ISR_RWU /!< Receiver wakeup from Mute mode flag /
AnnaBridge	189:f392fc9709a3	176	#define LL_LPUART_ISR_WUF USART_ISR_WUF /!< Wakeup from Stop mode flag /
AnnaBridge	189:f392fc9709a3	177	#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /!< Transmit enable acknowledge flag /
AnnaBridge	189:f392fc9709a3	178	#define LL_LPUART_ISR_REACK USART_ISR_REACK /!< Receive enable acknowledge flag /
AnnaBridge	189:f392fc9709a3	179	/**
AnnaBridge	189:f392fc9709a3	180	* @}
AnnaBridge	189:f392fc9709a3	181	*/
AnnaBridge	189:f392fc9709a3	182
AnnaBridge	189:f392fc9709a3	183	/** @defgroup LPUART_LL_EC_IT IT Defines
AnnaBridge	189:f392fc9709a3	184	* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
AnnaBridge	189:f392fc9709a3	185	* @{
AnnaBridge	189:f392fc9709a3	186	*/
AnnaBridge	189:f392fc9709a3	187	#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /!< IDLE interrupt enable /
AnnaBridge	189:f392fc9709a3	188	#define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /!< Read data register not empty interrupt enable /
AnnaBridge	189:f392fc9709a3	189	#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /!< Transmission complete interrupt enable /
AnnaBridge	189:f392fc9709a3	190	#define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /!< Transmit data register empty interrupt enable /
AnnaBridge	189:f392fc9709a3	191	#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /!< Parity error /
AnnaBridge	189:f392fc9709a3	192	#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /!< Character match interrupt enable /
AnnaBridge	189:f392fc9709a3	193	#define LL_LPUART_CR3_EIE USART_CR3_EIE /!< Error interrupt enable /
AnnaBridge	189:f392fc9709a3	194	#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /!< CTS interrupt enable /
AnnaBridge	189:f392fc9709a3	195	#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /!< Wakeup from Stop mode interrupt enable /
AnnaBridge	189:f392fc9709a3	196	/**
AnnaBridge	189:f392fc9709a3	197	* @}
AnnaBridge	189:f392fc9709a3	198	*/
AnnaBridge	189:f392fc9709a3	199
AnnaBridge	189:f392fc9709a3	200	/** @defgroup LPUART_LL_EC_DIRECTION Direction
AnnaBridge	189:f392fc9709a3	201	* @{
AnnaBridge	189:f392fc9709a3	202	*/
AnnaBridge	189:f392fc9709a3	203	#define LL_LPUART_DIRECTION_NONE (uint32_t)0x00000000U /!< Transmitter and Receiver are disabled /
AnnaBridge	189:f392fc9709a3	204	#define LL_LPUART_DIRECTION_RX USART_CR1_RE /!< Transmitter is disabled and Receiver is enabled /
AnnaBridge	189:f392fc9709a3	205	#define LL_LPUART_DIRECTION_TX USART_CR1_TE /!< Transmitter is enabled and Receiver is disabled /
AnnaBridge	189:f392fc9709a3	206	#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE \|USART_CR1_RE) /!< Transmitter and Receiver are enabled /
AnnaBridge	189:f392fc9709a3	207	/**
AnnaBridge	189:f392fc9709a3	208	* @}
AnnaBridge	189:f392fc9709a3	209	*/
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211	/** @defgroup LPUART_LL_EC_PARITY Parity Control
AnnaBridge	189:f392fc9709a3	212	* @{
AnnaBridge	189:f392fc9709a3	213	*/
AnnaBridge	189:f392fc9709a3	214	#define LL_LPUART_PARITY_NONE (uint32_t)0x00000000U /!< Parity control disabled /
AnnaBridge	189:f392fc9709a3	215	#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /!< Parity control enabled and Even Parity is selected /
AnnaBridge	189:f392fc9709a3	216	#define LL_LPUART_PARITY_ODD (USART_CR1_PCE \| USART_CR1_PS) /!< Parity control enabled and Odd Parity is selected /
AnnaBridge	189:f392fc9709a3	217	/**
AnnaBridge	189:f392fc9709a3	218	* @}
AnnaBridge	189:f392fc9709a3	219	*/
AnnaBridge	189:f392fc9709a3	220
AnnaBridge	189:f392fc9709a3	221	/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
AnnaBridge	189:f392fc9709a3	222	* @{
AnnaBridge	189:f392fc9709a3	223	*/
AnnaBridge	189:f392fc9709a3	224	#define LL_LPUART_WAKEUP_IDLELINE (uint32_t)0x00000000U /!< LPUART wake up from Mute mode on Idle Line /
AnnaBridge	189:f392fc9709a3	225	#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /!< LPUART wake up from Mute mode on Address Mark /
AnnaBridge	189:f392fc9709a3	226	/**
AnnaBridge	189:f392fc9709a3	227	* @}
AnnaBridge	189:f392fc9709a3	228	*/
AnnaBridge	189:f392fc9709a3	229
AnnaBridge	189:f392fc9709a3	230	/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
AnnaBridge	189:f392fc9709a3	231	* @{
AnnaBridge	189:f392fc9709a3	232	*/
AnnaBridge	189:f392fc9709a3	233	#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /!< 7 bits word length : Start bit, 7 data bits, n stop bits /
AnnaBridge	189:f392fc9709a3	234	#define LL_LPUART_DATAWIDTH_8B (uint32_t)0x00000000U /!< 8 bits word length : Start bit, 8 data bits, n stop bits /
AnnaBridge	189:f392fc9709a3	235	#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /!< 9 bits word length : Start bit, 9 data bits, n stop bits /
AnnaBridge	189:f392fc9709a3	236	/**
AnnaBridge	189:f392fc9709a3	237	* @}
AnnaBridge	189:f392fc9709a3	238	*/
AnnaBridge	189:f392fc9709a3	239
AnnaBridge	189:f392fc9709a3	240	/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
AnnaBridge	189:f392fc9709a3	241	* @{
AnnaBridge	189:f392fc9709a3	242	*/
AnnaBridge	189:f392fc9709a3	243	#define LL_LPUART_STOPBITS_1 (uint32_t)0x00000000U /!< 1 stop bit /
AnnaBridge	189:f392fc9709a3	244	#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /!< 2 stop bits /
AnnaBridge	189:f392fc9709a3	245	/**
AnnaBridge	189:f392fc9709a3	246	* @}
AnnaBridge	189:f392fc9709a3	247	*/
AnnaBridge	189:f392fc9709a3	248
AnnaBridge	189:f392fc9709a3	249	/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
AnnaBridge	189:f392fc9709a3	250	* @{
AnnaBridge	189:f392fc9709a3	251	*/
AnnaBridge	189:f392fc9709a3	252	#define LL_LPUART_TXRX_STANDARD (uint32_t)0x00000000U /!< TX/RX pins are used as defined in standard pinout /
AnnaBridge	189:f392fc9709a3	253	#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /!< TX and RX pins functions are swapped. /
AnnaBridge	189:f392fc9709a3	254	/**
AnnaBridge	189:f392fc9709a3	255	* @}
AnnaBridge	189:f392fc9709a3	256	*/
AnnaBridge	189:f392fc9709a3	257
AnnaBridge	189:f392fc9709a3	258	/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
AnnaBridge	189:f392fc9709a3	259	* @{
AnnaBridge	189:f392fc9709a3	260	*/
AnnaBridge	189:f392fc9709a3	261	#define LL_LPUART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /!< RX pin signal works using the standard logic levels /
AnnaBridge	189:f392fc9709a3	262	#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /!< RX pin signal values are inverted. /
AnnaBridge	189:f392fc9709a3	263	/**
AnnaBridge	189:f392fc9709a3	264	* @}
AnnaBridge	189:f392fc9709a3	265	*/
AnnaBridge	189:f392fc9709a3	266
AnnaBridge	189:f392fc9709a3	267	/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
AnnaBridge	189:f392fc9709a3	268	* @{
AnnaBridge	189:f392fc9709a3	269	*/
AnnaBridge	189:f392fc9709a3	270	#define LL_LPUART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /!< TX pin signal works using the standard logic levels /
AnnaBridge	189:f392fc9709a3	271	#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /!< TX pin signal values are inverted. /
AnnaBridge	189:f392fc9709a3	272	/**
AnnaBridge	189:f392fc9709a3	273	* @}
AnnaBridge	189:f392fc9709a3	274	*/
AnnaBridge	189:f392fc9709a3	275
AnnaBridge	189:f392fc9709a3	276	/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
AnnaBridge	189:f392fc9709a3	277	* @{
AnnaBridge	189:f392fc9709a3	278	*/
AnnaBridge	189:f392fc9709a3	279	#define LL_LPUART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) /
AnnaBridge	189:f392fc9709a3	280	#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. /
AnnaBridge	189:f392fc9709a3	281	/**
AnnaBridge	189:f392fc9709a3	282	* @}
AnnaBridge	189:f392fc9709a3	283	*/
AnnaBridge	189:f392fc9709a3	284
AnnaBridge	189:f392fc9709a3	285	/** @defgroup LPUART_LL_EC_BITORDER Bit Order
AnnaBridge	189:f392fc9709a3	286	* @{
AnnaBridge	189:f392fc9709a3	287	*/
AnnaBridge	189:f392fc9709a3	288	#define LL_LPUART_BITORDER_LSBFIRST (uint32_t)0x00000000U /!< data is transmitted/received with data bit 0 first, following the start bit /
AnnaBridge	189:f392fc9709a3	289	#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /!< data is transmitted/received with the MSB first, following the start bit /
AnnaBridge	189:f392fc9709a3	290	/**
AnnaBridge	189:f392fc9709a3	291	* @}
AnnaBridge	189:f392fc9709a3	292	*/
AnnaBridge	189:f392fc9709a3	293
AnnaBridge	189:f392fc9709a3	294	/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
AnnaBridge	189:f392fc9709a3	295	* @{
AnnaBridge	189:f392fc9709a3	296	*/
AnnaBridge	189:f392fc9709a3	297	#define LL_LPUART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /!< 4-bit address detection method selected /
AnnaBridge	189:f392fc9709a3	298	#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /!< 7-bit address detection (in 8-bit data mode) method selected /
AnnaBridge	189:f392fc9709a3	299	/**
AnnaBridge	189:f392fc9709a3	300	* @}
AnnaBridge	189:f392fc9709a3	301	*/
AnnaBridge	189:f392fc9709a3	302
AnnaBridge	189:f392fc9709a3	303	/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
AnnaBridge	189:f392fc9709a3	304	* @{
AnnaBridge	189:f392fc9709a3	305	*/
AnnaBridge	189:f392fc9709a3	306	#define LL_LPUART_HWCONTROL_NONE (uint32_t)0x00000000U /!< CTS and RTS hardware flow control disabled /
AnnaBridge	189:f392fc9709a3	307	#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /!< RTS output enabled, data is only requested when there is space in the receive buffer /
AnnaBridge	189:f392fc9709a3	308	#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) /
AnnaBridge	189:f392fc9709a3	309	#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE \| USART_CR3_CTSE) /!< CTS and RTS hardware flow control enabled /
AnnaBridge	189:f392fc9709a3	310	/**
AnnaBridge	189:f392fc9709a3	311	* @}
AnnaBridge	189:f392fc9709a3	312	*/
AnnaBridge	189:f392fc9709a3	313
AnnaBridge	189:f392fc9709a3	314	/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
AnnaBridge	189:f392fc9709a3	315	* @{
AnnaBridge	189:f392fc9709a3	316	*/
AnnaBridge	189:f392fc9709a3	317	#define LL_LPUART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /!< Wake up active on address match /
AnnaBridge	189:f392fc9709a3	318	#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /!< Wake up active on Start bit detection /
AnnaBridge	189:f392fc9709a3	319	#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 \| USART_CR3_WUS_1) /!< Wake up active on RXNE /
AnnaBridge	189:f392fc9709a3	320	/**
AnnaBridge	189:f392fc9709a3	321	* @}
AnnaBridge	189:f392fc9709a3	322	*/
AnnaBridge	189:f392fc9709a3	323
AnnaBridge	189:f392fc9709a3	324	/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
AnnaBridge	189:f392fc9709a3	325	* @{
AnnaBridge	189:f392fc9709a3	326	*/
AnnaBridge	189:f392fc9709a3	327	#define LL_LPUART_DE_POLARITY_HIGH (uint32_t)0x00000000U /!< DE signal is active high /
AnnaBridge	189:f392fc9709a3	328	#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /!< DE signal is active low /
AnnaBridge	189:f392fc9709a3	329	/**
AnnaBridge	189:f392fc9709a3	330	* @}
AnnaBridge	189:f392fc9709a3	331	*/
AnnaBridge	189:f392fc9709a3	332
AnnaBridge	189:f392fc9709a3	333	/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
AnnaBridge	189:f392fc9709a3	334	* @{
AnnaBridge	189:f392fc9709a3	335	*/
AnnaBridge	189:f392fc9709a3	336	#define LL_LPUART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /!< Get address of data register used for transmission /
AnnaBridge	189:f392fc9709a3	337	#define LL_LPUART_DMA_REG_DATA_RECEIVE (uint32_t)1U /!< Get address of data register used for reception /
AnnaBridge	189:f392fc9709a3	338	/**
AnnaBridge	189:f392fc9709a3	339	* @}
AnnaBridge	189:f392fc9709a3	340	*/
AnnaBridge	189:f392fc9709a3	341
AnnaBridge	189:f392fc9709a3	342	/**
AnnaBridge	189:f392fc9709a3	343	* @}
AnnaBridge	189:f392fc9709a3	344	*/
AnnaBridge	189:f392fc9709a3	345
AnnaBridge	189:f392fc9709a3	346	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	347	/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
AnnaBridge	189:f392fc9709a3	348	* @{
AnnaBridge	189:f392fc9709a3	349	*/
AnnaBridge	189:f392fc9709a3	350
AnnaBridge	189:f392fc9709a3	351	/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	189:f392fc9709a3	352	* @{
AnnaBridge	189:f392fc9709a3	353	*/
AnnaBridge	189:f392fc9709a3	354
AnnaBridge	189:f392fc9709a3	355	/**
AnnaBridge	189:f392fc9709a3	356	* @brief Write a value in LPUART register
AnnaBridge	189:f392fc9709a3	357	* @param __INSTANCE__ LPUART Instance
AnnaBridge	189:f392fc9709a3	358	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	359	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	360	* @retval None
AnnaBridge	189:f392fc9709a3	361	*/
AnnaBridge	189:f392fc9709a3	362	#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	363
AnnaBridge	189:f392fc9709a3	364	/**
AnnaBridge	189:f392fc9709a3	365	* @brief Read a value in LPUART register
AnnaBridge	189:f392fc9709a3	366	* @param __INSTANCE__ LPUART Instance
AnnaBridge	189:f392fc9709a3	367	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	368	* @retval Register value
AnnaBridge	189:f392fc9709a3	369	*/
AnnaBridge	189:f392fc9709a3	370	#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	189:f392fc9709a3	371	/**
AnnaBridge	189:f392fc9709a3	372	* @}
AnnaBridge	189:f392fc9709a3	373	*/
AnnaBridge	189:f392fc9709a3	374
AnnaBridge	189:f392fc9709a3	375	/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
AnnaBridge	189:f392fc9709a3	376	* @{
AnnaBridge	189:f392fc9709a3	377	*/
AnnaBridge	189:f392fc9709a3	378
AnnaBridge	189:f392fc9709a3	379	/**
AnnaBridge	189:f392fc9709a3	380	* @brief Compute LPUARTDIV value according to Peripheral Clock and
AnnaBridge	189:f392fc9709a3	381	* expected Baud Rate (20-bit value of LPUARTDIV is returned)
AnnaBridge	189:f392fc9709a3	382	* @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
AnnaBridge	189:f392fc9709a3	383	* @param __BAUDRATE__ Baud Rate value to achieve
AnnaBridge	189:f392fc9709a3	384	* @retval LPUARTDIV value to be used for BRR register filling
AnnaBridge	189:f392fc9709a3	385	*/
AnnaBridge	189:f392fc9709a3	386	#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
AnnaBridge	189:f392fc9709a3	387
AnnaBridge	189:f392fc9709a3	388	/**
AnnaBridge	189:f392fc9709a3	389	* @}
AnnaBridge	189:f392fc9709a3	390	*/
AnnaBridge	189:f392fc9709a3	391
AnnaBridge	189:f392fc9709a3	392	/**
AnnaBridge	189:f392fc9709a3	393	* @}
AnnaBridge	189:f392fc9709a3	394	*/
AnnaBridge	189:f392fc9709a3	395
AnnaBridge	189:f392fc9709a3	396	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	397	/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
AnnaBridge	189:f392fc9709a3	398	* @{
AnnaBridge	189:f392fc9709a3	399	*/
AnnaBridge	189:f392fc9709a3	400
AnnaBridge	189:f392fc9709a3	401	/** @defgroup LPUART_LL_EF_Configuration Configuration functions
AnnaBridge	189:f392fc9709a3	402	* @{
AnnaBridge	189:f392fc9709a3	403	*/
AnnaBridge	189:f392fc9709a3	404
AnnaBridge	189:f392fc9709a3	405	/**
AnnaBridge	189:f392fc9709a3	406	* @brief LPUART Enable
AnnaBridge	189:f392fc9709a3	407	* @rmtoll CR1 UE LL_LPUART_Enable
AnnaBridge	189:f392fc9709a3	408	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	409	* @retval None
AnnaBridge	189:f392fc9709a3	410	*/
AnnaBridge	189:f392fc9709a3	411	__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	412	{
AnnaBridge	189:f392fc9709a3	413	SET_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge	189:f392fc9709a3	414	}
AnnaBridge	189:f392fc9709a3	415
AnnaBridge	189:f392fc9709a3	416	/**
AnnaBridge	189:f392fc9709a3	417	* @brief LPUART Disable
AnnaBridge	189:f392fc9709a3	418	* @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
AnnaBridge	189:f392fc9709a3	419	* and current operations are discarded. The configuration of the LPUART is kept, but all the status
AnnaBridge	189:f392fc9709a3	420	* flags, in the LPUARTx_ISR are set to their default values.
AnnaBridge	189:f392fc9709a3	421	* @note In order to go into low-power mode without generating errors on the line,
AnnaBridge	189:f392fc9709a3	422	* the TE bit must be reset before and the software must wait
AnnaBridge	189:f392fc9709a3	423	* for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
AnnaBridge	189:f392fc9709a3	424	* The DMA requests are also reset when UE = 0 so the DMA channel must
AnnaBridge	189:f392fc9709a3	425	* be disabled before resetting the UE bit.
AnnaBridge	189:f392fc9709a3	426	* @rmtoll CR1 UE LL_LPUART_Disable
AnnaBridge	189:f392fc9709a3	427	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	428	* @retval None
AnnaBridge	189:f392fc9709a3	429	*/
AnnaBridge	189:f392fc9709a3	430	__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	431	{
AnnaBridge	189:f392fc9709a3	432	CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge	189:f392fc9709a3	433	}
AnnaBridge	189:f392fc9709a3	434
AnnaBridge	189:f392fc9709a3	435	/**
AnnaBridge	189:f392fc9709a3	436	* @brief Indicate if LPUART is enabled
AnnaBridge	189:f392fc9709a3	437	* @rmtoll CR1 UE LL_LPUART_IsEnabled
AnnaBridge	189:f392fc9709a3	438	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	439	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	440	*/
AnnaBridge	189:f392fc9709a3	441	__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	442	{
AnnaBridge	189:f392fc9709a3	443	return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
AnnaBridge	189:f392fc9709a3	444	}
AnnaBridge	189:f392fc9709a3	445
AnnaBridge	189:f392fc9709a3	446	/**
AnnaBridge	189:f392fc9709a3	447	* @brief LPUART enabled in STOP Mode
AnnaBridge	189:f392fc9709a3	448	* @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
AnnaBridge	189:f392fc9709a3	449	* LPUART clock selection is HSI or LSE in RCC.
AnnaBridge	189:f392fc9709a3	450	* @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
AnnaBridge	189:f392fc9709a3	451	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	452	* @retval None
AnnaBridge	189:f392fc9709a3	453	*/
AnnaBridge	189:f392fc9709a3	454	__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	455	{
AnnaBridge	189:f392fc9709a3	456	SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge	189:f392fc9709a3	457	}
AnnaBridge	189:f392fc9709a3	458
AnnaBridge	189:f392fc9709a3	459	/**
AnnaBridge	189:f392fc9709a3	460	* @brief LPUART disabled in STOP Mode
AnnaBridge	189:f392fc9709a3	461	* @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
AnnaBridge	189:f392fc9709a3	462	* @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
AnnaBridge	189:f392fc9709a3	463	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	464	* @retval None
AnnaBridge	189:f392fc9709a3	465	*/
AnnaBridge	189:f392fc9709a3	466	__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	467	{
AnnaBridge	189:f392fc9709a3	468	CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge	189:f392fc9709a3	469	}
AnnaBridge	189:f392fc9709a3	470
AnnaBridge	189:f392fc9709a3	471	/**
AnnaBridge	189:f392fc9709a3	472	* @brief Indicate if LPUART is enabled in STOP Mode
AnnaBridge	189:f392fc9709a3	473	* (able to wake up MCU from Stop mode or not)
AnnaBridge	189:f392fc9709a3	474	* @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
AnnaBridge	189:f392fc9709a3	475	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	476	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	477	*/
AnnaBridge	189:f392fc9709a3	478	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	479	{
AnnaBridge	189:f392fc9709a3	480	return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
AnnaBridge	189:f392fc9709a3	481	}
AnnaBridge	189:f392fc9709a3	482
AnnaBridge	189:f392fc9709a3	483	/**
AnnaBridge	189:f392fc9709a3	484	* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
AnnaBridge	189:f392fc9709a3	485	* @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
AnnaBridge	189:f392fc9709a3	486	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	487	* @retval None
AnnaBridge	189:f392fc9709a3	488	*/
AnnaBridge	189:f392fc9709a3	489	__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	490	{
AnnaBridge	189:f392fc9709a3	491	SET_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge	189:f392fc9709a3	492	}
AnnaBridge	189:f392fc9709a3	493
AnnaBridge	189:f392fc9709a3	494	/**
AnnaBridge	189:f392fc9709a3	495	* @brief Receiver Disable
AnnaBridge	189:f392fc9709a3	496	* @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
AnnaBridge	189:f392fc9709a3	497	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	498	* @retval None
AnnaBridge	189:f392fc9709a3	499	*/
AnnaBridge	189:f392fc9709a3	500	__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	501	{
AnnaBridge	189:f392fc9709a3	502	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge	189:f392fc9709a3	503	}
AnnaBridge	189:f392fc9709a3	504
AnnaBridge	189:f392fc9709a3	505	/**
AnnaBridge	189:f392fc9709a3	506	* @brief Transmitter Enable
AnnaBridge	189:f392fc9709a3	507	* @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
AnnaBridge	189:f392fc9709a3	508	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	509	* @retval None
AnnaBridge	189:f392fc9709a3	510	*/
AnnaBridge	189:f392fc9709a3	511	__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	512	{
AnnaBridge	189:f392fc9709a3	513	SET_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge	189:f392fc9709a3	514	}
AnnaBridge	189:f392fc9709a3	515
AnnaBridge	189:f392fc9709a3	516	/**
AnnaBridge	189:f392fc9709a3	517	* @brief Transmitter Disable
AnnaBridge	189:f392fc9709a3	518	* @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
AnnaBridge	189:f392fc9709a3	519	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	520	* @retval None
AnnaBridge	189:f392fc9709a3	521	*/
AnnaBridge	189:f392fc9709a3	522	__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	523	{
AnnaBridge	189:f392fc9709a3	524	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge	189:f392fc9709a3	525	}
AnnaBridge	189:f392fc9709a3	526
AnnaBridge	189:f392fc9709a3	527	/**
AnnaBridge	189:f392fc9709a3	528	* @brief Configure simultaneously enabled/disabled states
AnnaBridge	189:f392fc9709a3	529	* of Transmitter and Receiver
AnnaBridge	189:f392fc9709a3	530	* @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
AnnaBridge	189:f392fc9709a3	531	* CR1 TE LL_LPUART_SetTransferDirection
AnnaBridge	189:f392fc9709a3	532	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	533	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	534	* @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge	189:f392fc9709a3	535	* @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge	189:f392fc9709a3	536	* @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge	189:f392fc9709a3	537	* @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge	189:f392fc9709a3	538	* @retval None
AnnaBridge	189:f392fc9709a3	539	*/
AnnaBridge	189:f392fc9709a3	540	__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
AnnaBridge	189:f392fc9709a3	541	{
AnnaBridge	189:f392fc9709a3	542	MODIFY_REG(LPUARTx->CR1, USART_CR1_RE \| USART_CR1_TE, TransferDirection);
AnnaBridge	189:f392fc9709a3	543	}
AnnaBridge	189:f392fc9709a3	544
AnnaBridge	189:f392fc9709a3	545	/**
AnnaBridge	189:f392fc9709a3	546	* @brief Return enabled/disabled states of Transmitter and Receiver
AnnaBridge	189:f392fc9709a3	547	* @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
AnnaBridge	189:f392fc9709a3	548	* CR1 TE LL_LPUART_GetTransferDirection
AnnaBridge	189:f392fc9709a3	549	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	550	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	551	* @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge	189:f392fc9709a3	552	* @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge	189:f392fc9709a3	553	* @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge	189:f392fc9709a3	554	* @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge	189:f392fc9709a3	555	*/
AnnaBridge	189:f392fc9709a3	556	__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	557	{
AnnaBridge	189:f392fc9709a3	558	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE \| USART_CR1_TE));
AnnaBridge	189:f392fc9709a3	559	}
AnnaBridge	189:f392fc9709a3	560
AnnaBridge	189:f392fc9709a3	561	/**
AnnaBridge	189:f392fc9709a3	562	* @brief Configure Parity (enabled/disabled and parity mode if enabled)
AnnaBridge	189:f392fc9709a3	563	* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
AnnaBridge	189:f392fc9709a3	564	* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
AnnaBridge	189:f392fc9709a3	565	* (depending on data width) and parity is checked on the received data.
AnnaBridge	189:f392fc9709a3	566	* @rmtoll CR1 PS LL_LPUART_SetParity\n
AnnaBridge	189:f392fc9709a3	567	* CR1 PCE LL_LPUART_SetParity
AnnaBridge	189:f392fc9709a3	568	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	569	* @param Parity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	570	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	189:f392fc9709a3	571	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	572	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	189:f392fc9709a3	573	* @retval None
AnnaBridge	189:f392fc9709a3	574	*/
AnnaBridge	189:f392fc9709a3	575	__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
AnnaBridge	189:f392fc9709a3	576	{
AnnaBridge	189:f392fc9709a3	577	MODIFY_REG(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE, Parity);
AnnaBridge	189:f392fc9709a3	578	}
AnnaBridge	189:f392fc9709a3	579
AnnaBridge	189:f392fc9709a3	580	/**
AnnaBridge	189:f392fc9709a3	581	* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
AnnaBridge	189:f392fc9709a3	582	* @rmtoll CR1 PS LL_LPUART_GetParity\n
AnnaBridge	189:f392fc9709a3	583	* CR1 PCE LL_LPUART_GetParity
AnnaBridge	189:f392fc9709a3	584	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	585	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	586	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	189:f392fc9709a3	587	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	588	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	189:f392fc9709a3	589	*/
AnnaBridge	189:f392fc9709a3	590	__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	591	{
AnnaBridge	189:f392fc9709a3	592	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE));
AnnaBridge	189:f392fc9709a3	593	}
AnnaBridge	189:f392fc9709a3	594
AnnaBridge	189:f392fc9709a3	595	/**
AnnaBridge	189:f392fc9709a3	596	* @brief Set Receiver Wake Up method from Mute mode.
AnnaBridge	189:f392fc9709a3	597	* @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
AnnaBridge	189:f392fc9709a3	598	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	599	* @param Method This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	600	* @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge	189:f392fc9709a3	601	* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge	189:f392fc9709a3	602	* @retval None
AnnaBridge	189:f392fc9709a3	603	*/
AnnaBridge	189:f392fc9709a3	604	__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
AnnaBridge	189:f392fc9709a3	605	{
AnnaBridge	189:f392fc9709a3	606	MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
AnnaBridge	189:f392fc9709a3	607	}
AnnaBridge	189:f392fc9709a3	608
AnnaBridge	189:f392fc9709a3	609	/**
AnnaBridge	189:f392fc9709a3	610	* @brief Return Receiver Wake Up method from Mute mode
AnnaBridge	189:f392fc9709a3	611	* @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
AnnaBridge	189:f392fc9709a3	612	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	613	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	614	* @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge	189:f392fc9709a3	615	* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge	189:f392fc9709a3	616	*/
AnnaBridge	189:f392fc9709a3	617	__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	618	{
AnnaBridge	189:f392fc9709a3	619	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
AnnaBridge	189:f392fc9709a3	620	}
AnnaBridge	189:f392fc9709a3	621
AnnaBridge	189:f392fc9709a3	622	/**
AnnaBridge	189:f392fc9709a3	623	* @brief Set Word length (nb of data bits, excluding start and stop bits)
AnnaBridge	189:f392fc9709a3	624	* @rmtoll CR1 M LL_LPUART_SetDataWidth
AnnaBridge	189:f392fc9709a3	625	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	626	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	627	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	189:f392fc9709a3	628	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	189:f392fc9709a3	629	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	189:f392fc9709a3	630	* @retval None
AnnaBridge	189:f392fc9709a3	631	*/
AnnaBridge	189:f392fc9709a3	632	__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
AnnaBridge	189:f392fc9709a3	633	{
AnnaBridge	189:f392fc9709a3	634	MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
AnnaBridge	189:f392fc9709a3	635	}
AnnaBridge	189:f392fc9709a3	636
AnnaBridge	189:f392fc9709a3	637	/**
AnnaBridge	189:f392fc9709a3	638	* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
AnnaBridge	189:f392fc9709a3	639	* @rmtoll CR1 M LL_LPUART_GetDataWidth
AnnaBridge	189:f392fc9709a3	640	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	641	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	642	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	189:f392fc9709a3	643	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	189:f392fc9709a3	644	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	189:f392fc9709a3	645	*/
AnnaBridge	189:f392fc9709a3	646	__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	647	{
AnnaBridge	189:f392fc9709a3	648	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
AnnaBridge	189:f392fc9709a3	649	}
AnnaBridge	189:f392fc9709a3	650
AnnaBridge	189:f392fc9709a3	651	/**
AnnaBridge	189:f392fc9709a3	652	* @brief Allow switch between Mute Mode and Active mode
AnnaBridge	189:f392fc9709a3	653	* @rmtoll CR1 MME LL_LPUART_EnableMuteMode
AnnaBridge	189:f392fc9709a3	654	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	655	* @retval None
AnnaBridge	189:f392fc9709a3	656	*/
AnnaBridge	189:f392fc9709a3	657	__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	658	{
AnnaBridge	189:f392fc9709a3	659	SET_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge	189:f392fc9709a3	660	}
AnnaBridge	189:f392fc9709a3	661
AnnaBridge	189:f392fc9709a3	662	/**
AnnaBridge	189:f392fc9709a3	663	* @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
AnnaBridge	189:f392fc9709a3	664	* @rmtoll CR1 MME LL_LPUART_DisableMuteMode
AnnaBridge	189:f392fc9709a3	665	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	666	* @retval None
AnnaBridge	189:f392fc9709a3	667	*/
AnnaBridge	189:f392fc9709a3	668	__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	669	{
AnnaBridge	189:f392fc9709a3	670	CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge	189:f392fc9709a3	671	}
AnnaBridge	189:f392fc9709a3	672
AnnaBridge	189:f392fc9709a3	673	/**
AnnaBridge	189:f392fc9709a3	674	* @brief Indicate if switch between Mute Mode and Active mode is allowed
AnnaBridge	189:f392fc9709a3	675	* @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
AnnaBridge	189:f392fc9709a3	676	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	677	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	678	*/
AnnaBridge	189:f392fc9709a3	679	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	680	{
AnnaBridge	189:f392fc9709a3	681	return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
AnnaBridge	189:f392fc9709a3	682	}
AnnaBridge	189:f392fc9709a3	683
AnnaBridge	189:f392fc9709a3	684	/**
AnnaBridge	189:f392fc9709a3	685	* @brief Set the length of the stop bits
AnnaBridge	189:f392fc9709a3	686	* @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
AnnaBridge	189:f392fc9709a3	687	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	688	* @param StopBits This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	689	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	189:f392fc9709a3	690	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	189:f392fc9709a3	691	* @retval None
AnnaBridge	189:f392fc9709a3	692	*/
AnnaBridge	189:f392fc9709a3	693	__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
AnnaBridge	189:f392fc9709a3	694	{
AnnaBridge	189:f392fc9709a3	695	MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge	189:f392fc9709a3	696	}
AnnaBridge	189:f392fc9709a3	697
AnnaBridge	189:f392fc9709a3	698	/**
AnnaBridge	189:f392fc9709a3	699	* @brief Retrieve the length of the stop bits
AnnaBridge	189:f392fc9709a3	700	* @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
AnnaBridge	189:f392fc9709a3	701	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	702	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	703	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	189:f392fc9709a3	704	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	189:f392fc9709a3	705	*/
AnnaBridge	189:f392fc9709a3	706	__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	707	{
AnnaBridge	189:f392fc9709a3	708	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
AnnaBridge	189:f392fc9709a3	709	}
AnnaBridge	189:f392fc9709a3	710
AnnaBridge	189:f392fc9709a3	711	/**
AnnaBridge	189:f392fc9709a3	712	* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
AnnaBridge	189:f392fc9709a3	713	* @note Call of this function is equivalent to following function call sequence :
AnnaBridge	189:f392fc9709a3	714	* - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
AnnaBridge	189:f392fc9709a3	715	* - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
AnnaBridge	189:f392fc9709a3	716	* - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
AnnaBridge	189:f392fc9709a3	717	* @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
AnnaBridge	189:f392fc9709a3	718	* CR1 PCE LL_LPUART_ConfigCharacter\n
AnnaBridge	189:f392fc9709a3	719	* CR1 M LL_LPUART_ConfigCharacter\n
AnnaBridge	189:f392fc9709a3	720	* CR2 STOP LL_LPUART_ConfigCharacter
AnnaBridge	189:f392fc9709a3	721	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	722	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	723	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	189:f392fc9709a3	724	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	189:f392fc9709a3	725	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	189:f392fc9709a3	726	* @param Parity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	727	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	189:f392fc9709a3	728	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	729	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	189:f392fc9709a3	730	* @param StopBits This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	731	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	189:f392fc9709a3	732	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	189:f392fc9709a3	733	* @retval None
AnnaBridge	189:f392fc9709a3	734	*/
AnnaBridge	189:f392fc9709a3	735	__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
AnnaBridge	189:f392fc9709a3	736	uint32_t StopBits)
AnnaBridge	189:f392fc9709a3	737	{
AnnaBridge	189:f392fc9709a3	738	MODIFY_REG(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE \| USART_CR1_M, Parity \| DataWidth);
AnnaBridge	189:f392fc9709a3	739	MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge	189:f392fc9709a3	740	}
AnnaBridge	189:f392fc9709a3	741
AnnaBridge	189:f392fc9709a3	742	/**
AnnaBridge	189:f392fc9709a3	743	* @brief Configure TX/RX pins swapping setting.
AnnaBridge	189:f392fc9709a3	744	* @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
AnnaBridge	189:f392fc9709a3	745	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	746	* @param SwapConfig This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	747	* @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge	189:f392fc9709a3	748	* @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge	189:f392fc9709a3	749	* @retval None
AnnaBridge	189:f392fc9709a3	750	*/
AnnaBridge	189:f392fc9709a3	751	__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
AnnaBridge	189:f392fc9709a3	752	{
AnnaBridge	189:f392fc9709a3	753	MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
AnnaBridge	189:f392fc9709a3	754	}
AnnaBridge	189:f392fc9709a3	755
AnnaBridge	189:f392fc9709a3	756	/**
AnnaBridge	189:f392fc9709a3	757	* @brief Retrieve TX/RX pins swapping configuration.
AnnaBridge	189:f392fc9709a3	758	* @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
AnnaBridge	189:f392fc9709a3	759	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	760	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	761	* @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge	189:f392fc9709a3	762	* @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge	189:f392fc9709a3	763	*/
AnnaBridge	189:f392fc9709a3	764	__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	765	{
AnnaBridge	189:f392fc9709a3	766	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
AnnaBridge	189:f392fc9709a3	767	}
AnnaBridge	189:f392fc9709a3	768
AnnaBridge	189:f392fc9709a3	769	/**
AnnaBridge	189:f392fc9709a3	770	* @brief Configure RX pin active level logic
AnnaBridge	189:f392fc9709a3	771	* @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
AnnaBridge	189:f392fc9709a3	772	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	773	* @param PinInvMethod This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	774	* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	775	* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	776	* @retval None
AnnaBridge	189:f392fc9709a3	777	*/
AnnaBridge	189:f392fc9709a3	778	__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge	189:f392fc9709a3	779	{
AnnaBridge	189:f392fc9709a3	780	MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
AnnaBridge	189:f392fc9709a3	781	}
AnnaBridge	189:f392fc9709a3	782
AnnaBridge	189:f392fc9709a3	783	/**
AnnaBridge	189:f392fc9709a3	784	* @brief Retrieve RX pin active level logic configuration
AnnaBridge	189:f392fc9709a3	785	* @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
AnnaBridge	189:f392fc9709a3	786	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	787	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	788	* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	789	* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	790	*/
AnnaBridge	189:f392fc9709a3	791	__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	792	{
AnnaBridge	189:f392fc9709a3	793	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
AnnaBridge	189:f392fc9709a3	794	}
AnnaBridge	189:f392fc9709a3	795
AnnaBridge	189:f392fc9709a3	796	/**
AnnaBridge	189:f392fc9709a3	797	* @brief Configure TX pin active level logic
AnnaBridge	189:f392fc9709a3	798	* @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
AnnaBridge	189:f392fc9709a3	799	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	800	* @param PinInvMethod This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	801	* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	802	* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	803	* @retval None
AnnaBridge	189:f392fc9709a3	804	*/
AnnaBridge	189:f392fc9709a3	805	__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge	189:f392fc9709a3	806	{
AnnaBridge	189:f392fc9709a3	807	MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
AnnaBridge	189:f392fc9709a3	808	}
AnnaBridge	189:f392fc9709a3	809
AnnaBridge	189:f392fc9709a3	810	/**
AnnaBridge	189:f392fc9709a3	811	* @brief Retrieve TX pin active level logic configuration
AnnaBridge	189:f392fc9709a3	812	* @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
AnnaBridge	189:f392fc9709a3	813	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	814	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	815	* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	816	* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	817	*/
AnnaBridge	189:f392fc9709a3	818	__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	819	{
AnnaBridge	189:f392fc9709a3	820	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
AnnaBridge	189:f392fc9709a3	821	}
AnnaBridge	189:f392fc9709a3	822
AnnaBridge	189:f392fc9709a3	823	/**
AnnaBridge	189:f392fc9709a3	824	* @brief Configure Binary data logic.
AnnaBridge	189:f392fc9709a3	825	*
AnnaBridge	189:f392fc9709a3	826	* @note Allow to define how Logical data from the data register are send/received :
AnnaBridge	189:f392fc9709a3	827	* either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
AnnaBridge	189:f392fc9709a3	828	* @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
AnnaBridge	189:f392fc9709a3	829	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	830	* @param DataLogic This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	831	* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge	189:f392fc9709a3	832	* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge	189:f392fc9709a3	833	* @retval None
AnnaBridge	189:f392fc9709a3	834	*/
AnnaBridge	189:f392fc9709a3	835	__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
AnnaBridge	189:f392fc9709a3	836	{
AnnaBridge	189:f392fc9709a3	837	MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
AnnaBridge	189:f392fc9709a3	838	}
AnnaBridge	189:f392fc9709a3	839
AnnaBridge	189:f392fc9709a3	840	/**
AnnaBridge	189:f392fc9709a3	841	* @brief Retrieve Binary data configuration
AnnaBridge	189:f392fc9709a3	842	* @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
AnnaBridge	189:f392fc9709a3	843	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	844	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	845	* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge	189:f392fc9709a3	846	* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge	189:f392fc9709a3	847	*/
AnnaBridge	189:f392fc9709a3	848	__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	849	{
AnnaBridge	189:f392fc9709a3	850	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
AnnaBridge	189:f392fc9709a3	851	}
AnnaBridge	189:f392fc9709a3	852
AnnaBridge	189:f392fc9709a3	853	/**
AnnaBridge	189:f392fc9709a3	854	* @brief Configure transfer bit order (either Less or Most Significant Bit First)
AnnaBridge	189:f392fc9709a3	855	* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge	189:f392fc9709a3	856	* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge	189:f392fc9709a3	857	* @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
AnnaBridge	189:f392fc9709a3	858	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	859	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	860	* @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge	189:f392fc9709a3	861	* @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge	189:f392fc9709a3	862	* @retval None
AnnaBridge	189:f392fc9709a3	863	*/
AnnaBridge	189:f392fc9709a3	864	__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
AnnaBridge	189:f392fc9709a3	865	{
AnnaBridge	189:f392fc9709a3	866	MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
AnnaBridge	189:f392fc9709a3	867	}
AnnaBridge	189:f392fc9709a3	868
AnnaBridge	189:f392fc9709a3	869	/**
AnnaBridge	189:f392fc9709a3	870	* @brief Return transfer bit order (either Less or Most Significant Bit First)
AnnaBridge	189:f392fc9709a3	871	* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge	189:f392fc9709a3	872	* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge	189:f392fc9709a3	873	* @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
AnnaBridge	189:f392fc9709a3	874	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	875	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	876	* @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge	189:f392fc9709a3	877	* @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge	189:f392fc9709a3	878	*/
AnnaBridge	189:f392fc9709a3	879	__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	880	{
AnnaBridge	189:f392fc9709a3	881	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
AnnaBridge	189:f392fc9709a3	882	}
AnnaBridge	189:f392fc9709a3	883
AnnaBridge	189:f392fc9709a3	884	/**
AnnaBridge	189:f392fc9709a3	885	* @brief Set Address of the LPUART node.
AnnaBridge	189:f392fc9709a3	886	* @note This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge	189:f392fc9709a3	887	* for wake up with address mark detection.
AnnaBridge	189:f392fc9709a3	888	* @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
AnnaBridge	189:f392fc9709a3	889	* (b7-b4 should be set to 0)
AnnaBridge	189:f392fc9709a3	890	* 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
AnnaBridge	189:f392fc9709a3	891	* (This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge	189:f392fc9709a3	892	* for wake up with 7-bit address mark detection.
AnnaBridge	189:f392fc9709a3	893	* The MSB of the character sent by the transmitter should be equal to 1.
AnnaBridge	189:f392fc9709a3	894	* It may also be used for character detection during normal reception,
AnnaBridge	189:f392fc9709a3	895	* Mute mode inactive (for example, end of block detection in ModBus protocol).
AnnaBridge	189:f392fc9709a3	896	* In this case, the whole received character (8-bit) is compared to the ADD[7:0]
AnnaBridge	189:f392fc9709a3	897	* value and CMF flag is set on match)
AnnaBridge	189:f392fc9709a3	898	* @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
AnnaBridge	189:f392fc9709a3	899	* CR2 ADDM7 LL_LPUART_ConfigNodeAddress
AnnaBridge	189:f392fc9709a3	900	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	901	* @param AddressLen This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	902	* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge	189:f392fc9709a3	903	* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge	189:f392fc9709a3	904	* @param NodeAddress 4 or 7 bit Address of the LPUART node.
AnnaBridge	189:f392fc9709a3	905	* @retval None
AnnaBridge	189:f392fc9709a3	906	*/
AnnaBridge	189:f392fc9709a3	907	__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
AnnaBridge	189:f392fc9709a3	908	{
AnnaBridge	189:f392fc9709a3	909	MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD \| USART_CR2_ADDM7,
AnnaBridge	189:f392fc9709a3	910	(uint32_t)(AddressLen \| (NodeAddress << LPUART_POSITION_CR2_ADD)));
AnnaBridge	189:f392fc9709a3	911	}
AnnaBridge	189:f392fc9709a3	912
AnnaBridge	189:f392fc9709a3	913	/**
AnnaBridge	189:f392fc9709a3	914	* @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
AnnaBridge	189:f392fc9709a3	915	* @note If 4-bit Address Detection is selected in ADDM7,
AnnaBridge	189:f392fc9709a3	916	* only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
AnnaBridge	189:f392fc9709a3	917	* If 7-bit Address Detection is selected in ADDM7,
AnnaBridge	189:f392fc9709a3	918	* only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
AnnaBridge	189:f392fc9709a3	919	* @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
AnnaBridge	189:f392fc9709a3	920	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	921	* @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
AnnaBridge	189:f392fc9709a3	922	*/
AnnaBridge	189:f392fc9709a3	923	__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	924	{
AnnaBridge	189:f392fc9709a3	925	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> LPUART_POSITION_CR2_ADD);
AnnaBridge	189:f392fc9709a3	926	}
AnnaBridge	189:f392fc9709a3	927
AnnaBridge	189:f392fc9709a3	928	/**
AnnaBridge	189:f392fc9709a3	929	* @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
AnnaBridge	189:f392fc9709a3	930	* @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
AnnaBridge	189:f392fc9709a3	931	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	932	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	933	* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge	189:f392fc9709a3	934	* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge	189:f392fc9709a3	935	*/
AnnaBridge	189:f392fc9709a3	936	__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	937	{
AnnaBridge	189:f392fc9709a3	938	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
AnnaBridge	189:f392fc9709a3	939	}
AnnaBridge	189:f392fc9709a3	940
AnnaBridge	189:f392fc9709a3	941	/**
AnnaBridge	189:f392fc9709a3	942	* @brief Enable RTS HW Flow Control
AnnaBridge	189:f392fc9709a3	943	* @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	944	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	945	* @retval None
AnnaBridge	189:f392fc9709a3	946	*/
AnnaBridge	189:f392fc9709a3	947	__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	948	{
AnnaBridge	189:f392fc9709a3	949	SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge	189:f392fc9709a3	950	}
AnnaBridge	189:f392fc9709a3	951
AnnaBridge	189:f392fc9709a3	952	/**
AnnaBridge	189:f392fc9709a3	953	* @brief Disable RTS HW Flow Control
AnnaBridge	189:f392fc9709a3	954	* @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	955	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	956	* @retval None
AnnaBridge	189:f392fc9709a3	957	*/
AnnaBridge	189:f392fc9709a3	958	__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	959	{
AnnaBridge	189:f392fc9709a3	960	CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge	189:f392fc9709a3	961	}
AnnaBridge	189:f392fc9709a3	962
AnnaBridge	189:f392fc9709a3	963	/**
AnnaBridge	189:f392fc9709a3	964	* @brief Enable CTS HW Flow Control
AnnaBridge	189:f392fc9709a3	965	* @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	966	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	967	* @retval None
AnnaBridge	189:f392fc9709a3	968	*/
AnnaBridge	189:f392fc9709a3	969	__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	970	{
AnnaBridge	189:f392fc9709a3	971	SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge	189:f392fc9709a3	972	}
AnnaBridge	189:f392fc9709a3	973
AnnaBridge	189:f392fc9709a3	974	/**
AnnaBridge	189:f392fc9709a3	975	* @brief Disable CTS HW Flow Control
AnnaBridge	189:f392fc9709a3	976	* @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	977	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	978	* @retval None
AnnaBridge	189:f392fc9709a3	979	*/
AnnaBridge	189:f392fc9709a3	980	__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	981	{
AnnaBridge	189:f392fc9709a3	982	CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge	189:f392fc9709a3	983	}
AnnaBridge	189:f392fc9709a3	984
AnnaBridge	189:f392fc9709a3	985	/**
AnnaBridge	189:f392fc9709a3	986	* @brief Configure HW Flow Control mode (both CTS and RTS)
AnnaBridge	189:f392fc9709a3	987	* @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
AnnaBridge	189:f392fc9709a3	988	* CR3 CTSE LL_LPUART_SetHWFlowCtrl
AnnaBridge	189:f392fc9709a3	989	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	990	* @param HardwareFlowControl This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	991	* @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge	189:f392fc9709a3	992	* @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge	189:f392fc9709a3	993	* @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge	189:f392fc9709a3	994	* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge	189:f392fc9709a3	995	* @retval None
AnnaBridge	189:f392fc9709a3	996	*/
AnnaBridge	189:f392fc9709a3	997	__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
AnnaBridge	189:f392fc9709a3	998	{
AnnaBridge	189:f392fc9709a3	999	MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE, HardwareFlowControl);
AnnaBridge	189:f392fc9709a3	1000	}
AnnaBridge	189:f392fc9709a3	1001
AnnaBridge	189:f392fc9709a3	1002	/**
AnnaBridge	189:f392fc9709a3	1003	* @brief Return HW Flow Control configuration (both CTS and RTS)
AnnaBridge	189:f392fc9709a3	1004	* @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
AnnaBridge	189:f392fc9709a3	1005	* CR3 CTSE LL_LPUART_GetHWFlowCtrl
AnnaBridge	189:f392fc9709a3	1006	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1007	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1008	* @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge	189:f392fc9709a3	1009	* @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge	189:f392fc9709a3	1010	* @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge	189:f392fc9709a3	1011	* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge	189:f392fc9709a3	1012	*/
AnnaBridge	189:f392fc9709a3	1013	__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1014	{
AnnaBridge	189:f392fc9709a3	1015	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE));
AnnaBridge	189:f392fc9709a3	1016	}
AnnaBridge	189:f392fc9709a3	1017
AnnaBridge	189:f392fc9709a3	1018	/**
AnnaBridge	189:f392fc9709a3	1019	* @brief Enable Overrun detection
AnnaBridge	189:f392fc9709a3	1020	* @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
AnnaBridge	189:f392fc9709a3	1021	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1022	* @retval None
AnnaBridge	189:f392fc9709a3	1023	*/
AnnaBridge	189:f392fc9709a3	1024	__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1025	{
AnnaBridge	189:f392fc9709a3	1026	CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge	189:f392fc9709a3	1027	}
AnnaBridge	189:f392fc9709a3	1028
AnnaBridge	189:f392fc9709a3	1029	/**
AnnaBridge	189:f392fc9709a3	1030	* @brief Disable Overrun detection
AnnaBridge	189:f392fc9709a3	1031	* @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
AnnaBridge	189:f392fc9709a3	1032	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1033	* @retval None
AnnaBridge	189:f392fc9709a3	1034	*/
AnnaBridge	189:f392fc9709a3	1035	__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1036	{
AnnaBridge	189:f392fc9709a3	1037	SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge	189:f392fc9709a3	1038	}
AnnaBridge	189:f392fc9709a3	1039
AnnaBridge	189:f392fc9709a3	1040	/**
AnnaBridge	189:f392fc9709a3	1041	* @brief Indicate if Overrun detection is enabled
AnnaBridge	189:f392fc9709a3	1042	* @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
AnnaBridge	189:f392fc9709a3	1043	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1044	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1045	*/
AnnaBridge	189:f392fc9709a3	1046	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1047	{
AnnaBridge	189:f392fc9709a3	1048	return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
AnnaBridge	189:f392fc9709a3	1049	}
AnnaBridge	189:f392fc9709a3	1050
AnnaBridge	189:f392fc9709a3	1051	/**
AnnaBridge	189:f392fc9709a3	1052	* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge	189:f392fc9709a3	1053	* @rmtoll CR3 WUS LL_LPUART_SetWKUPType
AnnaBridge	189:f392fc9709a3	1054	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1055	* @param Type This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1056	* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge	189:f392fc9709a3	1057	* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge	189:f392fc9709a3	1058	* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge	189:f392fc9709a3	1059	* @retval None
AnnaBridge	189:f392fc9709a3	1060	*/
AnnaBridge	189:f392fc9709a3	1061	__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
AnnaBridge	189:f392fc9709a3	1062	{
AnnaBridge	189:f392fc9709a3	1063	MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
AnnaBridge	189:f392fc9709a3	1064	}
AnnaBridge	189:f392fc9709a3	1065
AnnaBridge	189:f392fc9709a3	1066	/**
AnnaBridge	189:f392fc9709a3	1067	* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge	189:f392fc9709a3	1068	* @rmtoll CR3 WUS LL_LPUART_GetWKUPType
AnnaBridge	189:f392fc9709a3	1069	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1070	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1071	* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge	189:f392fc9709a3	1072	* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge	189:f392fc9709a3	1073	* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge	189:f392fc9709a3	1074	*/
AnnaBridge	189:f392fc9709a3	1075	__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1076	{
AnnaBridge	189:f392fc9709a3	1077	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
AnnaBridge	189:f392fc9709a3	1078	}
AnnaBridge	189:f392fc9709a3	1079
AnnaBridge	189:f392fc9709a3	1080	/**
AnnaBridge	189:f392fc9709a3	1081	* @brief Configure LPUART BRR register for achieving expected Baud Rate value.
AnnaBridge	189:f392fc9709a3	1082	*
AnnaBridge	189:f392fc9709a3	1083	* @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
AnnaBridge	189:f392fc9709a3	1084	* according to used Peripheral Clock and expected Baud Rate values
AnnaBridge	189:f392fc9709a3	1085	* @note Peripheral clock and Baud Rate values provided as function parameters should be valid
AnnaBridge	189:f392fc9709a3	1086	* (Baud rate value != 0).
AnnaBridge	189:f392fc9709a3	1087	* @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
AnnaBridge	189:f392fc9709a3	1088	* a care should be taken when generating high baud rates using high PeriphClk
AnnaBridge	189:f392fc9709a3	1089	* values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
AnnaBridge	189:f392fc9709a3	1090	* @rmtoll BRR BRR LL_LPUART_SetBaudRate
AnnaBridge	189:f392fc9709a3	1091	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1092	* @param PeriphClk Peripheral Clock
AnnaBridge	189:f392fc9709a3	1093	* @param BaudRate Baud Rate
AnnaBridge	189:f392fc9709a3	1094	* @retval None
AnnaBridge	189:f392fc9709a3	1095	*/
AnnaBridge	189:f392fc9709a3	1096	__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
AnnaBridge	189:f392fc9709a3	1097	{
AnnaBridge	189:f392fc9709a3	1098	LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
AnnaBridge	189:f392fc9709a3	1099	}
AnnaBridge	189:f392fc9709a3	1100
AnnaBridge	189:f392fc9709a3	1101	/**
AnnaBridge	189:f392fc9709a3	1102	* @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
AnnaBridge	189:f392fc9709a3	1103	* (full BRR content), and to used Peripheral Clock values
AnnaBridge	189:f392fc9709a3	1104	* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
AnnaBridge	189:f392fc9709a3	1105	* @rmtoll BRR BRR LL_LPUART_GetBaudRate
AnnaBridge	189:f392fc9709a3	1106	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1107	* @param PeriphClk Peripheral Clock
AnnaBridge	189:f392fc9709a3	1108	* @retval Baud Rate
AnnaBridge	189:f392fc9709a3	1109	*/
AnnaBridge	189:f392fc9709a3	1110	__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
AnnaBridge	189:f392fc9709a3	1111	{
AnnaBridge	189:f392fc9709a3	1112	register uint32_t lpuartdiv = 0x0U;
AnnaBridge	189:f392fc9709a3	1113	register uint32_t brrresult = 0x0U;
AnnaBridge	189:f392fc9709a3	1114
AnnaBridge	189:f392fc9709a3	1115	lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
AnnaBridge	189:f392fc9709a3	1116
AnnaBridge	189:f392fc9709a3	1117	if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
AnnaBridge	189:f392fc9709a3	1118	{
AnnaBridge	189:f392fc9709a3	1119	brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
AnnaBridge	189:f392fc9709a3	1120	}
AnnaBridge	189:f392fc9709a3	1121
AnnaBridge	189:f392fc9709a3	1122	return (brrresult);
AnnaBridge	189:f392fc9709a3	1123	}
AnnaBridge	189:f392fc9709a3	1124
AnnaBridge	189:f392fc9709a3	1125	/**
AnnaBridge	189:f392fc9709a3	1126	* @}
AnnaBridge	189:f392fc9709a3	1127	*/
AnnaBridge	189:f392fc9709a3	1128
AnnaBridge	189:f392fc9709a3	1129	/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
AnnaBridge	189:f392fc9709a3	1130	* @{
AnnaBridge	189:f392fc9709a3	1131	*/
AnnaBridge	189:f392fc9709a3	1132
AnnaBridge	189:f392fc9709a3	1133	/**
AnnaBridge	189:f392fc9709a3	1134	* @brief Enable Single Wire Half-Duplex mode
AnnaBridge	189:f392fc9709a3	1135	* @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
AnnaBridge	189:f392fc9709a3	1136	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1137	* @retval None
AnnaBridge	189:f392fc9709a3	1138	*/
AnnaBridge	189:f392fc9709a3	1139	__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1140	{
AnnaBridge	189:f392fc9709a3	1141	SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge	189:f392fc9709a3	1142	}
AnnaBridge	189:f392fc9709a3	1143
AnnaBridge	189:f392fc9709a3	1144	/**
AnnaBridge	189:f392fc9709a3	1145	* @brief Disable Single Wire Half-Duplex mode
AnnaBridge	189:f392fc9709a3	1146	* @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
AnnaBridge	189:f392fc9709a3	1147	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1148	* @retval None
AnnaBridge	189:f392fc9709a3	1149	*/
AnnaBridge	189:f392fc9709a3	1150	__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1151	{
AnnaBridge	189:f392fc9709a3	1152	CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge	189:f392fc9709a3	1153	}
AnnaBridge	189:f392fc9709a3	1154
AnnaBridge	189:f392fc9709a3	1155	/**
AnnaBridge	189:f392fc9709a3	1156	* @brief Indicate if Single Wire Half-Duplex mode is enabled
AnnaBridge	189:f392fc9709a3	1157	* @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
AnnaBridge	189:f392fc9709a3	1158	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1159	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1160	*/
AnnaBridge	189:f392fc9709a3	1161	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1162	{
AnnaBridge	189:f392fc9709a3	1163	return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
AnnaBridge	189:f392fc9709a3	1164	}
AnnaBridge	189:f392fc9709a3	1165
AnnaBridge	189:f392fc9709a3	1166	/**
AnnaBridge	189:f392fc9709a3	1167	* @}
AnnaBridge	189:f392fc9709a3	1168	*/
AnnaBridge	189:f392fc9709a3	1169
AnnaBridge	189:f392fc9709a3	1170	/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
AnnaBridge	189:f392fc9709a3	1171	* @{
AnnaBridge	189:f392fc9709a3	1172	*/
AnnaBridge	189:f392fc9709a3	1173
AnnaBridge	189:f392fc9709a3	1174	/**
AnnaBridge	189:f392fc9709a3	1175	* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge	189:f392fc9709a3	1176	* @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
AnnaBridge	189:f392fc9709a3	1177	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1178	* @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	189:f392fc9709a3	1179	* @retval None
AnnaBridge	189:f392fc9709a3	1180	*/
AnnaBridge	189:f392fc9709a3	1181	__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge	189:f392fc9709a3	1182	{
AnnaBridge	189:f392fc9709a3	1183	MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << LPUART_POSITION_CR1_DEDT);
AnnaBridge	189:f392fc9709a3	1184	}
AnnaBridge	189:f392fc9709a3	1185
AnnaBridge	189:f392fc9709a3	1186	/**
AnnaBridge	189:f392fc9709a3	1187	* @brief Return DEDT (Driver Enable De-Assertion Time)
AnnaBridge	189:f392fc9709a3	1188	* @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
AnnaBridge	189:f392fc9709a3	1189	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1190	* @retval Time value expressed on 5 bits ([4:0] bits) : c
AnnaBridge	189:f392fc9709a3	1191	*/
AnnaBridge	189:f392fc9709a3	1192	__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1193	{
AnnaBridge	189:f392fc9709a3	1194	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> LPUART_POSITION_CR1_DEDT);
AnnaBridge	189:f392fc9709a3	1195	}
AnnaBridge	189:f392fc9709a3	1196
AnnaBridge	189:f392fc9709a3	1197	/**
AnnaBridge	189:f392fc9709a3	1198	* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge	189:f392fc9709a3	1199	* @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
AnnaBridge	189:f392fc9709a3	1200	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1201	* @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	189:f392fc9709a3	1202	* @retval None
AnnaBridge	189:f392fc9709a3	1203	*/
AnnaBridge	189:f392fc9709a3	1204	__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge	189:f392fc9709a3	1205	{
AnnaBridge	189:f392fc9709a3	1206	MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << LPUART_POSITION_CR1_DEAT);
AnnaBridge	189:f392fc9709a3	1207	}
AnnaBridge	189:f392fc9709a3	1208
AnnaBridge	189:f392fc9709a3	1209	/**
AnnaBridge	189:f392fc9709a3	1210	* @brief Return DEAT (Driver Enable Assertion Time)
AnnaBridge	189:f392fc9709a3	1211	* @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
AnnaBridge	189:f392fc9709a3	1212	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1213	* @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	189:f392fc9709a3	1214	*/
AnnaBridge	189:f392fc9709a3	1215	__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1216	{
AnnaBridge	189:f392fc9709a3	1217	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> LPUART_POSITION_CR1_DEAT);
AnnaBridge	189:f392fc9709a3	1218	}
AnnaBridge	189:f392fc9709a3	1219
AnnaBridge	189:f392fc9709a3	1220	/**
AnnaBridge	189:f392fc9709a3	1221	* @brief Enable Driver Enable (DE) Mode
AnnaBridge	189:f392fc9709a3	1222	* @rmtoll CR3 DEM LL_LPUART_EnableDEMode
AnnaBridge	189:f392fc9709a3	1223	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1224	* @retval None
AnnaBridge	189:f392fc9709a3	1225	*/
AnnaBridge	189:f392fc9709a3	1226	__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1227	{
AnnaBridge	189:f392fc9709a3	1228	SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge	189:f392fc9709a3	1229	}
AnnaBridge	189:f392fc9709a3	1230
AnnaBridge	189:f392fc9709a3	1231	/**
AnnaBridge	189:f392fc9709a3	1232	* @brief Disable Driver Enable (DE) Mode
AnnaBridge	189:f392fc9709a3	1233	* @rmtoll CR3 DEM LL_LPUART_DisableDEMode
AnnaBridge	189:f392fc9709a3	1234	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1235	* @retval None
AnnaBridge	189:f392fc9709a3	1236	*/
AnnaBridge	189:f392fc9709a3	1237	__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1238	{
AnnaBridge	189:f392fc9709a3	1239	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge	189:f392fc9709a3	1240	}
AnnaBridge	189:f392fc9709a3	1241
AnnaBridge	189:f392fc9709a3	1242	/**
AnnaBridge	189:f392fc9709a3	1243	* @brief Indicate if Driver Enable (DE) Mode is enabled
AnnaBridge	189:f392fc9709a3	1244	* @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
AnnaBridge	189:f392fc9709a3	1245	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1246	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1247	*/
AnnaBridge	189:f392fc9709a3	1248	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1249	{
AnnaBridge	189:f392fc9709a3	1250	return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
AnnaBridge	189:f392fc9709a3	1251	}
AnnaBridge	189:f392fc9709a3	1252
AnnaBridge	189:f392fc9709a3	1253	/**
AnnaBridge	189:f392fc9709a3	1254	* @brief Select Driver Enable Polarity
AnnaBridge	189:f392fc9709a3	1255	* @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
AnnaBridge	189:f392fc9709a3	1256	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1257	* @param Polarity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1258	* @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	1259	* @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	1260	* @retval None
AnnaBridge	189:f392fc9709a3	1261	*/
AnnaBridge	189:f392fc9709a3	1262	__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
AnnaBridge	189:f392fc9709a3	1263	{
AnnaBridge	189:f392fc9709a3	1264	MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
AnnaBridge	189:f392fc9709a3	1265	}
AnnaBridge	189:f392fc9709a3	1266
AnnaBridge	189:f392fc9709a3	1267	/**
AnnaBridge	189:f392fc9709a3	1268	* @brief Return Driver Enable Polarity
AnnaBridge	189:f392fc9709a3	1269	* @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
AnnaBridge	189:f392fc9709a3	1270	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1271	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1272	* @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	1273	* @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	1274	*/
AnnaBridge	189:f392fc9709a3	1275	__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1276	{
AnnaBridge	189:f392fc9709a3	1277	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
AnnaBridge	189:f392fc9709a3	1278	}
AnnaBridge	189:f392fc9709a3	1279
AnnaBridge	189:f392fc9709a3	1280	/**
AnnaBridge	189:f392fc9709a3	1281	* @}
AnnaBridge	189:f392fc9709a3	1282	*/
AnnaBridge	189:f392fc9709a3	1283
AnnaBridge	189:f392fc9709a3	1284	/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	189:f392fc9709a3	1285	* @{
AnnaBridge	189:f392fc9709a3	1286	*/
AnnaBridge	189:f392fc9709a3	1287
AnnaBridge	189:f392fc9709a3	1288	/**
AnnaBridge	189:f392fc9709a3	1289	* @brief Check if the LPUART Parity Error Flag is set or not
AnnaBridge	189:f392fc9709a3	1290	* @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
AnnaBridge	189:f392fc9709a3	1291	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1292	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1293	*/
AnnaBridge	189:f392fc9709a3	1294	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1295	{
AnnaBridge	189:f392fc9709a3	1296	return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
AnnaBridge	189:f392fc9709a3	1297	}
AnnaBridge	189:f392fc9709a3	1298
AnnaBridge	189:f392fc9709a3	1299	/**
AnnaBridge	189:f392fc9709a3	1300	* @brief Check if the LPUART Framing Error Flag is set or not
AnnaBridge	189:f392fc9709a3	1301	* @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
AnnaBridge	189:f392fc9709a3	1302	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1303	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1304	*/
AnnaBridge	189:f392fc9709a3	1305	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1306	{
AnnaBridge	189:f392fc9709a3	1307	return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
AnnaBridge	189:f392fc9709a3	1308	}
AnnaBridge	189:f392fc9709a3	1309
AnnaBridge	189:f392fc9709a3	1310	/**
AnnaBridge	189:f392fc9709a3	1311	* @brief Check if the LPUART Noise detected Flag is set or not
AnnaBridge	189:f392fc9709a3	1312	* @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
AnnaBridge	189:f392fc9709a3	1313	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1314	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1315	*/
AnnaBridge	189:f392fc9709a3	1316	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1317	{
AnnaBridge	189:f392fc9709a3	1318	return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
AnnaBridge	189:f392fc9709a3	1319	}
AnnaBridge	189:f392fc9709a3	1320
AnnaBridge	189:f392fc9709a3	1321	/**
AnnaBridge	189:f392fc9709a3	1322	* @brief Check if the LPUART OverRun Error Flag is set or not
AnnaBridge	189:f392fc9709a3	1323	* @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
AnnaBridge	189:f392fc9709a3	1324	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1325	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1326	*/
AnnaBridge	189:f392fc9709a3	1327	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1328	{
AnnaBridge	189:f392fc9709a3	1329	return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
AnnaBridge	189:f392fc9709a3	1330	}
AnnaBridge	189:f392fc9709a3	1331
AnnaBridge	189:f392fc9709a3	1332	/**
AnnaBridge	189:f392fc9709a3	1333	* @brief Check if the LPUART IDLE line detected Flag is set or not
AnnaBridge	189:f392fc9709a3	1334	* @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
AnnaBridge	189:f392fc9709a3	1335	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1336	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1337	*/
AnnaBridge	189:f392fc9709a3	1338	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1339	{
AnnaBridge	189:f392fc9709a3	1340	return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
AnnaBridge	189:f392fc9709a3	1341	}
AnnaBridge	189:f392fc9709a3	1342
AnnaBridge	189:f392fc9709a3	1343	/**
AnnaBridge	189:f392fc9709a3	1344	* @brief Check if the LPUART Read Data Register Not Empty Flag is set or not
AnnaBridge	189:f392fc9709a3	1345	* @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE
AnnaBridge	189:f392fc9709a3	1346	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1347	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1348	*/
AnnaBridge	189:f392fc9709a3	1349	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1350	{
AnnaBridge	189:f392fc9709a3	1351	return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
AnnaBridge	189:f392fc9709a3	1352	}
AnnaBridge	189:f392fc9709a3	1353
AnnaBridge	189:f392fc9709a3	1354	/**
AnnaBridge	189:f392fc9709a3	1355	* @brief Check if the LPUART Transmission Complete Flag is set or not
AnnaBridge	189:f392fc9709a3	1356	* @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
AnnaBridge	189:f392fc9709a3	1357	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1358	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1359	*/
AnnaBridge	189:f392fc9709a3	1360	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1361	{
AnnaBridge	189:f392fc9709a3	1362	return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
AnnaBridge	189:f392fc9709a3	1363	}
AnnaBridge	189:f392fc9709a3	1364
AnnaBridge	189:f392fc9709a3	1365	/**
AnnaBridge	189:f392fc9709a3	1366	* @brief Check if the LPUART Transmit Data Register Empty Flag is set or not
AnnaBridge	189:f392fc9709a3	1367	* @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE
AnnaBridge	189:f392fc9709a3	1368	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1369	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1370	*/
AnnaBridge	189:f392fc9709a3	1371	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1372	{
AnnaBridge	189:f392fc9709a3	1373	return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
AnnaBridge	189:f392fc9709a3	1374	}
AnnaBridge	189:f392fc9709a3	1375
AnnaBridge	189:f392fc9709a3	1376	/**
AnnaBridge	189:f392fc9709a3	1377	* @brief Check if the LPUART CTS interrupt Flag is set or not
AnnaBridge	189:f392fc9709a3	1378	* @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
AnnaBridge	189:f392fc9709a3	1379	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1380	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1381	*/
AnnaBridge	189:f392fc9709a3	1382	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1383	{
AnnaBridge	189:f392fc9709a3	1384	return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
AnnaBridge	189:f392fc9709a3	1385	}
AnnaBridge	189:f392fc9709a3	1386
AnnaBridge	189:f392fc9709a3	1387	/**
AnnaBridge	189:f392fc9709a3	1388	* @brief Check if the LPUART CTS Flag is set or not
AnnaBridge	189:f392fc9709a3	1389	* @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
AnnaBridge	189:f392fc9709a3	1390	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1391	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1392	*/
AnnaBridge	189:f392fc9709a3	1393	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1394	{
AnnaBridge	189:f392fc9709a3	1395	return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
AnnaBridge	189:f392fc9709a3	1396	}
AnnaBridge	189:f392fc9709a3	1397
AnnaBridge	189:f392fc9709a3	1398	/**
AnnaBridge	189:f392fc9709a3	1399	* @brief Check if the LPUART Busy Flag is set or not
AnnaBridge	189:f392fc9709a3	1400	* @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
AnnaBridge	189:f392fc9709a3	1401	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1402	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1403	*/
AnnaBridge	189:f392fc9709a3	1404	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1405	{
AnnaBridge	189:f392fc9709a3	1406	return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
AnnaBridge	189:f392fc9709a3	1407	}
AnnaBridge	189:f392fc9709a3	1408
AnnaBridge	189:f392fc9709a3	1409	/**
AnnaBridge	189:f392fc9709a3	1410	* @brief Check if the LPUART Character Match Flag is set or not
AnnaBridge	189:f392fc9709a3	1411	* @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
AnnaBridge	189:f392fc9709a3	1412	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1413	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1414	*/
AnnaBridge	189:f392fc9709a3	1415	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1416	{
AnnaBridge	189:f392fc9709a3	1417	return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
AnnaBridge	189:f392fc9709a3	1418	}
AnnaBridge	189:f392fc9709a3	1419
AnnaBridge	189:f392fc9709a3	1420	/**
AnnaBridge	189:f392fc9709a3	1421	* @brief Check if the LPUART Send Break Flag is set or not
AnnaBridge	189:f392fc9709a3	1422	* @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
AnnaBridge	189:f392fc9709a3	1423	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1424	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1425	*/
AnnaBridge	189:f392fc9709a3	1426	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1427	{
AnnaBridge	189:f392fc9709a3	1428	return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
AnnaBridge	189:f392fc9709a3	1429	}
AnnaBridge	189:f392fc9709a3	1430
AnnaBridge	189:f392fc9709a3	1431	/**
AnnaBridge	189:f392fc9709a3	1432	* @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
AnnaBridge	189:f392fc9709a3	1433	* @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
AnnaBridge	189:f392fc9709a3	1434	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1435	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1436	*/
AnnaBridge	189:f392fc9709a3	1437	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1438	{
AnnaBridge	189:f392fc9709a3	1439	return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
AnnaBridge	189:f392fc9709a3	1440	}
AnnaBridge	189:f392fc9709a3	1441
AnnaBridge	189:f392fc9709a3	1442	/**
AnnaBridge	189:f392fc9709a3	1443	* @brief Check if the LPUART Wake Up from stop mode Flag is set or not
AnnaBridge	189:f392fc9709a3	1444	* @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
AnnaBridge	189:f392fc9709a3	1445	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1446	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1447	*/
AnnaBridge	189:f392fc9709a3	1448	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1449	{
AnnaBridge	189:f392fc9709a3	1450	return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
AnnaBridge	189:f392fc9709a3	1451	}
AnnaBridge	189:f392fc9709a3	1452
AnnaBridge	189:f392fc9709a3	1453	/**
AnnaBridge	189:f392fc9709a3	1454	* @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
AnnaBridge	189:f392fc9709a3	1455	* @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
AnnaBridge	189:f392fc9709a3	1456	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1457	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1458	*/
AnnaBridge	189:f392fc9709a3	1459	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1460	{
AnnaBridge	189:f392fc9709a3	1461	return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
AnnaBridge	189:f392fc9709a3	1462	}
AnnaBridge	189:f392fc9709a3	1463
AnnaBridge	189:f392fc9709a3	1464	/**
AnnaBridge	189:f392fc9709a3	1465	* @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
AnnaBridge	189:f392fc9709a3	1466	* @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
AnnaBridge	189:f392fc9709a3	1467	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1468	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1469	*/
AnnaBridge	189:f392fc9709a3	1470	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1471	{
AnnaBridge	189:f392fc9709a3	1472	return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
AnnaBridge	189:f392fc9709a3	1473	}
AnnaBridge	189:f392fc9709a3	1474
AnnaBridge	189:f392fc9709a3	1475	/**
AnnaBridge	189:f392fc9709a3	1476	* @brief Clear Parity Error Flag
AnnaBridge	189:f392fc9709a3	1477	* @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
AnnaBridge	189:f392fc9709a3	1478	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1479	* @retval None
AnnaBridge	189:f392fc9709a3	1480	*/
AnnaBridge	189:f392fc9709a3	1481	__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1482	{
AnnaBridge	189:f392fc9709a3	1483	WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
AnnaBridge	189:f392fc9709a3	1484	}
AnnaBridge	189:f392fc9709a3	1485
AnnaBridge	189:f392fc9709a3	1486	/**
AnnaBridge	189:f392fc9709a3	1487	* @brief Clear Framing Error Flag
AnnaBridge	189:f392fc9709a3	1488	* @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
AnnaBridge	189:f392fc9709a3	1489	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1490	* @retval None
AnnaBridge	189:f392fc9709a3	1491	*/
AnnaBridge	189:f392fc9709a3	1492	__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1493	{
AnnaBridge	189:f392fc9709a3	1494	WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
AnnaBridge	189:f392fc9709a3	1495	}
AnnaBridge	189:f392fc9709a3	1496
AnnaBridge	189:f392fc9709a3	1497	/**
AnnaBridge	189:f392fc9709a3	1498	* @brief Clear Noise detected Flag
AnnaBridge	189:f392fc9709a3	1499	* @rmtoll ICR NCF LL_LPUART_ClearFlag_NE
AnnaBridge	189:f392fc9709a3	1500	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1501	* @retval None
AnnaBridge	189:f392fc9709a3	1502	*/
AnnaBridge	189:f392fc9709a3	1503	__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1504	{
AnnaBridge	189:f392fc9709a3	1505	WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
AnnaBridge	189:f392fc9709a3	1506	}
AnnaBridge	189:f392fc9709a3	1507
AnnaBridge	189:f392fc9709a3	1508	/**
AnnaBridge	189:f392fc9709a3	1509	* @brief Clear OverRun Error Flag
AnnaBridge	189:f392fc9709a3	1510	* @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
AnnaBridge	189:f392fc9709a3	1511	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1512	* @retval None
AnnaBridge	189:f392fc9709a3	1513	*/
AnnaBridge	189:f392fc9709a3	1514	__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1515	{
AnnaBridge	189:f392fc9709a3	1516	WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
AnnaBridge	189:f392fc9709a3	1517	}
AnnaBridge	189:f392fc9709a3	1518
AnnaBridge	189:f392fc9709a3	1519	/**
AnnaBridge	189:f392fc9709a3	1520	* @brief Clear IDLE line detected Flag
AnnaBridge	189:f392fc9709a3	1521	* @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
AnnaBridge	189:f392fc9709a3	1522	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1523	* @retval None
AnnaBridge	189:f392fc9709a3	1524	*/
AnnaBridge	189:f392fc9709a3	1525	__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1526	{
AnnaBridge	189:f392fc9709a3	1527	WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
AnnaBridge	189:f392fc9709a3	1528	}
AnnaBridge	189:f392fc9709a3	1529
AnnaBridge	189:f392fc9709a3	1530	/**
AnnaBridge	189:f392fc9709a3	1531	* @brief Clear Transmission Complete Flag
AnnaBridge	189:f392fc9709a3	1532	* @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
AnnaBridge	189:f392fc9709a3	1533	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1534	* @retval None
AnnaBridge	189:f392fc9709a3	1535	*/
AnnaBridge	189:f392fc9709a3	1536	__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1537	{
AnnaBridge	189:f392fc9709a3	1538	WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
AnnaBridge	189:f392fc9709a3	1539	}
AnnaBridge	189:f392fc9709a3	1540
AnnaBridge	189:f392fc9709a3	1541	/**
AnnaBridge	189:f392fc9709a3	1542	* @brief Clear CTS Interrupt Flag
AnnaBridge	189:f392fc9709a3	1543	* @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
AnnaBridge	189:f392fc9709a3	1544	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1545	* @retval None
AnnaBridge	189:f392fc9709a3	1546	*/
AnnaBridge	189:f392fc9709a3	1547	__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1548	{
AnnaBridge	189:f392fc9709a3	1549	WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
AnnaBridge	189:f392fc9709a3	1550	}
AnnaBridge	189:f392fc9709a3	1551
AnnaBridge	189:f392fc9709a3	1552	/**
AnnaBridge	189:f392fc9709a3	1553	* @brief Clear Character Match Flag
AnnaBridge	189:f392fc9709a3	1554	* @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
AnnaBridge	189:f392fc9709a3	1555	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1556	* @retval None
AnnaBridge	189:f392fc9709a3	1557	*/
AnnaBridge	189:f392fc9709a3	1558	__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1559	{
AnnaBridge	189:f392fc9709a3	1560	WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
AnnaBridge	189:f392fc9709a3	1561	}
AnnaBridge	189:f392fc9709a3	1562
AnnaBridge	189:f392fc9709a3	1563	/**
AnnaBridge	189:f392fc9709a3	1564	* @brief Clear Wake Up from stop mode Flag
AnnaBridge	189:f392fc9709a3	1565	* @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
AnnaBridge	189:f392fc9709a3	1566	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1567	* @retval None
AnnaBridge	189:f392fc9709a3	1568	*/
AnnaBridge	189:f392fc9709a3	1569	__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1570	{
AnnaBridge	189:f392fc9709a3	1571	WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
AnnaBridge	189:f392fc9709a3	1572	}
AnnaBridge	189:f392fc9709a3	1573
AnnaBridge	189:f392fc9709a3	1574	/**
AnnaBridge	189:f392fc9709a3	1575	* @}
AnnaBridge	189:f392fc9709a3	1576	*/
AnnaBridge	189:f392fc9709a3	1577
AnnaBridge	189:f392fc9709a3	1578	/** @defgroup LPUART_LL_EF_IT_Management IT_Management
AnnaBridge	189:f392fc9709a3	1579	* @{
AnnaBridge	189:f392fc9709a3	1580	*/
AnnaBridge	189:f392fc9709a3	1581
AnnaBridge	189:f392fc9709a3	1582	/**
AnnaBridge	189:f392fc9709a3	1583	* @brief Enable IDLE Interrupt
AnnaBridge	189:f392fc9709a3	1584	* @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
AnnaBridge	189:f392fc9709a3	1585	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1586	* @retval None
AnnaBridge	189:f392fc9709a3	1587	*/
AnnaBridge	189:f392fc9709a3	1588	__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1589	{
AnnaBridge	189:f392fc9709a3	1590	SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge	189:f392fc9709a3	1591	}
AnnaBridge	189:f392fc9709a3	1592
AnnaBridge	189:f392fc9709a3	1593	/**
AnnaBridge	189:f392fc9709a3	1594	* @brief Enable RX Not Empty Interrupt
AnnaBridge	189:f392fc9709a3	1595	* @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE
AnnaBridge	189:f392fc9709a3	1596	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1597	* @retval None
AnnaBridge	189:f392fc9709a3	1598	*/
AnnaBridge	189:f392fc9709a3	1599	__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1600	{
AnnaBridge	189:f392fc9709a3	1601	SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge	189:f392fc9709a3	1602	}
AnnaBridge	189:f392fc9709a3	1603
AnnaBridge	189:f392fc9709a3	1604	/**
AnnaBridge	189:f392fc9709a3	1605	* @brief Enable Transmission Complete Interrupt
AnnaBridge	189:f392fc9709a3	1606	* @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
AnnaBridge	189:f392fc9709a3	1607	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1608	* @retval None
AnnaBridge	189:f392fc9709a3	1609	*/
AnnaBridge	189:f392fc9709a3	1610	__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1611	{
AnnaBridge	189:f392fc9709a3	1612	SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge	189:f392fc9709a3	1613	}
AnnaBridge	189:f392fc9709a3	1614
AnnaBridge	189:f392fc9709a3	1615	/**
AnnaBridge	189:f392fc9709a3	1616	* @brief Enable TX Empty Interrupt
AnnaBridge	189:f392fc9709a3	1617	* @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE
AnnaBridge	189:f392fc9709a3	1618	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1619	* @retval None
AnnaBridge	189:f392fc9709a3	1620	*/
AnnaBridge	189:f392fc9709a3	1621	__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1622	{
AnnaBridge	189:f392fc9709a3	1623	SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge	189:f392fc9709a3	1624	}
AnnaBridge	189:f392fc9709a3	1625
AnnaBridge	189:f392fc9709a3	1626	/**
AnnaBridge	189:f392fc9709a3	1627	* @brief Enable Parity Error Interrupt
AnnaBridge	189:f392fc9709a3	1628	* @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
AnnaBridge	189:f392fc9709a3	1629	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1630	* @retval None
AnnaBridge	189:f392fc9709a3	1631	*/
AnnaBridge	189:f392fc9709a3	1632	__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1633	{
AnnaBridge	189:f392fc9709a3	1634	SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge	189:f392fc9709a3	1635	}
AnnaBridge	189:f392fc9709a3	1636
AnnaBridge	189:f392fc9709a3	1637	/**
AnnaBridge	189:f392fc9709a3	1638	* @brief Enable Character Match Interrupt
AnnaBridge	189:f392fc9709a3	1639	* @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
AnnaBridge	189:f392fc9709a3	1640	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1641	* @retval None
AnnaBridge	189:f392fc9709a3	1642	*/
AnnaBridge	189:f392fc9709a3	1643	__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1644	{
AnnaBridge	189:f392fc9709a3	1645	SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge	189:f392fc9709a3	1646	}
AnnaBridge	189:f392fc9709a3	1647
AnnaBridge	189:f392fc9709a3	1648	/**
AnnaBridge	189:f392fc9709a3	1649	* @brief Enable Error Interrupt
AnnaBridge	189:f392fc9709a3	1650	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge	189:f392fc9709a3	1651	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge	189:f392fc9709a3	1652	* - 0: Interrupt is inhibited
AnnaBridge	189:f392fc9709a3	1653	* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge	189:f392fc9709a3	1654	* @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
AnnaBridge	189:f392fc9709a3	1655	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1656	* @retval None
AnnaBridge	189:f392fc9709a3	1657	*/
AnnaBridge	189:f392fc9709a3	1658	__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1659	{
AnnaBridge	189:f392fc9709a3	1660	SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge	189:f392fc9709a3	1661	}
AnnaBridge	189:f392fc9709a3	1662
AnnaBridge	189:f392fc9709a3	1663	/**
AnnaBridge	189:f392fc9709a3	1664	* @brief Enable CTS Interrupt
AnnaBridge	189:f392fc9709a3	1665	* @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
AnnaBridge	189:f392fc9709a3	1666	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1667	* @retval None
AnnaBridge	189:f392fc9709a3	1668	*/
AnnaBridge	189:f392fc9709a3	1669	__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1670	{
AnnaBridge	189:f392fc9709a3	1671	SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge	189:f392fc9709a3	1672	}
AnnaBridge	189:f392fc9709a3	1673
AnnaBridge	189:f392fc9709a3	1674	/**
AnnaBridge	189:f392fc9709a3	1675	* @brief Enable Wake Up from Stop Mode Interrupt
AnnaBridge	189:f392fc9709a3	1676	* @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
AnnaBridge	189:f392fc9709a3	1677	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1678	* @retval None
AnnaBridge	189:f392fc9709a3	1679	*/
AnnaBridge	189:f392fc9709a3	1680	__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1681	{
AnnaBridge	189:f392fc9709a3	1682	SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge	189:f392fc9709a3	1683	}
AnnaBridge	189:f392fc9709a3	1684
AnnaBridge	189:f392fc9709a3	1685	/**
AnnaBridge	189:f392fc9709a3	1686	* @brief Disable IDLE Interrupt
AnnaBridge	189:f392fc9709a3	1687	* @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
AnnaBridge	189:f392fc9709a3	1688	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1689	* @retval None
AnnaBridge	189:f392fc9709a3	1690	*/
AnnaBridge	189:f392fc9709a3	1691	__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1692	{
AnnaBridge	189:f392fc9709a3	1693	CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge	189:f392fc9709a3	1694	}
AnnaBridge	189:f392fc9709a3	1695
AnnaBridge	189:f392fc9709a3	1696	/**
AnnaBridge	189:f392fc9709a3	1697	* @brief Disable RX Not Empty Interrupt
AnnaBridge	189:f392fc9709a3	1698	* @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE
AnnaBridge	189:f392fc9709a3	1699	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1700	* @retval None
AnnaBridge	189:f392fc9709a3	1701	*/
AnnaBridge	189:f392fc9709a3	1702	__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1703	{
AnnaBridge	189:f392fc9709a3	1704	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge	189:f392fc9709a3	1705	}
AnnaBridge	189:f392fc9709a3	1706
AnnaBridge	189:f392fc9709a3	1707	/**
AnnaBridge	189:f392fc9709a3	1708	* @brief Disable Transmission Complete Interrupt
AnnaBridge	189:f392fc9709a3	1709	* @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
AnnaBridge	189:f392fc9709a3	1710	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1711	* @retval None
AnnaBridge	189:f392fc9709a3	1712	*/
AnnaBridge	189:f392fc9709a3	1713	__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1714	{
AnnaBridge	189:f392fc9709a3	1715	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge	189:f392fc9709a3	1716	}
AnnaBridge	189:f392fc9709a3	1717
AnnaBridge	189:f392fc9709a3	1718	/**
AnnaBridge	189:f392fc9709a3	1719	* @brief Disable TX Empty Interrupt
AnnaBridge	189:f392fc9709a3	1720	* @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE
AnnaBridge	189:f392fc9709a3	1721	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1722	* @retval None
AnnaBridge	189:f392fc9709a3	1723	*/
AnnaBridge	189:f392fc9709a3	1724	__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1725	{
AnnaBridge	189:f392fc9709a3	1726	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge	189:f392fc9709a3	1727	}
AnnaBridge	189:f392fc9709a3	1728
AnnaBridge	189:f392fc9709a3	1729	/**
AnnaBridge	189:f392fc9709a3	1730	* @brief Disable Parity Error Interrupt
AnnaBridge	189:f392fc9709a3	1731	* @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
AnnaBridge	189:f392fc9709a3	1732	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1733	* @retval None
AnnaBridge	189:f392fc9709a3	1734	*/
AnnaBridge	189:f392fc9709a3	1735	__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1736	{
AnnaBridge	189:f392fc9709a3	1737	CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge	189:f392fc9709a3	1738	}
AnnaBridge	189:f392fc9709a3	1739
AnnaBridge	189:f392fc9709a3	1740	/**
AnnaBridge	189:f392fc9709a3	1741	* @brief Disable Character Match Interrupt
AnnaBridge	189:f392fc9709a3	1742	* @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
AnnaBridge	189:f392fc9709a3	1743	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1744	* @retval None
AnnaBridge	189:f392fc9709a3	1745	*/
AnnaBridge	189:f392fc9709a3	1746	__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1747	{
AnnaBridge	189:f392fc9709a3	1748	CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge	189:f392fc9709a3	1749	}
AnnaBridge	189:f392fc9709a3	1750
AnnaBridge	189:f392fc9709a3	1751	/**
AnnaBridge	189:f392fc9709a3	1752	* @brief Disable Error Interrupt
AnnaBridge	189:f392fc9709a3	1753	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge	189:f392fc9709a3	1754	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge	189:f392fc9709a3	1755	* - 0: Interrupt is inhibited
AnnaBridge	189:f392fc9709a3	1756	* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge	189:f392fc9709a3	1757	* @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
AnnaBridge	189:f392fc9709a3	1758	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1759	* @retval None
AnnaBridge	189:f392fc9709a3	1760	*/
AnnaBridge	189:f392fc9709a3	1761	__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1762	{
AnnaBridge	189:f392fc9709a3	1763	CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge	189:f392fc9709a3	1764	}
AnnaBridge	189:f392fc9709a3	1765
AnnaBridge	189:f392fc9709a3	1766	/**
AnnaBridge	189:f392fc9709a3	1767	* @brief Disable CTS Interrupt
AnnaBridge	189:f392fc9709a3	1768	* @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
AnnaBridge	189:f392fc9709a3	1769	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1770	* @retval None
AnnaBridge	189:f392fc9709a3	1771	*/
AnnaBridge	189:f392fc9709a3	1772	__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1773	{
AnnaBridge	189:f392fc9709a3	1774	CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge	189:f392fc9709a3	1775	}
AnnaBridge	189:f392fc9709a3	1776
AnnaBridge	189:f392fc9709a3	1777	/**
AnnaBridge	189:f392fc9709a3	1778	* @brief Disable Wake Up from Stop Mode Interrupt
AnnaBridge	189:f392fc9709a3	1779	* @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
AnnaBridge	189:f392fc9709a3	1780	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1781	* @retval None
AnnaBridge	189:f392fc9709a3	1782	*/
AnnaBridge	189:f392fc9709a3	1783	__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1784	{
AnnaBridge	189:f392fc9709a3	1785	CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge	189:f392fc9709a3	1786	}
AnnaBridge	189:f392fc9709a3	1787
AnnaBridge	189:f392fc9709a3	1788	/**
AnnaBridge	189:f392fc9709a3	1789	* @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1790	* @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
AnnaBridge	189:f392fc9709a3	1791	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1792	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1793	*/
AnnaBridge	189:f392fc9709a3	1794	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1795	{
AnnaBridge	189:f392fc9709a3	1796	return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
AnnaBridge	189:f392fc9709a3	1797	}
AnnaBridge	189:f392fc9709a3	1798
AnnaBridge	189:f392fc9709a3	1799	/**
AnnaBridge	189:f392fc9709a3	1800	* @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1801	* @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
AnnaBridge	189:f392fc9709a3	1802	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1803	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1804	*/
AnnaBridge	189:f392fc9709a3	1805	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1806	{
AnnaBridge	189:f392fc9709a3	1807	return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
AnnaBridge	189:f392fc9709a3	1808	}
AnnaBridge	189:f392fc9709a3	1809
AnnaBridge	189:f392fc9709a3	1810	/**
AnnaBridge	189:f392fc9709a3	1811	* @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1812	* @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
AnnaBridge	189:f392fc9709a3	1813	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1814	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1815	*/
AnnaBridge	189:f392fc9709a3	1816	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1817	{
AnnaBridge	189:f392fc9709a3	1818	return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
AnnaBridge	189:f392fc9709a3	1819	}
AnnaBridge	189:f392fc9709a3	1820
AnnaBridge	189:f392fc9709a3	1821	/**
AnnaBridge	189:f392fc9709a3	1822	* @brief Check if the LPUART TX Empty Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1823	* @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
AnnaBridge	189:f392fc9709a3	1824	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1825	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1826	*/
AnnaBridge	189:f392fc9709a3	1827	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1828	{
AnnaBridge	189:f392fc9709a3	1829	return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
AnnaBridge	189:f392fc9709a3	1830	}
AnnaBridge	189:f392fc9709a3	1831
AnnaBridge	189:f392fc9709a3	1832	/**
AnnaBridge	189:f392fc9709a3	1833	* @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1834	* @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
AnnaBridge	189:f392fc9709a3	1835	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1836	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1837	*/
AnnaBridge	189:f392fc9709a3	1838	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1839	{
AnnaBridge	189:f392fc9709a3	1840	return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
AnnaBridge	189:f392fc9709a3	1841	}
AnnaBridge	189:f392fc9709a3	1842
AnnaBridge	189:f392fc9709a3	1843	/**
AnnaBridge	189:f392fc9709a3	1844	* @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1845	* @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
AnnaBridge	189:f392fc9709a3	1846	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1847	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1848	*/
AnnaBridge	189:f392fc9709a3	1849	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1850	{
AnnaBridge	189:f392fc9709a3	1851	return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
AnnaBridge	189:f392fc9709a3	1852	}
AnnaBridge	189:f392fc9709a3	1853
AnnaBridge	189:f392fc9709a3	1854	/**
AnnaBridge	189:f392fc9709a3	1855	* @brief Check if the LPUART Error Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1856	* @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
AnnaBridge	189:f392fc9709a3	1857	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1858	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1859	*/
AnnaBridge	189:f392fc9709a3	1860	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1861	{
AnnaBridge	189:f392fc9709a3	1862	return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
AnnaBridge	189:f392fc9709a3	1863	}
AnnaBridge	189:f392fc9709a3	1864
AnnaBridge	189:f392fc9709a3	1865	/**
AnnaBridge	189:f392fc9709a3	1866	* @brief Check if the LPUART CTS Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1867	* @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
AnnaBridge	189:f392fc9709a3	1868	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1869	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1870	*/
AnnaBridge	189:f392fc9709a3	1871	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1872	{
AnnaBridge	189:f392fc9709a3	1873	return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
AnnaBridge	189:f392fc9709a3	1874	}
AnnaBridge	189:f392fc9709a3	1875
AnnaBridge	189:f392fc9709a3	1876	/**
AnnaBridge	189:f392fc9709a3	1877	* @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	1878	* @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
AnnaBridge	189:f392fc9709a3	1879	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1880	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1881	*/
AnnaBridge	189:f392fc9709a3	1882	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1883	{
AnnaBridge	189:f392fc9709a3	1884	return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
AnnaBridge	189:f392fc9709a3	1885	}
AnnaBridge	189:f392fc9709a3	1886
AnnaBridge	189:f392fc9709a3	1887	/**
AnnaBridge	189:f392fc9709a3	1888	* @}
AnnaBridge	189:f392fc9709a3	1889	*/
AnnaBridge	189:f392fc9709a3	1890
AnnaBridge	189:f392fc9709a3	1891	/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
AnnaBridge	189:f392fc9709a3	1892	* @{
AnnaBridge	189:f392fc9709a3	1893	*/
AnnaBridge	189:f392fc9709a3	1894
AnnaBridge	189:f392fc9709a3	1895	/**
AnnaBridge	189:f392fc9709a3	1896	* @brief Enable DMA Mode for reception
AnnaBridge	189:f392fc9709a3	1897	* @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
AnnaBridge	189:f392fc9709a3	1898	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1899	* @retval None
AnnaBridge	189:f392fc9709a3	1900	*/
AnnaBridge	189:f392fc9709a3	1901	__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1902	{
AnnaBridge	189:f392fc9709a3	1903	SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge	189:f392fc9709a3	1904	}
AnnaBridge	189:f392fc9709a3	1905
AnnaBridge	189:f392fc9709a3	1906	/**
AnnaBridge	189:f392fc9709a3	1907	* @brief Disable DMA Mode for reception
AnnaBridge	189:f392fc9709a3	1908	* @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
AnnaBridge	189:f392fc9709a3	1909	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1910	* @retval None
AnnaBridge	189:f392fc9709a3	1911	*/
AnnaBridge	189:f392fc9709a3	1912	__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1913	{
AnnaBridge	189:f392fc9709a3	1914	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge	189:f392fc9709a3	1915	}
AnnaBridge	189:f392fc9709a3	1916
AnnaBridge	189:f392fc9709a3	1917	/**
AnnaBridge	189:f392fc9709a3	1918	* @brief Check if DMA Mode is enabled for reception
AnnaBridge	189:f392fc9709a3	1919	* @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
AnnaBridge	189:f392fc9709a3	1920	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1921	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1922	*/
AnnaBridge	189:f392fc9709a3	1923	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1924	{
AnnaBridge	189:f392fc9709a3	1925	return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
AnnaBridge	189:f392fc9709a3	1926	}
AnnaBridge	189:f392fc9709a3	1927
AnnaBridge	189:f392fc9709a3	1928	/**
AnnaBridge	189:f392fc9709a3	1929	* @brief Enable DMA Mode for transmission
AnnaBridge	189:f392fc9709a3	1930	* @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
AnnaBridge	189:f392fc9709a3	1931	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1932	* @retval None
AnnaBridge	189:f392fc9709a3	1933	*/
AnnaBridge	189:f392fc9709a3	1934	__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1935	{
AnnaBridge	189:f392fc9709a3	1936	SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge	189:f392fc9709a3	1937	}
AnnaBridge	189:f392fc9709a3	1938
AnnaBridge	189:f392fc9709a3	1939	/**
AnnaBridge	189:f392fc9709a3	1940	* @brief Disable DMA Mode for transmission
AnnaBridge	189:f392fc9709a3	1941	* @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
AnnaBridge	189:f392fc9709a3	1942	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1943	* @retval None
AnnaBridge	189:f392fc9709a3	1944	*/
AnnaBridge	189:f392fc9709a3	1945	__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1946	{
AnnaBridge	189:f392fc9709a3	1947	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge	189:f392fc9709a3	1948	}
AnnaBridge	189:f392fc9709a3	1949
AnnaBridge	189:f392fc9709a3	1950	/**
AnnaBridge	189:f392fc9709a3	1951	* @brief Check if DMA Mode is enabled for transmission
AnnaBridge	189:f392fc9709a3	1952	* @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
AnnaBridge	189:f392fc9709a3	1953	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1954	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1955	*/
AnnaBridge	189:f392fc9709a3	1956	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1957	{
AnnaBridge	189:f392fc9709a3	1958	return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
AnnaBridge	189:f392fc9709a3	1959	}
AnnaBridge	189:f392fc9709a3	1960
AnnaBridge	189:f392fc9709a3	1961	/**
AnnaBridge	189:f392fc9709a3	1962	* @brief Enable DMA Disabling on Reception Error
AnnaBridge	189:f392fc9709a3	1963	* @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
AnnaBridge	189:f392fc9709a3	1964	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1965	* @retval None
AnnaBridge	189:f392fc9709a3	1966	*/
AnnaBridge	189:f392fc9709a3	1967	__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1968	{
AnnaBridge	189:f392fc9709a3	1969	SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge	189:f392fc9709a3	1970	}
AnnaBridge	189:f392fc9709a3	1971
AnnaBridge	189:f392fc9709a3	1972	/**
AnnaBridge	189:f392fc9709a3	1973	* @brief Disable DMA Disabling on Reception Error
AnnaBridge	189:f392fc9709a3	1974	* @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
AnnaBridge	189:f392fc9709a3	1975	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1976	* @retval None
AnnaBridge	189:f392fc9709a3	1977	*/
AnnaBridge	189:f392fc9709a3	1978	__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1979	{
AnnaBridge	189:f392fc9709a3	1980	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge	189:f392fc9709a3	1981	}
AnnaBridge	189:f392fc9709a3	1982
AnnaBridge	189:f392fc9709a3	1983	/**
AnnaBridge	189:f392fc9709a3	1984	* @brief Indicate if DMA Disabling on Reception Error is disabled
AnnaBridge	189:f392fc9709a3	1985	* @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
AnnaBridge	189:f392fc9709a3	1986	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1987	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1988	*/
AnnaBridge	189:f392fc9709a3	1989	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1990	{
AnnaBridge	189:f392fc9709a3	1991	return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
AnnaBridge	189:f392fc9709a3	1992	}
AnnaBridge	189:f392fc9709a3	1993
AnnaBridge	189:f392fc9709a3	1994	/**
AnnaBridge	189:f392fc9709a3	1995	* @brief Get the LPUART data register address used for DMA transfer
AnnaBridge	189:f392fc9709a3	1996	* @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	1997	* @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
AnnaBridge	189:f392fc9709a3	1998	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1999	* @param Direction This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2000	* @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
AnnaBridge	189:f392fc9709a3	2001	* @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
AnnaBridge	189:f392fc9709a3	2002	* @retval Address of data register
AnnaBridge	189:f392fc9709a3	2003	*/
AnnaBridge	189:f392fc9709a3	2004	__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
AnnaBridge	189:f392fc9709a3	2005	{
AnnaBridge	189:f392fc9709a3	2006	register uint32_t data_reg_addr = 0U;
AnnaBridge	189:f392fc9709a3	2007
AnnaBridge	189:f392fc9709a3	2008	if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
AnnaBridge	189:f392fc9709a3	2009	{
AnnaBridge	189:f392fc9709a3	2010	/* return address of TDR register */
AnnaBridge	189:f392fc9709a3	2011	data_reg_addr = (uint32_t) &(LPUARTx->TDR);
AnnaBridge	189:f392fc9709a3	2012	}
AnnaBridge	189:f392fc9709a3	2013	else
AnnaBridge	189:f392fc9709a3	2014	{
AnnaBridge	189:f392fc9709a3	2015	/* return address of RDR register */
AnnaBridge	189:f392fc9709a3	2016	data_reg_addr = (uint32_t) &(LPUARTx->RDR);
AnnaBridge	189:f392fc9709a3	2017	}
AnnaBridge	189:f392fc9709a3	2018
AnnaBridge	189:f392fc9709a3	2019	return data_reg_addr;
AnnaBridge	189:f392fc9709a3	2020	}
AnnaBridge	189:f392fc9709a3	2021
AnnaBridge	189:f392fc9709a3	2022	/**
AnnaBridge	189:f392fc9709a3	2023	* @}
AnnaBridge	189:f392fc9709a3	2024	*/
AnnaBridge	189:f392fc9709a3	2025
AnnaBridge	189:f392fc9709a3	2026	/** @defgroup LPUART_LL_EF_Data_Management Data_Management
AnnaBridge	189:f392fc9709a3	2027	* @{
AnnaBridge	189:f392fc9709a3	2028	*/
AnnaBridge	189:f392fc9709a3	2029
AnnaBridge	189:f392fc9709a3	2030	/**
AnnaBridge	189:f392fc9709a3	2031	* @brief Read Receiver Data register (Receive Data value, 8 bits)
AnnaBridge	189:f392fc9709a3	2032	* @rmtoll RDR RDR LL_LPUART_ReceiveData8
AnnaBridge	189:f392fc9709a3	2033	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2034	* @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	2035	*/
AnnaBridge	189:f392fc9709a3	2036	__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2037	{
AnnaBridge	189:f392fc9709a3	2038	return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge	189:f392fc9709a3	2039	}
AnnaBridge	189:f392fc9709a3	2040
AnnaBridge	189:f392fc9709a3	2041	/**
AnnaBridge	189:f392fc9709a3	2042	* @brief Read Receiver Data register (Receive Data value, 9 bits)
AnnaBridge	189:f392fc9709a3	2043	* @rmtoll RDR RDR LL_LPUART_ReceiveData9
AnnaBridge	189:f392fc9709a3	2044	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2045	* @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge	189:f392fc9709a3	2046	*/
AnnaBridge	189:f392fc9709a3	2047	__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2048	{
AnnaBridge	189:f392fc9709a3	2049	return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge	189:f392fc9709a3	2050	}
AnnaBridge	189:f392fc9709a3	2051
AnnaBridge	189:f392fc9709a3	2052	/**
AnnaBridge	189:f392fc9709a3	2053	* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
AnnaBridge	189:f392fc9709a3	2054	* @rmtoll TDR TDR LL_LPUART_TransmitData8
AnnaBridge	189:f392fc9709a3	2055	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2056	* @param Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	2057	* @retval None
AnnaBridge	189:f392fc9709a3	2058	*/
AnnaBridge	189:f392fc9709a3	2059	__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
AnnaBridge	189:f392fc9709a3	2060	{
AnnaBridge	189:f392fc9709a3	2061	LPUARTx->TDR = Value;
AnnaBridge	189:f392fc9709a3	2062	}
AnnaBridge	189:f392fc9709a3	2063
AnnaBridge	189:f392fc9709a3	2064	/**
AnnaBridge	189:f392fc9709a3	2065	* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
AnnaBridge	189:f392fc9709a3	2066	* @rmtoll TDR TDR LL_LPUART_TransmitData9
AnnaBridge	189:f392fc9709a3	2067	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2068	* @param Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge	189:f392fc9709a3	2069	* @retval None
AnnaBridge	189:f392fc9709a3	2070	*/
AnnaBridge	189:f392fc9709a3	2071	__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
AnnaBridge	189:f392fc9709a3	2072	{
AnnaBridge	189:f392fc9709a3	2073	LPUARTx->TDR = Value & 0x1FFU;
AnnaBridge	189:f392fc9709a3	2074	}
AnnaBridge	189:f392fc9709a3	2075
AnnaBridge	189:f392fc9709a3	2076	/**
AnnaBridge	189:f392fc9709a3	2077	* @}
AnnaBridge	189:f392fc9709a3	2078	*/
AnnaBridge	189:f392fc9709a3	2079
AnnaBridge	189:f392fc9709a3	2080	/** @defgroup LPUART_LL_EF_Execution Execution
AnnaBridge	189:f392fc9709a3	2081	* @{
AnnaBridge	189:f392fc9709a3	2082	*/
AnnaBridge	189:f392fc9709a3	2083
AnnaBridge	189:f392fc9709a3	2084	/**
AnnaBridge	189:f392fc9709a3	2085	* @brief Request Break sending
AnnaBridge	189:f392fc9709a3	2086	* @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
AnnaBridge	189:f392fc9709a3	2087	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2088	* @retval None
AnnaBridge	189:f392fc9709a3	2089	*/
AnnaBridge	189:f392fc9709a3	2090	__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2091	{
AnnaBridge	189:f392fc9709a3	2092	SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
AnnaBridge	189:f392fc9709a3	2093	}
AnnaBridge	189:f392fc9709a3	2094
AnnaBridge	189:f392fc9709a3	2095	/**
AnnaBridge	189:f392fc9709a3	2096	* @brief Put LPUART in mute mode and set the RWU flag
AnnaBridge	189:f392fc9709a3	2097	* @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
AnnaBridge	189:f392fc9709a3	2098	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2099	* @retval None
AnnaBridge	189:f392fc9709a3	2100	*/
AnnaBridge	189:f392fc9709a3	2101	__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2102	{
AnnaBridge	189:f392fc9709a3	2103	SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
AnnaBridge	189:f392fc9709a3	2104	}
AnnaBridge	189:f392fc9709a3	2105
AnnaBridge	189:f392fc9709a3	2106	/**
AnnaBridge	189:f392fc9709a3	2107	* @brief Request a Receive Data flush
AnnaBridge	189:f392fc9709a3	2108	* @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
AnnaBridge	189:f392fc9709a3	2109	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2110	* @retval None
AnnaBridge	189:f392fc9709a3	2111	*/
AnnaBridge	189:f392fc9709a3	2112	__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2113	{
AnnaBridge	189:f392fc9709a3	2114	SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
AnnaBridge	189:f392fc9709a3	2115	}
AnnaBridge	189:f392fc9709a3	2116
AnnaBridge	189:f392fc9709a3	2117	/**
AnnaBridge	189:f392fc9709a3	2118	* @}
AnnaBridge	189:f392fc9709a3	2119	*/
AnnaBridge	189:f392fc9709a3	2120
AnnaBridge	189:f392fc9709a3	2121	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	2122	/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	2123	* @{
AnnaBridge	189:f392fc9709a3	2124	*/
AnnaBridge	189:f392fc9709a3	2125	ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
AnnaBridge	189:f392fc9709a3	2126	ErrorStatus LL_LPUART_Init(USART_TypeDef LPUARTx, LL_LPUART_InitTypeDef LPUART_InitStruct);
AnnaBridge	189:f392fc9709a3	2127	void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
AnnaBridge	189:f392fc9709a3	2128	/**
AnnaBridge	189:f392fc9709a3	2129	* @}
AnnaBridge	189:f392fc9709a3	2130	*/
AnnaBridge	189:f392fc9709a3	2131	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	2132
AnnaBridge	189:f392fc9709a3	2133	/**
AnnaBridge	189:f392fc9709a3	2134	* @}
AnnaBridge	189:f392fc9709a3	2135	*/
AnnaBridge	189:f392fc9709a3	2136
AnnaBridge	189:f392fc9709a3	2137	/**
AnnaBridge	189:f392fc9709a3	2138	* @}
AnnaBridge	189:f392fc9709a3	2139	*/
AnnaBridge	189:f392fc9709a3	2140
AnnaBridge	189:f392fc9709a3	2141	#endif /* LPUART1 */
AnnaBridge	189:f392fc9709a3	2142
AnnaBridge	189:f392fc9709a3	2143	/**
AnnaBridge	189:f392fc9709a3	2144	* @}
AnnaBridge	189:f392fc9709a3	2145	*/
AnnaBridge	189:f392fc9709a3	2146
AnnaBridge	189:f392fc9709a3	2147	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	2148	}
AnnaBridge	189:f392fc9709a3	2149	#endif
AnnaBridge	189:f392fc9709a3	2150
AnnaBridge	189:f392fc9709a3	2151	#endif /* __STM32L0xx_LL_LPUART_H */
AnnaBridge	189:f392fc9709a3	2152
AnnaBridge	189:f392fc9709a3	2153	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/