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targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_mpu.h
<> 144:ef7eb2e8f9f7 3 * @brief Memory protection unit (MPU) peripheral API
<> 144:ef7eb2e8f9f7 4 * @version 4.2.1
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #ifndef __SILICON_LABS_EM_MPU_H__
<> 144:ef7eb2e8f9f7 34 #define __SILICON_LABS_EM_MPU_H__
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "em_device.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 39 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdbool.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 48 * @addtogroup EM_Library
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 ******************************************************************************/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 53 * @addtogroup MPU
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 ******************************************************************************/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @anchor MPU_CTRL_PRIVDEFENA
<> 144:ef7eb2e8f9f7 58 * Argument to MPU_enable(). Enables priviledged
<> 144:ef7eb2e8f9f7 59 * access to default memory map. */
<> 144:ef7eb2e8f9f7 60 #define MPU_CTRL_PRIVDEFENA MPU_CTRL_PRIVDEFENA_Msk
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @anchor MPU_CTRL_HFNMIENA
<> 144:ef7eb2e8f9f7 63 * Argument to MPU_enable(). Enables MPU during hard fault,
<> 144:ef7eb2e8f9f7 64 * NMI, and FAULTMASK handlers. */
<> 144:ef7eb2e8f9f7 65 #define MPU_CTRL_HFNMIENA MPU_CTRL_HFNMIENA_Msk
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /*******************************************************************************
<> 144:ef7eb2e8f9f7 68 ******************************** ENUMS ************************************
<> 144:ef7eb2e8f9f7 69 ******************************************************************************/
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /**
<> 144:ef7eb2e8f9f7 72 * Size of an MPU region.
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 typedef enum
<> 144:ef7eb2e8f9f7 75 {
<> 144:ef7eb2e8f9f7 76 mpuRegionSize32b = 4, /**< 32 byte region size. */
<> 144:ef7eb2e8f9f7 77 mpuRegionSize64b = 5, /**< 64 byte region size. */
<> 144:ef7eb2e8f9f7 78 mpuRegionSize128b = 6, /**< 128 byte region size. */
<> 144:ef7eb2e8f9f7 79 mpuRegionSize256b = 7, /**< 256 byte region size. */
<> 144:ef7eb2e8f9f7 80 mpuRegionSize512b = 8, /**< 512 byte region size. */
<> 144:ef7eb2e8f9f7 81 mpuRegionSize1Kb = 9, /**< 1K byte region size. */
<> 144:ef7eb2e8f9f7 82 mpuRegionSize2Kb = 10, /**< 2K byte region size. */
<> 144:ef7eb2e8f9f7 83 mpuRegionSize4Kb = 11, /**< 4K byte region size. */
<> 144:ef7eb2e8f9f7 84 mpuRegionSize8Kb = 12, /**< 8K byte region size. */
<> 144:ef7eb2e8f9f7 85 mpuRegionSize16Kb = 13, /**< 16K byte region size. */
<> 144:ef7eb2e8f9f7 86 mpuRegionSize32Kb = 14, /**< 32K byte region size. */
<> 144:ef7eb2e8f9f7 87 mpuRegionSize64Kb = 15, /**< 64K byte region size. */
<> 144:ef7eb2e8f9f7 88 mpuRegionSize128Kb = 16, /**< 128K byte region size. */
<> 144:ef7eb2e8f9f7 89 mpuRegionSize256Kb = 17, /**< 256K byte region size. */
<> 144:ef7eb2e8f9f7 90 mpuRegionSize512Kb = 18, /**< 512K byte region size. */
<> 144:ef7eb2e8f9f7 91 mpuRegionSize1Mb = 19, /**< 1M byte region size. */
<> 144:ef7eb2e8f9f7 92 mpuRegionSize2Mb = 20, /**< 2M byte region size. */
<> 144:ef7eb2e8f9f7 93 mpuRegionSize4Mb = 21, /**< 4M byte region size. */
<> 144:ef7eb2e8f9f7 94 mpuRegionSize8Mb = 22, /**< 8M byte region size. */
<> 144:ef7eb2e8f9f7 95 mpuRegionSize16Mb = 23, /**< 16M byte region size. */
<> 144:ef7eb2e8f9f7 96 mpuRegionSize32Mb = 24, /**< 32M byte region size. */
<> 144:ef7eb2e8f9f7 97 mpuRegionSize64Mb = 25, /**< 64M byte region size. */
<> 144:ef7eb2e8f9f7 98 mpuRegionSize128Mb = 26, /**< 128M byte region size. */
<> 144:ef7eb2e8f9f7 99 mpuRegionSize256Mb = 27, /**< 256M byte region size. */
<> 144:ef7eb2e8f9f7 100 mpuRegionSize512Mb = 28, /**< 512M byte region size. */
<> 144:ef7eb2e8f9f7 101 mpuRegionSize1Gb = 29, /**< 1G byte region size. */
<> 144:ef7eb2e8f9f7 102 mpuRegionSize2Gb = 30, /**< 2G byte region size. */
<> 144:ef7eb2e8f9f7 103 mpuRegionSize4Gb = 31 /**< 4G byte region size. */
<> 144:ef7eb2e8f9f7 104 } MPU_RegionSize_TypeDef;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * MPU region access permission attributes.
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 typedef enum
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 mpuRegionNoAccess = 0, /**< No access what so ever. */
<> 144:ef7eb2e8f9f7 112 mpuRegionApPRw = 1, /**< Priviledged state R/W only. */
<> 144:ef7eb2e8f9f7 113 mpuRegionApPRwURo = 2, /**< Priviledged state R/W, User state R only. */
<> 144:ef7eb2e8f9f7 114 mpuRegionApFullAccess = 3, /**< R/W in Priviledged and User state. */
<> 144:ef7eb2e8f9f7 115 mpuRegionApPRo = 5, /**< Priviledged R only. */
<> 144:ef7eb2e8f9f7 116 mpuRegionApPRo_URo = 6 /**< R only in Priviledged and User state. */
<> 144:ef7eb2e8f9f7 117 } MPU_RegionAp_TypeDef;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /*******************************************************************************
<> 144:ef7eb2e8f9f7 121 ******************************* STRUCTS ***********************************
<> 144:ef7eb2e8f9f7 122 ******************************************************************************/
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** MPU Region init structure. */
<> 144:ef7eb2e8f9f7 125 typedef struct
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 bool regionEnable; /**< MPU region enable. */
<> 144:ef7eb2e8f9f7 128 uint8_t regionNo; /**< MPU region number. */
<> 144:ef7eb2e8f9f7 129 uint32_t baseAddress; /**< Region baseaddress. */
<> 144:ef7eb2e8f9f7 130 MPU_RegionSize_TypeDef size; /**< Memory region size. */
<> 144:ef7eb2e8f9f7 131 MPU_RegionAp_TypeDef accessPermission; /**< Memory access permissions. */
<> 144:ef7eb2e8f9f7 132 bool disableExec; /**< Disable execution. */
<> 144:ef7eb2e8f9f7 133 bool shareable; /**< Memory shareable attribute. */
<> 144:ef7eb2e8f9f7 134 bool cacheable; /**< Memory cacheable attribute. */
<> 144:ef7eb2e8f9f7 135 bool bufferable; /**< Memory bufferable attribute. */
<> 144:ef7eb2e8f9f7 136 uint8_t srd; /**< Memory subregion disable bits. */
<> 144:ef7eb2e8f9f7 137 uint8_t tex; /**< Memory type extension attributes. */
<> 144:ef7eb2e8f9f7 138 } MPU_RegionInit_TypeDef;
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** Default configuration of MPU region init structure for flash memory. */
<> 144:ef7eb2e8f9f7 141 #define MPU_INIT_FLASH_DEFAULT \
<> 144:ef7eb2e8f9f7 142 { \
<> 144:ef7eb2e8f9f7 143 true, /* Enable MPU region. */ \
<> 144:ef7eb2e8f9f7 144 0, /* MPU Region number. */ \
<> 144:ef7eb2e8f9f7 145 FLASH_MEM_BASE, /* Flash base address. */ \
<> 144:ef7eb2e8f9f7 146 mpuRegionSize1Mb, /* Size - Set to max. */ \
<> 144:ef7eb2e8f9f7 147 mpuRegionApFullAccess, /* Access permissions. */ \
<> 144:ef7eb2e8f9f7 148 false, /* Execution allowed. */ \
<> 144:ef7eb2e8f9f7 149 false, /* Not shareable. */ \
<> 144:ef7eb2e8f9f7 150 true, /* Cacheable. */ \
<> 144:ef7eb2e8f9f7 151 false, /* Not bufferable. */ \
<> 144:ef7eb2e8f9f7 152 0, /* No subregions. */ \
<> 144:ef7eb2e8f9f7 153 0 /* No TEX attributes. */ \
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** Default configuration of MPU region init structure for sram memory. */
<> 144:ef7eb2e8f9f7 158 #define MPU_INIT_SRAM_DEFAULT \
<> 144:ef7eb2e8f9f7 159 { \
<> 144:ef7eb2e8f9f7 160 true, /* Enable MPU region. */ \
<> 144:ef7eb2e8f9f7 161 1, /* MPU Region number. */ \
<> 144:ef7eb2e8f9f7 162 RAM_MEM_BASE, /* SRAM base address. */ \
<> 144:ef7eb2e8f9f7 163 mpuRegionSize128Kb, /* Size - Set to max. */ \
<> 144:ef7eb2e8f9f7 164 mpuRegionApFullAccess, /* Access permissions. */ \
<> 144:ef7eb2e8f9f7 165 false, /* Execution allowed. */ \
<> 144:ef7eb2e8f9f7 166 true, /* Shareable. */ \
<> 144:ef7eb2e8f9f7 167 true, /* Cacheable. */ \
<> 144:ef7eb2e8f9f7 168 false, /* Not bufferable. */ \
<> 144:ef7eb2e8f9f7 169 0, /* No subregions. */ \
<> 144:ef7eb2e8f9f7 170 0 /* No TEX attributes. */ \
<> 144:ef7eb2e8f9f7 171 }
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /** Default configuration of MPU region init structure for onchip peripherals.*/
<> 144:ef7eb2e8f9f7 175 #define MPU_INIT_PERIPHERAL_DEFAULT \
<> 144:ef7eb2e8f9f7 176 { \
<> 144:ef7eb2e8f9f7 177 true, /* Enable MPU region. */ \
<> 144:ef7eb2e8f9f7 178 0, /* MPU Region number. */ \
<> 144:ef7eb2e8f9f7 179 0, /* Region base address. */ \
<> 144:ef7eb2e8f9f7 180 mpuRegionSize32b, /* Size - Set to minimum */ \
<> 144:ef7eb2e8f9f7 181 mpuRegionApFullAccess, /* Access permissions. */ \
<> 144:ef7eb2e8f9f7 182 true, /* Execution not allowed. */ \
<> 144:ef7eb2e8f9f7 183 true, /* Shareable. */ \
<> 144:ef7eb2e8f9f7 184 false, /* Not cacheable. */ \
<> 144:ef7eb2e8f9f7 185 true, /* Bufferable. */ \
<> 144:ef7eb2e8f9f7 186 0, /* No subregions. */ \
<> 144:ef7eb2e8f9f7 187 0 /* No TEX attributes. */ \
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /*******************************************************************************
<> 144:ef7eb2e8f9f7 192 ***************************** PROTOTYPES **********************************
<> 144:ef7eb2e8f9f7 193 ******************************************************************************/
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 200 * @brief
<> 144:ef7eb2e8f9f7 201 * Disable the MPU
<> 144:ef7eb2e8f9f7 202 * @details
<> 144:ef7eb2e8f9f7 203 * Disable MPU and MPU fault exceptions.
<> 144:ef7eb2e8f9f7 204 ******************************************************************************/
<> 144:ef7eb2e8f9f7 205 __STATIC_INLINE void MPU_Disable(void)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable fault exceptions */
<> 144:ef7eb2e8f9f7 208 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; /* Disable the MPU */
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 213 * @brief
<> 144:ef7eb2e8f9f7 214 * Enable the MPU
<> 144:ef7eb2e8f9f7 215 * @details
<> 144:ef7eb2e8f9f7 216 * Enable MPU and MPU fault exceptions.
<> 144:ef7eb2e8f9f7 217 * @param[in] flags
<> 144:ef7eb2e8f9f7 218 * Use a logical OR of @ref MPU_CTRL_PRIVDEFENA and
<> 144:ef7eb2e8f9f7 219 * @ref MPU_CTRL_HFNMIENA as needed.
<> 144:ef7eb2e8f9f7 220 ******************************************************************************/
<> 144:ef7eb2e8f9f7 221 __STATIC_INLINE void MPU_Enable(uint32_t flags)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk
<> 144:ef7eb2e8f9f7 224 | MPU_CTRL_HFNMIENA_Msk
<> 144:ef7eb2e8f9f7 225 | MPU_CTRL_ENABLE_Msk)));
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 MPU->CTRL = flags | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */
<> 144:ef7eb2e8f9f7 228 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** @} (end addtogroup MPU) */
<> 144:ef7eb2e8f9f7 233 /** @} (end addtogroup EM_Library) */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237 #endif
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 #endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #endif /* __SILICON_LABS_EM_MPU_H__ */